Lm2733 0.6 and 1.6-Mhz Boost Converters With 40-V Internal Fet Switch in Sot-23
Lm2733 0.6 and 1.6-Mhz Boost Converters With 40-V Internal Fet Switch in Sot-23
Lm2733 0.6 and 1.6-Mhz Boost Converters With 40-V Internal Fet Switch in Sot-23
LM2733
SNVS209F – NOVEMBER 2002 – REVISED DECEMBER 2014
LM2733 0.6 and 1.6-MHz Boost Converters With 40-V Internal FET Switch in SOT-23
1 Features 3 Description
•
1 40-V DMOS FET Switch The LM2733 switching regulators are current-mode
boost converters operating fixed frequency of 1.6
• 1.6 MHz (“X”), 0.6 MHz (“Y”) Switching Frequency MHz (“X” option) and 600 kHz (“Y” option).
• Low RDS(ON) DMOS FET
The use of SOT-23 package, made possible by the
• Switch Current up to 1A minimal power loss of the internal 1-A switch, and
• Wide Input Voltage Range (2.7 V – 14 V) use of small inductors and capacitors result in the
• Low Shutdown Current (< 1 µA) industry's highest power density. The 40-V internal
switch makes these solutions perfect for boosting to
• 5-Lead SOT-23 Package
voltages of 16 V or greater.
• Uses Tiny Capacitors and Inductors
These parts have a logic-level shutdown pin that can
• Cycle-by-Cycle Current Limiting
be used to reduce quiescent current and extend
• Internally Compensated battery life.
Protection is provided through cycle-by-cycle current
2 Applications limiting and thermal shutdown. Internal compensation
• White LED Current Source simplifies design and reduces component count.
• PDA’s and Palm-Top Computers
Device Information(1)
• Digital Cameras
PART NUMBER PACKAGE BODY SIZE (NOM)
• Portable Phones and Games
LM2733 SOT-23 (5) 2.90 mm x 1.60 mm
• Local Boost Regulator
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM2733
SNVS209F – NOVEMBER 2002 – REVISED DECEMBER 2014 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 10
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 11
3 Description ............................................................. 1 8 Application and Implementation ........................ 12
4 Revision History..................................................... 2 8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 3 9 Power Supply Recommendations...................... 18
6.1 Absolute Maximum Ratings ...................................... 3 10 Layout................................................................... 18
6.2 ESD Ratings.............................................................. 3 10.1 Layout Guidelines ................................................. 18
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 18
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 19
6.5 Electrical Characteristics........................................... 4 11.1 Trademarks ........................................................... 19
6.6 Typical Characteristics .............................................. 6 11.2 Electrostatic Discharge Caution ............................ 19
7 Detailed Description ............................................ 10 11.3 Glossary ................................................................ 19
7.1 Overview ................................................................. 10 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 10 Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
5-Pin
SOT-23 Package
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
SW 1 O Drain of the internal FET switch.
GND 2 GND Analog and power ground.
FB 3 I Feedback point that connects to external resistive divider.
SHDN 4 I Shutdown control input. Connect to VIN if this feature is not used.
VIN 5 I Analog and power input.
6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
MIN MAX UNIT
Input Supply Voltage (VIN) −0.4 14.5 V
FB Pin Voltage −0.4 6 V
SW Pin Voltage −0.4 40 V
SHDN Pin Voltage −0.4 VIN + 0.3 V
Power Dissipation (3) Internally Limited
Lead Temp. (Soldering, 5 sec.) 300 °C
Tstg Storage temperature −65 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of the limits set forth under the operating ratings which specify the intended range of operating
conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum power dissipation which can be safely dissipated for any application is a function of the maximum junction temperature,
TJ(MAX) = 125°C, the junction-to-ambient thermal resistance for the SOT-23 package, θJ-A = 265°C/W, and the ambient temperature,
TA. The maximum allowable power dissipation at any ambient temperature for designs using this device can be calculated using the
formula: If power dissipation exceeds the maximum specified above, the internal thermal protection
circuitry will protect the device by reducing the output voltage as required to maintain a safe junction temperature.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
1.06
1.05
1.04
Iq ACTIVE (mA)
1.03
1.02
1.01
0.99
0.98
-50 -25 0 25 50 75 100 125 150
o
TEMPERATURE ( C)
0.610
0.600
0.595
0.590
0.585
0.580
0.575
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (oC)
Figure 3. Oscillator Frequency vs Temperature - "X" Figure 4. Oscillator Frequency vs Temperature - "Y"
93.4 96.55
96.5
93.3
96.45
93.2
MAX DUTY CYCLE
MAX DUTY CYCLE (%)
96.4
93.1 96.35
96.3
93.0
96.25
92.9 96.2
96.15
92.8
96.1
92.7 96.05
-40 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 150
Figure 5. Max. Duty Cycle vs Temperature - "X" Figure 6. Max. Duty Cycle vs Temperature - "Y"
80 VIN = 10V
VIN = 5V
70
EFFICIENCY (%)
60
VIN = 3.3V
50
40
30
20
10
0
0 200 400 600 800 1000
Figure 11. Efficiency vs Load Current (VOUT = 12 V) - "X" Figure 12. Efficiency vs Load Current (VOUT = 15 V) - "X"
EFFICIENCY (%)
VIN = 5V
EFFICIENCY (%)
70 70 VIN = 5V
60 VIN = 3.3V 60
50 50
40 40
30 30
20 20
10 10
0 0
0 100 200 300 400 500 600 700 0 50 100 150 200 250 300 350 400
LOAD CURRENT (mA) LOAD CURRENT (mA)
Figure 13. Efficiency vs Load Current (VOUT = 20 V) - "X" Figure 14. Efficiency vs Load Current (VOUT = 25 V) - "X"
100 100
90 90
80 VIN = 10V 80 VIN = 10V
EFFICIENCY (%)
70
EFFICIENCY (%)
70
60 VIN = 5V
60
50 50
40 40
30 30
20 20
10
10
0
0
0 50 100 150 200 250 300 350 0 50 200
100 150
LOAD CURRENT (mA) LOAD CURRENT (mA)
Figure 15. Efficiency vs Load Current (VOUT = 30 V) - "X" Figure 16. Efficiency vs Load Current (VOUT = 35 V) - "X"
90
80
VIN=10V
70
EFFICIENCY (%)
60
50
40
30
20
10
0
0 50 100 150 200
Figure 17. Efficiency vs Load Current (VOUT = 40 V) - "X" Figure 18. Efficiency vs Load (VOUT = 15 V) - "Y"
Figure 19. Efficiency vs Load (VOUT = 20 V) - "Y" Figure 20. Efficiency vs Load (VOUT = 25 V) - "Y"
Figure 21. Efficiency vs Load (VOUT = 30 V) - "Y" Figure 22. Efficiency vs Load (VOUT = 35 V) - "Y"
7 Detailed Description
7.1 Overview
The LM2733 device is a switching converter IC that operates at a fixed frequency (0.6 or 1.6 MHz) using current-
mode control for fast transient response over a wide input voltage range and incorporate pulse-by-pulse current
limiting protection. Because this is current mode control, a 50 mΩ sense resistor in series with the switch FET is
used to provide a voltage (which is proportional to the FET current) to both the input of the pulse width
modulation (PWM) comparator and the current limit amplifier.
At the beginning of each cycle, the S-R latch turns on the FET. As the current through the FET increases, a
voltage (proportional to this current) is summed with the ramp coming from the ramp generator and then fed into
the input of the PWM comparator. When this voltage exceeds the voltage on the other input (coming from the
Gm amplifier), the latch resets and turns the FET off. Since the signal coming from the Gm amplifier is derived
from the feedback (which samples the voltage at the output), the action of the PWM comparator constantly sets
the correct peak current through the FET to keep the output volatge in regulation.
Q1 and Q2 along with R3 - R6 form a bandgap voltage reference used by the IC to hold the output in regulation.
The currents flowing through Q1 and Q2 will be equal, and the feedback loop will adjust the regulated output to
maintain this. Because of this, the regulated output is always maintained at a voltage level equal to the voltage at
the FB node "multiplied up" by the ratio of the output resistive divider.
The current limit comparator feeds directly into the flip-flop, that drives the switch FET. If the FET current reaches
the limit threshold, the FET is turned off and the cycle terminated until the next clock pulse. The current limit
input terminates the pulse regardless of the status of the output of the PWM comparator.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
The equation shown for calculating duty cycle incorporates terms for the FET switch voltage and diode forward
voltage. The actual duty cycle measured in operation will also be affected slightly by other power losses in the
circuit such as wire losses in the inductor, switching losses, and capacitor ripple current losses from self-heating.
Therefore, the actual (effective) duty cycle measured may be slightly higher than calculated to compensate for
these power losses. A good approximation for effective duty cycle is :
DC (eff) = (1 - Efficiency x (VIN/VOUT)) (4)
Where the efficiency can be approximated from the curves provided.
During the 0.390 µs ON time, the inductor current ramps up 0.176 A and ramps down an equal amount during
the OFF time. This is defined as the inductor “ripple current”. It can also be seen that if the load current drops to
about 33 mA, the inductor current will begin touching the zero axis which means it will be in discontinuous mode.
A similar analysis can be performed on any boost converter, to make sure the ripple current is reasonable and
continuous operation will be maintained at the typical load current values.
1600 1600
1400 1400
1200 1200
VIN = 3.3V
1000 VIN = 3.3V 1000
800 800
VIN = 2.7V
VIN = 2.7V
600 600
400 400
200 200
0 0
0 20 40 60 80 100 0 20 40 60 80 100
Figure 26. Switch Current Limit vs Duty Cycle - "X" Figure 27. Switch Current Limit vs Duty Cycle - "Y"
Figure 28. Max. Load Current vs VIN - "X" Figure 29. Max. Load Current vs VIN - "Y"
The voltage across the inductor during ON time is 4.8V. Minimum inductance value is found by:
V = L X dl/dt, L = V X (dt/dl) = 4.8 (0.524µ/1) = 2.5 µH (13)
In this case, a 2.7 µH inductor could be used assuming it provided at least that much inductance up to the 1A
current value. This same analysis can be used to find the minimum inductance for any boost application. Using
the slower switching “Y” version requires a higher amount of minimum inductance because of the longer
switching period.
Figure 31. Efficiency vs. Load Current (5-12V, X-version) Figure 32. Efficiency vs. Load Current (5-20V X-version)
10 Layout
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 23-Oct-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM2733XMF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 S52A
LM2733XMF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 S52A
& no Sb/Br)
LM2733XMFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 S52A
& no Sb/Br)
LM2733YMF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 S52B
LM2733YMF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 S52B
& no Sb/Br)
LM2733YMFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 S52B
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 23-Oct-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Jul-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Jul-2015
Pack Materials-Page 2
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