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    AXI Lite Design

    Uploaded by

    ganapathi

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    AXI Lite Design

    Uploaded by

    ganapathi
    22 views4 pages

    Original Title

    AXI-Lite-Design

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

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    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    22 views4 pages

    AXI Lite Design

    Uploaded by

    ganapathi

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 4

    AXI Lite Design

    Master AXI-Lite Specification

    • Write through AXI-Lite Protocol app_wdata


    app_wdone
    • User provides write data on app_wdata app_waddr
    app_werror
    port
    app_wen app_rdone
    • User provides write address on app_rdata
    app_waddr port Master AXI-Lite
    app_rerror
    • When user enables app_wen the block app_raddr
    writes data, through AXI-Lite block
    app_ren
    • After finishing the block sets up AXI-Lite
    app_wdone and app_werror ports
    • Read through AXI-Lite Protocol
    • User provides read data address on
    app_raddr port
    • When user enables app_ren the block
    reads data, through AXI-Lite block
    • After finishing the block sets up
    app_rdone and app_rerror ports
    Simulate Master AXI-Lite
    • We will connect our designed AXI-Lite Master to AXI_Lite Slave Verification IP
    • Exchange the data between them

    app_wdone
    app_wdata
    app_werror
    app_waddr
    app_wen app_rdone System
    app_rdata Verilog AXI-Lite Slave AXI-Lite
    Master AXI-Lite Interface Verification IP
    TB app_rerror Object
    app_raddr
    app_ren AXI-Lite
    Slave AXI-Lite Specification

    • Write Data: when Master want to write app_rdata app_wdata


    the Slave AXI app_waddr
    • Returns master provided write data to its app_wen
    app_wdata port
    • Returns master provided write address to it Slave AXI-Lite
    app_waddr port AXI-Lite
    app_raddr
    • Enables app_wen output app_ren
    • Read data: When master want to read
    data
    • Slave gets the master read address on it
    app_raddr output port
    • Slave activates its app_ren output
    • After that slave reads its app_rdata input
    and sends to master

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