Nothing Special   »   [go: up one dir, main page]
Scribd Logo
Upload

Welcome to Scribd!

  • 2K views

    Flip Flop Experiment

    Uploaded by

    Deepak Kumbhar
    This document describes an assignment to study three types of flip-flops: R-S, D, and J-K. It includes circuit diagrams, truth tables, and procedures to build and test each flip-flop using a circuit board and digital trainer kit. The theory section explains how each flip-flop works by analyzing cases in their truth tables. It defines a flip-flop as a bi-stable circuit with two stable output states. Key points about each flip-flop type are provided. Questions at the end assess understanding of flip-flops and how to form a T-flip-flop from a JK flip-flop.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Flip Flop Experiment

    Uploaded by

    Deepak Kumbhar
    2K views5 pages
    This document describes an assignment to study three types of flip-flops: R-S, D, and J-K. It includes circuit diagrams, truth tables, and procedures to build and test each flip-flop using a circuit board and digital trainer kit. The theory section explains how each flip-flop works by analyzing cases in their truth tables. It defines a flip-flop as a bi-stable circuit with two stable output states. Key points about each flip-flop type are provided. Questions at the end assess understanding of flip-flops and how to form a T-flip-flop from a JK flip-flop.

    Original Description:

    Flip Flop Experiment

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes an assignment to study three types of flip-flops: R-S, D, and J-K. It includes circuit diagrams, truth tables, and procedures to build and test each flip-flop using a circuit board and digital trainer kit. The theory section explains how each flip-flop works by analyzing cases in their truth tables. It defines a flip-flop as a bi-stable circuit with two stable output states. Key points about each flip-flop type are provided. Questions at the end assess understanding of flip-flops and how to form a T-flip-flop from a JK flip-flop.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    2K views5 pages

    Flip Flop Experiment

    Uploaded by

    Deepak Kumbhar
    This document describes an assignment to study three types of flip-flops: R-S, D, and J-K. It includes circuit diagrams, truth tables, and procedures to build and test each flip-flop using a circuit board and digital trainer kit. The theory section explains how each flip-flop works by analyzing cases in their truth tables. It defines a flip-flop as a bi-stable circuit with two stable output states. Key points about each flip-flop type are provided. Questions at the end assess understanding of flip-flops and how to form a T-flip-flop from a JK flip-flop.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 5

    Assignment 6

    Aim: Study of flip- flop:

    1. R-S flip- flop


    2. D-flip- flop
    3. J-K flip- flop

    Requirements: Circuit Board/ Digital Trainer kit and connecting wires.

    Circuit Diagram with Truth table :

    1. SR Flip-flop

    Fig. a. S-R Flip-Flop

    Truth table: -

    Inputs Output
    Inference
    CLK S R Q Q
    0 X X X X No change
    1 0 0 X X No change
    1 0 1 0 1 Reset
    1 1 0 1 0 Set
    1 1 1 1 1 Invalid

    2. D Flip-flop

    3
    Truth table:

    Inputs Output
    Inference
    CLK D Q
    0 X X No change
    1 0 0 Reset
    1 1 1 Set

    3. JK Flip-Flop

    Truth table: -

    Inputs Output
    Inference
    CLK J K Q Q
    0 X X X X No change
    1 0 0 X X No change
    1 0 1 0 1 Reset
    1 1 0 1 0 Set
    1 1 1 1 1 Toggle

    Procedure:

    1. Make the connection for RS flip flop


    2. Apply the proper inputs and clock signal.
    3. Observe the corresponding outputs and compare with the table given
    4. Repeat the same procedure for JK and D-F.F.

    3
    Observation Table:
    1. SR Flip-flop

    Inputs Q (Output) Q
    LED Logic LED Logic
    CLK S R
    State Level State Level
    0 X X
    1 0 0
    1 0 1
    1 1 0
    1 1 1

    2. D FF
    Inputs Q (Output)
    CLK D LED State Logic Level
    0 X
    1 0
    1 1

    3. J-K Flip-flop

    Inputs Q (Output) Q
    LED Logic LED Logic
    CLK J K
    State Level State Level
    0 X X
    1 0 0
    1 0 1
    1 1 0
    1 1 1

    Theory:
    A flip-flop is a bi-stable electronic circuit. Flip-flop has 2 stable output states,0 and 1.
    The stable state of a flip-flop can be changed only by changing the set of its inputs.
    R-S Flip-flop: is basically a device that has 2 inputs along with the clock and 2 outputs, one output
    being the complement of the other. 2 inputs are called Set and Reset.
    The clocked RS flip flop has additional input called clock which control the action of flip-flop.
    When clock goes low, we get a stable output. Circuit will operate as an RS flip-flop only when clock
    goes high.
    3
    Case1: When S=0,R=0; clock pulse have no effect. Output Q retains its last value.
    So No change in the output..
    Case 2: When S=0 and R=1;
    Q=0 and Q=1... Hence flip-flop is in Reset condition.
    Case 3: When S=1 and R=0
    Q=1 and Q=0...Hence flip-flop is in Set condition.
    Case 4: When S=R=1,outputs of NAND gates A and B are 0.So both gates C and D receive one input as
    0.Hence their outputs go to 1 .
    Thus Q=Q=1, which is not possible as Q and Q should be complementary. This is not allowed condition
    D Flip Flop:-
    The D Flip-Flop is very useful when a signal bit is to be stored. It can be developed from RS flip –flop
    using a signal inverter.
    The flip flop has a1 i/p & a clock.
    Case1: When D=0 S=0, R=1
    Q=0. The flip-flop is in Reset state.
    Case 2: When D=1 S=1, R=0
    So Q=1 hence flip-flop is in Set state.
    Q will always follow D input after some time delay. Hence it is also called as Delay flip-flop.
    J-K flip-flop:-
    In JK flip-flop, output Q is fed as an additional input to gate A and Q is fed as an additional input to
    gate B apart from JK inputs and clock.
    Case 1: When J & K both are low both the NAND gate are disabled, c/k pulse have no effect. The o/p
    of Q retains its last value i.e. No change in the outputs
    Case 2: If ‘J’ is low & ’K ’is high the upper gate is disabled.
    So flip-flop is in Reset condition.
    When J is high & K is low,
    Q=1 and Q-0 i.e. flip-flop is in Set state.
    Case 4: When J & K is high, Q and Q are inverted. This is called as toggling mode.
    That means the flip flop will toggle.

    Result:

    3
    Conclusion:

    Questions:

    1. Define Flip-Flop and mention its types.

    2. Explain how T-Flip-flop is formed by using JK Flip-Flop.

    Assignment Evaluation
    0: Not Done [ ] 1: Incomplete [ ] 2:Late Complete [ ]

    3: Needs Improvement [ ] 4: Complete [ ] 5: Well Done [ ]

    Signature of Instructor

    You might also like