6.002 Homework and Solutions

Name _______________________
Section ______________________
Massachusetts Institute of Technology

Department of Electrical Engineering and Computer Science
6.002 Circuits and Electronics

Spring 2001
Homework #1
Handout S01-013
Issued: 2/8/2001 Due: 2/16/2001
For this problem set only, do your work directly on these pages and turn them in.
Read Chapters 1 through 4.
Problem 1.1: With attention to the convention of associated variables, add and label the missing
variables on the circuits below. Be sure to indicate polarities!
a)
2 4
v2 i4
i1 1 3 v3 5 i5
b)
i1 1 4 i4
i3
3 6 v6
2 v2 5 v5
c) How many nodes are there in circuit a)? ______ In circuit b)? ______
Name _______________________
Section ______________________
d) Using the variables shown and those you have provided, write KVL statements for all
the meshes (think fishnets) in circuit b). Use the space below:
e) Label the nodes of circuit a) as a, b, ..., n, and using the variables shown and those you
have supplied, write KCL statements for each node. Use the space below:
Problem 1.2: In each of the following circuits, determine the values of the indicated voltages
and/or currents. (Voltages are in volts and currents are in amperes.)
a)
3 5 v1 = ______________
v1 v2 = ______________
v3 v3 = ______________
1 v2
b)
3 5 v1 = ______________
v2 = ______________
2 -1
1 i2 i3 v3 = ______________
2 v1 v2 v3
i2 = ______________
i3 = ______________
Name _______________________
Section ______________________
Problem 1.3: For each of the circuits below express the resistance R , or the equivalent conduc-
tance G = 1 ⁄ R , at the terminals in terms of the element resistances R n (or conductances
G n = 1 ⁄ R n ). Write your answers next to the circuits.
a)
R1
R2
R3
b)
R1 R2 R3
c)
R1
R2 R3
d)
R2
R1
R3
Name _______________________
Section ______________________
e) Can the same methods be used to find the resistance at the terminals of the circuit
below? If so, express it; if not, explain why not.
R1 R4
R3
R2 R5
Problem 1.4: In each of the following circuits determine the voltages and/or currents indicated.
The units are volts (V), milliamperes (mA), and kilo-ohms (kΩ).
a)
1
10 2 v=?
b)
v=?
1
5 6 i=? 2
Name _______________________
Section ______________________
c)
3
v=? 1 2 1
d)
2 2
10
v=?
4 1
Problem 1.5: For each of the following circuits, using the assigned node-to-reference voltages,
write a set of node equations (KCL statements) sufficient to solve for the node voltages. Do not
solve them!
a)
G2
G1 G3
e1 e2
V1 G4 I1 I2 G5
Name _______________________
Section ______________________
b)
e1
R1 R4
R2
I e2 e3
R5
R3
Problem 1.6: This problem concerns Thevenin and Norton equivalents.
a) A gray box has the terminal characteristics shown. Devise both Thevenin and Norton
equivalent circuits which represent the terminal characteristics of the box. Be sure to
show element values and source polarities and label the terminals.
.
i (milliamperes)
i
GRAY a 5
v
v (Volts)
BOX b
-2
Name _______________________
Section ______________________
Thevenin:
Norton:
b) Determine the Thevenin equivalent at the terminals indicated of the circuit shown
below. Label the terminals and indicate element values and source polarity.
a b
2 kΩ
6 kΩ
10 Volts 3 kΩ
3 kΩ
1 mA
Approximately how many hours did you spend on this problem set? ____________

Spring 2001
Homework #2
Handout S01-016
Issued: 2/15/2001 Due: 2/23/2001
Read Chapter 6.
Problem 2.1: This problem is concerned with nodal analysis and the superposition theorem. A
linear circuit containing two sources is shown below. Conductance values are in mhos (Ω-1).
A
0.1 0.2
iA
V 0.1 0.2 I
a) Write node equations which enable the complete determination of the voltages and
currents in the circuit.
b) Solve these equations for the node to reference voltages (in terms of V and I) and cal-
culate the value of the current iA (also in terms of V and I) in the resistor marked A.
Pay attention to the polarity of iA!
c) Sketch the circuit when the voltage source is acting alone and the current source is
dead.
d) By inspection, and the use of series-parallel relationships, determine the component of

iA that results from the voltage source alone.
e) Sketch the circuit when the current source is acting alone and the voltage source is
dead.
f) As in part d), determine the component of iA that results from the current source alone.
g) Add the components determined in d) and f) together. Compare this result for iA with
that you obtained in part b).
If the results are not the same, check your answer.
Problem 2.2: Consider a sheet of conducting material of thickness 10 microns (10x10-6 m) and
of bulk resistivity ρ or σ = 0.1 Ω-cm (such a layer of resistive material might be created in a sili-
con integrated circuit.).
a) What is the sheet resistance of this material? (Sheet resistance, denoted by R , is

defined as the resistance between perfect conductors connected to the opposite edges
of a square piece of the conducting material.)
b) What should be the dimensions (width W and length L) of a rectangular piece of this
material which has a resistance between opposite edges of 820 Ω? The minimum per-
missible dimension is 0.6 micron.
c) What is the approximate resistance of the piece of this material sketched below?
0.5 3
1.5
Problem 2.3: This problem is concerned with equivalent circuits. Two gray boxes are connected
as shown.
ia ib
BOX a b BOX
v 3 kΩ
A a’ b’ B
As shown the voltage v across the 3 kΩ resistor is 8 V.

When the 3 kΩ resistor is replaced by a short circuit, the currents at the terminals of the boxes are
ia = -5 mA and ib = 1 mA.
a) What is the value of v when the 3 kΩ resistor is replaced by an open circuit (i.e., the
resistor is removed)?
b) Is there sufficent information to determine the Norton equivalent circuits of each box?
Explain.
c) You are now free to cut the connections between the boxes. What single measurement
would you make on either (but not both) box to determine the Norton equivalents of
both boxes?
d) Assume a value for that measurement and specify the equivalent circuits of each box.
Problem 2.4: This problem and the next deal with Boolean algebra and the implementation of
logic functions with gates.
a) The truth tables for the functions H(A,B,C) and J(A,B,C) are shown below:
A B C H J
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 1
1 0 0 0 0
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1
Write corresponding logic functions for H and J.
b) Implement H(A,B,C) with 2-input NAND gates.
c) Implement J(A,B,C) with 2-input NOR gates.
Problem 2.5: Using NAND and NOR gates implement the functions shown below:
a) F1 = A + CB +ABC
b) F2 = (A+C)(B+D)(C+A+B)

Spring 2001
Homework #3
Handout S01-020
Issued: 2/22/2001 Due: 3/2/2001
Read Chapter 7.
Problem 3.1: Derive truth tables and Boolean expressions for the digital circuits a, c, and f shown in
Problem 1 at the end of Chapter 6 of the course notes. (Figure 6.29)
Problem 3.2: This problem is concerned with the design of a MOSFET switch (see Figure 7.11 in the
course notes) which must satisfy a prescribed static discipline. The transistor has the following
characteristics:
On resistance: 100-500 ohms

Threshold voltage: 1.8-2.6 volts
(These ranges reflect normal manufacturing variances for a specific FET type.)
The available supply voltage is 5 volts. For reasons of switching speed (which will be discussed in a few
weeks) the resistor R L between the drain and power supply may not exceed 10kΩ . The static discipline is:
V OH = 4.5V
V IH = 3.0V
V IL = 1.5V
V OL = 0.5V
See Sections 6.1 and 6.2 of the course notes for definitions.
a) What is the permissible range of values for R L that satisfy the static discipline?
b) What is the noise margin for a low input?
c) What is the noise margin for a high input?
d) Assume that n of these transistors are used to create a multiple-input NAND gate. What is
the value of R L that maximizes n?
e) What is the largest possible value of n?

Problem 3.3: A buffer has the input/output transfer characteristic shown below:
Vout
2
0
0 1 2 3 4 5
Vin
a) Find values of the voltages V OL , V IL , V IH , and V OH such that this buffer satisfies the static
discipline shown in Figure 6.7 of the course notes.
b) What are the zero and one noise margins for the values you have chosen?
Problem 3.4: A three-terminal device shown below has the characteristices indicated:
c
i
b
+
?
v
-
a
When v is less than 3 volts, terminal c is connected to terminal a. When v is greater than 4 volts, terminal
c is isolated and i must be zero.
a) Devise and sketch a circuit in which this device functions as a buffer. Label input and output
terminals. Prepare a truth table showing values of the input and output voltages of your
circuit.
b) Using one or more of these devices, devise and sketch a two input AND gate.
c) Repeat for a two input OR gate.
d) Can you use this device to create an inverter? Explain.


Spring 2001
Homework #4
Handout S01-025
Issued: 3/1/2001 Due: 3/9/2001
Read Chapter 5.
Problem 4.1: Use MOSFETS and resistors to create circuit-level implementations of the follow-
ing logic functions. Use the switch model (S model) for the transistors. Assume that each vari-
able is available in true and complementary forms.
a) AB+CD
b) (A+B)(C+D)
Problem 4.2: Write Boolean expressions that describe the functions of circuits (a) and (b) in Fig-
ure 7.39 of the notes (page 258).
Problem 4.3: Consider the N-input NOR gate shown below. Assume that each transistor has an
on resistance of RON.
Vs
A1 A2 An-1 An
a) For what set of inputs does the gate consume the maximum amount of power?
b) Derive an expression for this worst case power.
c) What is the value of the worst-case power for R=10 KΩ, RON=0.5 KΩ, VS=5 V?
Problem 4.4: Consider the circuit module shown right comprising
T1
a pair of series connected n-channel MOSFETs and a resistor. The
module has four terminals, T1, T2, T3, and T4. Using one or more
circuit modules, implement the Boolean function X=AB+AB. The
implementation must clearly show how the circuit modules are T2
interconnected, how A and B and the power supply are connected to
the implementation, and at which terminal the output X appears.
In developing the implementation make the following four assump- T3

tions. First, assume that the ground potential is 0 V and that a 5-V T4
power supply is available. Second, assume that a logical 1 is repre-
sented by the voltage of 5 V, and that a logical 0 is represented by
the voltage of 0 V. Third, assume that A and B are both available in
their true and complementary forms. Fourth, assume that the MOS-
FETs behave as ideal switches that turn on when a logical 1 is
applied to the gate and turn off when a logical 0 is applied.
Problem 4.5: The semiconductor diode in the circuit below has the i-v characteristic indicated.
i qv
– 10  kT 
------
0.5 kΩ i = 10 e – 1 A
1 kΩ  
10 mA v
i1 kT
v ------ = 25 mV.
q
Determine the values of v and i.
Hint: Think about the applicability of techniques learned earlier before you write nonlinear equa-
tions.

Spring 2001
Homework #5
Handout S01-031
Issued: 3/8/2001 Due: 3/16/2001
Problem 5.1: Use graphical techniques to determine the current and voltage across the the nonlin-
ear element.
R=2.5kΩ
+
v
10v N.L.
i -
i (mA)
i-v graph for 4

nonlinear
element
3
0
v (volts)
0 1 2 3 4 5 6
Problem 5.2: The circuit shown below contains a single nonlinear element, whose i-v characteris-
tic is indicated.
5Ω
i
1Ω
+ + kv2
v1
+
v
i= { 0
v>0
v<0
5Ω 1v N.L.
2A N.L. v
k = 0.5 mhos
-------------
- volt
-
- i
a) Using linear circuit techniques, reduce the portion of the circuit contianing sources and resis-
tors to a Thevenin or Norton equivalent.
b) Determine the current i and the voltage v for the nonlinear element.
c) Determine the voltage v1 across the current source.

Problem 5.3: The semiconductor diode is used as a variable attenuator in the circuit shown below.
1k
+ Diode characteristics:
qv
VI i  ------
kT 
+ i = I S  e – 1
 
v vO
vi
- – 11
I S = 10 Amperes
-
kT
------ = 25millivolts
q
a) Determine the incremental resistance of the semiconductor diode. Express the result in terms of
the dc operating point current I in the diode. Make reasonable approximations in this analysis,
and pay attention to the units!
b) Devise and sketch an incremental or small-signal model for this attenuator which shows vi, the
small-signal input voltage, and vo, the small-signal component of the output voltage vO. Deter-
mine the attenuation ratio vo/vi .
c) What is the range of I required for an attenuation ratio in the range:
vo
0.01 < ----- < 0.1
vi
Again, make reasonable approximations.
d) The dc source VI establishes an operating point for the diode. Using an ideal-diode-offset-volt-
age-source model for the diode with an offset voltage of 0.6 volts, determine the range of VI nec-
essary for the diode operating point currents in the range defined in c) shown above.
Problem 5.4: The circuit below is that of a symmetrical clipper.
R=10k
+
vI
vO
Its purpose is to limit the range of vO to a narrow range even though vI may go well beyond that
range.
a) Using ideal-diode-offset-voltage models for the diodes (with an offset voltage of 0.5v), sketch
and dimension the transfer characteristic vO vs vI.
b)Now, using the ideal-diode-offset-voltage-series-resistor model (with the same offset voltage as
in a) and a series resistance of 100 ohms) revise the sketch developed in a) to reflect the imperfect
clipping action of the circuit.

Spring 2001
Homework #5
Handout S01-031
Issued: 3/8/2001 Due: 3/16/2001
Problem 5.1: Use graphical techniques to determine the current and voltage across the the nonlin-
ear element.
R=2.5kΩ
+
v
10v N.L.
i -
i (mA)
i-v graph for 4

nonlinear
element
3
0
v (volts)
0 1 2 3 4 5 6
Problem 5.2: The circuit shown below contains a single nonlinear element, whose i-v characteris-
tic is indicated.
5Ω
i
1Ω
+ + kv2
v1
+
v
i= { 0
v>0
v<0
5Ω 1v N.L.
2A N.L. v
k = 0.5 mhos
-------------
- volt
-
- i
a) Using linear circuit techniques, reduce the portion of the circuit contianing sources and resis-
tors to a Thevenin or Norton equivalent.
b) Determine the current i and the voltage v for the nonlinear element.
c) Determine the voltage v1 across the current source.

Problem 5.3: The semiconductor diode is used as a variable attenuator in the circuit shown below.
1k
+ Diode characteristics:
qv
VI i  ------
kT 
+ i = I S  e – 1
 
v vO
vi
- – 11
I S = 10 Amperes
-
kT
------ = 25millivolts
q
a) Determine the incremental resistance of the semiconductor diode. Express the result in terms of
the dc operating point current I in the diode. Make reasonable approximations in this analysis,
and pay attention to the units!
b) Devise and sketch an incremental or small-signal model for this attenuator which shows vi, the
small-signal input voltage, and vo, the small-signal component of the output voltage vO. Deter-
mine the attenuation ratio vo/vi .
c) What is the range of I required for an attenuation ratio in the range:
vo
0.01 < ----- < 0.1
vi
Again, make reasonable approximations.
d) The dc source VI establishes an operating point for the diode. Using an ideal-diode-offset-volt-
age-source model for the diode with an offset voltage of 0.6 volts, determine the range of VI nec-
essary for the diode operating point currents in the range defined in c) shown above.
Problem 5.4: The circuit below is that of a symmetrical clipper.
R=10k
+
vI
vO
Its purpose is to limit the range of vO to a narrow range even though vI may go well beyond that
range.
a) Using ideal-diode-offset-voltage models for the diodes (with an offset voltage of 0.5v), sketch
and dimension the transfer characteristic vO vs vI.
b)Now, using the ideal-diode-offset-voltage-series-resistor model (with the same offset voltage as
in a) and a series resistance of 100 ohms) revise the sketch developed in a) to reflect the imperfect
clipping action of the circuit.

Spring 2001
Homework #6
Handout S01-36
Issued: 3/15/2001 Due: 3/23/2001
Problem 6.1: The transistor in the amplifier circuit below has the indicated source-drain charac-
teristics.
+ VS
0.8 - vGS = 5 V
VS = 6 V 0.7 -
RL = 8 kΩ
0.6 -
RL
0.5 - 4V
iD (mA)
0.4 -
0.3 - 3V
+
0.2 - 2V
+ vO 0.1 -
vI vGS = 1 V
-
-
-
-
-
-
-
-
-
-
-
-
- - 1 2 3 4 5 6
vGS = 0 V
vDS (volts)
a) What are the intercepts on the axes of the characteristic curves of the circuit constraint
imposed by VS and RL (i.e., the load line)?
b) Using graphical techniques, construct a table showing the dependance of vO on vI and

sketch (and dimension to the extent possible) the transfer characteristic (vO vs vI) of
this amplifier.
vo
c) Estimate the incremental or small-signal voltage gain ----- of this amplifier at an operat-
vi
ing point defined by VGS = 3 volts.
Problem 6.2: The transistor in the amplifier circuit shown below can be modeled using the
switch-current-source model shown.
+ VS
RL
D
iD
K
 ---- ( V – V T ) 2 For V > V and V > V - V
+ G i D =  2 GS GS T DS GS T
 0 For V GS < V T
+ vO 
vI
- - K = 0.1 mA/volt2
S VT = 1 volt
VS = 10 V
RL = 5 kΩ
a) Derive an equation which reflects the dependence of vO on vI for vI > 0.
b) Sketch and dimension the transfer characteristic vO vs. vI of this amplifier over the
entire region of vI for which the transistor model is valid.
c) Devise a small-signal model which relates the incremental output voltage vo to the
incremental input voltage vi and determine the value of the transconductance gm at the
operating point defined by VGS = 2 volts.
d) What is the small-signal voltage gain of this amplifier around the operating point
defined by VGS = 2 volts.
Problem 6.3: The circuit shown below has two outputs, vA and vB.
VS = 12 V
R = 5 kΩ
R K
 ---- ( V – V T ) 2 For V > V and V > V - V
i D =  2 GS GS T DS GS T
 0 For VGS < VT

+
+ K = 2 mA/volt2
vA VT = 2 V
vI +
R vB
- - -
a) This circuit is intended to operate under static (DC or operating point) conditions
whith vDS = 6 volts. Specify the operating-point value VI of the input voltage vI which
achieves the operating point.
b) What are the corresponding operating-point values of VA and VB?
c) Devise a small-signal model for this circuit and label the small-signal input and output
voltages denoted by vi, va, and vb.
d) Use the current-source model shown above to calculate the small signal transconduc-
tance gm (see Section 9.2 of notes: page 323) at the operating point defined in a).
va vb
e) Derive expressions for the small-signal voltage gains ----- and ----- . Note that vgs does
vi vi
not equal vi in this circuit. Evaluate these expressions for the transconductance deter-
mined in d) and the indicated resistance value.
Problem 6.4: For each of the four circuits with dependant sources shown below, evaluate the
indicated ratios.
a) + + vo
R1 R2 ----- = voltage transfer ratio
βvR vO vi
vi
+
R1 vR β>1
- - -
b) i R2
+ v = resistance seen
R1 - --
αv i at the terminals
v +
α>0
-
c) + +
ii vo
-----= voltage transfer ratio
R0 βii vi
R2 vO
vi β>1 vi
---- = resistance seen at
R1 i i the input terminals
- -
d) io
vo
+ ----- = the output resistance
- io
+ αv vi = 0
+ vO
v- α>0 vo
vi +
----- = the open circuit voltage
- R vi transfer ratio
- io = 0

Spring 2001
Homework #7
Handout S01-041
Issued: 3/22/2001 Due: 4/6/2001
Read Chapters 12 and 13.
Problem 7.1: For each of the three circuits shown below, write a differential equation that
describes the circuit for t > 0, and determine the indicated responses. Assume the switches close
or open at t = 0. Sketch and dimension the responses.
a) The switch closes at t = 0. For t < 0, v = -5 volts. Find i(t) and v(t) for t ≥ 0 .
–6
C = 1µF ( or 10 Farad )
+ +v-
10 volts i R = 1kΩ
-
b) The switch closes at t = 0. For t < 0, v = 0. Find i(t) and v(t) for t ≥ 0 .
R1
C = 1µF
i R 1 = 3kΩ
+
+ R 2 = 6kΩ
10 volts R2 v
- C -
c) The switch opens at t = 0. For t < 0, i =+3 amperes. Find i(t) and v(t) for t ≥ 0 .
+
L = 0.1Henry
2A R i L v
R = 1kΩ
-
Problem 7.2: The circuit of a NOT gate that provides one input to a pair of NAND gates is
shown below:
VS = +5 V
R = 20 kΩ
R R R R
+
vo
A -
+
v1 B C
S +
- v2
-
Represent the FETs by the switch-resistor model with the gate-to-source capacitance included
(at right).
D
a) Draw a diagram for this circuit with the FETs
replaced by the model. R ON = 100Ω
G C = 10 –11 F
b) Write a differential equation that describes v1(t) V T = 2 volts
when the switch S is open. + C
RON
c) Find the solution for this equation that applies VGS
when the switch S changes instantaneously (at
t=0). Sketch and dimension this response.
- S
Switch is open when VGS < VT
d) What is the time delay ∆t before transistor A Switch is closed when VGS > VT
turns on?
e) Write a differential equation that describes v2(t), t > 0, once the switch in the model of
transistor A closes. Make reasonable approximations!
f) Find the solution to this equation that applies when transistor A switches from OFF
(output high) to ON (output low). Sketch and dimension the response of v2(t).
g) What is the total time delay before transistors B and C turn off?
h) Finally, assume switch S closes instantaneously at t′ = 0 . What is the time delay, t′ ,

before transistors B and C turn off?
Problem 7.3: An RL circuit is shown below:
R1
+
+
vs(t) = Vs u-1(t) R2 v
- L
-
 0, t < 0
The source is a step of magnitude Vs. That is: v s ( t ) = 
Vs, t ≥ 0
The current in the inductor is zero for t < 0.
a) Write a differential equation for v(t) and solve it for t > 0. Sketch and dimension your
result.
b) The input is changed to an impulse of magnitude (area) Λ . That is:

vs(t) = Λ u0(t)
Without solving the differential equation again, derive an expression for v(t) for t > 0.
Sketch and dimension the result.
c) The input is changed to a ramp of magnitude (slope) M. That is:

vs
slope = M
vs(t) = M u-2(t)
0 t
Without solving the differential equations again, derive an expression for v(t) for t > 0.
vs(t)
Vb
d) The input is changed to that shown below:
Va
0 τ t
Show that this input can be decomposed into two ramps and two steps.
e) Using your results from a) and c) above, by superposing reponse to step and ramp
inputs, derive an expression for v(t) for t > 0.

Spring 2001
Homework #8
Handout S01-045
Issued: 4/5/2001 Due: 4/13/2001
Read Chapters 12 and 13.
Problem 8.1: In the circuits below, all of the energy storage elements are at rest for t < 0. That is,
the capacitors are at zero volts and the inductors are at zero current. In each case determine the
values of the indicated variables at the designated times. Try to determine these values by inspec-
tion of the circuit, without developing complete solutions. [Note that u0(t) and u-1(t) denote the
unit impulse and the unit step functions respectively. V, I, λ, and Q are amplitudes.]
Volts Amps Volts Amps

CIRCUIT v(0+) i(0+) v( ∞ ) i (∞ )
A
B
C
D
E
F
R R
+ +
i i
V u-1(t) + v λ u0(t) +
- C - C v
- -
Circuit A Circuit B
1
R
+ i
+
i
Q u0(t) I u-1(t) R L v
C v
-
-
Circuit C Circuit D
i
+ i
+
λ u0(t) + R L v Q u0(t) R L v
-
- -
Circuit E Circuit F
Problem 8.2: This problem concerns the responses of two single-energy storage units to several
excitations.
R1 +v -
C
Vs(t) + L i R2 is(t) R1 R2
-
Circuit A Circuit B
a) Let Vs(t) = λuo(t), where λ is an amplitude in volt-seconds and u0(t) is the unit
impulse. Assume i(0-) = 0 (circuit initially at rest). Find, sketch and dimension i(t).
b) Repeat for i(0-) = -I.
c) Let vs(t) = Vu-1(t) and i(0-) = 0, (i.e., the circuit is initially at rest). Find, sketch and
dimension i(t).
d) Let is(t) = Iu-1(t) where I is an amplitude in amperes and u-1(t) is the unit step.
Assume v(0-) = -V. Find, sketch and dimension v(t).
2
e) Let is(t) = Mu-2(t) where M is an amplitude in amperes per second and u-2(t) is the unit
ramp. Assume v(0-) = -V. Find, sketch and dimension v(t).
Problem 8.3: The circuit below is initially at rest. Find i(t) and v(t). Sketch and dimension both.
i(t)
L
--- = RC .
R
C L
+ v(t) -
+
-
V u-1(t)
R R
Problem 8.4: This problem relates to the phase-splitter circuit of Problem 6.3 (HW#6), that lin-
earities arise from the fact that the incremental outputs are equal in magnitude and opposite in
sign. All the parameters of Problem 6.3 and the stated operating point apply to this problem.
Each output is loaded by a capacitor, as shown below:
VS = 12 V
R = 5 kΩ
R
+
C vA
-
+
+
vI
R C vB
-
-
a) Revise the small-signal model of Problem 6.3, part c) to reflect the addition of the
capacitors.
3
b) Find expressions for, sketch and dimension the waveforms for va(t) and vb(t) when the
incremental component vi(t) of the input is:
vi(t) = v u-1(t), v is a positive number
c) Explain why the time constants that appear in va(t) and vb(t) are different.
d) Determine the maximum values of v for which the solutions found in b) above apply.
That is, find the largest value of v for which the small signal model is valid.
e) Assume now that vi(t) has the form shown below and v is the value found in d) and the
pulse length T is many time constants.
vi(t)
0
t
T
If the capacitance C is small enough, the responses va(t) and vb(t) for t ≥ T will be
identical to that for 0 < t < T except for a change of sign. However, for some greater
value of C (call it Cmax) the responses of the circuit for T > t, this will not be true
because the small-signal model becomes invalid for a reason different from that of d)
above.
Explain why the model fails, and find expressions for va(t’) and vb(t’) where t’=0 for
t=T. Sketch and dimension your results.
4

Spring 2001
Homework #9
Handout S01-051
Issued: 4/12/2001 Due: 4/20/2001
Problem 9.1: A transistor amplifier is shown to the right. The

VS = 6 V
input voltage is v I = V I + v i cos ωt , where VI is set to an operat-
ing point in the active region, and vi is the amplitude of a small
signal.
R = 5 kΩ L = 10 mH
a) Sketch a small-signal circuit and label all elements of
the model. Assume gm = 10-2 Ω-1. +
vO
vI +
- -
b) The output voltage will be of the form vO = VO + vo
cos(ωt + φο),where VO is the operating point value of
vO and vo and φο are the amplitude and phaseof the
small-signal output voltage. Evaluate vo and φο as functions of ω.
V
c) Evaluate A ( ω ) = -----o- , where V o is the complex amplitude of the output voltage.
Vi
R
d) What is the high-frequency ( ω » --- ) asymptote of A ( ω ) ? Call this value A H .
L
e) Sketch and diagram a Bode diagram for A ( ω ) . That is, plot

i) log A ( ω ) vs. log ω , and
ii) ∠ A ( ω ) vs. log ω , where ∠ A ( ω ) denotes the phase angle of A ( ω ) .
Problem 9.2: A circuit which involves an ideal diode as

well as an inductor and capacitor is shown below. The iL L = 1 mH
circuit is at rest for t < 0. +
Vu-1(t) +
vc
a) What are the values of iL(0+) and vc(0+)? -
C = 10µF
-
b) What is the state of the diode at t = 0+ (i.e., is

it a short or an open)?
c) Write differential equations for iL(t) and vc(t) with the diode closed (i.e., active).
d) Determine iL(t) and vc(t).
e) Find the time t1 at which the diode opens.
f) What are the values of iL(t) and vc(t) for t > t1?
Problem 9.3: The circuits below are driven by sinusoids and are in the sinusoidal steady-state.
V
In each case determine the complex input impedance Z ( s ) = -----i and the indicated voltage trans-
Ii
V
fer ratio A ( s ) = -----o- . Express each function as a ratio of polynomials in s.
Vi
a) b) c)
Ii R1 Ii R1 C1
Ii C
+ C + + C2 +
+ +
Vi R2 Vo Vi R2 Vo
Vi Vo
- - - -
- R1 -
Problem 9.4: For each of the transfer functions shown below, sketch and dimension Bode dia-
grams showing log A and ∠ A vs. log ω . In each case, s = jω.
s
a) A ( s ) = k ------------- , where s1 = 102 sec-1, k = 102
s + s1
1
b) A ( s ) = k ------------- , where s1 = 105 sec-1, k = 102
s + s1
s
c) A ( s ) = k ------------------------------------- , where s1 = 102 sec-1, s2 = 105 sec-1, k = 102
( s + s1 ) ( s + s2 )
Note that these three functions correspond to the transfer functions of the three circuits in Problem
9.3: they are a) a high-pass filter, b) a low-pass filter, and c) a band-pass filter. The realizations of
Problem 9.3 are by no means unique; filters can be realized in many ways.

Spring 2001
Homework #10
Handout S01-055
Issued: 4/19/2001 Due: 4/27/2001
Read Chapter 18
Problem 10.1: Each of the circuits shown below is in the sinusoidal steady state. In each case,
determine Z(s), the input impedance, and A(s), the voltage transfer ratio. Represent the imped-
ances of resistors, capacitors and inductors by R, 1/Cs and Ls, respectively, and clear your expres-
sions of fractions, representing each as a ratio of polynomials.
For each circuit:

Vi Vo
Z(s) = A(s) =
Ii Vi
V and I denote complex amplitudes and Z is an input impedance.

a) b)
R C
+
+
+ +
Ii Vi
Ii Vi C L Vo
C Vo
- -
- -
c)
R1 C1
+
+
Ii Vi R2 Vo
C2
- -
Problem 10.2: A linear circuit has a voltage transfer ratio of the form:
+ + K = 103
s
Vi Linear Vo A(s) =K
Circuit
s + s1 s = 102 sec-1
- -
a) Let s = jω. Express A(jω) in polar form. That is, find A(jω) and A(jω)
such that:
A(jω) = A(jω) e j A(jω)
b) The input voltage vi(t) for which Vi is the complex amplitude is, in the sinusoidal-
steady-state, of the form:
vi(t) = |Vi| cos(ωt + θ)
such that Vi = Vejθ (V is a real number). The output voltage vo(t) for which Vo is the
complex amplitude is, in the sinusoidal-steady-state, of the form:
vo(t) = |Vo(ω)| cos(ωt + φ(ω)).
Find expressions for Vo(ω), |Vo(ω)| , and φ(ω ).
For Problems 3 and 4, you will be making Bode plots. MATLAB is an excellent tool to use. For a
quick introduction to MATLAB, please look at SIPB’s Inessential MATLAB (http://
www.mit.edu/afs/sipb/project/www/matlab/imatlab/imatlab.html). In MATLAB, type
“help bode” and “help tf” for instructions on how to create a bode plot and a transfer function.
Problem 10.3: For an appropriate set of circuit parameters, the voltage transfer ratio of the cir-
s
cuit of part (c) of Problem 10.1 can be expressed as A ( s ) = K ------------------------------------- , where s 1 = 10
( s + s1 ) ( s + s2 )
4 4
sec-1, s 2 = 10 sec-1, and K = 0.2 × 10 .
a) Let s = jω. Εxpress A(jω) in polar form.
b) There is a range of frequencies for which A ( jω ) ≈ B ⋅ j ω , where B is a constant.

What is B and what is the range of frequencies for which this approximation applies?
D
c) There is a range of frequencies for which A ( jω ) ≈ ------ , where D is a constant. What is
jω
D and what is the range of frequencies for which this approximation applies?
d) There is a range of frequencies for which A ( jω ) ≈ F , where F is a constant. What is

B and what is the range of frequencies for which this approximation applies?
e) Sketch a Bode plot showing the frequency dependence of A ( jω ) and ∠ A ( jω ) .

That is, plot log 10 A ( jω ) versus log 10ω and ∠ A ( jω ) versus log 10ω for
6
1 ≤ ω ≤ 10 sec-1. Label all slopes and intercepts.
Note that this circuit is a bandpass filter.
Problem 10.4: The voltage transfer ratio of the circuit of part (b) of Problem 10.1 can be
V 2αs
expressed as follows: A ( s ) = -----o- = ---------------------------------
2
-.
2
Vi s + 2αs + ω 0
a) Express α and ω0 in terms of the circuit parameters R, L, and C.
b) Let s = jω. Express A(jω) in polar form, using the parameters α and ω0.
c) Assume that α << ωo (light damping), sketch a Bode plot showing the frequency
dependence of A(jω); that is, plot log 10 A ( jω ) and ∠ A ( jω ) versus log 10ω for
–2 2
10 ω 0 ≤ ω ≤ 10 ω 0 . Define the slopes and intercepts of the low-frequency and high-
frequency asymptotes. Mark the frequency for which A(jω) is a maximum and find the
value of A(jω) at that maximum.
Note that this circuit is, for α << wo, a narrow-band filter.
6.002 { Circuits and Electronics
Spring 2001
Homework #11
Handout S01-060
Due 5/11/01
Introduction
This homework assignment focuses on the analysis and design of a system for playing back a
digitally-stored audio signal. Additionally, this assignment serves as the pre-lab exercises for
Lab #4, which will involve the construction, testing and demonstration of the audio playback
system. Consequently, you should save a copy of your results for use during Lab #4.
A block diagram of the audio playback system is shown in Figure 1. At the center of the system
is a digital memory in which 32,768 samples of the audio signal are stored. Each sample in the
memory has a unique numerical address between 0 and 32,767, inclusive. Consecutive samples are
stored at consecutive addresses.
To obtain 32,768 consecutive samples of the audio signal, 4.096 seconds of continuous analog
audio signal are rst sampled at an 8-kHz rate. The analog audio samples are then digitized by an
8-bit analog-to-digital converter. That is, the samples are quantized to take on one of 256 possible
discrete digital values between 0 and 255, inclusive. Here, the digital value of 0 corresponds to the
most positive signal voltage, and the digital value of 255 corresponds to the most negative signal
voltage. The resulting digital data is then written into the memory.
To retrieve the stored audio signal samples in sequence at the proper rate, the memory is
addressed by a counter which counts from 0 to 32,767 at an 8-kHz rate established by an external
clock. After counting to 32,767 the counter returns to 0, and the retrieval process repeats itself.
As the memory address increments, the corresponding data appears at the memory output. This
data is converted back to an analog voltage in a piecewise constant manner by a digital-to-analog
converter.
During the course of recording and playing back the analog audio signal, the signal is sampled
Headphone
D/A Low-
Clock Counter Memory Pass Volume
Converter Control
Filter
Figure 1: block diagram of the audio playback system.

in time, quantized in amplitude, and reconstructed in a piecewise constant manner. As you will
learn in 6.003, this process introduces undesirable high-frequency components into the signal. To
minimize the perceived impact of these components, the signal is ltered by a low-pass lter after it
is reconstructed by the digital-to-analog converter. Finally, the signal is fed into a volume control
stage which in turn drives a headphone.
In the course of this homework assignment you will analyze and design four of the functional
blocks shown in Figure 1. These blocks are the clock, the digital-to-analog converter, the low-pass
lter and the volume control. In Lab #4, you will construct these blocks and verify that they
perform as desired. Then, you will combine them with the counter, the read-only memory and the
speaker to construct and demonstrate the entire audio play-back system. Since you will construct
the system from the components in your 6.002 lab kit, your design of the blocks must account for
the fact that the available components are limited.
Problem 1: The Clock

The circuit shown in Figure 2 is the system clock, which is a square-wave oscillator followed by a
CMOS inverter; the inverter functions only as a buer. The oscillator is constructed from another
CMOS inverter, a resistor and a capacitor. Both inverters are powered between the positive supply
voltage VS and ground, and both exhibit the hysteretic input-output characteristic dened in the
gure. The inverters are otherwise ideal.
(A) Assume that vCAP has just charged up to VH so that vOSC has just switched to 0 V. How much
time elapses before vCAP decays to VL , which in turn causes vOSC to switch to VS ?
(B) Assume that vCAP has just decayed to VL so that that vOSC has just switched to VS . How
much time elapses before vCAP charges up to VH , which in turn causes vOSC to switch to 0 V?
(C) Determine the frequency of the oscillator in terms of R, C , VL , VH and VS .
(D) Assume that VL = 1:8 V, VH = 3:0 V and VS = 5:0 V. Choose values for R and C so that the
oscillator oscillates at or very near 8-kHz. Since oscillator frequency alone under species R
IN OUT
+
+
vCAP C + vCLK vOUT
- vOSC
- -
VS
vIN
VL VH VS
Figure 2: the system clock.

and C , there is no single correct choice. Therefore, choose values for R and C that are easily
implemented with the components in the 6.002 lab kit.
(E) For the choice of R and C from Part (D), sketch and clearly label a single graph that displays
vCAP , vOSC and vCLK as a function of time over one period of oscillation.
Problem 2: The Digital-To-Analog Converter

The circuit shown in Figure 3 is the digital-to-analog converter. The voltage sources vDB0 through
vDB7 represent the voltages supplied by the eight data bits of the digital memory, DB0 through
DB7. These voltages will be approximately 5 V when the corresponding data bit is a logical high,
and approximately 0 V when the corresponding data bit is a logical low. The voltage vOFF , which
is set by a potentiometer, is an oset voltage that is used to center the output of the converter
around 0 V. Assume that the op-amp in the converter is ideal.
(A) Determine vDAC as a function of vDB0 through vDB7 , and vOFF .
(B) With vOFF = 0 V, the output of the digital-to-analog converter should span the range of 0 V
to 2:5 V. Thus, the output of the converter should be given by
vDAC = 2:5 V
X7 2 DBi
i
i=0 255
where each data bit DBi takes on the numerical value of 1 when high and 0 when low. In this
manner, each successive data bit from DB0 to DB7 is given a voltage weighting twice that of
the preceding data bit, making it possible for the converter to output voltages from 0 V to
2:5 V in steps of 2:5=255 V. Given this, determine R2 in terms of R1 .
The voltage rating of the headphone is approximately 1.25 V. Since the low-pass lter and
buer between the converter and the speaker both have unity voltage gain over the frequency
R1 R1 R1
2R1 2R1 2R1 2R1 2R1 2R1
+ vDB0
-
+ vDB1
- vDB6 +- vDB7 +-
R2
+5V
-
+ +
vDAC
-
+
vOFF
-
Figure 3: the digital-to-analog converter.

range of interest, the output range of the analog-to-digital converter must be designed to match
the headphone rating. This is why the range is chosen to be 0 V to -2.5 V, with vOFF = 0.
Note further that the output range of the converter is negative. This is because the converter
is based upon the inverting amplier conguration.
(C) The role of vOFF is to oset the output of the digital-to-analog converter so that it is centered
around 0 V. That is, with DB0 through DB7 all low, vDAC should be 1.25 V, and with DB0
through DB7 all high, vDAC should be 1:25 V. Given this, what must be the value of vOFF ?
(D) Assume that R1 = 10 k
. Use the result of Part (B) to determine R2 .
Problem 3: The Low-Pass Filter

The circuit shown in Figure 4 is the low-pass lter. It is a second-order lter, and is driven by the
output of the digital-to-analog converter. Its purpose is to remove the high-frequency components
of the audio signal that result from the sampling, quantization and reconstruction of that signal.
Assume that the op-amp in the lter is ideal.
(A) Assume that the low-pass lter operates in sinusoidal steady state with vDAC = <fVdac ej!t g
and vLPF = <fVlpf ej!t g where Vdac and Vlpf are complex amplitudes. Find the input-output
transfer function HLPF (!) of the lter where HLPF (!) Vlpf =Vdac .
(B) Using the results of Part (A), nd the magnitude and phase of HLPF(!).
(C) There is no best design for the low-pass lter to meet the needs of the audio playback system.
However, with the appropriate choice of C1 , C2 and R, the transfer function of one good design
will take the form
jHLPF(!)j = 1 + (!=! 1
LPF )2
where !LPF is a specied frequency. For this design, show that the low-frequency and high-
frequency asymptotes of jHLPF (!)j intersect at ! = !LPF, and therefore that !LPF is the
frequency that delineates the pass band of the low-pass amplier.
(D) What constraints must be imposed on C1 , C2 and R to obtain the low-pass lter transfer
C1 -
+
+
R R vLPF
+ -
vDAC - C2
Figure 4: the low-pass lter.

function described in Part (C)?
(E) Given that the low-pass lter is to be designed as described in Part (C), use the results of Part
(D) to choose values for C1 , C2 and R so that !LPF 2 4000 rad/s. Since the results of
Part (D) under specify C1 , C2 and R, there is no single correct choice. Therefore, choose C1 ,
C2 and R so that they are easily implemented with the components in the 6.002 lab kit.
(F) Given the choice of C1 , C2 and R from Part (E), determine !LPF, and plot both the log-
magnitude and phase of HLPF(!) against log-frequency for 2 101 rad=s ! 2 105
rad/s.
Problem 4: The Volume Control

Figure 5 shows the output of the low-pass lter driving the volume control stage, which in turn
drives the headphone. A potentiometer is used for R2 so that the gain of the circuit can be easily
adjusted.
Because there exists a coupling capacitor at its input, the volume control stage behaves like a
high-pass lter. In this way, the volume control stage is designed to prevent a possibly damaging
DC voltage from being applied to the headphone. Such a voltage component could be present in
vLPF if, for example, vOFF in the analog-to-digital converter is not properly adjusted to balance the
output of the converter.
(A) Assume that the volume control stage operates in sinusoidal steady state with vLPF = <fVlpf ej!t g
and vOUT = <fVout ej!t g where Vlpf and Vout are complex amplitudes. Find the input-output
transfer function HAMP(!) of the volume control stage where HAMP(!) Vout =Vlpf .
(B) Using the result of Part (A), nd the magnitude and phase of HAMP(!).
(C) Let !AMP be the frequency at which the low-frequency and high-frequency asymptotes of
jHAMP(!)j intersect. Determine !AMP in terms of R1, R2 and C .
(D) Choose values for R1 , R2 and C so that !AMP 2 100 Hz, and jHAMPMAX (!)j = 1 for
! !AMP. Since these conditions alone under specify R1 , R2 and C , there is no single
correct choice. Therefore, choose values for R1 , R2 and C that are easily implemented with
the components in the 6.002 lab kit.
R2
C R1
-
+ +
vLPF +
- vOUT Speaker
-
Figure 5: the volume control stage.

Problem 5: Connecting The Blocks
In the complete audio playback system the output of the digital-to-analog converter is connected
directly to the input of the low-pass lter, and the output of the low-pass lter is connected directly
to the input of the volume control stage, as shown in Figure 1. Thus, the lter loads the converter,
and the amplier loads the lter. Explain why this loading could be ignored in Problems 2, 3 and
4. That is, explain why the converter, lter and volume control stage may each be analyzed and
designed in isolation.

Spring 2001
Homework #3 Solutions
Handout S01-027
Problem 3.1: Derive truth tables and Boolean expressions for the digital circuits a, c, and f shown in
Problem 1 at the end of Chapter 6 of the course notes. (Figure 6.29)
Table 1: Problem 3.1 Truth Tables
A B C Zc Zf
A B C D Za
0 0 0 0 0 0 1
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 1 1 1
0 1 0 0 0 1 1
0 1 0 1 0 1 1
0 1 1 0 0 0 1
0 1 1 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Figure 6.29(a) X = A ⋅ B, Y = C ⋅ D, Z a = X ⋅ Y = X + Y = A ⋅ B + C ⋅ D
Figure 6.29(c) X = A ⋅ B, Y = B ⋅ C, Z c = X ⋅ Y = X + Y = A ⋅ B + B ⋅ C
Figure 6.29(f) X = A + B, Y = B + C, Z f = X ⋅ Y = X + Y = A + B + B + C = A + C + 1 = 1
Problem 3.2: This problem is concerned with the design of a MOSFET switch (see Figure 7.11 in the
course notes) which must satisfy a prescribed static discipline. The transistor has the following
characteristics:
On resistance: 100-500 ohms
Threshold voltage: 1.8-2.6 volts
(These ranges reflect normal manufacturing variances for a specific FET type.)
The available supply voltage is 5 volts. For reasons of switching speed (which will be discussed in a few
weeks) the resistor R L between the drain and power supply may not exceed 10kΩ . The static discipline is:
V OH = 4.5V
V IH = 3.0V
V IL = 1.5V
V OL = 0.5V
See Sections 6.1 and 6.2 of the course notes for definitions.
a) What is the permissible range of values for R L that satisfy the static discipline?
The value of R L affects the static discipline in the high or one state. Using the SR model for the
RL
+
V 5 VDC
+ + -
VIN RON V
- OUT
-
MOSFET, gives the above lump-element circuit. The equation for V OUT is simply the voltage divider
R on
equation: V out = --------------------- ⋅ 5V . From the given V OL , we know that V OUT cannot fall above 0.5 V.
R on + R L
Therefore by setting V OUT to 0.5 V and accounting for the range of values for R ON , we can solve for
R L . For R ON = 100Ω , R L ≥ 900Ω and for R ON = 500Ω , R L ≥ 4500Ω. We were told the maximum value for
R L was 10kΩ . Therefore the range of permissible values is 4.5kΩ ≤ R L ≤ 10kΩ .
b) What is the noise margin for a low input?

By definition, NM0= V IL – V OL = 1.0V , but by the manufacturer’s specifications (with R L = 10kΩ and
R ON = 500Ω ) NM0 = 1.8 V - 0.24 V = 1.56 V.
c) What is the noise margin for a high input?

By definition, NM1= V OH – V IH = 1.5V , but by the manufacturer’s specifications NM1 = 5.0 V - 2.6 V =
2.4 V
d) Assume that n of these transistors are used to create a multiple-input NAND gate. What is
the value of R L that maximizes n?
The equation relating n, R L , and R ON is R L = 9 ⋅ n ⋅ R on
which is linear and therefore the maximum n is the maximum
R L = 10kΩ . RL
+
V 5 VDC
+ + -
e) What is the largest possible value of n? n.R ON V
V - OUT
If all of the R ON = 100Ω (which is the value that maximizes n), IN-
10kΩ 1
then n = ------------- ⋅ --- ≅ 11
100Ω 9
Problem 3.3: A buffer has the input/output transfer characteristic shown below:
a) Find values of the voltages V OL , V IL , V IH , and V OH such that this buffer satisfies the static
discipline shown in Figure 6.7 of the course notes.
This is a binary buffer, not to be confused with an analog buffer. In order to maximize the noise margins,
we set V IL and V IH at values for which the corresponding outputs are farthest from the inputs; thus
V IL = 1.0V and V IH = 4.0V , so that V OL = 0.5V and V OH = 4.5 . Note that other values could have been
chosen; these are merely the set that maximize the noise margins.
b) What are the zero and one noise margins for the values you have chosen?
NM0 = 0.5 V and NM1 = 0.5 V.
Problem 3.4: A three-terminal device shown below has the characteristics indicated:
c
i
b
+
?
v
-
a
When v is less than 3 volts, terminal c is connected to terminal a. When v is greater than 4 volts, terminal
c is isolated and i must be zero.
a) Devise and sketch a circuit in which this device functions as a buffer. Label input and output
terminals. Prepare a truth table showing values of the input and output voltages of your
circuit.
RL
+
V 5 VDC
+ -
? V
VIN + - OUT
-
Table 2: Buffer I/O
Vin Vout
0-3 V 0V
4-5 V 5V
b) Using one or more of these devices, devise and sketch a two input AND gate.
c) Repeat for a two input OR gate.
b: c:
RL RL
5 VDC
5 VDC
+ + + +
? V V VOUT V
+ - OUT - ? - -
VIN1 ?
- VIN1 + VIN2
? -
VIN2
d) Can you use this device to create an inverter? Explain.
Yes! Since the device is ON when the input is low, and OFF
when the input is high, we simply reverse the position of the
device and the pull-up (now a pull-down) resistor from the
?
“usual” MOSFET inverter. Interestingly, this device has + +
essentially the same characteristics as a relay with the two VIN V 5 VDC
- + -
reference pins tied together: when the input is low, the RL V
- OUT
electromagnet is inactive and there is a connection between
the other pins; when the input is high, the electromagnet
becomes active and breaks the connection.

Spring 2001
Handout S01-032
Problem 4.1: Use MOSFETS and resistors to create circuit-level implementations of the following
logic functions. Use the switch model (S model) for the transistors. Assume that each variable is
available in true and complementary forms.
a) AB + CD
b) (A+B)(C+D)
Answer:
The realizations shown here are not unique; many others are possible and some are simpler.
a)
RL RL
out
+
A C Vs
-
AB + CD
B D
Out = AB+CD
1
Problem 1b)
RL RL RL
A+B out
(A+B)(C+D) +
Vs
-
A B
C D
Out = (A+B)(C + D)
Problem 4.2: Write Boolean expressions that describe the functions of circuits (a) and (b) in
Figure 7.39 of the notes (page 258).
Answer:
a) OUT = A
b) OUT = A + B = AB
Problem 4.3: Consider the N-input NOR gate shown below. Assume that each transistor has an on
resistance of RON.
Vs
RL
A1 A2 . . . An-1 An
2
a) For what set of inputs does the gate consume the maximum amount of power?
b) Derive an expression for this worst case power.
c) What is the value of the worst-case power for RL = 10kΩ, RON = 0.5KΩ, Vs = 5V?
Answer:
V 2s
a) Power =
RON + RL
The power is maximum when RON is small. Since the MOSFETs are all in parallel, this occurs
when all the inputs are ON and the effective ON-resistance is RON/n.
b) For the maximum power described in a) above,
V 2s
Power =
RON
+ RL
n
c) For the given values of Vs, RON and RL,
25V 2 25
Power = = mW
 0.5  0.5
+ 10
 + 10  KΩ
 n  n
T1
Problem 4.4: Consider the circuit module show right comprising a

pair of series connected n-channel MOSFETs and a resistor. The
T2
module has four terminals, T1, T2, T3, and T4. Using one or more
circuit modules, implement the Boolean function X = AB + AB.
The implementation must clearly show how the circuit modules are T3
interconnected, how A and B and the power supply are connected to
the implementation, and at which terminal the output X appears. T4
3
Problem 4.4: Continued
In developing the implementation, make the following four assumptions. First, assume that the
ground potential is 0V and that a 5-V power supply is available. Second, assume that a logical 1 is
represented by the voltage of 5V, and that a logical 0 is represented by the voltage of 0V. Third,
assume that A and Bare both available in their true and complementary forms. Fourth, assume that
the MOSFETs behave as ideal switches that turn on when a logical 1 is applied to the gate and turn
off when a logical 0 is applied.
Answer #1: This is the intended answer to this problem. Full points will be awarded if
you approached the problem this way.
To analyze the module, look at the S model with a voltage source connected at T1, inputs at
T2 and T3 and the output at T4. When both inputs are high the module may be represented as:
Vs
Since RL‡RON, the output reduces to Vout = Vs (the
RON output is a logical 1) for both inputs high. Note that the
inputs (T2 and T3) are in series, which constitutes an AND
RON relation, and is a logical 1 for both inputs high. In
+ RL summary, then, this module is a non-inverting AND gate
RL Vout = Vs
- 2 RON + RL which, when the inputs A and B are high, returns AB.
Since A and B are available in true and complementary form, the function X may be implemented as
follows:
A A
+
B B 5V
-
+
R Out R
-
Out = AB+AB
4
Answer #2: This is the correct answer. There is a bug in the circuit and here is the way
to fix it. Full points will also be awarded if you modified the module this way.
Let’s take a second look at the S model with a voltage source connected at T1, inputs at T2 and
T3 and the output at T4. When both inputs are high, Vout = Vs = 5 volts at the output T4, which
essentially sets a voltage of 5 volts at the source, thereby making VGS = 0. The MOSFET at T3
turns off for VGS < VT. With the given module, the problem is not solvable. We must alter
the module as shown to create a NAND gate. Note that in this case, the original resistor plays
no role in this circuit.
Vs
Problem 4.5: The semiconductor diode in the circuit below has the i-v characteristic indicated.
Ω
0.5 kΩ
i i
10mA Ω
1 kΩ
+
+
V i1 V
-
-
5
Determine the value of v and i.
Hint: Think about the applicability of techniques learned earlier before you write nonlinear
equations.
Answer:
The diode is removed from the circuit, and a Thevenin equivalent of the linear circuit is obtained.
Ω
0.5 kΩ i
+
Ω
0.5 kΩ
i Redraw circuit
10mA Ω
1 kΩ 10mA Ω
1 kΩ
+
-
i1
-
(a) (b)
The circuit b) is the original circuit a) redrawn as seen from the terminal. This circuit will
be used to evaluate the diode current id= i. Under open-circuit conditions, i = 0, so that a
voltage drop is realized over the 1 kΩ resistor alone.
Voc = IR = (10mA)(1kΩ) = 10V
With the current source removed, and looking back into the circuit from the point of view
of the terminal, one sees the two resistors in series.
RTh = 0.5kΩ + 1kΩ = 1.5KΩ
Ω
1.5 kΩ
id
10V + +
- vd
-
6
Applying KVL gives the following non-linear equation:
10V − id (1.5kΩ ) = v d
 vd 
10V − (1.5kΩ )(10 −10
Amps ) e 25mV − 1 = vd
 
 
 vd 
( −7

)
10V − 1.5 × 10 V  e 25mV − 1 = v d

 
This reduces to:
 10V − v d 
0.025V ∗ ln −7
+ 1 = v d
 1.5 × 10 V 
This equation may be solved using a calculator or computer, or you may solve it by hand
to yield the following results:
Ans: vd = 449.2 mV; id = 6.367mA;

i1 = 10mA - id = 3.633mA
7

Spring 2001
Handout S01-038
Problem 5.1: To analyze the circuit graphically, we superimpose the network constraint (the
straight line) on the graph of the device i-v characteristic, as below:
i (mA)
i-v graph for Vth/Rth

4
nonlinear
element
i = 3.1mA
3
1/Rth
2
1
v = 2.3V
0
v (volts)
0 1 2 3 4 5 6
Hence, v=2.3 V and i=3.1 mA. These, of course, are approximate values based on eyeballing the
graph.
Problem 5.2: The circuit shown above contains a single nonlinear element, whose i-v character-
istic is indicated.
a) To construct a Thevenin or Norton equivalent, we first 1Ω
remove the nonlinear element from the circuit: 5Ω

2A
+
5Ω 1V
-
Then, convert the branch containing the voltage source 1Ω
and a 5 Ω resistor from a Thevenin form to its Norton
2A 0.2Α
equivalent:
5Ω 5Ω
Now you can sum the current sources, and convert the parallel 1Ω
resistances to an equivalent resistance:
2.2A
2.5Ω
Finally, we write down the Thevenin equivalent circuit: 3.5Ω
5.5V
+
-
b) To find the current and voltage, we must solve a system of equations: the i-v constraint
imposed by the Thevenin equivalent circuit (1) and the i-v characteristic for the nonlin-
ear device (2).
5.5V v
i = ------------ – ------------ (1)
3.5Ω 3.5Ω
1 2
i = --- v (2)
2
Plugging (2) into (1) and rearranging, we get

1 2 2 11
--- v + --- v – ------ = 0 (3)
2 7 7
Solving the quadratic equation, then, we get

2 4 22
v = – --- ± ------ + ------ (4)
7 49 7
We choose the positive solution, because for negative v, i=0 from the device equation.
Approximating the value of the square root as 12.5/7, we get that v=10.5/7 or v=1.5 V.
Plugging in the value of v into equation (1), we get that i=8/7 or approximately i=1.15
A.
c) By KVL, the voltage v1 across the current source is just v1 = v + iR, where v is the
voltage across the nonlinear element, i is the current through the nonlinear element,
and R is the resistance of the resistor in series with the non-linear element (1Ω). Thus,
v1 = 1.5 + 1.15 = 2.65 V.
Problem 5.3:
1 di
a) To find the incremental resistance of the diode, we set ---------- = . Thus,
R inc dv v = VO
qV O
----------
1 q kT
---------- = ------I S e . (5)
R inc kT
We must write this in terms of the operating point current, I, instead of the voltage, VO,
however. Therefore, it is necessary to relate VO to I:
qV O
 ---------
kT
- 
I = I Se – 1 . (6)
 
qV O
----------
kT
At this point, we will approximate equation (6) because e » 1 ; this leaves us with
qV O
----------
kT
I = I Se . (7)
Substituting equation (7) into equation (5), and inverting both sides, we find that
kT
R inc = ------ . (8)
qI
b) To compute the small-signal gain, we redraw the circuit in its 1kΩ

small-signal form: +
+
kT vi vo
vo ------ - kT/qI
qI -
This is a voltage divider, so, ----- = --------------------------------- . (9)
vi kT 3
------ + 1 ×10 Ω
qI
c) To ensure that the attenuation ratio is in the range 0.01 < vo/vi < 0.1, we first make the
approximation that the incremental resistance of the diode is much smaller than 1kΩ, so
that equation (9) reduces to
kT
vo ------
qI
----- = -------------------
3
(10).
vi 1 ×10 Ω
–3
25 ×10  1 
- ------------- (11), and so
Solving for I and substituting kT/q = 25 mV, we get I = -------------------
3 v ⁄ v 
1 ×10 o i
0.25m A < I < 2.5mA .
d) In this model, the voltage across the diode is 0.6 V, and so the voltage across the resistor is
VI - 0.6 V. We can write KVL for the circuit:
3
V I = 1 ×10 I + 0.6 . (12)
Thus, 0.85V < V I < 3.1V .
Problem 5.4:
a) In this model, when -0.5 < vI < 0.5, both diodes act as open circuits, and vO = vI. In addi-
tion, the voltage across a diode can never go above 0.5V, so once one of the diodes turns
on, vO remains constant (note that the diodes cannot be on simultaneously). Thus, the
graph below:
1.5
0.5
Vo
−0.5
−1
−1.5
−2
−3 −2 −1 0 1 2 3
Vi
b) Now, when a diode turns on, there is a resistance in series with it, and vO is no longer a
constant. The series resistance of the diode now acts as a voltage divider with the 10 kΩ
100
resistor. Thus, v O = 0.5 + ( v I – 0.5 ) -----------------------------
4
- , which is graphed below:
1 ×10 + 100
3
1
Vo
−1
−2
−3
−10 −8 −6 −4 −2 0 2 4 6 8 10
Vi

Spring 2001
Handout S01-042
Problem 6.1:
a) What are the intercepts on the axes of the characteristic curves of the circuit constraint
imposed by VS and RL (i.e., the load line)?
After removing the MOSFET, the circuit is shown below. The iDS and vo relationship
of this circuit is the load line, which are the contraints imposed by Vs and RL .
RL
iDS Vs - Vo = i
DS
+ RL
+ V vo
- S
iDS = - vo + Vs = -0.125 v0 + 0.75
- RL RL
y-intercept: 0.75 x-intercept: 6
b) Using graphical techniques, construct a table showing the dependance of vO on vI and

sketch (and dimension to the extent possible) the transfer characteristic (vO vs vI) of
this amplifier.
By superimposing the load line on the transfer curve, we can locate the intersections
which are the iD’s with varying Vgs as inputs.
0.8 - vGS = 5 V
0.7 -
0.6 -
0.5 - 4V
iD (mA)
0.4 -
0.3 - 3V
0.2 - 2V
0.1 -
vGS = 1 V
-
-
-
-
-
-
-
-
-
-
-
-
1 2 3 4 5 6
vGS = 0 V
vDS (volts)
VI (VGS) Vo Vo
-
0 6
6 -
1 5.5 5 -
4 -
2 4.5 3 -
2 -
3 3.5 1 -
2 vi
-
-
4
-
-
-
-
1 2 3 4 5 6
5 0.75
vo
c) Estimate the incremental or small-signal voltage gain ----- of this amplifier at an operat-
vi
ing point defined by VGS = 3 volts.
dv o
Small-signal gain at VGS= 3 is -------- . The slope of the tangent line of the trans-
dv i Vi = 3V
fer function is approximately the average of (3.5-4.5)/1 and (2-3.5)/1 = -1.25
Problem 6.2:
a) Derive an equation which reflects the dependence of vO on vI for vI > 0.
For vI < VT = 1V, the switch is open. vo = Vs = 10V. For vI > VT ,
K
vo = VS - VR = VS - iDRL = Vs - (vI - VT)2 RL
2
= 10 - 0.25(vI - 1)2
b) Sketch and dimension the transfer characteristic vO vs. vI of this amplifier over the
entire region of vI for which the transistor model is valid.
vDS > vGS - vT and vGS > VT

--> vo > vin - 1V and vin > 1V
Vo
-
12 -
10 -
8 -
6 -
4 -
2 -
vi
-
-
-
-
-
-
-
1 2 3 4 5 6 7 8
c) Devise a small-signal model which relates the incremental output voltage vo to the
incremental input voltage vi and determine the value of the transconductance gm at the
operating point defined by VGS = 2V.
diD
= K (VGS - VT) = gm = 0.1mA/V2 (2-1 V ) = 0.1 mA
dvgs V
Small-signal model:
+ +
vI +- vgs gmvgs RL vo
- -
d) What is the small-signal voltage gain of this amplifer around the operating point
defined by VGS = 2V.
vo = -gmvgsRL = - gmvI RL
small signal gain of the stage:

vo
= -gmRL = - (.1mA/V)(5kohm) = - 0.5
vi
Problem 6.3:
a+b)There are four unknowns: ID, VI, VA and VB. We need 4 linearly independent equa-
tions.
ID = K (VI - VB - VT)2 ID = (VS - VA)/R
2
VDS = 6V = VA - VB ID = (VB - 0)/R
Solving this system equations, we get:
VA = 9V VB = 3V ID = 0.6mA VI = 5.7746V
c) Devise a small-signal model for this circuit and label the small-signal input and output
voltages denoted by vi, va, and vb.
+ +
vgs gmvgs
vi + - R va
- +
vb R
- -
d) Use the current-source model shown above to calculate the small signal transconduc-
tance gm (see Section 9.2 of notes: page 323) at the operating point defined in a).
gm = 2 K ID = 1.55 mA/V
va vb
e) Derive expressions for the small-signal voltage gains ----- and ----- . Note that vgs does
vi vi
not equal vi in this circuit. Evaluate these expressions for the transconductance deter-
mined in d) and the indicated resistance value.
vi = vb + vgs vgs = vi - vb
vb = gm vgs R = gmR (vi - vb)
vb gmR
= = 0.886
vi 1 + g mR
gmR
va = -gmvgsR = - gmR(vi-vb) = -gmR (vi - vi )
1 + g mR
va gmR
= -gmR (1 - ) = - 0.886
vi 1 + gmR
Problem 6.4: For each of the four circuits with dependant sources shown below, evaluate the
indicated ratios.
a) + +
vR = 0.5 vi
R1 R2
βvR vO vo = - β vR R2
vi
+ vo - β R2
=
R1 vR β>1 vi 2
- - -
b) i R2 v (v - (- αv) )
i= +
R1 R2
+
R1 - 1
v + αv v
=
α>0 i 1 + 1 + α
- R1 R2 R2
c)
+ +
ii
R0 βii
R2 vO
vi e β>1
R1
- -
i1 + β i1 = e / R1
vi
vi - e = Ro + (β + 1)R1
= i1 ii
R0
vi vo - βR2
vo = - β i1R2 = - βR2 =
Ro + (β + 1)R1 vi Ro + (β + 1)R1
d) io
+
-
+ αv
+ vO
v-
e = −v
vi=0
R
-
e + αe = vo
vo
= R (1 + α)
e = ioR io v = 0V
i
io = 0
+ v = vi
-
+ αv vo = - αv = - αvi
vi + vO
+ v vo
- =-α
vi
- - ιο = 0

Spring 2001
Handout S01-047
Problem 7.1: For each of the three circuits shown below, write a differential equation that
describes the circuit for t > 0, and determine the indicated responses. Assume the switches close
or open at t = 0. Sketch and dimension the responses.
a) The switch closes at t = 0. For t < 0, v = -5 volts. Find i(t) and v(t) for t ≥ 0 .
–6
C = 1µF ( or 10 Farad )
e1
+ +v-
10 volts i R = 1kΩ
-
Here is the sketch of the response, see math on next page.

v(t) i(t)
10 15
5 10
v (volts)
i (mA)
0 5
−5 0
0 2 4 6 8 0 2 4 6 8
t (sec) x 10
−3 t (sec) −3
x 10
Nodal analysis for the circuit for t ≥ 0 . Then solve the resulting differential equations.
0 – e1 plugging in: e 1 = 10 – v
-------------- + i c = 0
R
dv
v – 10 dv and i c = C ------
-------------- + C ------ = 0 dt
R dt
dv
v + RC ------ = 10 v ( t ) = vh ( t ) + v p ( t )
dt
dv h ( t )
v h ( t ) + RC --------------- = 0 v p ( t ) = 10
dt
–t
-------- –3
v h ( t ) = Ae
RC
RC = ( 1k ) ( 1uF ) = 10
–t
---------
- – +
v(0 ) = v(0 ) = – 5 = A + 10
–3
10
v ( t ) = v h ( t ) + v p ( t ) = Ae + 10
–t
---------
–3
- A = – 15
10
v ( t ) = – 15e + 10 volts
–t –t
---------
–3
- ---------
–3
-
dv –6 3 10 10
i ( t ) = C ------ = 10 ( – 15 ) ( – 10 )e = 15e milliAmperes
dt
b) The switch closes at t = 0. For t < 0, v = 0. Find i(t) and v(t) for t ≥ 0 .
R1
C = 1µF
i R 1 = 3kΩ
+
+ R 2 = 6kΩ
10 volts R2 v
- C -
v(t) i(t)
7 3.5
6
3
2.5
4
v (volts)
i (mA)
3
2
1.5
1
0 1
0 0.005 0.01 0 0.005 0.01
t (sec) t (sec)
v – 10 v – 0 dv
-------------- + ----------- + i c = 0 i c = C ------
R1 R2 dt
v – 10 v dv
-------------- + ------ + C ------ = 0
R1 R2 dt
v  ------ + ------ + C ------ = ------

1 1 dv 10
 R 1 R 2 dt R1
R1 R2 10R 2
v +  ------------------ C ------ = ------------------
dv
 R 1 + R 2 dt R1 + R2 v ( t ) = vh ( t ) + v p ( t )
–t 10R 2
v h ( t ) = Ae
-----
τ
R1 R2
τ = ------------------C = 2x10
–3 v p ( t ) = -------------------
R1 + R2 R1 + R2
–0
------ 10R 2 10R 2
τ
v( 0– ) = v( 0 + ) = Ae + ------------------ = 0 A = – ------------------
R1 + R2 R1 + R2
t t
– --
20  – --
v ( t ) =  – ------ e
20 τ 20 τ
+ ------ = ------  1 – e  volts
 3 3 3 
t t
10 – v 10 20 20 – -τ- – --
τ
i ( t ) = -------------- = ------ – --------- + --------- e = 1.11 + 2.22e milliAmperes
R1 R 1 3R 1 3R 1
c) The switch opens at t = 0. For t < 0, i =+3 amperes. Find i(t) and v(t) for t ≥ 0 .
+
L = 0.1Henry
2A R i L v
R = 1kΩ
-
di 1
v–0
2 + ----------- + i = 0 v = L ----- i = --- ∫ v dv + const
R dt L
v 1
2 + --- + --- ∫ v dv + const = 0
R L
1 dv 1
--- ------ + --- v = 0
R dt L
L dv v ( t ) = vh ( t ) + v p ( t )
--- ------ + v = 0
R dt
– t  ---
R
 L
v h ( t ) = Ae v p(t ) = 0 v ( t = 0 ) = – 5000v
t
– t  ---
R – ---------
-
 L 10
–4
v ( t ) = – 5000e = – 5000e volts
1
i ( t ) = --- ∫ v dv + const
L
 R  R
1 L   L 
– t --- – t ---
 L
i ( t ) = ---  – ---  – 5000e  + const = 5e
L  R  
– 0  ---
R
 L
i ( t = 0 ) = 3 = 5e + const const = – 2
t
– ---------
–4
-
10
i ( t ) = 5e –2
v(t) i(t)
0 3
−500 2.5
−1000 2
−1500 1.5
−2000 1
v (volts)
i (A)
−2500 0.5
−3000 0
−3500 −0.5
−4000 −1
−4500 −1.5
−5000 −2
0 2 4 6 8 0 2 4 6 8
t (sec) −4
x 10 t (sec) −4
x 10
Problem 7.2: The circuit of a NOT gate that provides one input to a pair of NAND gates is
shown below:
VS = +5 V D
R = 20 kΩ R ON = 100Ω
R R R R C = 10 –11 F
G
V T = 2 volts
+
v
+ C
A -o RON
+ VGS
v1 B C
S + -
- v2 S
-
Switch is open when VGS < VT
Switch is closed when VGS > VT
Represent the FETs by the switch-resistor model with the
gate-to-source capacitance included (at right).
a) Draw a diagram for this circuit with the FETs replaced by the model.
VS = +5 V
R R R R R = 20 kΩ
R ON = 100Ω
+ C = 10 –11 F
RON C R C v
ON -o
C RON C RON C RON
b) Write a differential equation that describes v1(t) when the switch S is open.
v1 – 5 dv 1
- + C -------- = 0
-------------
R dt
dv 1
v 1 + RC -------- = 5
dt
c) Find the solution for this equation that applies when the switch S changes instanta-
neously (at t=0). Sketch and dimension this response.
v ( t ) = vh ( t ) + v p ( t ) v(t)
–t
--------
RC
v h ( t ) = Ae v p(t ) = 5 5
– +
v(0 ) = v(0 ) = 0 = A+5 A = –5
t t
 – --------
RC  – ----------------
2x10 
–7
v(t ) = 51 – e  = 51 – e  volts
   
τ=2x10-7 t
d) What is the time delay ∆t before transistor A turns on?
∆t
 – ----------------
2x10 
–7
v ( ∆t ) = V T = 2v = 5  1 – e 
 
∆t = – 2x10 ln  1 – --- = 1.02x10 seconds

–7 2 –7
 5
e) Write a differential equation that describes v2(t), t > 0, once the switch in the model of
transistor A closes. Make reasonable approximations!
Since RON << R we can approximate the circuit as having only having RON and 2 x C.
v2 dv 2
- + 2C -------- = 0
---------
R ON dt
dv 2
v 2 + 2CR ON -------- = 0
dt
f) Find the solution to this equation that applies when transistor A switches from OFF
(output high) to ON (output low). Sketch and dimension the response of v2(t).
v 2 ( t ) = v 2h ( t ) + v 2 p ( t ) v2(t)
t 5
– -----------------
2CR ON
v 2h ( t ) = Ae v2 p ( t ) = 0
(t = 0)
– -----------------
2CR ON
v 2 ( t = 0 ) = Ae = A = 5
t t
– ----------------- – ----------------
–9
2CR ON 2x10
v ( t ) = 5e = 5e τ=2x10-9 t
g) What is the total time delay before transistors B and C turn off?
t
– ----------------
–9
2x10
v ( t ) = 5e = 2
t = – 2x10 ln  --- = 1.832x10

–9 2 –9
 5
–7
t total = t + ∆t = 1.04x10 seconds
h) Finally! assume switch S closes instantaneously at t′ = 0 . What is the time delay,

∆t′ , before transistors B and C turn on?
Because the gate of Mosfet A is shorted to ground, it turns off instantaneously. Therefore
we only have to do the time constant for node of the gates of Mosfets B and C.
v2 – 5 dv 2
- + 2C -------- = 0
-------------
R dt
dv 2
v 2 + 2RC -------- = 5
dt
t' t'
 – -----------
2RC  4x10 
– ----------------
–7
v 2 ( t' ) = 5  1 – e  = 51 – e 
   
∆t'
 – ----------------
4x10 
–7
v 2 ( ∆t' ) = 5  1 – e  = 2
 
∆t' = – 4x10 ln  1 – --- = 2.04x10

–7 2 –7
 5 
Problem 7.3: An RL circuit is shown below:
R1
+
+
vs(t) = Vs u-1(t) R2 v
- L
-
 0, t < 0
The source is a step of magnitude Vs. That is: v s ( t ) = 
Vs, t ≥ 0
The current in the inductor is zero for t < 0.
a) Write a differential equation for v(t) and solve it for t > 0. Sketch and dimension your
result.
V s – v(t ) v(t ) di L ( t )
- = --------- + i L ( t )
-------------------- v ( t ) = L --------------
R1 R2 dt
V s R2 = v ( t ) ( R1 + R2 ) + R1 R2 iL ( t )
V R 1 + R 2 di L ( t )
------s = L  ------------------ -------------- + i L ( t )
R1  R 1 R 2  dt V
i p ( t ) = ------s
R1
iL ( t ) = ih ( t ) + i p ( t )
R1 + R2
i h ( t ) = Ae –t / τ τ = L  ------------------
 R1 R2 
V V
iL ( 0– ) = iL ( 0 + ) = 0 = A + ------s A = – ------s
R1 R1
Vs
i L ( t ≥ 0 ) = ------ ( 1 – e –t / τ ) v(t)
R1 R2
Vs -------------------
di L ( t ) R1 + R2
v ( t ) = L --------------
dt
R2
v ( t ≥ 0 ) = V s ------------------e –t / τ
R1 + R2
t
τ=L(R1+R2)/(R1R2)
b) The input is changed to an impulse of magnitude (area) Λ . That is:
vs(t) = Λ u0(t)
Without solving the differential equation again, derive an expression for v(t) for t > 0.
input:
t
Λ d ( V s u –1 ( t ) )
Λu 0 ( t ) = ------ -----------------------------
Vs dt
output:
Λ dv old ( t ) R2 2R
v new ( t ) = ------ ------------------- = – Λ  ------------------ ------ e –t / τ
1
V s dt  R 1 + R 2 L R2 2R
– Λ  ------------------- ------
1
 R 1 + R 2 L
vnew(t)
c) The input is changed to a ramp of magnitude (slope) M. That is:

vs
slope = M
vs(t) = M u-2(t)
0 t
Without solving the differential equations again, derive an expression for v(t) for t > 0.
input: vnew(t)
M
Mu –2 ( t ) = ----- ∫ V s u –1 ( t ) dt
L
M ------
Vs R1
output:
M L
v new ( t ) = ------ ∫ v old ( t ) dt = M ------ ( 1 – e –t / τ )
Vs R1
t
vs(t)
Vb
d) The input is changed to that shown below:
Va
0 τ t
Show that this input can be decomposed into two ramps and two steps.
(V b – V a)
v s ( t ) = V a u –1 ( t ) – V b u –1 ( t – τ ) + ------------------------ ( u –2 ( t ) – u –2 ( t – τ ) )
τ
e) Using your results from a) and c) above, by superposing reponse to step and ramp
inputs, derive an expression for v(t) for t > 0.
(t – τ) (t – τ)
 R2     L  ( V b – V a )  –t / τ – --------------
–e τ 
– --------------- -
v ( t ) = ------------------ V a e – t / τ – V be τ – ------ ------------------------ e
 R 1 + R 2    R 1 τ  

Spring 2001
Homework #8 - Solutions
Handout S01-53
Problem 8.1:
Volts Amps Volts Amps

CIRCUIT v(0+) i(0+) v( ∞ ) i (∞ )
A 0 V/R V 0
B λ/RC -λ/R2C 0 0
C Q/C 0 Q/C 0
D IR 0 0 I
E 0 λ/L 0 λ/L
F -QR2/L QR/L 0 0
Problem 8.2:
R1 +v -
C
Vs(t) + L i R2 is(t) R1 R2
-
Circuit A Circuit B
a) Since an impulse is the derivative of a step, the impulse response will be the derivative
of the step response.
t t L ( R1 + R2 )
 – -- – -- where τ = --------------------------
-
d λ τ λ τ R1 R2
i(t ) = ------ 1 – e = ---------e
d t R1   R1 τ
 
Parts b) and c) will use this same time constant.
1
t i(t)
λR 2 – --
τ
i ( t ) = --------------------------- e λ R2
L ( R1 + R2 ) --------------------------
-
L ( R1 + R2 )
0
t
b) The response due to the initial condition is added to the result found in part a).
t t i(t)
λR 2 – -- – --
τ τ
i ( t ) = --------------------------- e + ( – I )e
L ( R1 + R2 )
λ R2
--------------------------
-–I
t L ( R1 + R2 )
– --
λR τ
i ( t ) =  --------------------------
2
- – I e t
 L ( R1 + R2 )  0
t i(t)
 – --
V τ
c) i ( t ) = ------ 1 – e V
R1   ------
  R1
0
t
d) The voltage v immediately after the step is still -V.

After a long time the capacitor looks like an open, so the voltage v is the voltage across
R1 which is -IR1.
The time constant is τ = C(R1 + R2). This is the same time constant used in part e).
t
– -- t
τ –V
v ( t ) = – I R 1 + ( I R 1 – V )e
– IR
v(t)
2
e) Since a ramp is the integral of a step, the ramp response will be the integral of the step
response. Note that this does not apply to the response due to the initial condition on
the capacitor. We will first find the response due only to the ramp, setting the initial
condition to zero (ZSR: Zero State Response). Then we will find the response due only
to the initial condition, setting the input to zero (ZIR: Zero Input Response). The solu-
tion will be the sum of these two responses.
ZSR
t t
 – --
τ
– --
τ
v ( t ) = ∫ – M R 1  1 – e  dt = – M R 1 t – M R 1 τe + k
 
For the ZSR, v(0) = 0. We will use this to find the constant of integration, k.
v ( 0 ) = – M R1 τ + k = 0 ⇒ k = M R1 τ
t
– --
τ
v ( t ) = – M R 1 t – M R 1 τe + M R1 τ
ZIR
t
– --
τ
vt ) = – V e
Total
t
– --
τ
v ( t ) = – M R 1 t – ( M R 1 τ + V )e + M R1 τ
t
–V
– M R1
v(t)
3
Problem 8.3: The voltage source drives each branch independantly, so we can solve for v1(t) and
v2(t) separately.
.
i(t)
i1(t) i2(t)
C L
+ v(t) -
+ v1(t) v2(t)
-
V u-1(t)
R R
L
τ = --- = RC
R
t t t
– --  – --  – -τ- 
v ( t ) = v1 ( t ) – v2 ( t ) = V e
τ
– V 1 – e 
τ
⇒ v ( t ) = V  2e – 1
   
t t
v1 ( t ) v2 ( t ) 1  – -τ-  – -- 
i ( t ) = i 1 ( t ) + i 2 ( t ) = -----------
τ
- + ------------ = ---  V e + V  1 – e  
R
⇒ i(t ) V
= ----
R R   R
v(t) i(t)
V V
----
R
–V
0
t 0
t
Problem 8.4:
a) +
vgs gmvgs +
vi + - ib C va
- R
+ -
R C vb
-
4
b) vb(0) = va(0) = 0.
After a long time the capacitors reach steady state and act like open circuits. Following
are the steady state values of va and vb (using gm = 1.55 mA/V as found in Problem
6.3)
Rg m v
v b = Rg m v gs = Rg m ( v – v b ) ⇒ v b = ------------------- = 0.886v
1 + Rg m
v a = – v b = – 0.886 v
Now let’s find the time constant for vb by finding the equivalent resistance seen from
the terminals of the capacitor at vb. First set vi to zero.
v b = R [ i b + g m ( 0 – v b ) ] ⇒ v b ( 1 + g m R ) = Ri b
v R
----b- = R THb = ------------------- = 0.57Ω
ib 1 + Rg m
τ = CR THb = 0.57C
We now have all the information we need to solve for vb.
t vb(t)
 – --
τ
v b = 0.866v  1 – e 
  0.866v
0
t
Notice that the current through the RC pair associated with vb is the same as the cur-
rent through the RC pair associated with va. Noting the polarity difference we can see
that va= -vb.
t
 – --
τ t
v a = – 0.866 v  1 – e 
 
– 0.866 v
va(t)
c) This question should be deleted. The time constants are equivalent.
5
d) The maximum value of v is determined by the saturation conditions.
v DS ≥ v GS – V T
v A – v B ≥ v I – v B – V T The vB’s cancel.
V A + va ≥ V I + vi – V T
From Problem 6.3, VA = 9V, VI = 5.77V, VT = 2V.
9 + v a ≥ 5.77 + v – 2
5.23 ≥ v – v a = v + 0.886v = 1.886v
v ≤ 2.773V
e) For t < T, the capacitors get charged and vb (T) = 0.886v = 0.886(2.77V) = 2.45 V.
-> vB(T) = VB(T) + vb(T) = 3V + 2.45 V = 5.45 V.
Immediately after t = T, vB(T+) = 5.4 V.
At this time vi = 0 so vI = VI = 5.77 V.
So VGS = VI - VB = 5.77 V - 5.4 V = 0.33 V just after t= T.
This clearly does not satisfy the saturation condition that VGS > VT so the MOSFET
does not conduct and the small signal voltages for each capacitor simply discharges
through the associated resistor.
Note that the solution does not depend on the value of the capacitor, as mentioned in
the problem statement.
t′ t′
– ---
τ
– ---
τ τ = RC
v a ( t′ ) = – 2.45e v b ( t′ ) = 2.45e
t vb(t)
2.45volts
– 2.45 volts
va(t)
0
t
6

Spring 2001
Handout S01-058
Issued: 4/12/2001
Problem 9.1: A transistor amplifier is shown to the right. The input voltage is
v I = V I + v i cos ωt , where VI is set to an operating point in the active region, and vi is the ampli-
jωt
tude of a small signal. v o = Re { V o e }
a) Sketch a small-signal circuit and label all elements of R = 5 kΩ

the model. Assume gm = 10-2 Ω-1.
+
b) Evaluate vo and φο as functions of ω. vi vo
gm v i
-
– jω LRgm Vi
V o = – ( jω L || R ) ⋅ I d = -----------------------------
-
jω L + R L = 10 mH
gm RLωv i
φ o = atan  --------
R
vo = V -----o- v i = -------------------------------
Vi 2 2  ω L
R + ( ωL )
Vo – jω gm R
c) A ( ω ) = ------ = --------------------
-
Vi R
--- + jω
L
R
d) What is the high-frequency ( ω » --- ) asymptote of A ( ω ) ? A H = – gm R .
L
e) Sketch and diagram a Bode diagram for A ( ω ) . That is, plot

i) log A ( ω ) vs. log ω , and
ii) ∠ A ( ω ) vs. log ω , where ∠ A ( ω ) denotes the phase angle of A ( ω ) .
Bode Diagrams
1.5
1
Phase (deg); Magnitude (Log)
0.5
−80
−100
−120
−140
−160
−180
4 5 6 7
10 10 10 10
Frequency (rad/sec)
Problem 9.2: A circuit which involves an ideal diode as

well as an inductor and capacitor is shown below. The iL L = 1 mH
circuit is at rest for t < 0. +
Vu-1(t) +
vc
a) What are the values of iL(0+) and vc(0+)? -
C = 10µF
-
iL(0+) = 0 (initially the inductor is an open circuit)
vC(0+) = 0 (initially the capacitor is a closed circuit)
b) What is the state of the diode at t = 0+ (i.e., is it a short or an open)?
The voltage drops across the inductor, leaving the voltage across the diode zero. For the ideal
diode, this is the short, closed, forward-biased, or active state.
c) Write differential equations for iL(t) and vc(t) with the diode closed (i.e., active).
1 d d
iL(t ) = iC(t ) --- ∫ v L = C v C ∫ V – ∫ vC = LC v C
L dt dt
2
d
V u –1 = v C + LC v
2 C
dt
2
1 di di
V u –1 = v C + v L = ---- ∫ i + L CV u 0 = i + LC 2
C dt dt
d) Determine iL(t) and vc(t).
We’ll solve vc(t) and then use the constituent relationship to find iC(t) = iL(t).
General solution with homogenous solution and particular integral:
–s1 t –s2 t
vc ( t ) = K 1 e + K 2e +V
1
Characteristic equation: LCs2+1 = 0 gives s 1, s 2 = ± j ------- = ± jω o
LC
From initial conditions:
vC(t=0) = 0 = K1 + K2 + V
d
i ( t ) = C v C = – Cs 1 K 1 – Cs 2 K 2 = 0 gives K1 = -V/2 and K2 = -V/2
dt
Solution:
– jt jt
------------ ------------
V LC V LC
v c ( t ) = V – ---- e – ---- e = V – V cos ( ω o t )
2 2
i ( t ) = VCω o sin ( ω o t )
e) Find the time t1 at which the diode opens.

The ideal diode can not have a negative current, but i(t) goes both positive and negative in the
equation above. In this case, the ideal diode allows the current to pass to the capacitor but
stops the inductor from pulling the current back. The first time the current i(t) goes from posi-
π
tive to negative is when ω o t = π ∴t 1 = ------
ωo
f) What are the values of iL(t) and vc(t) for t > t1?
After t1, i(t) = 0 and vC(t) = 2V.
Problem 9.3: The circuits below are driven by sinusoids and are in the sinusoidal steady-state.
V
In each case determine the complex input impedance Z ( s ) = -----i and the indicated voltage trans-
Ii
V
fer ratio A ( s ) = -----o- . Express each function as a ratio of polynomials in s.
Vi
1 sRC + 1
V i = Z ( s )I i Z a ( s ) = R + ------ = --------------------
sC sC
a) V R s
A a = -----o- = ----------------- = -----------------
Vi 1 1
R + ------ s + --------
sC RC
1 sR 1 R 2 C + R 1 + R 2
Z b ( s ) = R 2 || ------ + R 1 = --------------------------------------------
-
sC sR 2 C + 1
1
b) R 2 || ------ R2
sC
A b ( s ) = ------------------------------- = --------------------------------------------
-
1 sR R C + R + R
R 2 || ------ + R 1 1 2 1 2
sC
2
1 1 s R1 R2 C 1 C 2 + s ( R1 C 1 + R2 C 1 + R2 C 2 ) + 1
Z c ( s ) = R 2 || --------- + R 1 + --------- = ----------------------------------------------------------------------------------------------------------
-
sC 2 sC 1 2
s R C C + sC 1 1 2 1
c) 1
R 2 || ---------
sC 2 sR 2 C 1
A c ( s ) = ------------------------------------------------
- = ----------------------------------------------------------------------------------------------------------
2
-
1 1 ( )
R 2 || --------- + R 1 + --------- s R R
1 2 1 2 C C + s R 1 1C + R C
2 1 + R 2 2C + 1
sC 2 sC 1
Problem 9.4: For each of the transfer functions shown below, sketch and dimension Bode dia-
grams showing log A and ∠ A vs. log ω . In each case, s = jω.
a)
Bode Diagrams for 9.4a
1.5
1
Phase (deg); Magnitude (log)
0.5
100
80
60
40
20
0
0 1 2 3
10 10 10 10
Frequency (rad/sec)
Bode Diagrams for 9.4b
−2.5
−3
−3.5
−4
−20
−40
−60
−80
−100
4 5 6
10 10 10
Frequency (rad/sec)
Bode Diagrams for 9.4c
−2.5
−3
−3.5
−4
100
50
−50
−100
0 1 2 3 4 5 6
10 10 10 10 10 10 10
Frequency (rad/sec)

Spring 2001

Handout S01-063
Problem 10.1: Each of the circuits shown below is in the sinusoidal steady state. In each case,
determine Z(s), the input impedance, and A(s), the voltage transfer ratio. Represent the imped-
ances of resistors, capacitors and inductors by R, 1/Cs and Ls, respectively, and clear your expres-
sions of fractions, representing each as a ratio of polynomials.
For each circuit:

Vi Vo
Z(s) = A(s) =
Ii Vi
V and I denote complex amplitudes and Z is an input impedance.

a) In the frequency domain, the circuit elements may be represented by their impedances.
Ii R
+ +
1
-------
Vi SC Vo
- -
For impedances in series,

1 SRC + 1
Z ( S ) = R + ------- = --------------------
SC SC
Solve for A(s) using the voltage divider property
Vo
A ( S ) = -------
Vi
This gives
1
-------
SC Vo 1
Vo = -----------------Vi A ( S ) = ------- = --------------------
1 Vi 1 + RCS
------- + R
SC
b)
Ii R
+
+
Vi 1 Vo
------- SL
SC
- -
Z ( S ) = R +  ------- || LS
1
 SC 
Which simplifies to
LS R + LCS 2 + LS
Z ( S ) = R + ----------------------- = -------------------------------------
1 + LCS 2 1 + LCS 2
Again, noting that the voltage Vo is the voltage drop across the parallel impedance
1
------- || LS
Vo SC
------- = ----------------------------------- = A ( S )
Vi
R +  ------- || LS
1
 SC 
Simplification gives
LS
A ( S ) = -----------------------------------------
R + RLCS 2 + LS
c)
1
----------
Ii R1 SC 1
+
+
1
Vi R2 ----------
SC 2
Vo
- -
Z C2 Z
R2
Z = Z R1 + Z C1 + ----------------------------
Z R2 + Z C2
2
R2 R1 R2 C 1 C 2 S + R1 C 1 S + R2 C 2 S + R2 C 1 S + 1
1
Z = R 1 + ---------- + --------------------------- = -----------------------------------------------------------------------------------------------------------------------
SC 1 SR 2 C + 1 2
2 R 2 C 1 C 2 S + SC 1
Note that Vo is the voltage drop across the parallel impedance defined by
1 R2
R 2 || ---------- = ---------------------------
SC 2 SR C + 1
2 2
so that
R2
---------------------------
Vo SC 2 R 2 + 1
------- = ---------------------------
Vi Z
R 2  R 2 C 2 C 1 S + SC 1
2
  Vo
A ( S ) = ------------------------------------------------------------------------------------------------------------------------------------------------------------- = -------
Vi
( SC 2 R 2 + 1 )  R 1 R 2 C 1 C 2 S + R 1 C 1 S + R 2 C 2 S + R 2 C 1 S + 1
2
 
Problem 10.2: A linear circuit has a voltage transfer ratio of the form:
+ + K = 103
s
Vi Linear Vo A(s) =K
Circuit
s + s1 s = 102 sec-1
- -
a) Let s = jω. Express A(jω) in polar form. That is, find A(jω) and A(jω)
such that:
A(jω) = A(jω) e j A(jω)
Solution:
jω jξ
A ( jω ) = K ------------------- = A ( jω ) e
jω + S 1
Kω π ω π ω
where A ( jω ) = --------------------------- and ∠ A ( jω ) = ξ =  --- – arc tan ------ = --- – arc tan ---------
2 2 2 S 1 2 100
ω + S1
π ω
j  --- – arc tan ---------
1000Kω 2 100
A ( jω ) = --------------------------- e
2 4
ω + 10
b) The input voltage vi(t) for which Vi is the complex amplitude is, in the sinusoidal-
steady-state, of the form:
vi(t) = |Vi| cos(ωt + θ)
such that Vi = Vejθ (V is a real number). The output voltage vo(t) for which Vo is the
complex amplitude is, in the sinusoidal-steady-state, of the form:
vo(t) = |Vo(ω)| cos(ωt + φ(ω)).
Find expressions for Vo(ω), |Vo(ω)| , and φ(ω ).
Solution:
v O ( t ) = A ( jω ) v i ( t )
 j ( ωt + θ ) 
where v i = Vi cos ( ωt + θ ) = Re  Vie 
 
 jξ j ( ωt + θ )  KVω  j ( ωt + ξ + θ ) 
v O(t ) = Re  A ( jω ) e Vi e  = --------------------------- Re  e
2 

  2
ω + S1 
KVω
= --------------------------- cos ( ωt + ξ + θ )
2 2
ω + S1
= Vo ( jω ) cos ( ωt + φ ( ω ) ) given
then from the calculated value for vO(t)

KVω
Vo ( jω ) = ---------------------------
2 2
ω + S1
π ω
φ ( ω ) = ( ξ + θ ) =  θ + --- – arc tan ---------
 2 100
π ω
j  θ + --- – arc tan ---------
jφ ( ω ) 1000KVω  2 100
Vo ( ω ) = Vo ( jω ) e = --------------------------- e
2 4
ω + 10
Problem 10.3: For an appropriate set of circuit parameters, the voltage transfer ratio of the cir-
s
cuit of part (c) of Problem 10.1 can be expressed as A ( s ) = K ------------------------------------- , where s 1 = 10
( s + s1 ) ( s + s2 )
4 4
sec-1, s 2 = 10 sec-1, and K = 0.2 × 10 .
a) Let s = jω. Εxpress A(jω) in polar form.
Solution:
jω
A ( jω ) = K -------------------------------------------------
( jω + S 1 ) ( jω + S 2 )
Kω
A ( jω ) = ------------------------------------------------------------------
 ω 2 + S1 2  ω 2 + S2 2 (1)
  
π ω ω
∠ A ( jω ) =  --- – atan  ------ – atan  ------ 
2 S  S 
1 2
π ω  ω 
j  --- – atan  ------ – atan  --------- 
3 2  10  10 4 
2x10 ω
A ( jω ) = ----------------------------------------------------------------- e
 ω 2 + 10 2  ω 2 + 10 8
  
Note from the expressions for A(s) and A(jω), poles exist at ω=S1 and ω=S2.
b) There is a range of frequencies for which A ( jω ) ≈ B ⋅ j ω , where B is a constant.

What is B and what is the range of frequencies for which this approximation applies?
Solution:
A ( jω ) = B ( jω )
A ( jω ) = Bω
log A ( jω ) = log ( B ) + log ( ω ) (2)
log |A| increases with log(ω) with an intercept at log(B) when log(ω) = 0 and a slope of
+1. This indicates that the relevant values of ω are increasing from 0 through to the first
pole S1.
Taking the log of equation (1) gives

2 2 8
log A = log ( 2000 ) + log ( ω ) – log ω + 100 – log ω + 10 (3)
for ω < 10 sec-1
log A = ( 3.3 + log ( ω ) – 1.15 – 4 )
or
log A = – 1.85 + log ( ω )
Using the above equation and equation (2) we obtain
log B = – 1.85 or B = 1.4x10-2
The range of frequencies is 0 ≤ ω ≤ 10 sec-1

log |A|
- 0.7
Slope ≅ 1
-1.85
log (ω)|
1
D
c) There is a range of frequencies for which A ( jω ) ≈ ------ , where D is a constant. What is
jω
D and what is the range of frequencies for which this approximation applies?
Solution:
D
A ( jω ) = ------
jω
D
A ( jω ) = ----
ω
log A ( jω ) = ( log D – log ( ω ) )
Using equation (3) for w>S2=104 sec-1 we obtain

log ( ω ) – log A = 5.15
log D = 5.15
5
D = 1.4x10
log |A|
- 0.7
Slope ≅ – 1
log (ω)|
4 5.15
4
The range of frequencies is 10 ≤ ω
d) There is a range of frequencies for which A ( jω ) ≈ F , where F is a constant. What is

B and what is the range of frequencies for which this approximation applies?
Solution:
A ( jω ) = F
and log A ( jω ) = log F
Using equation (3) for the frequency range 10 ≤ ω ≤ 10 4sec-1
log A = ( 3.3 + 2 – 2 – 4 ) = – 0.7

log |A|
log A = ( 3.3 + 3 – 3 – 4 ) = – 0.7
F = 0.2
- 0.7
log (ω)|
1 4
e) Sketch a Bode plot showing the frequency dependence of A ( jω ) and ∠ A ( jω ) .
That is, plot log 10 A ( jω ) versus log 10ω and ∠ A ( jω ) versus log 10ω for
6
1 ≤ ω ≤ 10 sec-1. Label all slopes and intercepts.
We can put the plots from parts b) through d) together to obtain the Bode plot
log |A|
∠ A ( jω )
- 0.7 π/2
π/4
-1.85 S2
S1 log (ω)
log (ω)|
1 4
−π/2
Note that this circuit is a bandpass filter.
Problem 10.4: The voltage transfer ratio of the circuit of part (b) of Problem 10.1 can be
expressed as follows: V 2αs .
A ( s ) = -----o- = ---------------------------------
2
-
2
Vi s + 2αs + ω 0
a) Express α and ω0 in terms of the circuit parameters R, L, and C.
From the circuit, A(s) may be re-expressed in the form

S
--------
RC
A ( S ) = -----------------------------------
2 S 1
S + -------- + -------
RC LC
We can now compare A(s) directly with the equation give above and we see that
S 1
2αS = -------- or α = ----------
-
RC 2RC
1
2 1
ωo = ------- or ω 0 = ------------
LC LC
b) Let s = jω. Express A(jω) in polar form, using the parameters α and ω0.
2 jαω
A ( jω ) = -------------------------------------------------
2 2
2 jαω + ( ωo – ω )
jθ
A ( jω ) = A ( jω ) e
 2 2
ωo – ω 
j  atan ------------------------
2α  2αω 
= ---------------------------------------------------------- e
2 2 2
2  ωo – ω 
( 2α ) +  ------------------------
 ω 
c) Assume that α << ωo (light damping), sketch a Bode plot showing the frequency
dependence of A(jω); that is, plot log 10 A ( jω ) and ∠ A ( jω ) versus log 10ω for
–2 2
10 ω 0 ≤ ω ≤ 10 ω 0 . Define the slopes and intercepts of the low-frequency and high-
frequency asymptotes. Mark the frequency for which A(jω) is a maximum and find the
value of A(jω) at that maximum.
For α << ωo,
2α
A ( jω ) = -----------------------------
 ωo 2 – ω 2
 ------------------------
 ω 
For ω=10-2 ωo and ω=102 ωo, the denominator has a value of 104ωo2
For ω=10-1 ωo and ω=101 ωo, the denominator has a value of 98.01ωo2
For ω=10-1/2 ωo and ω=101/2 ωo, the denominator has a value of 65.61ωo2
2α
For ω=ωo, |A(jω)|= ------------------
-= 1
2
( 2α )
log |A|
-2 -1 1 2
log (ω)|
-5
-6
-7
∠ A ( jω )
π/2
-2 -1 1 2
log (ω)|
- π/2
ω=ω0
6.002 { Circuits and Electronics
Spring 2001
Handout S01-072
Introduction
This homework assignment focuses on the analysis and design of a system for playing back a
digitally-stored audio signal. Additionally, this assignment serves as the pre-lab exercises for
Lab #4, which will involve the construction, testing and demonstration of the audio playback
system. Consequently, you should save a copy of your results for use during Lab #4.
A block diagram of the audio playback system is shown in Figure 1. At the center of the system
is a digital memory in which 32,768 samples of the audio signal are stored. Each sample in the
memory has a unique numerical address between 0 and 32,767, inclusive. Consecutive samples are
stored at consecutive addresses.
To obtain 32,768 consecutive samples of the audio signal, 4.096 seconds of continuous analog
audio signal are rst sampled at an 8-kHz rate. The analog audio samples are then digitized by an
8-bit analog-to-digital converter. That is, the samples are quantized to take on one of 256 possible
discrete digital values between 0 and 255, inclusive. Here, the digital value of 0 corresponds to the
most positive signal voltage, and the digital value of 255 corresponds to the most negative signal
voltage. The resulting digital data is then written into the memory.
To retrieve the stored audio signal samples in sequence at the proper rate, the memory is
addressed by a counter which counts from 0 to 32,767 at an 8-kHz rate established by an external
clock. After counting to 32,767 the counter returns to 0, and the retrieval process repeats itself.
As the memory address increments, the corresponding data appears at the memory output. This
data is converted back to an analog voltage in a piecewise constant manner by a digital-to-analog
converter.
During the course of recording and playing back the analog audio signal, the signal is sampled
in time, quantized in amplitude, and reconstructed in a piecewise constant manner. As you will
Headphone
D/A Low-
Clock Counter Memory Pass Volume
Converter Control
Filter
Figure 1: block diagram of the audio playback system.

learn in 6.003, this process introduces undesirable high-frequency components into the signal. To
minimize the perceived impact of these components, the signal is ltered by a low-pass lter after it
is reconstructed by the digital-to-analog converter. Finally, the signal is fed into a volume control
stage which in turn drives a headphone.
In the course of this homework assignment you will analyze and design four of the functional
blocks shown in Figure 1. These blocks are the clock, the digital-to-analog converter, the low-pass
lter and the volume control. In Lab #4, you will construct these blocks and verify that they
perform as desired. Then, you will combine them with the counter, the read-only memory and
the headphone to construct and demonstrate the entire audio play-back system. Since you will
construct the system from the components in your 6.002 lab kit, your design of the blocks must
account for the fact that the available components are limited.
Problem 1: The Clock

The circuit shown in Figure 2 is the system clock, which is a square-wave oscillator followed by a
CMOS inverter; the inverter functions only as a buer. The oscillator is constructed from another
CMOS inverter, a resistor and a capacitor. Both inverters are powered between the positive supply
voltage VS and ground, and both exhibit the hysteretic input-output characteristic dened in the
gure. The inverters are otherwise ideal.
R
IN OUT
+
+
vCAP C + vCLK vOUT
- vOSC
- -
VS
vIN
VL VH VS
Figure 2: the system clock.

(A) Assume that vCAP has just charged up to VH so that vOSC has just switched to 0 V. How much
time elapses before vCAP decays to VL , which in turn causes vOSC to switch to VS ?
ANSWER: As shown in the gure below, the capacitor now begins to discharge from VH
toward zero. This is a ZIR problem and the capacitor voltage is given by
vCAP = VH e t=RC
We want to solve for the time at which vCAP = VL . This time is denoted by T2 in the gure.
VL = VH e T2 =RC
Solve to get:
V
T2 = RC ln H
VL
vOSC
VS
VH
vCAP
VL
-
0
T1 T2
(B) Assume that vCAP has just decayed to VL so that vOSC has just switched to VS . How much
time elapses before vCAP charges up to VH , which in turn causes vOSC to switch to 0 V?
ANSWER: Now the capacitor starts to charge from VL toward VS . The solution for the
capacitor voltage contains both ZIR and ZSR:
vCAP = VS + (VL VS ) e t=RC
We want to solve for the time at which vCAP reaches VH . This time is denoted by T1 in the
gure.
VH = VS + (VL VS ) e T1 =RC
Solve to get
V VL
T1 = RC ln S
V V S H
(C) Determine the frequency of the oscillator in terms of R, C , VL , VH and VS .
ANSWER: The period T of the oscillator is
T = T1 + T2 = RC ln S
(V VL )VH
(VS VH )VL
The frequency f is the inverse of the period and is given by
f=
1= 1
T RC ln ((VVSS VVLH))VVHL
(D) Assume that VL = 1:8 V, VH = 3:0 V and VS = 5:0 V. Choose values for R and C so that the
oscillator oscillates at or very near 8-kHz. Since oscillator frequency alone under species R
and C , there is no single correct choice. Therefore, choose values for R and C that are easily
implemented with the components in the 6.002 lab kit.
ANSWER: f = 8KHz is equivalent to T = 1=f = 125s. Pick C = :0047F , we solve for
R using the equation in part (C):
T
R= ( VS VL )VH = 27K
C ln (VS VH)VL
which is a standard resistor value.
(E) For the choice of R and C from Part (D), sketch and clearly label a single graph that displays
vCAP , vOSC and vCLK as a function of time over one period of oscillation.
ANSWER: Using equations developed in (A) and (B) we get T1 = 59:6s and T2 = 64:8s.
We notice that T1 6= T2 . This does not aect the operation of the clock because the counter is
triggered by either the rising or the falling edge but not both.
vOSC vCLK
5V
3V
vCAP
1.8V
-
0V t (us)
T1= 59.6 us T2 = 64.8 us
Problem 2: The Digital-To-Analog Converter

The circuit shown in Figure 3 is the digital-to-analog converter. The voltage sources vDB0 through
vDB7 represent the voltages supplied by the eight data bits of the digital memory, DB0 through
DB7. These voltages will be approximately 5 V when the corresponding data bit is a logical high,
and approximately 0 V when the corresponding data bit is a logical low. The voltage vOFF , which
is set by a potentiometer, is an oset voltage that is used to center the output of the converter
around 0 V. Assume that the op-amp in the converter is ideal.
R1 R1 R1
2R1 2R1 2R1 2R1 2R1 2R1
+ vDB0
-
+ vDB1
- vDB6 +- vDB7 +-
R2
+5V
-
+ +
vDAC
-
+
vOFF
-
Figure 3: the digital-to-analog converter.

(A) Determine vDAC as a function of vDB0 through vDB7 , and vOFF . Hint: see Exercise 3.2.
ANSWER: The resistive network at the negative terminal of the Op Amp is called a R-2R
ladder. We can solve it by using the superposition principle. We turn o all the sources except
one, say vDB0 , and then apply Thevenin theorem repeatedly across each \T" node from left to
right, as shown in the gure below.
R1 T R1 T
T T
2R1 2R1 2R1 2R1 2R1 2R1
+ vDB0
-
R1
R1 R1 R1 2R1
vDB0 + ==> vDB0 + ===> vDB0 +

2 - 4 - 256 -
As demonstrated above, the Thevenin voltage is cut by half across each \T" node, and the
Thevenin resistance is always R1 . Eventually we simplify the network into one source in series
with one resistor at the negative terminal of the Op Amp. Since we have turned vOFF o, what
we have now is a simple inverting conguration, and the output is given by:
R2 vDB0
vDAC =
3R1 28
Repeating the same procedure for each vDBi , with vOFF set to zero, we result in the following
equation,
vDAC =
X
R2 7 vDBi
3R1 i=1 28 i
=
X
R2 7 2i
3R1 i=1 28 vDBi
Next we consider the eect of vOFF , when all the vDBi 's are set to zero. The resistance R
looking into the R-2R ladder is R = R1 + 2R1 = 3R1 , as shown in the previous gure. It
then follows that
R
vDAC = vOFF (1 + 2 )
3R 1
Finally, the total solution is
vDAC =
X
R2 7 2i
8
R
vDBi + vOFF (1 + 2 )
3R1 i=1 2 3R1
(B) With vOFF = 0 V, the output of the digital-to-analog converter should span the range of 0 V
to 2:5 V. Thus, the output of the converter should be given by
vDAC = 2:5 V
X7 2 DBi
i
i=0 255
where each data bit DBi takes on the numerical value of 1 when high and 0 when low. In this
manner, each successive data bit from DB0 to DB7 is given a voltage weighting twice that of
the preceding data bit, making it possible for the converter to output voltages from 0 V to
2:5 V in steps of 2:5=255 V. Given this, determine R2 in terms of R1 .
The voltage rating of the headphone is approximately 1.25 V. Since the low-pass lter and
volume control circuit between the converter and the headphone both have unity voltage gain
over the frequency range of interest, the output range of the analog-to-digital converter must
be designed to match the headphone rating. This is why the range is chosen to be 0 V to -2.5
V, with vOFF = 0. Note further that the output range of the converter is negative. This is
because the converter is based upon the inverting amplier conguration.
ANSWER: The vDAC equation provided above must equal to the one derived in part (A).
When all the bits are on,
R2 255
vDAC = 2:5V =
3R 256 5V
1
Solving for R2 get
R2 =
3 256 R = 1:51R
510 1 1
(C) The role of vOFF is to oset the output of the digital-to-analog converter so that it is centered
around 0 V. That is, with DB0 through DB7 all low, vDAC should be 1.25 V, and with DB0
through DB7 all high, vDAC should be 1:25 V. Given this, what must be the value of vOFF ?
ANSWER: Setting all bits to 0 we get
vDAC = 1:25 = vOFF (1 +
R2 256
3R1 ) = vOFF (1 + 510 )
This gives us
vOFF = :83V
(D) Assume that R1 = 10 k

. Use the result of Part (B) to determine R2 .
ANSWER R2 is found by directly applying the equation found in part (B):
R2 = 1:51R1 = 15:1K
Problem 3: The Low-Pass Filter

The circuit shown in Figure 4 is the low-pass lter. It is a second-order lter, and is driven by the
output of the digital-to-analog converter. Its purpose is to remove the high-frequency components
of the audio signal that result from the sampling, quantization and reconstruction of that signal.
Assume that the op-amp in the lter is ideal.
(A) Assume that the low-pass lter operates in sinusoidal steady state with vDAC = <fv~DAC ej!t g
and vLPF = <fv~LPF ej!t g where v~DAC and v~LPF are complex amplitudes. Find the input-output
transfer function HLPF (!) of the lter where HLPF (!) v~LPF =v~DAC .
ANSWER: Unfortunately, there is no simple way to solve this circuit. We are forced to
return to the Node Method. There are three nodes in the circuit, but the Ideal Op-Amp
Model allows us to assume that v+ = v = vLPF . By using this simplication, we can avoid
writing a node equation for the output node. I am dening the internal node as e~.
For the v+ node:
v~LPF v~LPF e~
1 + R
=0
j!C2
C1 -
+
+
R R vLPF
+ -
vDAC - C2
Figure 4: the low-pass lter.

For the v node:
v~LPF e~
1 + v~LPFR e~ + v~DACR e~ = 0
j!C1
We choose to solve the rst equation for e~ and substitute into the second. Mathematically, it is
irrelevant how we solve, but practically, it tends to be easier to solve the most simple equation
rst, and substitute into more and more complicated expressions.
e~ = v~LPF (1 + j!RC2 )
Substituting in for e~ and factoring out a v~LPF gives us:
v~LPF (
(1 + j!RC2 ) 1 + (1 + j!RC2 ) 1 + 1 + j!RC2 ) = v~DAC
1 R R R
j!C1
Solving for v~v~DAC

LPF and we have:
v~ 1
HLPF (!) = LPF =
v~DAC 1 !2 R2 C1 C2 + 2j!RC2
(B) Using the results of Part (A), nd the magnitude and phase of HLPF(!).
ANSWER:
jHLPF(!)j = (1 p 1
!2 R2 C1 C2 )2 + (2!RC2 )2
6 HLPF(!) = 0 arctan 1 2!!RC 2

2 R2 C1 C2
(C) There is no best design for the low-pass lter to meet the needs of the audio playback system.
However, with the appropriate choice of C1 , C2 and R, the transfer function of one good design
will take the form
jHLPF(!)j = 1 + (!=!1
LPF )2
where !LPF is a specied frequency. For this design, show that the low-frequency and high-
frequency asymptotes of jHLPF (!)j intersect at ! = !LPF, and therefore that !LPF is the
frequency that delineates the pass band of the low-pass amplier.
ANSWER: The low and high frequency asymptotes are calculated by including only the
lowest and highest order ! terms respectively. Continue to simplify in this manner until you
are left with only one term containing !.
For ! !LPF we drop the ! term because it is much less than 1. The result is very simple:
HLPF (! !LPF ) 1
For ! !LPF we drop the 1 term because it is much less than !. The result is still simple:
HLPF (! !LPF )
1
(!=!LPF )2
Solving for the intercept of these equations gives the expected ! = !LPF . This is known as the
cut-o frequency.
(D) What constraints must be imposed on C1 , C2 and R to obtain the low-pass lter transfer
function described in Part (C)?
ANSWER: Our current equation for jHLPF(!)j does not look much like our desired result,
but let's try multiplying out the denominator.
jHLPF(!)j = q1 1
2!2 R2 C1 C2 + (!2 R2 C1 C2 )2 + 4!2 R2 C22
If we let C1 = C2 = C , then we can easily factor that equation.
p p
jHLPF(!)j = 1 + 2!2 R2C12 + (!2 R2C 2)2 = (1 + !12R2C 2)2 = 1 + !12R2C 2
This nal form looks a lot more like what we want. We can see that !LPF = 1=(RC )
(E) Given that the low-pass lter is to be designed as described in Part (C), use the results of Part
(D) to choose values for C1 , C2 and R so that !LPF 2 4000 rad/s. Since the results of
Part (D) under specify C1 , C2 and R, there is no single correct choice. Therefore, choose C1 ,
C2 and R so that they are easily implemented with the components in the 6.002 lab kit.
ANSWER: We see that RC = 1=(2 4000) 3:98 10 5 . To choose a good value for R
and C we need to consider the parasitic elements in the circuit and the device non-idealities.
There are parasitic capacitances between the pins in the protoboard. Those tend to be on the
order of single picofarads. We need our C value to be much larger than that to be resistant to
interference.
The resistor choice is eected by the presence of source resistances and input and output
resistances of the op-amps. In addition there are parasitic inductances. If the resistance is
too small, the parasitic RLC circuits may be under-damped and cause ringing. In general we
choose a resistance of a few k
s. We have an R = 3:9k
lets try that.
R = 3:9k
requires that C = :0102F . Since this is much larger than a picofarad, and we
have a :01F capacitor in our kit, it seems that these values are a good choice.
Just to check, we see that our RC = 3:9 10 5 . This is about 2 % o of the desired frequency,
which is much less than the error of either the resistor or the capacitor.
(F) Given the choice of C1 , C2 and R from Part (E), determine !LPF, and plot both the log-
magnitude and phase of HLPF(!) against log-frequency for 2 101 rad=s ! 2 105
rad/s.
ANSWER: From above we see that !LPF = 2:56 104 = 2 4081rad=s.
Bode Diagrams
−10
−20
−30
Phase (deg); Magnitude (dB)
−40
−50
−60
−50
−100
−150
3 4 5 6
10 10 10 10
Frequency (rad/sec)
Problem 4: The Volume Control
Figure 5 shows the output of the low-pass lter driving the volume control stage, which in turn
drives the headphone. A potentiometer is used for R2 so that the gain of the circuit can be easily
adjusted.
Because there exists a coupling capacitor at its input, the volume control stage behaves like a
high-pass lter. In this way, the volume control circuit is designed to prevent a possibly damaging
DC voltage from being applied to the headphone. Such a voltage component could be present in
vLPF if, for example, vOFF in the analog-to-digital converter is not properly adjusted to balance the
output of the converter.
(A) Assume that the volume control stage operates in sinusoidal steady state with vLPF = <fv~LPF ej!t g
and vOUT = <fv~OUT ej!t g where v~LPF and v~OUT are complex amplitudes. Find the input-
output transfer function HAMP(!) of the power amplier where HAMP (!) v~OUT =v~LPF .
ANSWER: We can use the equation for an inverting op-amp to write down the answer
directly.
v~ R2 j!R2 C
HAMP(!) = OUT = 1 =
v~LPF R1 + j!C 1 + j!R1 C
Remember that this comes from assuming that v = v+ = 0 and that the current into v = 0.
(B) Using the result of Part (A), nd the magnitude and phase of HAMP(!).
ANSWER:
jHLPF(!)j = q1 +!R!22CR2C2
1
6 HLPF (!) = =2 arctan !R11 C
(C) Let !AMP be the frequency at which the low-frequency and high-frequency asymptotes of
jHAMP(!)j intersect. Determine !AMP in terms of R1, R2 and C .
R2
C R1
-
+ +
vLPF +
- vOUT Speaker
-
Figure 5: the power amplier.

ANSWER: This problem can be approached just as in Problem 3C:
For ! R1 C we drop the ! term because it is much less than 1. The result is simple:
HLPF(! R1 C ) !R2 C
Which goes to zero as ! goes to zero. This matches our intuition that the capacitor becomes
an open circuit at low frequencies.
For ! R1 C we drop the 1 because it is much less than !. The result is what we expect from
noticing that the capacitor behaves like a short at high frequencies:
R
HLPF (! R1 C ) 2
R1
Solving for the intercept of these equations gives the expected ! = R11 C = !AMP .
(D) Choose values for R1 , R2 and C so that !AMP 2 100 Hz, and jHAMPMAX (!)j = 1 for
! !AMP. Since these conditions alone under specify R1 , R2 and C , there is no single
correct choice. Therefore, choose values for R1 , R2 and C that are easily implemented with
the components in the 6.002 lab kit.
ANSWER: jHAMPMAX (!)j = 1 requires that R1 = R2MAX = R. So now we only need to
choose two values, R and C . The key here is that RC > 1=(2 100) 1:59 10 3
Using the same criteria as in the previous problem, one possible combination is:
R1 = R2MAX = 100k
C = 0:022F
To check: ! = 1=(RC ) = 454:5rad=s = 2 72Hz
Problem 5: Connecting The Blocks

In the complete audio playback system the output of the digital-to-analog converter is connected
directly to the input of the low-pass lter, and the output of the low-pass lter is connected directly
to the input of the volume control, as shown in Figure 1. Thus, the lter loads the converter, and
the volume control stage loads the lter. Explain why this loading could be ignored in Problems 2,
3 and 4. That is, explain why the converter, lter and amplier may each be analyzed and designed
in isolation.
ANSWER: The key to this simplicity is the op-amp. Using the ideal model of the op-
amp (which turns out to be a relatively accurate model) we see that the output of each stage
is independent of the amount of current supplied. That is to say, the op-amp in the digital-to-
analog converter has the same output value no matter how much current the low-pass lter draws.
Similarly, the op-amps in the low-pass lter and output stage maintain the same output voltage
regardless of the current drawn.

Spring 2001
Handout S01-018
Problem 1.1: Recall that the convention of associated variables requires that current be defined
to enter the positive terminal of the device.
a)
i2 v4
a b c
2 4
v2 i4
i1 1 v1 i3 3 v3 v5 5 i5
b)
i1 1 v1 v4 4 i4
i3
3 i6 6 v6
v3
i2 2 v2 i5 5 v5
c) The 4 nodes in a) and the 4 in b) are circled above.
d) Top left loop: v 1 + v 3 – v 4 = 0

Bottom left loop: v 2 – v 3 + v 5 = 0
Right loop: v 4 – v 5 – v 6 = 0
e) Labeling the nodes of circuit as above, here are the KCL statements for each node.
Node a: i 1 + i 2 = 0
Node b: – i 2 + i 3 – i 4 = 0
Node c: i 4 + i 5 = 0
Node d: – i 1 – i 3 – i 5 = 0
Problem 1.2: In each of the following circuits, determine the values of the indicated voltages
and/or currents. (Voltages are in volts and currents are in amperes.)
a) v 1 = 5 – 3 = 2
v2 = – 1 + v1 = 1
v3 = 1 + 3 = 4
b) v 1 = – 2 – 3 = – 5
v2 = v1 = –5
v3 = v2 + 5 = 0
i2 = 2 – 1 – ( –1 ) = 2
i3 = –1
Problem 1.3:
a) The resistors are in series, so the resistances add: R = R 1 + R 2 + R 3 .
b) The resistors are in parallel, so the conductances add: G = G 1 + G 2 + G 3 .
c) The first resistor is in series with the parallel combination of the others, so
1 R2 ⋅ R3
R = R 1 + -------------------- , and therefore R = R 1 + ------------------ .
G2 + G3 R2 + R3
d) The first resistor is in parallel with the series combination of the others, so
1 G2 ⋅ G3 R1 ⋅ ( R2 + R3 )
G = G 1 + ------------------ , and therefore G = G 1 + -------------------
- , or R = ---------------------------------
-.
R2 + R3 G2 + G3 R1 + R2 + R3
e) We cannot use the rules for series and parallel combinations because there are no ele-
ments or that are strictly in series or strictly in parallel.
Problem 1.4:
a) From the previous problem, we see that R = 1 + 2 + 2 = 5kΩ . The current through
the resistors is 10/5 = 2 mA, so v = (2 mA)(2 kΩ) = 4 V. Alternately, we can use the
voltage divider formula to obtain the same answer.
b) Using the current divider formula, we find that the current through the left branch is
i = -5/3 mA. The current through the right branch is -10/3 mA, so the voltage across
the resistor is 10/3 V. Note the application of the associated variables convention!
c) The voltage across the 2 kΩ resistor is 2 V, so the current through the 1 kΩ resistor is 2
mA. The current through the 3 kΩ resistor is therefore 3 mA, so the voltage across
that resistor is 9 V. The total voltage across the resistor network is 11 V, but due to the
polarity of the source the answer is -11 V.
d) The left branch has resistance 6 kΩ, the right branch, 3 kΩ. Thus the current is split,
with a third flowing through the left and two thirds through the right. The voltage
across the terminals is therefore (4 kΩ)(10/3 mA) - (1 kΩ)(20/3 mA) = 20/3 V.
Problem 1.5: When applying KCL, it is important to be consistent with respect to the direction
of current flow (i.e., into or out from the node). We choose to consider currents flowing out from
the node to be positive.
a) At e 1 : G 1 ⋅ ( e 1 – V ) + G 4 ⋅ ( e 1 – 0 ) + I 1 + G 3 ⋅ ( e 1 – e 2 ) = 0
At e 2 : G 2 ⋅ ( e 2 – V ) + G 5 ⋅ ( e 2 – 0 ) + ( – I 2 ) + G 3 ⋅ ( e 2 – e 1 ) = 0
e1 – e2 e1 – e3
b) At e 1 : I + ---------------
- + ---------------- = 0
R1 R4
e2 – e1 e2 – 0 e2 – e3
At e 2 : ---------------
- + -------------- + ---------------- = 0
R1 R3 R2
e3 – e1 e3 – e2 e3 – V
At e 3 : ---------------
- + ---------------- + --------------- = 0
R4 R2 R5
Note that terms containing the difference of two unknowns appear, negated, in the
equation for the corresponding nodes.
Problem 1.6:
a) The open circuit (i.e., zero current) voltage is voc = 5 V, the short circuit (i.e., zero volt-
age) current is isc = -2 mA, so RT = voc/isc = 2.5 kW. Thus we have the following
Thevenin (left) and Norton (right) circuit equivalents:
a a
2.5 kΩ
5V 2 mA 2.5 kΩ
b b
b) We note that terminal a is at +6 V, while terminal b is at +2 V, so the open circuit volt-

age is +4 V. To determine the equivalent resistance, we turn off the internal, indepen-
dent sources: the voltage source becomes a short circuit, and the current source
becomes an open circuit. The result is that we have two parallel combinations acting
in series, so R T = 2 || 3 + 3 || 6 = 1.2 + 2 = 3.2 kW.
a
3.2 kΩ
4V
b

Spring 2001
Handout S01-022
Problem 2.1:
a) First we will label the ground and the unknown node voltages, e1 and e2.
A
0.1 e1 0.2 e2
iA
V 0.1 0.2 I
Now write KCL equations at each node. We will use the convention that all currents
leaving a node are positive.
node 1: 0.1 ( e 1 – V ) + 0.2 ( e 1 – e 2 ) + 0.1e 1 = 0 0.4e 1 – 0.2e 2 = 0.1V
node 2: 0.2 ( e 2 – e 1 ) + 0.2e 2 – I = 0 – 0.2 e 1 + 0.4e 2 = I
b) 2 ( 0.4e 1 – 0.2e 2 = 0.1V ) + ( – 0.2 e 1 + 0.4e 2 = I ) ⇒ 0.6e 1 = I + 0.2V

5 1
⇒ e 1 = --- I + --- V
3 3
– 0.2  --- I + --- V  + 0.4e 2 = I ⇒ e 2 = --- I + ---  --- I + --- V  ⇒ e 2 = ------ I + --- V
5 1 5 1 5 1 10 1
3 3  2 2 3  3  3 6
i A = 0.2 ( e 1 – e 2 ) = ---  --- V – --- I ⇒ i A = ------ V – --- I

1 1 5 1 1
56 3  30 3
c) Remember that to remove a current 10 e1 5 e2
source, make it an open circuit. Notice that
we have converted the conductances to
iA
resistances.
V 10 5
d) First let’s combine the two 5Ω resistors to create a 10Ω 10 e1

resistor, which is then in parallel with another 10Ω resis-
tor. These two combine to form a 5Ω resistor. We have
now reduced the cirtcuit to the one on the right. Using the
5 1 V 5
voltage divider relation we have e 1 = --------------- V = --- V .
10 + 5 3
From the figure in part (c) we can see that
e1 1
- ⇒ i A = ------ V .
i A = -----------
5+5 30
e) Remember that to remove a 10 5

e1 e2
voltage source, make it a short
circuit.
iA
10 5 I
f) First let’s combine the two 10Ω resistors into 5

e1 e2
a 5Ω resistor. This results in the circuit on the
right. Noticing that iA flows through the two
iA
5Ω resistors in series, we can use the current
divider relation, so 5 5 I
5 1
i A = – --------------------------I ⇒ i A = – --- I .
(5 + 5) + 5 3
g) 1 1 The answers agree!

i A = ------ V – --- I
30 3
Problem 2.2:
–2
ρ 0.1 ×10 Ω ⋅ m
a) R = ------------------------- = ------------------------------------- = 100Ω
thinkness –6
10 ×10 m
L L 820Ω
b) R = ----- R ⇒ ----- = ------------- = 8.2
W W 100Ω
Let’s choose W = 1 micron. This forces L = 8.2 micron.
Note that this is just one possible combination of the length and width.
c)
0.5 3
1.5
The material can be broken into 7 squares so R ≈ 7 R = 700 Ω.
Problem 2.3:
a) Let’s replace each box with it’s Norton equivalent circuit.
ia ib
IA a b IB
RA RB
v 3 kΩ
a’ b’
The values found for ia and ib when the 3

kΩ resistor was replaced with a short are IA+IB=4 mA
exactly -IA and -IB, so IA= -5 mA and
IB= 3 mA. Combining the two current
RA||RB
v 3 kΩ
sources and the two unknown resistors
we have the circuit on the right.
We know that with the 3kΩ resistor in the circuit, v = 8 V so we can determine the par-
allel combination of RA and RB in the following way.
8V = 4mA ( 3kΩ ( R 1 R 2 ) ) ⇒ ( 3kΩ ( R 1 R 2 ) ) = 2kΩ
1 1 1
⇒ ------------------ = ---------- – ---------- ⇒ R 1 R 2 = 6kΩ
R1 R2 2kΩ 3kΩ
Therefore, when the 3 kΩ resistor is removed, v = 4mA ( R 1 R 2 ) ⇒ v = 24V .
b) No. As you can see above, with the given information we can only find the Norton cur-
rents and the parallel combination of their resistances.
c) Find the open circuit voltage of either box. This would give you enough information to
find the Norton resistance of that box. Since we know the value of the parallel combi-
nation we can easily find the other Norton resistance.
d) Assume the open circuit voltage of box A (from a to a’) is 50 V. Therefore

V
R A = 50 ----------- = 10kΩ and then
5mA
1 1 1 1 1
------- = ------------------ – ------- = ---------- – ------------- ⇒ R B = 15kΩ .
RB R1 R2 R A 6kΩ 10kΩ
Box A Box B
5mA -1mA
a b
10kΩ 15kΩ
a’ b’
Problem 2.4:
a) The functions for H and J simply comprise of one boolean term for each “1” in the
truth table.
H(A,B,C) = A B C + ABC + ABC

J(A,B,C) = A B C + ABC + ABC + ABC + ABC
b) Let’s first simplify H:

H(A,B,C) = A B C + ABC + ABC = A B C + (A+A)BC = A B C + BC
= (A B + B)C = (A + B)C = AC +BC
Now we need to put it in a form that will let us implement it with 2-input NAND gates.
H(A,B,C) = AC +BC = AC + BC = AC ⋅ BC
Note that inversion can be accomplished in the following man-

ner. This can also be accomplished with a NOR gate.
We can now implement H with 2-input NAND gates.
Notice that J can also be written as the compliment of all terms resulting in a “0” in the
truth table.
J(A,B,C) = ABC + ABC + ABC = ABC + AC ( B + B ) = ABC + AC
J(A,B,C) = ( ( A + B ) + C ) + ( A + C )
Problem 2.5:
a) F 1 = A + CB + ABC = A + CB = A + CB
b) F 2 = ( A + C ) ( B + D ) ( C + A + B ) = ( A + C ) ( B + D ) ( C + A + B )
F2 = ( A + C ) + (B + D) + (C + A + B)

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Name _______________________

Massachusetts Institute of Technology

6.002 Circuits and Electronics

Issued: 2/8/2001 Due: 2/16/2001

Read Chapters 1 through 4.

Problem 1.6: This problem concerns Thevenin and Norton equivalents.

6.002 Circuits and Electronics

Issued: 2/15/2001 Due: 2/23/2001

d) By inspection, and the use of series-parallel relationships, determine the component of

If the results are not the same, check your answer.

a) What is the sheet resistance of this material? (Sheet resistance, denoted by R , is

As shown the voltage v across the 3 kΩ resistor is 8 V.

Write corresponding logic functions for H and J.

b) Implement H(A,B,C) with 2-input NAND gates.

c) Implement J(A,B,C) with 2-input NOR gates.

6.002 Circuits and Electronics

Issued: 2/22/2001 Due: 3/2/2001

On resistance: 100-500 ohms

b) What is the noise margin for a low input?

c) What is the noise margin for a high input?

e) What is the largest possible value of n?

c) Repeat for a two input OR gate.

d) Can you use this device to create an inverter? Explain.

6.002 Circuits and Electronics

Issued: 3/1/2001 Due: 3/9/2001

b) Derive an expression for this worst case power.

In developing the implementation make the following four assump- T3

Determine the values of v and i.

6.002 Circuits and Electronics

Issued: 3/8/2001 Due: 3/16/2001

Read Chapters 11 through 12.

i-v graph for 4

c) Determine the voltage v1 across the current source.

c) What is the range of I required for an attenuation ratio in the range:

6.002 Circuits and Electronics

Issued: 3/8/2001 Due: 3/16/2001

Read Chapters 11 through 12.

i-v graph for 4

c) Determine the voltage v1 across the current source.

c) What is the range of I required for an attenuation ratio in the range:

6.002 Circuits and Electronics

Issued: 3/15/2001 Due: 3/23/2001

Read Chapters 8 through 9.

b) Using graphical techniques, construct a table showing the dependance of vO on vI and

a) Derive an equation which reflects the dependence of vO on vI for vI > 0.

b) What are the corresponding operating-point values of VA and VB?

6.002 Circuits and Electronics

Issued: 3/22/2001 Due: 4/6/2001

Read Chapters 12 and 13.

h) Finally, assume switch S closes instantaneously at t′ = 0 . What is the time delay, t′ ,

b) The input is changed to an impulse of magnitude (area) Λ . That is:

c) The input is changed to a ramp of magnitude (slope) M. That is:

6.002 Circuits and Electronics

Issued: 4/5/2001 Due: 4/13/2001

Read Chapters 12 and 13.

Volts Amps Volts Amps

b) Repeat for i(0-) = -I.

Each output is loaded by a capacitor, as shown below:

6.002 Circuits and Electronics