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PCF8574
SCPS068J – JULY 2001 – REVISED MARCH 2015

PCF8574 Remote 8-Bit I/O Expander for I2C Bus

1 Features 3 Description
•
1 Low Standby-Current Consumption of 10 μA Max This 8-bit input/output (I/O) expander for the two-line
bidirectional bus (I2C) is designed for 2.5-V to 6-V
• I2C to Parallel-Port Expander VCC operation.
• Open-Drain Interrupt Output
The PCF8574 device provides general-purpose
• Compatible With Most Microcontrollers remote I/O expansion for most microcontroller
• Latched Outputs With High-Current Drive families by way of the I2C interface [serial clock
Capability for Directly Driving LEDs (SCL), serial data (SDA)].
• Latch-Up Performance Exceeds 100 mA The device features an 8-bit quasi-bidirectional I/O
Per JESD 78, Class II port (P0–P7), including latched outputs with high-
current drive capability for directly driving LEDs. Each
2 Applications quasi-bidirectional I/O can be used as an input or
output without the use of a data-direction control
• Telecom Shelters: Filter Units
signal. At power on, the I/Os are high. In this mode,
• Servers only a current source to VCC is active.
• Routers (Telecom Switching Equipment)
• Personal Computers Device Information (1)
PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)
• Personal Electronics
TVSOP (20) 5.00 mm × 4.40 mm
• Industrial Automation SOIC (16) 10.30 mm × 7.50 mm
• Products with GPIO-Limited Processors PDIP (16) 19.30 mm × 6.35 mm
PCF8574
TSSOP (20) 6.50 mm × 4.40 mm
QFN (16) 3.00 mm × 3.00 mm
VQFN (20) 4.50 mm × 3.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

VCC
SDA
I2C or SMBus Master
SCL P0
(e.g. Processor)
INT P1 Peripheral Devices
P2 RESET, ENABLE,
P3 or control inputs
PCF8574
P4 INT or status
A0 P5 outputs
A1 P6 LEDs
A2 P7
GND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCF8574
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Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ....................................... 11
2 Applications ........................................................... 1 8.3 Feature Description................................................. 12
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 13
4 Revision History..................................................... 2 9 Application and Implementation ........................ 15
9.1 Application Information............................................ 15
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 15
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Power Supply Recommendations ..................... 18
10.1 Power-On Reset Requirements ........................... 18
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4 11 Layout................................................................... 20
6.4 Thermal Information .................................................. 4 11.1 Layout Guidelines ................................................. 20
6.5 Electrical Characteristics........................................... 5 11.2 Layout Example .................................................... 21
6.6 I2C Interface Timing Requirements........................... 5 12 Device and Documentation Support ................. 22
6.7 Switching Characteristics .......................................... 5 12.1 Trademarks ........................................................... 22
6.8 Typical Characteristics .............................................. 6 12.2 Electrostatic Discharge Caution ............................ 22
7 Parameter Measurement Information .................. 8 12.3 Glossary ................................................................ 22
8 Detailed Description ............................................ 11 13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................. 11
Information ........................................................... 22

4 Revision History
Changes from Revision I (November 2015) to Revision J Page

• Corrected part number in Device Information table ............................................................................................................... 1

Changes from Revision H (January 2015) to Revision I Page

• Added Junction temperature to the Absolute Maximum Ratings .......................................................................................... 4

• Changed Supply Current (A) To: Supply Current (µA) and fSCL = 400 kHz to fSCL = 100 kHz in Figure 1 ............................ 6
• Changed Supply Current (A) To: Supply Current (µA) in Figure 1 ........................................................................................ 6
• Changed Supply Current (A) To: Supply Current (µA) and fSCL = 400 kHz to fSCL = 100 kHz in Figure 3 ............................ 6

Changes from Revision G (May 2008) to Revision H Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1

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5 Pin Configuration and Functions

RGT PACKAGE RGY PACKAGE DGV OR PW PACKAGE
(TOP VIEW)
16 SDA (TOP VIEW) (TOP VIEW)
15 SCL

INT
14 INT

P7
13 P7
INT 1 20 P7
1 20 SCL 2 19 P6
SCL 2 19 P6 NC 3 18 NC
VCC 1 12 P6
NC 3 18 NC SDA 4 17 P5
A0 2 11 P5
SDA 4 17 P5 VCC 5 16 P4
A1 3 10 P4 6 15
VCC 5 16 P4 A0 GND
A2 4 9 GND A0 6 15 GND A1 7 14 P3
A1 14 P3 8 13
P0 5
P1 6

P3 8
P2 7

7 NC NC
NC 8 13 NC A2 9 12 P2
A2 9 12 P2 P0 10 11 P1
10 11

P0

P1
DW OR N PACKAGE
(TOP VIEW)

A0 1 16 VCC
A1 2 15 SDA
A2 3 14 SCL
P0 4 13 INT
P1 5 12 P7
P2 6 11 P6
P3 7 10 P5
GND 8 9 P4

Pin Functions
PIN
TYPE DESCRIPTION
NAME RGT RGY DGV or PW DW or N
Address inputs 0 through 2. Connect directly to VCC or ground.
A [0..2] 2, 3, 4 6, 7, 9 6, 7, 9 1, 2, 3 I
Pullup resistors are not needed.
GND 9 15 15 8 — Ground
INT 14 1 1 13 O Interrupt output. Connect to VCC through a pullup resistor.
NC - 3, 8, 13, 18 3, 8, 13, 18 - — Do not connect
5, 6, 7, 8, 10, 11, 12, 10, 11, 12, 4, 5, 6, 7,
P[0..7] 10, 11, 12, 14, 16, 17, 14, 16, 17, 9, 10, 11, I/O P-port input/output. Push-pull design structure.
13 19, 20 19, 20 12
SCL 15 2 2 14 I Serial clock line. Connect to VCC through a pullup resistor
SDA 16 4 4 15 I/O Serial data line. Connect to VCC through a pullup resistor.
VCC 1 5 5 16 — Voltage supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
(2)
VI Input voltage range –0.5 VCC + 0.5 V
VO Output voltage range (2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 –20 mA
IOK Input/output clamp current VO < 0 or VO > VCC ±400 μA
IOL Continuous output low current VO = 0 to VCC 50 mA
IOH Continuous output high current VO = 0 to VCC –4 mA
Continuous current through VCC or GND ±100 mA
TJ Junction temperature 150 °C
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 1500
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
2000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 2.5 6 V
VIH High-level input voltage 0.7 × VCC VCC + 0.5 V
VIL Low-level input voltage –0.5 0.3 × VCC V
IOH High-level output current –1 mA
IOL Low-level output current 25 mA
TA Operating free-air temperature –40 85 °C

6.4 Thermal Information

PCF8574
THERMAL METRIC (1) DGV DW N PW RGT RGY UNIT
20 PINS 16 PINS 16 PINS 20 PINS 16 PINS 20 PINS
θJA Junction-to-ambient thermal resistance 92 57 67 83 53 37 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
VIK Input diode clamp voltage II = –18 mA 2.5 V to 6 V –1.2 V
VPOR Power-on reset voltage (2) VI = VCC or GND, IO = 0 6V 1.3 2.4 V
IOH P port VO = GND 2.5 V to 6 V 30 300 μA
IOHT P port transient pullup current High during acknowledge, VOH = GND 2.5 V –1 mA
SDA VO = 0.4 V 2.5 V to 6 V 3
IOL P port VO = 1 V 5V 10 25 mA
INT VO = 0.4 V 2.5 V to 6 V 1.6
SCL, SDA ±5
II INT VI = VCC or GND 2.5 V to 6 V ±5 μA
A0, A1, A2 ±5
IIHL P port VI ≥ VCC or VI ≤ GND 2.5 V to 6 V ±400 μA
Operating mode VI = VCC or GND, IO = 0, fSCL = 100 kHz 40 100
ICC 6V μA
Standby mode VI = VCC or GND, IO = 0 2.5 10
Ci SCL VI = VCC or GND 2.5 V to 6 V 1.5 7 pF
SDA 3 7
Cio VIO = VCC or GND 2.5 V to 6 V pF
P port 4 10

(1) All typical values are at VCC = 5 V, TA = 25°C.

(2) The power-on reset circuit resets the I2C-bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC).

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12)
MIN MAX UNIT
fscl I2C clock frequency 100 kHz
2
tsch I C clock high time 4 μs
tscl I2C clock low time 4.7 μs
tsp I2C spike time 100 ns
2
tsds I C serial data setup time 250 ns
tsdh I2C serial data hold time 0 ns
ticr I2C input rise time 1 μs
ticf I2C input fall time 0.3 μs
2
tocf I C output fall time (10-pF to 400-pF bus) 300 ns
tbuf I2C bus free time between stop and start 4.7 μs
tsts I2C start or repeated start condition setup 4.7 μs
2
tsth I C start or repeated start condition hold 4 μs
tsps I2C stop condition setup 4 μs
tvd Valid data time SCL low to SDA output valid 3.4 μs
2
Cb I C bus capacitive load 400 pF

6.7 Switching Characteristics

over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 13)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
tpv Output data valid SCL P port 4 μs
tsu Input data setup time P port SCL 0 μs
th Input data hold time P port SCL 4 μs
tiv Interrupt valid time P port INT 4 μs
tir Interrupt reset delay time SCL INT 4 μs

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6.8 Typical Characteristics

TA = 25°C (unless otherwise noted)

120 90
fSCL = 100 kHz SCL = VCC
All I/Os unloaded 80 All I/Os unloaded
100
VCC = 5 V 70
Supply Current (mA)

Supply Current (mA)

VCC = 5 V
80 60
50
60
40 VCC = 2.5 V
40 30 VCC = 3.3 V
VCC = 3.3 V
20
20
VCC = 2.5 V 10
0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

Figure 1. Supply Current vs Temperature Figure 2. Standby Supply Current vs Temperature

100 20
fSCL = 100 kHz VCC = 2.5 V
90 All I/Os unloaded 18
80 16 TA = −40ºC
Supply Current (mA)

70 ISINK (mA) 14
60 12 TA = 25ºC
50 10
40 8
30 6
20 4 TA = 85ºC

10 2
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6
Supply Voltage (V) Vol (V)

Figure 3. Supply Current vs Supply Voltage Figure 4. I/O Sink Current vs Output Low Voltage
25 35
VCC = 3.3 V VCC = 5 V
30 TA = −40ºC
20 TA = −40°C
25 TA = 25ºC
ISINK (mA)

TA = 25°C
15
ISINK (mA)

20

10 15

10
TA = 85°C TA = 85ºC
5
5

0 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL (V) VOL (V)

Figure 5. I/O Sink Current vs Output Low Voltage Figure 6. I/O Sink Current vs Output Low Voltage

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Typical Characteristics (continued)

TA = 25°C (unless otherwise noted)
600 45
VCC = 2.5 V
TA = −40ºC
40
500 VCC = 5 V, ISINK = 10 mA
35
TA = 25ºC
400 30

ISOURCE (mA)
VOL (mV)

VCC = 2.5 V, ISINK = 10 mA

25
300
20
200 VCC = 5 V, 15
VCC = 2.5 V, ISINK = 1 mA TA = 85°C
10
100 ISINK = 1mA
5
0 0
−50 −25 0 25 50 75 100 125 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Temperature (°C) VCC − VOH (V)

Figure 7. I/O Output Low Voltage vs Temperature Figure 8. I/O Source Current vs Output High Voltage
45 45
VCC = 3.3 V VCC = 5 V
40 TA = 25ºC 40 TA = −40ºC

35 TA = −40ºC 35
TA = 25ºC
30 ISOURCE (mA) 30
ISOURCE (mA)

25 25
20 20
15 15
TA = 85ºC
10 TA = 85ºC 10
5 5
0 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VCC − VOH (V) VCC − VOH (V)

Figure 9. I/O Source Current vs Output High Voltage Figure 10. I/O Source Current vs Output High Voltage
350

300 VCC = 5 V

250
VCC − VOH (V)

VCC = 3.3 V

200 VCC = 2.5 V

150

100

50

0
−50 −25 0 25 50 75 100 125
Temperature (ºC)

Figure 11. I/O High Voltage vs Temperature

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7 Parameter Measurement Information

VCC

RL = 1 kΩ

Pn
DUT

CL = 10 pF to 400 pF

LOAD CIRCUIT

2 Bytes for Complete Device

Programming

Stop Start Bit 0 Stop

Condition Condition Bit 7 Bit 6 LSB Acknowledge Condition
(P) (S) MSB (R/W) (A) (P)

tscl tsch

0.7 × VCC
SCL
0.3 × VCC
ticr tPHL tsts
tbuf ticf
tsp tPLH
0.7 × VCC
SDA
0.3 × VCC
ticf ticr tsdh tsps
tsth tsds Repeat
Start Stop
Start or
Condition Condition
Repeat
Start
Condition VOLTAGE WAVEFORMS

Figure 12. I2C Interface Load Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

Acknowledge
From Slave
Start Acknowledge
Condition From Slave
R/W
Slave Address Data From Port Data From Port

S 0 1 0 0 A2 A1 A0 1 A Data 1 A Data 3 1 P

1 2 3 4 5 6 7 8 A A

tir B
tir
B

INT

A
tiv tsps
A
Data
Into Data 1 Data 2 Data 3
Port

0.7 × VCC 0.7 × VCC

INT SCL
R/W A
0.3 × VCC 0.3 × VCC

tiv tir

0.7 × VCC 0.7 × VCC

Pn INT
0.3 × VCC 0.3 × VCC

View A−A View B−B

Figure 13. Interrupt Voltage Waveforms

0.7 × VCC
SCL W A D
0.3 × VCC
Slave
Acknowledge

SDA

tpv

Pn

Last Stable Bit

Unstable
Data

Figure 14. I2C Write Voltage Waveforms

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Parameter Measurement Information (continued)

VCC VCC

RL = 1 kΩ RL = 4.7 kΩ

DUT SDA DUT INT

CL = 10 pF to 400 pF CL = 10 pF to 400 pF

GND GND
SDA LOAD CONFIGURATION INTERRUPT LOAD CONFIGURATION

Figure 15. Load Circuits

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8 Detailed Description

8.1 Overview
The PCF8574 device is an 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.5-V to 5.5-
V VCC operation. It provides general-purpose remote I/O expansion for most micro-controller families via the I2C
interface (serial clock, SCL, and serial data, SDA, pins).
The PCF8574 device provides an open-drain output (INT) that can be connected to the interrupt input of a
microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After
time, tiv, INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed
to the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs in
the read mode at the acknowledge bit after the rising edge of the SCL signal, or in the write mode at the
acknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledge
clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of
the I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, or
writing to, another device does not affect the interrupt circuit. This device does not have internal configuration or
status registers. Instead, read or write to the device I/Os directly after sending the device address (see Figure 16
and Figure 17).
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate by way of the I2C bus. Therefore, PCF8574 can remain a simple
slave device.
An additional strong pullup to VCC allows fast rising edges into heavily loaded outputs. This device turns on when
an output is written high and is switched off by the negative edge of SCL. The I/Os should be high before being
used as inputs.

8.2 Functional Block Diagram

8.2.1 Simplified Block Diagram of Device

PCF8574
13 Interrupt
INT LP Filter
Logic

1 4
A0 P0
2
A1 5
3 P1
A2 6
P2
14
SCL 7
Input I2CBus P3
Shift I/O
15 Filter Control 8 Bit
SDA Register Port 9
P4
10
P5
11
P6
12
P7

Write Pulse

16 Read Pulse
VCC Power-On
8 Reset
GND

Pin numbers shown are for the DW and N packages.

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Functional Block Diagram (continued)

8.2.2 Simplified Schematic Diagram of Each P-Port Input/Output

Write Pulse VCC

100 µA

Data From
D Q
Shift Register
FF
CI P0−P7
S
Power-On
Reset
D Q
GND
FF
CI
Read Pulse S

To Interrupt
Data to Logic
Shift Register

8.3 Feature Description

8.3.1 I2C Interface
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, most-
significant bit (MSB) first, including the data direction bit (R/W). This device does not respond to the general call
address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA I/O
during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the slave device must not
be changed between the start and the stop conditions.
The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values
read from the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte
is followed by an acknowledge sent from this device. If other data bytes are sent from the master, following the
acknowledge, they are ignored by this device. Data are output only if complete bytes are received and
acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during the
clock cycle for the acknowledge.
A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the
master.

8.3.2 Interface Definition

BIT
BYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
2
I C slave address L H L L A2 A1 A0 R/W
I/O data bus P7 P6 P5 P4 P3 P2 P1 P0

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8.3.3 Address Reference

INPUTS I2C BUS SLAVE

I2C BUS SLAVE 8-BIT
8-BIT WRITE
A2 A1 A0 READ ADDRESS
ADDRESS
65 (decimal), 41 64 (decimal), 40
L L L
(hexadecimal) (hexadecimal)
67 (decimal), 43 66 (decimal), 42
L L H
(hexadecimal) (hexadecimal)
69 (decimal), 45 68 (decimal), 44
L H L
(hexadecimal) (hexadecimal)
71 (decimal), 47 70 (decimal), 46
L H H
(hexadecimal) (hexadecimal)
73 (decimal), 49 72 (decimal), 48
H L L
(hexadecimal) (hexadecimal)
75 (decimal), 4B 74 (decimal), 4A
H L H
(hexadecimal) (hexadecimal)
77 (decimal), 4D 76 (decimal), 4C
H H L
(hexadecimal) (hexadecimal)
79 (decimal), 4F 78 (decimal), 4E
H H H
(hexadecimal) (hexadecimal)

8.4 Device Functional Modes

Figure 16 and Figure 17 show the address and timing diagrams for the write and read modes, respectively.
Integral Multiples of Two Bytes

SCL 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ACK
Start From Slave
ACK ACK
Condition From Slave From Slave
R/W
Slave Address Data Data

SDA S 0 1 0 0 A2 A1 A0 0 A P7 P6 1 P0 A P7 P0 A

P5
Write to
Port

Data Output Data A0

and B0
Voltage
Valid
tpv

P5 Output
Voltage

P5 Pullup IOH
Output IOHT
Current

INT

tir

Figure 16. Write Mode (Output)

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Device Functional Modes (continued)

SCL 1 2 3 4 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
5

ACK ACK ACK

R/W From Slave From Master From Master

SDA S 0 1 0 0 A2 A1 A0 1 A P7 P6 P5 P4 P3 P2 P1 P0 A P7 P6 P5 P4 P3 P2 P1 P0 A P7 P6

Read From
Port

Data Into
Port
P7 to P0 P7 to P0

th tsu

INT

tiv tir tir

A. A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be
stopped at any moment bya stop condition. When this occurs, data present at the latest ACK phase is valid (output
mode). Input data is lost.

Figure 17. Read Mode (Input)

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 18 shows an application in which the PCF8574 device can be used.

9.2 Typical Application

VCC
100 kΩ
(1) (1) 16 2 kΩ
VCC 10 kΩ 10 kΩ 10 kΩ (x 3)
VCC
15
SDA SDA 4 Subsystem 1
P0 (e.g., temperature sensor)
Master 14
SCL SCL 5
Controller P1 INT
13
INT INT
6
P2
7
RESET
P3
GND Subsystem 2
PCF8574
9 (e.g., counter)
P4
10
P5 A

3
A2 P6 11 Controlled Device
2 (e.g., CBT device)
ENABLE
A1
P7 12
1
A0 B

GND ALARM
8

Subsystem 3
(e.g., alarm system)

VCC
(1) The SCL and SDA pins must be tied directly to VCC because if SCL and SDA are tied to an auxiliary power supply
that could be powered on while VCC is powered off, then the supply current, ICC, will increase as a result.
A. Device address is configured as 0100000 for this example.
B. P0, P2, and P3 are configured as outputs.
C. P1, P4, and P5 are configured as inputs.
D. P6 and P7 are not used and must be configured as outputs.

Figure 18. Application Schematic

Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: PCF8574
PCF8574
SCPS068J – JULY 2001 – REVISED MARCH 2015 www.ti.com

Typical Application (continued)

9.2.1 Design Requirements

9.2.1.1 Minimizing ICC When I/Os Control LEDs

When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 18. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode,
with threshold voltage VT, and when a P-port is configured as an input the LED will be off but VI is a VT drop
below VCC.
For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or
equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 19 shows a high-
value resistor in parallel with the LED. Figure 20 shows VCC less than the LED supply voltage by at least VT.
Both of these methods maintain the I/O VI at or above VCC and prevents additional supply current consumption
when the P-port is configured as an input and the LED is off.
VCC

LED 100 kΩ
VCC

LEDx

Figure 19. High-Value Resistor in Parallel With LED

3.3 V 5V

VCC LED

LEDx

Figure 20. Device Supplied by a Lower Voltage

16 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated

Product Folder Links: PCF8574

 PCF8574
www.ti.com SCPS068J – JULY 2001 – REVISED MARCH 2015

Typical Application (continued)

9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL:
VCC - VOL(max)
Rp(min) =
IOL (1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
tr
Rp(max) =
0.8473 ´ Cb (2)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the PCF8574 device, Ci for
SCL or Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the
bus.

9.2.3 Application Curves

25 1.8
Standard-mode
Fast-mode 1.6
20 1.4

1.2
Rp(max) (kOhm)

Rp(min) (kOhm)

15
1

0.8
10
0.6

5 0.4

0.2 VCC > 2V

VCC <= 2
0 0
0 50 100 150 200 250 300 350 400 450 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Cb (pF) D008
VCC (V) D009
Standard-mode Fast-mode VOL = 0.2*VCC, IOL = 2 mA when VCC ≤ 2 V
(fSCL= 100 kHz, tr = 1 µs) (fSCL= 400 kHz, tr= 300 ns) VOL = 0.4 V, IOL = 3 mA when VCC > 2 V
Figure 21. Maximum Pull-Up resistance (Rp(max)) Figure 22. Minimum Pull-Up Resistance (Rp(min))
vs Bus Capacitance (Cb) vs Pull-Up Reference Voltage (VCC)

Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: PCF8574
PCF8574
SCPS068J – JULY 2001 – REVISED MARCH 2015 www.ti.com

10 Power Supply Recommendations

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, the PCF8574 device can be reset to its default conditions by using the
power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset.
This reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 23 and Figure 24.
VCC

Ramp-Up Ramp-Down Re-Ramp-Up

VCC_TRR_GND

Time
Time to Re-Ramp
VCC_RT VCC_FT VCC_RT

Figure 23. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC

VCC

Ramp-Down Ramp-Up

VCC_TRR_VPOR50

VIN drops below POR levels

Time
Time to Re-Ramp
VCC_FT VCC_RT

Figure 24. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC

Table 1 specifies the performance of the power-on reset feature for PCF8574 for both types of power-on reset.

Table 1. Recommended Supply Sequencing and Ramp Rates (1)

PARAMETER MIN TYP MAX UNIT
VCC_FT Fall rate See Figure 23 1 100 ms
VCC_RT Rise rate See Figure 23 0.01 100 ms
VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 23 0.001 ms
VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 24 0.001 ms
Level that VCCP can glitch down to, but not cause a functional
VCC_GH See Figure 25 1.2 V
disruption when VCCX_GW = 1 μs
Glitch width that will not cause a functional disruption when
VCC_GW See Figure 25 μs
VCCX_GH = 0.5 × VCCx
VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V
VPORR Voltage trip point of POR on fising VCC 1.033 1.428 V

(1) TA = –40°C to 85°C (unless otherwise noted)

18 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated

Product Folder Links: PCF8574

 PCF8574
www.ti.com SCPS068J – JULY 2001 – REVISED MARCH 2015

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 25 and Table 1 provide more
information on how to measure these specifications.
VCC

VCC_GH

Time

VCC_GW

Figure 25. Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 26 and Table 1 provide more details on this specification.
VCC

VPOR

VPORF

Time

POR

Time

Figure 26. VPOR

Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: PCF8574
PCF8574
SCPS068J – JULY 2001 – REVISED MARCH 2015 www.ti.com

11 Layout

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the PCF8574 device, common PCB layout practices should be followed
but additional concerns related to high-speed data transfer such as matched impedances and differential pairs
are not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in
the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors should be placed as close to the PCF8574 device as possible. These best practices are shown in
Figure 27.
For the layout example provided in Figure 27, it would be possible to fabricate a PCB with only 2 layers by using
the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND).
However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is
common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate
the other internal layer to a power plane. In a board layout using planes or split planes for power and ground,
vias are placed directly next to the surface mount component pad which needs to attach to VCC or GND and the
via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal
trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 27.

20 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated

Product Folder Links: PCF8574

 PCF8574
www.ti.com SCPS068J – JULY 2001 – REVISED MARCH 2015

11.2 Layout Example

LEGEND
Power or GND Plane
To I 2C Master
VIA to Power Plane
VCC
VIA to GND Plane

By-pass/De-coupling
capacitors

1 A0 VCC 16

2 A1 SDA 15

3 A2 SCL 14
PCF8574
4 P0 INT 13

5 P1 P7 12
To I/Os

6 P2 P6 11

To I/Os
7 P3 P5 10

8 GND P4 9

GND

Figure 27. Layout Example for PCF8574

Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: PCF8574
PCF8574
SCPS068J – JULY 2001 – REVISED MARCH 2015 www.ti.com

12 Device and Documentation Support

12.1 Trademarks
All trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

22 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated

Product Folder Links: PCF8574

 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

PCF8574DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574
& no Sb/Br)
PCF8574DGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574
& no Sb/Br)
PCF8574DW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8574
& no Sb/Br)
PCF8574DWR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8574
& no Sb/Br)
PCF8574DWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8574
& no Sb/Br)
PCF8574DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8574
& no Sb/Br)
PCF8574N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 PCF8574N
& no Sb/Br)
PCF8574NE4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 PCF8574N
& no Sb/Br)
PCF8574PW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574
& no Sb/Br)
PCF8574PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574
& no Sb/Br)
PCF8574PWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574
& no Sb/Br)
PCF8574PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574
& no Sb/Br)
PCF8574RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 ZWJ
& no Sb/Br)
PCF8574RGYR ACTIVE VQFN RGY 20 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PF574
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCF8574DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PCF8574DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PCF8574DWRG4 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PCF8574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PCF8574RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
PCF8574RGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCF8574DGVR TVSOP DGV 20 2000 367.0 367.0 35.0
PCF8574DWR SOIC DW 16 2000 350.0 350.0 43.0
PCF8574DWRG4 SOIC DW 16 2000 350.0 350.0 43.0
PCF8574PWR TSSOP PW 20 2000 367.0 367.0 38.0
PCF8574RGTR VQFN RGT 16 3000 346.0 346.0 35.0
PCF8574RGYR VQFN RGY 20 3000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RGT0016B SCALE 3.600
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

1 MAX C

SEATING PLANE

0.05
0.00 0.08

1.6 0.05 (0.2) TYP

5 8
EXPOSED
THERMAL PAD
12X 0.5
4
9

4X SYMM
17
1.5

1
12
0.3
16X
0.2
16 13 0.1 C A B
PIN 1 ID SYMM
(OPTIONAL) 0.05
0.5
16X
0.3

4219033/A 08/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGT0016B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.6)
SYMM
16 13

16X (0.6)

1
12

16X (0.25)
17 SYMM
(2.8)
(0.55)
TYP
12X (0.5)
9
4

( 0.2) TYP
VIA
5 8
(R0.05) (0.55) TYP
ALL PAD CORNERS
(2.8)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4219033/A 08/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGT0016B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.47)
16 13

16X (0.6)

1
12

16X (0.25)

17 SYMM
(2.8)

12X (0.5)

9
4

METAL
ALL AROUND

5 8
SYMM
(R0.05) TYP

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

84% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4219033/A 08/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
 PACKAGE OUTLINE
DW0016A SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4220721/A 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP

(9.3)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220721/A 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP
(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220721/A 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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