IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO.

11, NOVEMBER 2007 2969

Design and Fabrication of Asymmetric MOSFETs

Using a Novel Self-Aligned Structure
Jong Pil Kim, Student Member, IEEE, Woo Young Choi, Member, IEEE, Jae Young Song, Student Member, IEEE,
Sang Wan Kim, Jong Duk Lee, Member, IEEE, and Byung-Gook Park, Member, IEEE

Abstract—A novel asymmetric MOSFET with no lightly doped

drain on the source side is simulated on bulk Si using a device
simulator (SILVACO). To overcome the problems of the conven-
tional asymmetric process, a novel asymmetric MOSFET using
a mesa structure and a sidewall spacer gate is proposed, and it
provides a self-alignment process, aggressive scaling, and better
uniformity. First of all, we have compared the simulated character-
istics of the asymmetric and symmetric MOSFETs. Basically, both
asymmetric and symmetric MOSFETs have an n-type channel
and the same physical parameters. Compared with the symmetric
MOSFET, the asymmetric MOSFET shows better device perfor-
mance. Moreover, we have successfully fabricated 50-nm asym-
metric NMOSFETs based on simulation results and investigated
its operation and characteristics.
Index Terms—Asymmetric MOSFET, lightly doped drain
(LDD), mesa structure, sidewall spacer gate.

I. INTRODUCTION

M OSFET scaling has been accelerated thanks to its ex-

cellent performance and scaling properties. However, as
the size of the device is reduced down to the deep submicrom-
eter region, it suffers from some critical problems [1], [2]. One Fig. 1. Fabrication sequences of the conventional asymmetric LDD process
of them is the breakdown in a short-channel MOSFET when the implemented in a CMOS process.
drain voltage exceeds a certain voltage. When the field exceeds
As MOSFETs are scaled down to the nanoscale region, the
mid-105 V/cm, impact ionization takes place at the drain, which
parasitic resistance in the LDD region may impose a greater
leads to an abrupt increase of drain current. It can be relieved to
detrimental effect to the driving current. Asymmetric LDD
some extent by using a lightly doped drain (LDD) structure,
devices have been studied in the device level for 0.5-µm tech-
which reduces the peak field in a MOSFET [3]. However,
nology [5], [6].
the drain current is reduced due to the parasitic resistance in
However, there are some critical problems in the previous
the LDD region. Because of the recent industry emphasis on
study in terms of self-alignment. Fig. 1 shows the conventional
high-speed technology, it is very important to optimize the
process of an asymmetric MOSFET. Because an asymmetric
LDD design in a short-channel MOSFET for maximum cur-
structure with LDD on the drain side is formed with a pho-
rent drive capability while maintaining acceptable hot-carrier
tomask, self-alignment is not possible in the conventional case.
reliability [4].
It means that the gate length is limited by the alignment error.
One way to optimize the LDD design is through the use
The disadvantages of the conventional process stem from the
of asymmetric structures with no LDD on the source side.
fact that every photolithography equipment has an alignment
error. If a small alignment error occurs, the gate length will be
varied. Therefore, the electrical characteristics are not uniform.
Manuscript received May 4, 2007; revised July 16, 2007. This work was For the suppression of these undesirable effects, the gate length
supported in part by the BK21 program and by the Nano-Systems Institute should be set large enough to endure alignment errors. It leads
(NSI-NCRC) program sponsored by the Korea Science and Engineering Foun-
dation (KOSEF). The review of this paper was arranged by Editor M. J. Kumar.
to a limit in scaling down.
J. P. Kim, J. Y. Song, S. W. Kim, J. D. Lee, and B.-G. Park are with the Inter- We have examined an asymmetric MOSFET with the shape
University Semiconductor Research Center, School of Electrical Engineering, of a mesa structure using a sidewall spacer gate and compared
Seoul National University, Seoul 151-742, Korea (e-mail: jpkim78@snu.ac.kr).
W. Y. Choi is with the Inter-University Semiconductor Research Center, it with the conventional MOSFET.
School of Electrical Engineering, Seoul National University, Seoul 151-742, In this paper, we compare the device performances between
Korea, and also with the University of California, Berkeley, CA 94720 USA. asymmetric and symmetric NMOSFETs using a device simula-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. tor (SILVACO). Moreover, we have actually fabricated 50-nm
Digital Object Identifier 10.1109/TED.2007.906969 asymmetric NMOSFETs based on the simulation results.
0018-9383/$25.00 © 2007 IEEE
2970 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 11, NOVEMBER 2007

II. DEVICE STRUCTURE AND THE FABRICATION STEPS

To overcome the problems of the conventional fabrication
method, a novel fabrication method is proposed. As mentioned
above, we introduced not only a mesa shape to make an asym-
metric LDD structure but also a sidewall spacer gate to reduce
the channel length. Contrary to the conventional process, self-
alignment is possible in the proposed process. The proposed
process has some advantages over the conventional one as
follows.
Aggressive scaling down is feasible. In the conventional
process, the length of the gate (LG ) is dependent on the
alignment error of the photomask to implant the asymmetric
LDD. However, in the proposed process, once the source region
is defined, the rest of the regions are automatically aligned to it.
Additionally, the length of gate is determined by the width of
the sidewall spacer, not by the photolithography limit. Thus, a
state-of-the-art photolithography equipment is not necessary.
The device performance is uniform. As mentioned above,
the length of the gate that significantly affects the device
performance is determined by the width of the sidewall spacer.
The patterning method using the sidewall spacer is known as
an efficient way to define patterns uniformly and reproducibly
[7]–[10]. Therefore, the proposed method can implement uni-
form gate length from die to die and from wafer to wafer. Fig. 2. Key fabrication process flow of the proposed device. First, As+
As mentioned above, despite the advantages, there are some ions are implanted, and then a mesa-shaped source is formed by TEOS and
Si etching. After channel doping for threshold voltage adjustment, the gate
issues in terms of the integration of the asymmetric LDD oxide is formed using an RTO process, and the sidewall spacer gate is formed
process in a standard CMOS process. The cointegration of next to the source. We dope the LDD region with low energy, and then a
asymmetric LDD and standard MOSFETs would bring about TEOS sidewall spacer is formed for deep drain implantation to minimize
the resistance. In the final step, the RTA process activates impurities with
an increase in complexity and hence the cost compared to minimized diffusion.
standard CMOSFET process due to the following reasons. First
of all, to separately dope the N+ and P+ mesa structure, two
additional photolithography layers must be introduced. Second,
to form the gates of the asymmetric and standard MOSFET on
a single substrate, two separate deposition, doping, and etch
steps should be performed. This is because the spacer width
ultimately determines the channel length of asymmetric LDD
devices, thus requiring the gate spacer to be very thin, while
for long-channel standard MOSFETs, a thin gate layer is not
feasible considering the gate series resistance. Therefore, there
is still much room for improvement within the framework of
the integration.
We have fabricated a 50-nm self-aligned asymmetric
NMOSFET structure. Fig. 2 shows the key process flow of
the asymmetric n-channel device. We adopt a ring-shaped
Fig. 3. Layout of proposed asymmetric devices. A ring-shaped gate structure
gate structure, as illustrated in Fig. 3. Although we use this is used for fabrication convenience. Since the area of the source and drain is
structure for fabrication convenience, it causes some critical quite large, a high OFF current is inevitable in this structure.
problems in terms of device performance. A ring-shaped gate
structure does not have an active area mask for device isolation. vapor deposition (PECVD). After the first photolithography
Moreover, the fabricated devices using this structure have a step, the TEOS layer is etched, and subsequently, the silicon
high leakage current because of the channels of the addi- substrate is etched until the low-doped substrate is exposed. The
tional parasitic long-channel MOSFETs and experience a con- source region takes the shape of a mesa. The etched thickness of
siderable overlap capacitance. The starting wafers are p-type silicon is 150 nm. However, it is not easy to control the junction

100 bulk silicon wafers with a 10- to 15-Ω-m resistivity. depth. So we have simulated source implantation energies by
At first, to make the source region doped, ion implantation is splitting them into three types to make the junction depth of
performed. As+ ions are implanted at 60 keV. The dose was the source similar to the height of the source. Then, B+ ions
set to be 1 × 1015 cm−2 . Then, a 50-nm-thick tetraethoxysilane are implanted at 60 keV to adjust the threshold voltage. The
(TEOS) layer is deposited using plasma-enhanced chemical dose is set to be 3 × 1013 cm−2 . After channel doping for
KIM et al.: DESIGN AND FABRICATION OF ASYMMETRIC MOSFETs USING A NOVEL SELF-ALIGNED STRUCTURE 2971

threshold voltage adjustment, the gate oxide (TOX = 2 nm) is

grown at 900 ◦ C for 25 s using rapid thermal oxidation (RTO),
and then a 50-nm-thick polysilicon layer is deposited by low-
pressure chemical vapor deposition and doped by POCl3 . The
polysilicon thickness is very important because it determines
the channel length. Then, the second photolithography is per-
formed to define the gate pad. One noteworthy thing is that only
the gate pad, not the gate region, is patterned by the photomask.
Sequentially, the polysilicon layer is etched anisotropically to
form a sidewall spacer gate. Gate reoxidation was done to
suppress hot-carrier damages. Subsequently, low-energy ion
implantation is performed for the shallow LDD region. As+
ions are implanted with a dose of 5 × 1014 cm−2 at 2 keV. Then,
a 140-nm-thick TEOS layer is deposited and etched to form a
TEOS sidewall spacer. A TEOS sidewall spacer is formed for
high-energy drain implantation to minimize the drain parasitic
resistance. To form the drain region, As+ ion implantation is
done with a dose of 1 × 15 cm−2 at 20 keV. Next, wafers are
annealed at 1000 ◦ C for 5 s in a rapid thermal anneal (RTA)
tool to activate the dopants with minimal dopant diffusion. In
the back-end process, as a premetal dielectric (PMD) layer, a
200-nm-thick TEOS layer is deposited by PECVD, which is
followed by a contact-hole lithography where contact holes are
opened in the photoresist to the TEOS on top of the source,
drain, and gate pad regions. Using the resist as a mask, the
PMD layer is then etched down to the silicon source/drain and
polysilicon gate pad regions. The TEOS hard mask, which is
used as the source region with the shape of a mesa structure,
is etched by overetching during PMD layer etching. Next, as
a premetal cleaning process, wafers are dipped into a 50 : 1
buffered hydrofluoric acid (BHF) solution for 120 s. A 700-nm-
thick aluminum with 1% silicon was sputtered on the wafer, and
then the fourth photolithography is performed to define metal
Fig. 4. Cross-sectional (a) SEM and (b) TEM image of the fabricated asym-
pads by an image reversal photolithography process using the metric NMOSFET. Its gate length and source mesa height are 50 and 150 nm,
contact hole mask. Using the mask, aluminum is etched away respectively.
to define metal pads that are used to make probe contacts. The
final step of the process is a forming alloy annealing. The aim of
this step is to reduce the interface trap density by allowing the
hydrogen to react with the dangling bonds and to improve the
electrical contact of the metal layer to the underlying silicon.
Following the above process steps, we have successfully
fabricated self-aligned asymmetric MOSFETs for the first time.
Fig. 4 shows the cross-sectional SEM and transmission electron
microscope (TEM) image of the fabricated 50-nm asymmetric
NMOSFET. We have dipped the fabricated devices into a
diluted hydrofluoric acid chemical bath for the duration of Fig. 5. Device structures of (left) symmetric and (right) asymmetric
30 s to conduct the staining process. We have confirmed that NMOSFET. Basically, these structures have the same physical parameters.
the gate length, gate oxide thickness, and source mesa height
are almost 50, 2, and 150 nm, respectively. In case of the 50-nm symmetric NMOSFET, the threshold
voltage (VTH ) is 0.18 V and the subthreshold swing (SS)
is 78.4 mV/dec at VDS = 1 V. For the asymmetric one,
the threshold voltage and SS are 0.2 V and 78 mV/dec at
III. RESULTS AND DISCUSSIONS
VDS = 1 V, respectively. The drain-induced barrier lowering
Fig. 5 shows the device structures of the asymmetric and (DIBL) is 61 mV/V for the asymmetric MOSFET. In case
symmetric NMOSFETs used in the simulation work. The of the 25-nm symmetric NMOSFET, the threshold voltage
symmetric NMOSFET has the same physical parameters and (VTH ) is 0 V and the SS is 157 mV/dec at VDS = 1 V.
channel length. Fig. 6 illustrates the transfer characteristics For the asymmetric one, the threshold voltage and SS are
of the simulated asymmetric and symmetric NMOSFETs. 0.11 V and 104 mV/dec at VDS = 1 V, respectively. DIBL
2972 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 11, NOVEMBER 2007

TABLE I
RESULTS OF DEVICE SIMULATIONS

Fig. 7 illustrates the output characteristic curves of the

simulated asymmetric and symmetric NMOSFETs. When the
gate length is reduced from 50 to 25 nm, two interesting results
are observed in Fig. 7. First, when the drain voltage is swept
from 0 to 1.2 V at VG = 0 V, the drain current of the symmetric
NMOSFET increases very slowly, as seen in Fig. 7, while that
of the asymmetric one at the same conditions exhibits zero
current (ID = 0 A). This difference can be explained in the
following way. In the case of the symmetric NMOSFET, the
Fig. 6. ID –VG transfer characteristic curves of simulated symmetric and depletion region at the drain side is increased when the drain
asymmetric NMOSFETs. When the gate length is reduced from 50 to 25 nm, voltage is applied from 0 to 1.2 V so that the punch-through
the asymmetric device has a smaller SS and DIBL as well as a high ON / OFF
current ratio than the symmetric one. (a) 50-nm NMOSFET devices. (b) 25-nm phenomenon takes place. However, the proposed structure that
NMOSFET devices. has an elevated source results in a much less punch-through
phenomenon than the symmetric one.
is 160 mV/V for the asymmetric MOSFET. The simulation As seen in Fig. 7, the other interesting observation is that the
results are summarized in Table I. ION and IOFF are obtained linear region of the drain current curve at VG = 1 V does not
at VG − VTH = 1 V and VG = 0 V, respectively. When increase when we compare it with VG = 0.5 V. These results
the gate length is reduced, the asymmetric NMOSFET imply that the resistance is very large. However, the resistance
has small SS and DIBL as well as high ON / OFF current ratio in of the asymmetric NMOSFET shows a different situation. The
comparison with the symmetric NMOSFET, as shown in Fig. 6. slope of the output curve in the linear region is determined by
The more gate length is reduced, the more the proposed device the summation of the source resistance (RS ), drain resistance
structure has immunity against the short-channel effects (SCEs) (RD ), and channel resistance (RCH ), which is controlled by
of planar MOSFETs. The driving current of the asymmetric the gate. However, if the resistance of the source and drain is
NMOSFET is higher than that of the symmetric one because large, the change of channel resistance has a weaker influence
the parasitic resistance of the source region is decreased by on the total resistance. Finally, by removing the LDD region of
removing the LDD. In other words, removing the LDD from the source side in our proposed device, the parasitic resistance
the source side results in a much less voltage drop in the source- of the source side is decreased compared to conventional
side LDD region. Therefore, it is expected that the asymmetric devices so that the transconductance is increased.
MOSFET can be operated at a lower VDD . Furthermore, the We have fabricated a 50-nm asymmetric NMOSFET
OFF current of the asymmetric NMOSFET is less than that of based on the simulation results. The ID –VG and ID –VD
the symmetric one because the depletion region profile from characteristics of the fabricated device are shown in Figs. 8 and
source to body of these devices is different from each other. 9, respectively.
KIM et al.: DESIGN AND FABRICATION OF ASYMMETRIC MOSFETs USING A NOVEL SELF-ALIGNED STRUCTURE 2973

Fig. 8. ID –VG characteristics of the fabricated asymmetric NMOSFET

whose channel length and width are 50 nm and 20 µm, respectively.

Fig. 7. ID –VD output characteristic curves of symmetric and asymmetric

NMOSFETs. The asymmetric NMOSFET shows a higher conductance value Fig. 9. ID –VD characteristics of the 50-nm asymmetric NMOSFET. The
than the symmetric device. (a) 50-nm NMOSFET devices. (b) 25-nm driving current (ION ) is 310 µA/µm at VG = VD = 1.2 V.
NMOSFET devices.

When we compare the ID –VG characteristics (Fig. 8) of large source/drain resistance of the ring-shaped gate structure.
the fabricated device with the simulated results on 50-nm For further improvement in the ON / OFF current ratio, the fol-
devices [Fig. 6(a)], we can observe a considerable difference lowing can be thought of as solutions: photolithography mask
in terms of the OFF current. Although the device shows normal modification, silicidation, and substrate doping concentration
transistor operation, the OFF current is quite high because we reduction.
used a ring-shaped gate mask structure with a large pad area, as
seen in Fig. 3. In the proposed device, the OFF current consists
IV. CONCLUSION
of the gate-to-source and drain-to-substrate leakage. We have
applied reverse bias between the drain and body terminals to We have introduced an asymmetric NMOSFET with the
extract the drain-to-substrate leakage current while floating shape of a mesa and no LDD on the source side. It has merits in
other terminals (source and gate). The drain-to-substrate terms of device scalability and performance. First, this structure
leakage current is 12.41 µA at VDB = 0.05 V. Therefore, it is can have a uniform channel length by using sidewall spacer
confirmed that the high OFF current is mostly due to the drain- gate and self-aligned fabrication. In addition, this structure can
to-substrate leakage. The fabricated asymmetric NMOSFET increase the driving current by removing the LDD region of the
with W/L = 20 µm/50 nm has a driving current (ION ) source side as in the previous study.
of 310 µA/µm at VG = VD = 1.2 V. When we compared The performance of the asymmetric NMOSFET is examined.
the ID –VD characteristics (Fig. 9) of the fabricated device Compared with symmetric NMOSFET, the asymmetric device
with the simulated results on 50-nm devices [Fig. 7(a)], the exhibits high ION and suppresses the SCE.
ON current is smaller than the simulation results in spite of We have successfully fabricated the 50-nm asymmetric
normal output characteristics. A small ON current is due to the NMOSFET and investigated its operation and characteristics.
2974 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 11, NOVEMBER 2007

R EFERENCES Sang Wan Kim was born in Daegu, Korea, in 1983.

He received the B.S. degree from Seoul National
[1] M. Lundstrom, “Device physics at the scaling limit: What matters?” in University, Seoul, Korea, in 2006. He is currently
IEDM Tech. Dig., 33.1.1-33.1.4, Dec. 2003. working toward the M.S. degree in electrical engi-
[2] W. Y. Choi, B. Y. Choi, D.-S. Woo, J. D. Lee, and B.-G. Park, “Reverse- neering at Seoul National University.
order source drain formation with double offset spacer (RODOS) for low- His current research interests include nanoscale
power and high-speed application,” IEEE Trans. Nanotechnol., vol. 2, CMOS device modeling, measurement, characteriza-
no. 4, pp. 210–216, Dec. 2003. tion, and fabrication.
[3] Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices.
Cambridge, U.K.: Cambridge Univ. Press.
[4] J. F. Chen, J. Tao, P. Fang, and C. Hu, “Performance and reliabil-
ity comparison between asymmetric and symmetric LDD devices and
logic gates,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 367–371,
Mar. 1999. Jong Duk Lee (M’79) received the Ph.D. degree
[5] T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, and C. F. Codella, from the University of North Carolina, Chapel Hill,
“Asymmetric halo source GOLD drain (HS-GOLD) deep sub-half micron in 1975.
n-MOSFET design for reliability and performance,” in IEDM Tech. Dig., From 1975 to 1978, he was an Assistant Profes-
Dec. 1989, pp. 617–620. sor with the Department of Electronics Engineer-
[6] T. Horiuchi, T. Homma, Y. Murao, and K. Okumura, “An asymmetric ing, Kyungpook National University, Daegu, Korea.
sidewall process for high performance LDD MOSFET’,” IEEE Trans. In 1978, he studied microelectric technology in
HP-ICL, Palo Alto, CA, and soon afterward was with
Electron Devices, vol. 41, no. 2, pp. 186–190, Feb. 1994.
the Korea Institute of Electronic Technology (KIET)
[7] S.-K. Sung, Y. J. Choi, J. D. Lee, and B.-G. Park, “Realization of ultra-
as the Director of the Semiconductor Division. He
fine lines using sidewall structures and their application to nMOSFETs,”
established the KIET Kumi Facility and introduced
J. Korean Phys. Soc., vol. 35, pp. S693–696, Dec. 1999.
the first polysilicon gate technology in Korea by developing 4-K SRAM, 32-K
[8] S.-K. Sung, J. S. Sim, D. H. Kim, J. D. Lee, and B.-G. Park, “Nanoscale- and 64-K Mask ROMs, and one-chip eight-bit microcomputer. In July 1983, he
wire patterning using side-wall and quantum dot memory device fabrica- was with the Department of Electronics Engineering, Seoul National University
tion,” J. Korean Phys. Soc., vol. 40, no. 1, pp. 128–131, Jan. 2002. (SNU), Seoul, Korea, which has been merged with the School of Electrical
[9] D. H. Kim, S.-K. Sung, J. S. Sim, K. R. Kim, J. D. Lee, B.-G. Park, Engineering in 1992, where he is currently a Professor. He established the Inter-
B. H. Choi, S. W. Hwang, and D. Ahn, “Single-electron transistor based university Semiconductor Research Center (ISRC) in 1985 and was the Director
on silicon-on-insulator quantum wire fabricated by a side-wall patterning from 1987 to 1989. He was the Chairman of the Electronics Engineering
method,” Appl. Phys. Lett., vol. 79, no. 23, pp. 3812–3814, Dec. 2001. Department from 1994 to 1996. While on leave from SNU in 1996, he was
[10] W. Y. Choi, B. Y. Choi, Y. J. Choi, D.-S. Woo, S.-K. Sung, J. D. Lee, the Head of the Display R&D Center for a year with Samsung SDI Company,
and B.-G. Park, “Fabrication of a 30-nm planar nMOSFETs based on Ltd. His current research interests include sub-0.1-µm CMOS structure and
the sidewall patterning technique,” J. Korean Phys. Soc., vol. 41, no. 4, technology, CMOS image sensors, field emission display (FED), and organic
pp. 497–500, Oct. 2002. LEDs and TFTs.
Dr. Lee is a member of ECS, AVS, SID, KPS, KVS, IEEK, and KSS. He was
a member of the steering committee for the International Vacuum Microelec-
tronics Conference (IVMC) from 1997 to 2001 and the Korean Conference on
Jong Pil Kim (S’06) was born in Yeongcheon Semiconductors (KCS) from 1998 to 2008. He was the Conference Chairman
Kyungpook, Korea, in 1978. He received the B.S. de- of IVMC’97 and KCS’98, who successfully led IVMC’97 and KCS’98. He
gree from Kyonggi University, Kyonggi-Do, Korea, was also a member of the International Electron Devices Meeting (IEDM)
in 2004. He is currently working toward the Ph.D. Subcommittee on Detectors, Sensors and Displays operated by IEEE Electron
degree in electrical engineering at Seoul National Devices Society from 1998 to 1999. He was elected to the first President of
University, Seoul, Korea. the Korean Information Display Society in June 1999 and had served until
December 31, 2001.
His current research interests include nanoscale
CMOS device modeling, measurement, characteriza-
tion, and fabrication.
Byung-Gook Park (M’90) received the B.S. and
M.S. degrees in electronics engineering from Seoul
National University, Seoul, Korea, in 1982 and 1984,
respectively, and the Ph.D. degree in electrical en-
gineering from Stanford University, Stanford, CA,
Woo Young Choi (S’05–M’07) was born in Incheon, in 1990.
Korea, in 1978. He received the B.S., M.S., and From 1990 to 1993, he was with AT&T Bell
Ph.D. degrees from Seoul National University, Laboratories, Murray Hill, NJ, where he contributed
Seoul, Korea, in 2000, 2002, and 2006, respectively. to the development of 0.1-µm CMOS and its char-
Since 2006, he has been a Post-Doctor with the acterization. From 1993 to 1994, he was with Texas
University of California, Berkeley. He has authored Instruments Incorporated, Dallas, TX, where he de-
or coauthored over 70 papers. He is the holder of veloped 0.25-µm CMOS. Since 1994, he has been with Seoul National
three Korea patents. His current research interests University, where he was an Assistant Professor in the School of Electrical
include CMOS and CMOS-compatible novel de- Engineering (SoEE) and is currently a Professor. While on sabbatical leave
vice modeling, characterization, measurement, fab- from Seoul National University, in 2002, he was a Visiting Professor with
rication, and nanoelectromechanical system (NEMS) Stanford University. He has authored and coauthored over 490 research papers
technology. in journals and conference proceedings. He is the holder of 27 Korean and five
U.S. patents. His current research interests include the design and fabrication
of nanoscale CMOS, Flash memories, silicon quantum devices, and organic
thin-film transistors.
Dr. Park is currently the Executive Director of the Institute of Electronics
Jae Young Song (S’05) was born in Daejeon, Korea,
Engineers of Korea (IEEK) and the Treasurer of IEEE Seoul Section. He has
in 1979. He received the B.S. degree from Chungnam
served as a committee member on several international conferences, including
National University, Daejeon, in 2004. He is cur-
Microprocesses and Nanotechnology, IEEE International Electron Devices
rently working toward the Ph.D. degree in electri-
Meeting, International Conference on Solid State Devices and Materials, and
cal engineering at Seoul National University, Seoul, IEEE Silicon Nanoelectronics Workshop (Technical Program Chair in 2005
Korea. and General Chair in 2007). He received “Best Teacher” Award from SoEE
His current research interests include nanoscale in 1997, the Doyeon Award for Creative Research from the Inter-university
CMOS device modeling, measurement, characteriza- Semiconductor Research Center (ISRC) in 2003, the Haedong Paper Award
tion, and fabrication. from IEEK in 2005, and the Educational Award from College of Engineering,
SNU, in 2006.