El Programador Subestándar - Modo Router en Modem SENDTEL MS8-8817 CANTV
El Programador Subestándar - Modo Router en Modem SENDTEL MS8-8817 CANTV
El Programador Subestándar - Modo Router en Modem SENDTEL MS8-8817 CANTV
July 2009
SG6105A
Power Supply Supervisor + Regulator + PWM
Features Description
PC Half-Bridge (or 494) Power Supply Supervisor + SG6105A controller is designed for switching-mode
two 431 + PWM power supplies for desktop PCs. It provides all the
functions necessary to monitor and control the output of
High Integration with Few External Components the power supply. Remote ON/OFF control, power-good
Over-Voltage Protection for 3.3V, 5V, and 12V circuitry, and protection features against over-voltage
and over-power are implemented. It directly senses all
Under-Voltage Protection for 3.3V, 5V, and 12V the output rails for OVP without the need for external
Under-Voltage Protection for -12V and/or -5V dividers. An innovative AC-signal sampling circuitry
provides a sufficient power-down warning signal for PG.
Over-Power and Short-Circuit Protection
A built-in timer generates accurate timing for the control
Power-Down Warning Circuitry circuit, including the PS-off delay. The cycle-by-cycle
Power-Good Circuitry PWM switching prevents the power transformer from
saturation and ensures the fastest response for the
Delay Time for PSON and PG Signal short-circuit protection, which greatly reduces stress for
Remote ON/OFF Function power transistors. Two internal precision TL431 shunt
regulators provide stable reference voltage and a driver
On-Chip Oscillator and Error Amplifier for 3.3V and 5V standby regulation.
Two Shunt Regulators for 3.3V and 5V-Standby Utilizing minimum external components, the SG6105A
Latching PWM for Cycle-by-Cycle Switching includes the functions for push-pull and/or half-bridge
topology, decreasing production cost and PCB space,
Push-Pull PWM Operation and Totem Pole Outputs and increasing the MTBF for power supply.
Soft-Start and Maximum 93% Duty Cycle
Applications
Switching mode power supply for computers:
AT
NLX
SFX (micro-ATX)
Ordering Information
Operating
Part
Temperature Eco Status Package Packing Method
Number
Range
SG6105ADZ -40 to +105°C RoHS 20-pin Dual In-Line Package (DIP) Tube
SG6105ADY -40 to +105°C Green 20-pin Dual In-Line Package (DIP) Tube
SG6105A
2μA VREF
0.7V
DSD
Delay
300ms
UV
Detector
OV Delay OP1
Protector 3ms
9
SET
D Q
CLR Q
UV
Protector OP2
S
SET
Q
8
3.2V
R Q
VCC
CLR
FB1
5V D
SET
Q
O.S.C 14
NVP 64μA 2.1V Q
Delay
CLR
OPP FB2
11
Delay
15ms
VCC
12
PSON VREF2
1.4V On/Off Delay
Delay
50ms
1 16ms 2ms
18 17 16
SS IN COMP
20
T : D = DIP
SG6105ATP P : Z = Lead Free
XXXXXXXXYWWV Null=Regular Ppackage
XXXXXXXX: Wafer Lot
Y: Year; WW: Week
V: Assembly Location
1
※Marking for SG6105ADZ (Pb-free)
F- Fairchild Logo
Z- Plant Code
X- 1 Digit Year Code
Y- 1 Digit Week Code
TT: 2 Digits Die Run Code
T: Package Type (D=DIP)
P: Y:Green Package
M: Manufacture Flow Code
Pin Configuration
5.7 2 .6 0 0
5.5 2 .5 5 0
ICC-OP(mA)
VREF (V)
5.3 2 .5 0 0
5.1 2 .4 5 0
4.9 2 .4 0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -2 5 -10 5 20 35 50 65 80 95 1 10 1 25
6.000 67.000
66.000
5.000
fOSC (KHz)
VOH (V)
65.000
4.000
64.000
63.000
3.000
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)
Figure 7. PWM Output Voltage vs. Temperature Figure 8. Frequency vs. Temperature
89.500 2.600
89.450
89.400
2.550
DCMAX (%)
89.350
V2.5 (V)
89.300
89.250
2.500
89.200
89.150
89.100 2.450
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)
Figure 9. MAX Duty Cycle vs. Temperature Figure 10. Reference Voltage vs. Temperature
2.610 4.180
2.600
4.160
2.590
VOVP (V)
VUVP (V)
2.580
4.140
2.570
2.560
4.120
2.550
2.540 4.100
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)
Figure 11. 3.3V VUVP vs. Temperature Figure 12. 3.3V VOVP vs. Temperature
3.700 6.180
3.600 6.160
VOVP (V)
VUVP (V)
3.500 6.140
3.400 6.120
3.300 6.100
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)
Figure 13. 5V VUVP vs. Temperature Figure 14. 5V VOVP vs. Temperature
7.060 14.600
7.050 14.550
VUVP (V)
VOVP (V)
7.040 14.500
7.030 14.450
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)
Figure 15. 12V VUVP vs. Temperature Figure 16. 12V VOVP vs. Temperature
1. Over-voltage and under-voltage protection for 3. The power-good signal is asserted to indicate
3.3V, 5V, and 12V without external divider. the 3.3V, 5V, and 12V is above the under-
voltage threshold level. PG pin goes high when
2. Over-power protection. the above condition is reached. A 2K pull-up
resistor may connect to 5V.
3. UV protection for -12V and/or -5V.
4. The VCC can be supplied from the 5V-standby.
4. Power-down warning for power-good signal.
5. When the VCC voltage is higher than 7V,
5. Power-good signal and power-fail lockup. besides the shunt regulator, the circuit is
6. Remote on/off control. shutdown and reset. No extra power supply is
needed.
7. Delay time for PSON and PS-off signal.
6. Two internal high-precision 431 shunt
8. Two shunt regulators for 3.3V and 5V-standby regulators are built-in to provide stable
regulation. reference voltages.
9. Complete pulse width modulation (PWM) control 7. Complete PWM control circuitry, including the
circuitry. error amplifier for push-pull or half-bridge
10. On-chip oscillator. operation.
Introduction
The application guide shows the key features of
SG6105A and illustrates how to design in an ATX
switching mode power supply (SMPS). SG6105A is VDD
suitable for half-bridge, push-pull topology and
incorporates with a four-channel supervisor, including
5V-standby. The PWM section of SG6105A comprises
a built-in 65kHz oscillator and high-immunity circuits,
which protect the system from noise interference and
provide more noise margins for improper PCB layout. OP2
SG6105A has OVP and UVP for 12V, 5V, and 3.3V. R1 R2
NVP is used for negative voltage protection, such as – OPP
12V and/or –5V. The UVAC (AC fails detection) is applied C1 R3
to detect AC line condition. Two built-in internal
precision TL431 shunt regulators can be used for 3.3V
or 5V auxiliary standby power.
Figure 18. OPP Protection Circuit
AC Fails Detection
Through a resistor divider, UVAC is connected to the Negative Voltage Protection (NVP)
secondary power transformer for detecting the AC line
condition. Once the voltage of UVAC is lower than 0.7V The NVP provides an under-voltage protection (UVP)
for a period of time, such as 200µs, the PG (power- for negative voltage outputs. An under-voltage
good) signal is pulled low to indicate an AC line power- represents the phenomenal of the overload condition in
down condition. The voltage amplitude of the PWM negative voltage output. For example, the –12V output
switching signal in the secondary power transformer is may drop to –10V during the overload situation. A
proportional to the AC line voltage. Adjust the ratio of resistor determining the threshold of the protection is
resistor divider to decide the threshold of power-down connected from pin NVP to the negative voltage output.
warning. A small capacitor is connected from UVAC to Via this resistor, NVP outputs a 64µA constant current
ground for filtering the switching noise. to the negative voltage output. When the NVP voltage is
over 2.1V and the situation kept for longer than 7ms,
SG6105A locks the power outputs off:
VS
VO VNVP=64µA × (R1 + R2) – V-12V (1)
The power outputs are locked off when VNVP ≥ 2.1V.
R1
0.7V
UVAC
R2 C1
VCC
PSON
3.3V,5V,12V
tPSON(ON) tUVP
NVP
tPSON(OFF) tNVP
SS(on/off)
tPSOFF
PG
tPG
VCC
PSON
OPP
tOPP
SS(on/off)
PG
SG6105A
24.892-26.924
PIN #1
6.223-6.477
1.524 7.620
3.175-3.429
2.921-3.810
5.334 MAX
2.540 0-15
0.381 MIN
0.457
9.017 TYP
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MS-001,
VARIATIONS AD
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
0.25MM.
D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED
0.25MM.
E. DRAWING FILE NAME: N20SREV1
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.