Ca 3524
Ca 3524
Ca 3524
This application note reviews pulse-width modulated (PWM) circuits, and the CA1524 series of pulse-width modulator ICs particularly intended for this type of application. It also includes descriptions of basic switching-regulator circuits, the generic CA1524 Series IC, its use in a variable switched power supply application, together with a variety of its unique circuit applications. The CA1524, CA2524, and CA3524 Series, a family of integrated circuits containing a pulse-width modulator and related control circuits, are particularly applicable to switching regulators, flyback converters, dc-to-dc converters and the like. These ICs operate with a power supply in the 8V to 40V range for use in both low and high power regulators. The CA1524 series ICs contain the following circuit functions: 5V temperature compensated zener reference, precision RC oscillator, transconductance error amplifier, current-limiting amplifier, control comparator, shutdown circuit, and dual output transistor
switches. The circuits functions make these devices attractive for a wide variety of other applications; e.g., low frequency pulse generators, automotive temperature voltage regulators, battery chargers, electronic bathroom scales, etc. The CA1524 family of ICs is supplied in 16 lead plastic and ceramic (frit) packages, and is also available in chip form. Data on these types are found in the datasheet le number 1239. CA1524 Series IC Features The CA1524 PWM on-chip functions shown in the functional block diagram of Figure 1 include an error amplifier, a comparator, an oscillator, a flip-flop, and a voltage regulator. The error amplifier senses the difference between the actual and the desired regulator output and applies this signal to the comparators positive input. The output of this stage is in turn a function of the error signal and the oscillators ramp voltage.
V+ 15 VREF 16
REFERENCE REGULATOR 5V
+5V TO ALL INTERNAL CIRCUITS +5V CA 12 FLIP FLOP SA 11 INV. INPUT NONINV. INPUT OSC OUT EB 14 (+) C.L. SENSE (-) C.L. SENSE RT CT GND 9 COMPENSATION AND COMPARATOR C.L. CURRENT LIMITING AMPLIFIER 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREF V+ EMITTER B COLLECTOR B COLLECTOR A EMITTER A SHUTDOWN COMPENSATION AND COMPARATOR
TOP VIEW
3 OSC OUT +5V OSCILLATOR RT +5V 7 CT INV. INPUT NON-INV. INPUT ERROR AMP + 1k 10 SHUTDOWN 10k COMPARATOR +5V
EA CB
13 SB
+5V + C.L. -
1 2
+ SENSE - SENSE
4 5
GND
Copyright
include a zener voltage reference, transconductance error amplier, precision RC oscillator, pulse width modulator, pulse steering ip-op, dual alternating output switches, and current limiting and shutdown circuitry. A complete schematic is shown in Figure 4
100 DC AC 60 SERIES PASS 40 SERIES-PASS REGULATOR SWITCHING REGULATOR
80 EFFICIENCY - (%)
20
VO + 1
PO AC = PIN
VO VO + 2
FIGURE 2. EFFICIENCY CURVES FOR LINEAR (SERIES-PASS) REGULATOR AND PULSE-WIDTH MODULATED SWITCHING REGULATOR (PWM)
Voltage Reference Section The CA1524 Series devices contain an internal series voltage regulator employing a zener reference to provide a nominal 5 volts output, which is used to bias all internal timing and control circuitry. The output of this regulator is available at terminal 16 and is capable of supplying up to 50mA output current. For higher currents, the circuit of Figure 3 may be used with an external p-n-p transistor and bias resistor. The internal regulator may be bypassed for operation from a xed 5V supply by connecting both terminal 15 and 16 to the input voltage, which must not exceed 6V.
IL TO IA DEPENDING ON CHOICE FOR Q1 16 VREF 10F + -
15 VIN A R1 500 Q1 Q2 Q7 Q6 R12 10K Q3 Q4 R2 2.7K Q10 RC 10K R3 6.3K D1 10K Q11 1.9K R14 450 C4 Q19 RA 5.3K R8 8.4K QA R19 R18 18.7 18.7 K K Q12 R6 500 C2 20pF Q14 R9 500 Q15 N+ P R4 500 8 GND OSC SECTION ERROR AMP Q42 Q43 Q47 Q48 R43 7.4K Q59 Q60 R10 1K Q20 Q22 R15 25K F G H I Q24 PULSE STEERING FLIP-FLOP R17 R18 18.7 18.7 K K Q21 Q23 C Q9 C1 20pF RD Q16 R11 500 R13 6 Q13 Q17 Q18 R5 1K R7 1K REFERENCE SECTION B
D2
RB 4.8K
D E
Q5
6 RT
Q44 Q49 Q50 R44 1.8K Q51 Q46 Q45 R39 1K R41 24K R40 560 R42 19.8K Q52 R45 25K Q53 Q54
Q61
NON-INV. INPUT J
7 CT
Q62
K L
A OUTPUT A B Q33
OUTPUT B
COLL. A
12 Q34
R33 200
Q35
Q40
13
COLL. B
CB 1pF
D3 RE 500
RF 500
Q37
Q38
C R21 43.3K D E R23 8.7K Q26 Q27 F G H I R52 1.96K R54 1.96K COMPARATOR R27 5K R24 5K NOR NOR R30 43.3K
R25 5K
R28 8.7K
COMP 10 9
Q65
Q67
Q68 J R49 1K Q64 Q63 R51 10K CURRENT LIMIT SECTION Q66 Q72 C3 45pF Q68 R53 1.8K
Q70 Q71
R50 10K K L 5
Q73
5.00
4.98
4.96
1.0
FIGURE 8. TYPICAL OUTPUT STAGE DEAD TIME AS A FUNCTION OF TIMING CAPACITOR VALUE
If a small value of CT must be used, the pulse width can be further expanded by the addition of a shunt capacitor in the order of 100pF (but no greater then 1000pF), from terminal 3 to ground. This shunt capacitor will expand the dead time from 0.5s to 5.0s when required. When the oscillator output pulse is used as a sync input to an oscilloscope, the cable and input capacitances may increase the pulse width slightly. A 2k resistor at terminal 3 will usually provide sufcient decoupling of the cable. The upper limit of the pulse width is determined by the maximum duty cycle acceptable. To provide an expansion of the dead time without loading the oscillator, the circuit of Figure 9 may be used.
16
TA = +25oC V+ = 20V OUTPUT DUTY CYCLE (%) 48 40 32 24 16 8 0 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 COMPARATOR VOLTAGE (V) CT =1000pF RT = 5k fOSC = 20kHz CT = 2700pF RT = 6.19k fOSC = 60kHz
5K
This diode clamp will limit the output voltage of the error amplier; it also limits the error ampliers source output current to about 200A. Curves for selecting the values of the oscillator resistor (RT) and the oscillator capacitor (CT), as a function of oscillator period (t), are shown in Figure 10. The oscillator period is determined by RT and CT, with an approximate value of t = RTCT, where RT is in ohms, CT is in F, and t is in s. Excess lead lengths, which product stray capacitances, should be avoided in connecting RT and CT to their respective terminals.
FIGURE 11. TYPICAL DUTY CYCLE AS A FUNCTION OF COMPARATOR VOLTAGE (AT TERMINAL 9)
Error Amplier Section The error amplier consists of a differential pair (Q56, Q57) with an active load (Q61 and Q62) forming a differential transconductance amplier. Since Q61 is driven by a constant current source, Q62, the output impedance ROUT, terminal 9, is very high ( 5M). The gain is:
Av = gmR = 8 lc R/2KT = 104, ROUTRL where R = ROUT = RL RL = , Av 104
104
103 1
10
Since ROUT is extremely high, the gain can be easily reduced from a nominal 104 (80dB) by the addition of an external shunt resistor from terminal 9 to ground as shown in Figure 12. The output amplier terminal is also used to compensate the system for AC stability. The frequency response and phase shift curves are shown in Figure 12. The uncompensated amplier has a single pole at approximately 250Hz and a unity gain crossover at 3MHz.
80 70 VOLTAGE GAIN (dB) 60 50 40 0 RL = RL = 3M RL = 1M RL = 300k RL = 100k OPEN LOOP GAIN PHASE ANGLE (oC) 90o 50 105 103 FREQUENCY (Hz) 104
For example, to obtain an oscillator period (t), select C 1 = 0.1 F and RT = 10k . Based on these values the output dead time is 0.7 s. For series regulator applications, the two outputs can be connected in parallel to provide an effective 0% - 90% duty cycle with the output stage frequency being equal to that of the oscillator. Since separate output terminals are provided, push-pull and flyback applications are possible. The flip-flop divides the frequency such that the duty cycle of each output is 0% - 45% and the overall frequency is half that of the oscillator. Curves of the output duty cycle as a function of the voltage at terminal 9 are shown in Figure 11.
10
102
Due to the low gain of this circuit, there is a transition region as the current limit amplier takes over pulse width control from the error amplier. For testing purposes, the threshold is dened as the input voltage to the current limiting amplier to get 25% duty cycle with the error amplier signaling maximum duty cycle. In addition to constant current limiting, terminal 4 and 5 may also be used in transformer coupled circuits to sense primary current and shorten an output pulse, should transformer saturation occur (See Figure 37). Another application is to ground terminal 5 and use terminal 4 as an additional shutdown terminal: i.e. the output will be off with terminal 4 open and on when it is grounded. Finally, foldback current limiting can be provided with the network of Figure 14. This circuit can reduce the short circuit current (ISC) to approximately 1/3 the maximum available output current (IMAX).
VO = 5V SA//SB R1
R2
I MAX
O - V + ------------------- = -----RS TH R1 + R2 I V TH RS
V R2
RS 5 SENSE
V TH I SC
R1R2 = 2.5KW R1 + R2
FIGURE 14. FOLDBACK CURRENT-LIMITING CIRCUIT USED TO REDUCE POWER DISSIPATION UNDER SHORTED OUTPUT CONDITIONS
Output Section The CA1524 Series outputs are two identical n-p-n transistors with both collectors and emitters uncommitted. Each output transistor response for the wide range of oscillator frequencies. Current limiting of the output section is set at 100mA for each output and 100mA total if both outputs are paralleled. Having both emitters and collectors available provides the versatility to drive either n-p-n or p-n-p external transistors. Curves of the output saturation voltage as a function of temperature and output current are shown in Figures 15 and 16 respectively.
Current Limiting Section The current limiting section consists of two transistors (Q64, Q66) connected to the error amplier output terminal. By matching the base-to-emitter voltages of Q64 and Q66 and assuming negligible voltage drop across R51: VTHRESHOLD = VBE(Q64) + I(Q65)R53 - VBE(Q66) = I(Q65)R53 200mV Although this circuit provides a small threshold with a negligible temperature coefcient, some limitations to its use must be considered. The circuit has a 11 volt common mode range which requires sensing in the ground line. The other factor to consider is that the frequency compensation provided by R51, C3 and Q64 produces a roll-off pole at approximately 300Hz.
0.9 D1 0.8 V+ SA SB 0.7 -75 -50 -25 0 25 50 75 100 125 150 175 V+ SA SB | V+ | > | VO | AMBIENT TEMPERATURE (oC) D1 -VO V+ < VO +VO
NOTE: Diode D1 Is Necessary To Prevent Reverse Emitter-Base Breakdown of Transistor Switch SA FIGURE 17. CAPACITOR-DIODE COUPLED VOLTAGE MULTIPLIER OUTPUT STAGES
SA//SB V+ +VO V+ > VO
1.0
0.5
There are a number of possible output congurations in the application of the CA1524 to voltage regulator circuits, they fall into three basic classications: 1. Capacitor diode coupled voltage multipliers 2. Inductor capacitor single ended circuits 3. Transformer coupled circuits Examples of these congurations are shown in Figures 17, 18 and 19. In each case, the switches can be either the output transistors in the CA1524 or added external transistors, depending on the load current requirements. Capacitor diode coupled voltage multipliers are particularly useful in those low-power applications where inductive components are undesirable. Although the efciencies of these voltage multipliers may not be as good as their inductive component counterparts, they are more efcient than the series-pass circuit.
FIGURE 18. SINGLE-ENDED INDUCTOR CIRCUITS WHERE THE TWO OUTPUTS ARE CONNECTED IN PARALLEL (i.e.; SA//SB)
V+ VO
SA//B
1. Push-Pull circuits 2. Voltage Multipliers; (capacitor diode filters) 3. Half or full bridge circuits The oscillator has a dead band feature to ensure against both output transistors conducting simultaneously. This dead band applies not only to the internal transistors, but for any additional drivers used for push-pull applications. When using push-pull and bridge circuits, the dead time becomes important. Since the frequency of the oscillator is 1/RTCT, a good method for establishing dead band time is to select f first, CT second, and then RT. The value of CT determines the dead time or discharging rate of CT. The curves in Figures 8 and 10 are used for this purpose. The oscillator provides a ramp at the CT terminal with an equivalent dead time pulse at Pin 3 for slaving multiple units. This terminal can also be used as an oscilloscope sync. With an output resistance of 2K at Pin 3, capacitive loading of this terminal will be adequate for most applications, but for larger systems some type of external dead time adjustment must be employed. To provide an expansion of the dead time without loading the oscillator, the simple 5k potentiometer and diode arrangement shown in Figure 9 can be used. The output frequency of each individual output stage is approximately half that of the oscillator frequency. When the stages are connected in parallel, fOSC = fOUT. The selection of components - capacitors, diodes, inductors, transformer cores, etc., depends primarily on the operating frequency of the switching regulator. It is important, therefore, that care be exercised in the selection of these components. Capacitors should have low equivalent series resistance (ESR) and low equivalent series inductance (ESL), because high ESR is the principal cause of capacitor ripple, and high ESL causes high frequency ringing in the MHz region. Most capacitor manufacturers rate capacitance at 120Hz, a frequency quite different from the 20kHz - 100kHz operating frequency of PWM regulator circuits. Because the characteristics of capacitors may change with change in frequency, the careful selection of close tolerance capacitors will tend to offset any degradation in PWM regulator performance resulting from the difference in the frequency rating of capacitor vs PWM regulator circuit operating frequency. Free-wheeling diode clamps must have fast turn on and low distributed capacitance. The DC resistance of inductors should be kept low to minimize the effects of added losses that may occur at high load currents. In addition, the selection of the size and type of transformer core will also depend on the input voltage range and on the output voltage and current requirements.
SA
Q1
+ -
VO
SB
SB
Q2
SA FULL BRIDGE
Single-Ended Applications
+ VIN B CA1524 PWM A C Q1 D1 C1
LI
SA//SB
+
VIN
-
VOUT
-
VIN
-
SA//SB
VOUT
-
The Buck Regulator shown in Figure 20 operates by chopping an unregulated DC voltage. The frequency of the circuit waveforms remains constant but the duty cycle is varied to effect regulation. The output LC filter, together with the free-wheeling diode D1, smooths the chopped waveform. With VO set at some selected level by means of the reference voltage, the sample of the output voltage applied t the input of the CA1524 error amplifier adjusts the duty cycle in response to changes in load currents. When transistor Q1 is turned on diode D1 is nonconductive and current flows from VIN through L1 to +VO. When Q1 is off, the reserve energy in C1 provides the necessary current to the load. The overall output regulation depends primarily on the characteristics of the CA1524 and on the design of the output filter. Switching regulator circuits are categorized for single-ended and dual-ended (bridge) applications. The basic circuits shown in Figures 22 through 30 include an inductive element. In these circuits SA represents transistor A, SB transistor B, and SA/SB indicated that both transistors can be connected in parallel. A description of the single-ended and dual-ended bridge configuration is given in subsequent pages.
VIN TIME VIN-VSAT VIN-V SAT VAK IO IDC TIME VO OUTPUT VOLTAGE TON TOFF WAVEFORM AT B WAVEFORM AT A
VOUT VIN
VIN
-
VOUT
+
FIGURE 24. VARIATION OF THE BOOST OR STEP-UP REGULATOR RESEMBLES THE FLYBACK REGULATOR AND CAN BE EITHER STEP-UP OR STEP-DOWN
VIN SA//SB
-
VOUT
-
FLYBACK CONVERTER
VIN SA//SB
-
VOUT
-
WAVEFORM AT C THIGH TLOW TIME INDUCTOR CURRENT FLYBACK CONVERTER WITH CLAMP WINDING
The clamp winding returns excess stored energy to the line, thereby preventing avalanche in the switching transistor. FIGURE 25. FLYBACK CONVERTER (OPERATING MODEL FOR THIS CONVERTER IS THE BOOST REGULATOR)
10
VIN SA//SB
-
VOUT
-
FORWARD CONVERTER
VIN SA//SB
-
VOUT
-
FIGURE 26. FORWARD CONVERTER (OPERATING MODEL FOR THIS CONVERTER IS THE BUCK REGULATOR)
Dual-Ended (Bridge) Applications For low-to-medium-power applications from 100 to 200 watts.
SA
SB
VOUT SA SB
-
VIN
-
CC -
11
D1 AC IN D2 D1-D4 A15A
D3 36 VDC
2N6388 (PNP DARLINGTON) Q1 R2 1.5 10W 0.01F L1 20mH D5 = RURD410 C3 10000F 100V
7V - 30V 0A - 3A C5 25F C4 0.1F L2 50mH RETURN BIFILAR WINDING C6 25F NON-POLAR VOUT
D4 5100F 100V
R1 1K 1W
NON-POLAR
C7 0.1F R3 10K R6 2K
16
15
14
13
12
11
10
9 R10 16K
CA1524
1 2 3 4 5 6 7 8
R4 5K
R5 2K
VOLTAGE CONTROL
fOSC = 20KHz
SILVER MICA
Although most switching regulator designs and applications imply a xed output voltage, the CA1524 Series can be applied to a variable-output-voltage power supply. This type of circuit provides many advantages:
SA
Q1
+ -
SB VOUT CC
Q3
1. Excellent overall efciency for the full output range; generates less heat, thereby reducing cooling requirements. 2. Input current level maximum output current level. 3. Limited dependence on VIA (i.e., VIN VOUT max. +2) at the power supplys maximum output current level. 4. Light weight due to small, light cores. 5. Space saver. and some disadvantages: 1. Low output voltage due to the limited lower end range of the error amplier (i.e., VOUT min 0, but = 7V in this particular application). 2. Losses in efciency when output current levels are within the range of the no load dissipation for the IC and pass transistor. 3. Time lag in changing voltage levels at no load or light loads. This time lag is due to two conditions: A. VC cannot change instantaneously; and B. CT remains charged since it is not performing its function of supply current to the output load when the free wheeling diode conducts.
SB
Q2
SA
Q4
Capacitor CC and diode clamps have same function as in the half-bridge circuit. In the full-bridge circuit full line voltage can be applied to the primary winding to approximately double the power output of the half-bridge circuit.
Regulator Applications
The Variable Switcher The following review of some of the characteristics and unique design features of a variable switching pulse-widthmodulated (PWM) circuit will provide the equipment designer with some of the basic principles of a PWM circuit and its associated circuitry, and a better understanding of the CA1524 Series ICs intended for this type of application.
12
EFFICIENCY - (%)
90
FIGURE 32A. FIGURE 32. EFFICIENCY CURVE FOR THE VARIABLE OUTPUT VOLTAGE POWER SUPPLY SHOWN IN FIGURE 31
5 REGULATION INPUT CURRENT (A) VO = 30V VO = 25V 4 VO = 20V 3 VO = 15V VO = 10V VO = 7V 1
where tON is the on time in s, T is the oscillator period in s; and Q1 is operating in a saturated mode. The following table shows both the calculated and measured data for the regulator circuit of Figure 31.
VO (ILOAD = 3A) (V) 30 20 10 tON (CALC.) (s) 40.15 26.77 13.88 tON (MEAS.) (s) 40.50 26.45 13.70
FIGURE 32B. FIGURE 32. EFFICIENCY CURVE FOR THE VARIABLE OUTPUT VOLTAGE POWER SUPPLY SHOWN IN FIGURE 3
As the load current increases, the level of the input voltage to the D5-L1-C3 lter network decreases slightly due to an increase in the saturation voltage of Q1. this change in load causes the ON time of Q1s base to increase in proportion to the decrease in voltage at Q1s collector. This decrease in voltage, in turn, adjusts the output voltage at C3. Resistor R7 controls the output voltage level. The efciency curve for the variable output voltage power supply is shown in Figure 32 at load currents in the range of 0.5A to 3A over the full output voltage range (7V - 30V). The efciency of the variable switcher falls short of the ideal due to the losses incurred during the fall time of Q1s collector voltage. Use of a lower frequency would improve efciency, but would require more expensive inductive and capacitive components. Even though the efciency values shown in Figure 32 are appreciably lower at the lower output voltages, the overall efciency of the PWM variable supply is superior to that of the linear variable supply.
13
FIGURE 33A.
All Photos: VIN = 33Vdc, Horizontal - 10s/Div Vertical Scale Factors: Upper Trace: CA1524 Output Voltage (Pins 12, 13) = 20V/Div Middle Trace: Q1 Collector Voltage = 20V/Div NOTES: Lower Trace:L1 Current = 0.5A/Div, Figures 33A, B, D, E; 0.1A/Div, Figures 33C, F
Variable output switching power supply design employ pulse width modulation techniques to achieve high performance. Note that on times of Q1 and the CA1524 are more dependent on the circuits output voltage than by the output current to the load
FIGURE 33. TYPICAL VOLTAGE AND CURRENT WAVEFORMS FOR CA1524 PWM REGULATOR OPERATED WITH P-N-P PASS TRANSISTOR AND SERIES LC AND DIODE FILTER NETWORK
A major factor in the improved efciency of the switching regulator is that output current does not have to be equal to input current as the output voltage swings between the end points of its range. The curves in Figure 32B show the ing regulator accomplishes its high level of efciency. At some combinations of output voltages and currents, the large reservoir energy capacitor (C3) supplies the difference between the required load current and available input current (see Figure 31). Note that the switching regulator has a higher efciency for DC than AC - due primarily to the additional losses caused by the input bridge rectiers D1 through D4 in Figure 31. However, the advantage of the linear regulator is also apparent, it can provide output voltage down to nearly zero volts. Figure 33 shows the variation in ON time as a function of output loadings as measured at the base and collector of Q1 respectively. The regulated output voltages are 30, 20, and 10V, respectively with load currents of from 3A to 1A. The lower curve is the inductor current for the same voltages and loads. Note the change in the duty cycle and inductor current level waveforms in response to the short ON time required to supply the 30V output voltage level.
Radio frequency interference (RFI) is usually generated with any switching regulator and certain networks must be added to minimize this interference. R2 and C2 (Figure 31) provide a snubber network for the switching current transients of diode D5 to reduce the level of the RFI generated. The output lter network L2 and C4 through C6 provides a bilar coil which additionally suppresses the switching noise. Varistors and input L-C lters can also be employed. Pulse-Width Modulator (PWM) Supply Details The CA1524 provides all sense and control functions in the variable output voltage power supply design of Figure 31. In this application, the ICs two alternately switched output stages (pins 12 and 13) are connected in parallel to drive the switching transistor (Q1). The PWM IC provides an on drive signal to Q1 that, in effect, spans a 0% to 90% duty cycle. (The ICs output transistors can each provide a 0% to 45% duty cycle during their alternate on periods, but when the outputs are connected in parallel their separate on times effectively add serially.) This 0% to 90% duty cycle span makes possible the designs wide output voltage/current range without manual switching.
14
V+ +28V R2 5K 5K 0.1F 5K 3K R1 5K 1 2 1 16 1 6 1 7 1 0.02F 3 1 10 1 8 1 CA3524 0.9mH 15 1 12 1 11 1 13 1 14 1 4 1 5 1 9 1 0.001F 50K 0.1 2K RURD410 2N6388 Q1 500F +5V IA
V-
15
V+ +15V R2 15K 1 R1 5K 2 1 16 1 6 1 7 1 0.01F 3 1 10 1 8 1 CA3524 6 1 12 1 IN1341B 11 1 13 1 14 1 4 1 5 1 9 1 0.01F IN4001 50F R1 = 5K R2 = R1 ( | VO | + 2.5) (VREF - 2.5) 20F IN4001 -5V 20mA
5K 5K 0.1F 2K
FIGURE 35. CAPACITOR DIODE OUTPUT CIRCUIT TABLE 1. INPUT vs OUTPUT VOLTAGE AND FEEDBACK RESISTOR VALUES FOR IL = 40mA (For capacitor diode output circuit shown in Figure 35) VO (V) -0.5 -2.5 -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 -9.0 -10 R2 (k) 6 10 11 13 15 17 19 21 23 25 V+ (Min) (V) 8 9 10 11 12 13 14 15 16 17 VO (V) -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 R2 (k) 27 29 31 33 35 37 39 41 43 45 V+ (Min) (V) 18 19 20 21 22 23 24 25 26 27
V+ +5V + 100F 25K 5K 5K 2K 5K 1 2 1 16 1 6 1 7 1 0.02F 3 1 10 1 8 1 CA3524 15 1 300 12 1 11 1 13 1 14 1 4 1 5 1 9 1 + 0.001F 4.7F 2N2102 620 IN914 510 1M 200
RURD620
+15V
50F
0.1F
50F RURD620 2N6290 CORE: FEROX CUBE 2213P - A250 - 387 OR EQUIVALENT -15V
16
Other Applications
Single-Ended Switching Regulator The CA1524 in the circuit of Figure 34 has both output stages connected in parallel to produce an effective 0% 90% duty cycle. Transistor Q1 is pulsed on and off by these output stages. Regulation is achieved from the feedback provided by R1 and R2 to the error amplier which adjusts the on-time of the output transistors according to the load current being drawn. Various output voltages can be obtained by adjusting R1 ad R2. The use of an output inductor requires an R-C phase compensation network to stabilize the system. Current limiting is set at 1.9A by the sense resistor R3. Capacitor Diode Output Circuit A capacitor diode output lter is used in Figure 35 to convert +15Vdc to -5Vdc at output currents up to 50mA. Since the output transistors have built-in current limiting, no additional current limiting is needed. Table 1 gives the required minimum input voltage and feedback resistor values, R2, for an output voltage range of -0.5V to -20V with an output current of 40mA. Flyback Converter Figure 36 shows a yback converter circuit for generating a dual 15V output at 20mA from a 5V regulated line. Reference voltage is provided by the input and the internal reference generator is unused. Current limiting in this circuit is accomplished by sensing current in the primary line and resetting the soft start circuit. Push-Pull Converter The output stages of the CA1524 provide the drive for transistors Q1 and Q2 in the push-pull application of Figure 37. Since the internal ip-op divides the oscillator frequency
17
V+ +28V 5K 1 5K 2K 0.01F 6 1 7 1 3 1 10 1 8 1 CA3524 14 1 4 1 2N6292 5 1 9 1 0.001F 20K 0.1F + 100F RURP1510 2 1 16 1 15 1 1K 1W 12 1 11 1 13 1 1K 20T 5T 1K 20T 5T + 1500F 5V 5A 1K 1W
5K 5K
2N6292
RURP1510 1mH
0.1F
18
2K
TO PIN 9
1.1K
1.1K
R2 10K
1 2 3
16 15 14 V+ = 9V
1/ S2 2
TO PIN 12 OUTPUT 1
2K
4 5 6
CA3524
13 12 11 10 9
1.5K
1/ S1 2
1/ S2 2
OUTPUT 2A 1.5K
1/ S1 2
R1 50K 0.1F
7 8
SWITCH
TO PIN 1
OUTPUT PULSES 0V - 5V -
SILVER MICA
S1 S2
PL1 OSCILLATOR 20KHz (PART OF CA1524) S PL2 AC AMP CA3130 PEAK TO PEAK DETECTOR LOW PASS FILTER
DC VOLTAGE
19
S PL2
300K 9V 2.5V
A B C
16 15 14 13 12 11 10 9
CA1524
4.7K
4.7K 4.7K
6.2K
+5V
ZERO ADJUSTMENT
50K 8
A B C 5 3 4 CA3162E DIGIT DRIVERS 11 HIGH INPUTS: LOW 10 13 GAIN ADJUSTMENT 10K 7 16 15 1 2 6 2 1 7 8 3 CA3161E 13 12 11 10 9 15 14
BCD OUTPUTS
20