TPS735 500-Ma, Low Quiescent Current, Low Noise, High PSRR, Low-Dropout Linear Regulator
TPS735 500-Ma, Low Quiescent Current, Low Noise, High PSRR, Low-Dropout Linear Regulator
TPS735 500-Ma, Low Quiescent Current, Low Noise, High PSRR, Low-Dropout Linear Regulator
TPS735
SBVS087M – JUNE 2008 – REVISED JUNE 2018
TPS735
2.2 µF
EN GND NR
Ceramic
VEN
Optional bypass capacitor, C ,
NR
to reduce output noise
and increase PSRR
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS735
SBVS087M – JUNE 2008 – REVISED JUNE 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 13
2 Applications ........................................................... 1 8.1 Application Information............................................ 13
3 Description ............................................................. 1 8.2 Typical Applications ................................................ 13
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 16
5 Pin Configuration and Functions ......................... 4 10 Layout................................................................... 16
6 Specifications......................................................... 5 10.1 Layout Guidelines ................................................. 16
6.1 Absolute Maximum Ratings ...................................... 5 10.2 Layout Example .................................................... 16
6.2 ESD Ratings.............................................................. 5 10.3 Power Dissipation ................................................. 17
6.3 Recommended Operating Conditions....................... 5 10.4 Estimating Junction Temperature ......................... 18
6.4 Thermal Information .................................................. 6 10.5 Package Mounting ................................................ 19
6.5 Electrical Characteristics........................................... 7 11 Device and Documentation Support ................. 20
6.6 Typical Characteristics .............................................. 8 11.1 Device Support...................................................... 20
7 Detailed Description ............................................ 10 11.2 Documentation Support ........................................ 20
7.1 Overview ................................................................. 10 11.3 Trademarks ........................................................... 20
7.2 Functional Block Diagrams ..................................... 10 11.4 Electrostatic Discharge Caution ............................ 20
7.3 Feature Description................................................. 11 11.5 Glossary ................................................................ 20
7.4 Device Functional Modes........................................ 12 12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Updated data sheet text to latest data sheet and translation standards ............................................................................... 1
• Changed "Ultra-Low Noise" to "Low Noise" in document title ............................................................................................... 1
• Changed Low IQ from 46 μA to 45 μA in Features, Description, and Application Information sections. ................................ 1
• Changed "Standard" to "Ceramic" in Features list ................................................................................................................. 1
• Changed 6-pin package from "SON" to "WSON" in Features list ......................................................................................... 1
• Deleted printers, WiFi®, WiMax Modules, cellular phones, smart phones and microprocessor power from
Applications section ............................................................................................................................................................... 1
• Added post DC/DC ripple filtering, IP network cameras, macro base stations, and thermostats to Applications section ..... 1
• Changed TA to TJ in Description section ............................................................................................................................... 1
• Changed 6-pin package from "SON" to "WSON" in Description section .............................................................................. 1
• Changed package in Device Information table from VSON (6) to WSON (6)........................................................................ 1
• Changed 6-pin DRB package designator from "VSON" to "SON" in Pin Configurations and Functions section .................. 4
• Changed 6-pin DRV package designator from "VSON" to "WSON" in Pin Configurations and Functions section .............. 4
• Added "feedback resistor" parameter to Recommended Operating Conditions table ........................................................... 5
• Changed DRV package designator from "VSON" to "WSON" in Thermal Information table ................................................ 6
• Changed DRB package designator from "VSON" to "SON" in Thermal Information table ................................................... 6
• Changed TPS735 Ground Pin Current (Disable) vs Temperature in Typical Characteristics section ................................... 8
• Changed TPS735 Dropout Voltage vs Output Current in Typical Characteristics section..................................................... 8
• Updated Equation 1 ............................................................................................................................................................. 14
• Changed x-axis scale from "10 ms/div" to "10 µs/div" in Figure 17 ..................................................................................... 15
• Changed x-axis scale from "10 ms/div" to "10 µs/div" in Figure 18 ..................................................................................... 15
• Changed VOUT starting value to 0 V in Figure 19 ................................................................................................................ 15
• Updated Equation 2 ............................................................................................................................................................. 17
• Updated Equation 3 ............................................................................................................................................................. 17
• Changed DRV package designator from "SON" to "WSON" in Measuring Points for TT and TB......................................... 19
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information sections ............................................................................................... 1
• Added first bullet item in Features list ................................................................................................................................... 1
• Changed fourth bullet item in Features list to "fixed outputs of 1.2 V" .................................................................................. 1
• Changed eighth bullet item in Features list ........................................................................................................................... 1
• Changed last bullet in Features list ....................................................................................................................................... 1
• Changed last Applications list item ........................................................................................................................................ 1
• Changed Pin Configuration and Functions section; updated table format and pin descriptions to meet new standards ..... 4
• Changed CNR value notation from 0.01 µF to 10 nF throughout Electrical Characteristics.................................................... 7
• Changed feedback voltage parameter values and measured test conditions ....................................................................... 7
• Changed output current limit maximum specified value ........................................................................................................ 7
• Changed power-supply rejection ratio typical specified values for 100 Hz, 10 kHz, and 100 kHz frequency test
conditions ............................................................................................................................................................................... 7
• Added note (1) to Figure 1 .................................................................................................................................................... 8
• Changed y-axis title for Figure 6 ............................................................................................................................................ 8
• Changed y-axis title for Figure 7 ............................................................................................................................................ 8
• Changed footnote for Figure 13............................................................................................................................................ 10
• Changed reference to noise-reduction capacitor (CNR) to feed-forward capacitor (CFF) in Transient Response................. 11
• Changed noise-reduction capacitor to feed-forward capacitor in Figure 16 ........................................................................ 13
• Changed references to "noise-reduction capacitor" (CNR) to "feed-forward capacitor" (CFF) and section title from
"Feedback Capacitor Requirements" to "Feed-forward Capacitor Requirements" in Feed-Forward Capacitor
Requirements section ........................................................................................................................................................... 14
• Changed CNR value notation from 0.01 µF to 10 nF in Output Noise section...................................................................... 14
• Added last sentence to first paragraph of Startup and Noise Reduction Capacitor section ................................................ 11
• Corrected typo in Electrical Characteristics table for VOUT specification, DRV package test conditions, VOUT ≤ 2.2V........... 7
• Revised bullet point in Features list to show very low dropout of 280 mV............................................................................. 1
• Changed dropout voltage typical specification from 250mV to 280mV.................................................................................. 7
OUT 1 8 IN OUT 1 6 IN
Thermal
NC 2 7 NC FB,NR 2 Pad 5 NC
Thermal
Pad
FB,NR 3 6 NC GND 3 4 EN
GND 4 5 EN
Not to scale
Pin Functions
PIN
NO I/O DESCRIPTION
NAME
DRV DRB
Input supply. A 0.1-µF to 1-µF, low ESR capacitor must be placed from this pin to ground
IN 6 8 I
near the device.
GND 3 4 — Ground. The pad must be tied to GND.
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator
EN 4 5 I
into shutdown mode. The EN pin can be connected to the IN pin if not used.
This pin is only available for the fixed voltage versions. Connecting an external capacitor to
NR 2 3 — this pin bypasses noise that is generated by the internal band gap and allows the output
noise to be reduced to very low levels. The maximum recommended capacitor is 0.01 μF.
This pin is only available for the adjustable version. The FB pin is the input to the control-loop
FB 2 3 I error amplifier, and is used to set the output voltage of the device. This pin must not be left
floating.
This pin is the output of the regulator. A small, 2.2-μF ceramic capacitor is required from this
OUT 1 1 O pin to ground to assure stability. The minimum output capacitance required for stability is 2
µF.
NC 5 2, 6, 7 — Not internally connected.
Thermal pad —
6 Specifications
6.1 Absolute Maximum Ratings
at –40°C ≤ TJ and TA ≤ +125°C (unless otherwise noted). All voltages are with respect to GND. (1)
MIN MAX UNIT
VIN –0.3 7 V
VEN –0.3 VIN + 0.3 V
Voltage
VFB –0.3 1.6 V
VOUT –0.3 VIN + 0.3 V
IOUT Current Internally limited A
PD(tot) Continuous total power dissipation See Thermal Information
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed as Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated as Recommended Operating Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2 x 2 thermal via array.
ii. DRV: The exposed pad is connected to the PCB ground layer through a 2 x 2 thermal via array. Due to size limitation of thermal
pad, 0.8-mm pitch array is used which is off the JEDEC standard.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
ii DRV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-in × 3-in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections.
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
0.5 0.5
TJ = 125°C
0.4 0.4 TJ = 85°C
Change in Output Voltage (%)
2.52
2.82 TJ = –40°C
2.81 2.51
2.8 2.5
2.79 2.49
2.78
2.48
2.77
2.47
2.76
2.75 2.46
2.74 2.45
0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500
Load (mA) Load (mA)
The y-axis range is ±2% of 2.8 V The y-axis range is ±2% of 2.5 V
50
400 VIN = 3.3 V
Ground Pin Current (nA)
350
40
300
30 250
TJ = 125°C 200
20
TJ = 85°C 150
TJ = 25°C 100
10 TJ = 0°C
50
TJ = –40°C
0 0
0 50 100 150 200 250 300 350 400 450 500 -40 -25 -10 5 20 35 50 65 80 95 110 125
Output Current (mA) Junction Temperature (°C)
Figure 5. TPS735 Ground Pin Current vs Figure 6. TPS735 Ground Pin Current (Disable) vs
Output Current Temperature
TJ = +25°C 60
250
PSRR (dB)
50
200
TJ = 0°C 40
150 IOUT = 1 mA
TJ = –40°C 30
IOUT = 100 mA
100 20 IOUT = 200 mA
50 10 IOUT = 250 mA
IOUT = 500 mA
0 0
0 50 100 150 200 250 300 350 400 450 500 10 100 1k 10k 100k 1M 10M
Output Current (mA) Frequency (Hz)
VEN = 0.4 V (VIN – VOUT = 1 V)
Figure 7. TPS735 Dropout Voltage vs Output Current Figure 8. Power-Supply Ripple Rejection vs Frequency
90 90
80 80
70 70
60 60
PSRR (dB)
PSRR (dB)
50 50
40 40
IOUT = 1 mA
30 30 IOUT = 1 mA
IOUT = 100 mA
IOUT = 100 mA
20 IOUT = 200 mA 20
IOUT = 200 mA
IOUT = 250 mA
10 10 IOUT = 250 mA
IOUT = 500 mA IOUT = 500 mA
0 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)
(VIN – VOUT = 0.5 V) (VIN – VOUT = 0.3 V)
Figure 9. Power-Supply Ripple Rejection vs Frequency Figure 10. Power-Supply Ripple Rejection vs Frequency
140 30
120 25
Total Noise (mVRMS)
100
20
80
15
60
10
40
20 5
0 0
0.01 0.1 1 10 0 5 10 15 20 25
Capacitance on the NR Pin (nF) Output Capacitance (mF)
CNR = 0.01 µF, IOUT = 1 mA
Figure 11. TPS73525 RMS Noise vs CNR Figure 12. TPS735 RMS Noise vs COUT
7 Detailed Description
7.1 Overview
The TPS735 of low dropout (LDO) regulator combines the high performance required by radio frequency (RF)
and precision analog applications with ultra-low current consumption. High PSRR is provided by a high-gain,
high-bandwidth error loop with good supply rejection and very low headroom (VIN – VOUT). Fixed voltage versions
provide a noise reduction pin to bypass noise that is generated by the band-gap reference and to improve PSRR.
A quick-start circuit fast-charges this capacitor at start-up. The combination of high performance and low ground
current make the TPS735 device designed for portable applications. All versions have thermal and overcurrent
protection and are specified from –40°C ≤ TJ ≤ +125°C.
IN OUT
400 W
2 mA
Current
Limit
EN Thermal Overshoot
Shutdown Detect
UVLO
Quickstart
1.208 V
(1) NR
Bandgap
500 kW
GND
(1) The 1.2-V fixed voltage version has a 1-V band gap instead of a 1.208-V circuit.
IN OUT
400 W
Current 3.3 MW
Limit
EN Thermal Overshoot
Shutdown Detect
UVLO
1.208 V
FB
Bandgap
500 kW
GND
7.3.2 Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage TTL-CMOS levels. When
shutdown capability is not required, the EN pin can connect to the IN pin.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input voltage is less than the UVLO threshold minus Vhys, or has not yet exceeded the UVLO threshold.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 lists the conditions that result in different modes of operation.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
V IN OUT V
IN OUT
TPS735
2.2 µF
EN GND NR
Ceramic
V
EN Optional bypass capacitor
to reduce output noise
and increase PSRR.
V IN OUT V
IN OUT
TPS735 R C
1 FF
2.2 µF
EN GND FB Ceramic
R
2
V
EN
3.5 3.5
3 3
2.5 2.5
2 2
Voltage (V)
Voltage (V)
1.5 1.5
1 1
Figure 17. TPS735 Turnon Response (VIN = VEN) Figure 18. TPS735 Turnon Response Using EN
7
VOUT COUT = 470 mF OSCON
6 200 mV/div
VIN = VEN COUT = 10 mF
5 200 mV/div
4
Voltage (V)
COUT = 2.2 mF
200 mV/div
3
1 VOUT
500 mA IOUT
0
500 mA/div 1 mA
-1
10 ms/div 10 ms/div
RL = 5 Ω VIN = 3 V
Figure 19. TPS73525 Power-Up and Power-Down Figure 20. TPS735 Load Transient Response
(VIN = VEN)
4V
VOUT
VIN
0.5 V/div 3V
10 ms/div
10 Layout
Input GND
Plane
VOUT
CIN(1)
OUT 1 8 IN
NC 2 7 NC VIN
CNR(1) Thermal
COUT(1)
Pad
NR/FB 3 6 NC
GND 4 5 EN
Output GND
Plane
(1) CIN and COUT are 0603 capacitors and CNR is a 0402 capacitor. The footprint is shown to scale with package size.
NOTE
When the device is used in a condition of high input and low output voltages, PD can
exceed the junction temperature rating even when the ambient temperature is at room
temperature.
Equation 3 is an example calculation for the power dissipation (PD) of the DRB package.
PD = (6.5 V - 1.2 V) ´ 500 mA = 2.65 W
(3)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output performance.
On the DRB package, the primary conduction path for heat is through the exposed thermal pad to the PCB. The
pad can be connected to ground or left floating. The pad must be attached to an appropriate amount of copper
PCB area to ensure that the device does not overheat. The maximum allowable junction-to-ambient thermal
resistance depends on the maximum ambient temperature, maximum device junction temperature, and power
dissipation of the device. Equation 4 calculates the maximum junction-to-ambient thermal resistance.
125qC TA
RTJA
PD (4)
100
qJA (°C/W)
80
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10
Board Copper Area (in2)
Note: θJA value at board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard.
Figure 23 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effects of heat spreading in the ground plane and must not be used to estimate
actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction Temperature section.
where:
• PD is the power dissipation calculated with Equation 2,
• TT is the temperature at the center-top of the device package, and
• TB is the PCB temperature measured 1 mm away from the device package on the PCB surface (as shown in
Figure 25). (5)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see Using New Thermal Metrics, available for download at
www.ti.com.
30
15
10
DRV Y
JT
5 DRB
0
0 1 2 3 4 5 6 7 8 9 10
Board Copper Area (in2)
TT on top
of device TT on top
of device
TB on PCB TB on PCB
surface surface
1 mm 1 mm
(a) Example DRB (SON) Package Measurement (b) Example DRV (WSON) Package Measurement
(1) Power dissipation may limit operating range. See Thermal Information .
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 13-Jun-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPS73501DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBK
& no Sb/Br)
TPS73501DRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBK
& no Sb/Br)
TPS73501DRVR ACTIVE WSON DRV 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 SDR
& no Sb/Br)
TPS73501DRVT ACTIVE WSON DRV 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 SDR
& no Sb/Br)
TPS73512DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTT
& no Sb/Br)
TPS73512DRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTT
& no Sb/Br)
TPS73515DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWH
& no Sb/Br)
TPS73515DRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWH
& no Sb/Br)
TPS73525DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBM
& no Sb/Br)
TPS73525DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBM
& no Sb/Br)
TPS73525DRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBM
& no Sb/Br)
TPS73525DRVR ACTIVE WSON DRV 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 NSW
& no Sb/Br)
TPS73525DRVT ACTIVE WSON DRV 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 NSW
& no Sb/Br)
TPS73527DRVR ACTIVE WSON DRV 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAK
& no Sb/Br)
TPS73527DRVT ACTIVE WSON DRV 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAK
& no Sb/Br)
TPS735285DRVR ACTIVE WSON DRV 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAW
& no Sb/Br)
TPS735285DRVT ACTIVE WSON DRV 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAW
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jun-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPS73533DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CVY
& no Sb/Br)
TPS73533DRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CVY
& no Sb/Br)
TPS73533DRVR ACTIVE WSON DRV 6 3000 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM -40 to 125 CVY
& no Sb/Br) CU NIPDAUAG
TPS73533DRVT ACTIVE WSON DRV 6 250 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM -40 to 125 CVY
& no Sb/Br) CU NIPDAUAG
TPS73534DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTU
& no Sb/Br)
TPS73534DRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTU
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jun-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive: TPS735-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Dec-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Dec-2018
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Dec-2018
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73525DRBR SON DRB 8 3000 338.0 355.0 50.0
TPS73525DRBT SON DRB 8 250 338.0 355.0 50.0
TPS73525DRVR WSON DRV 6 3000 203.0 203.0 35.0
TPS73525DRVT WSON DRV 6 250 203.0 203.0 35.0
TPS73527DRVR WSON DRV 6 3000 205.0 200.0 33.0
TPS73527DRVR WSON DRV 6 3000 203.0 203.0 35.0
TPS73527DRVT WSON DRV 6 250 203.0 203.0 35.0
TPS735285DRVR WSON DRV 6 3000 203.0 203.0 35.0
TPS735285DRVT WSON DRV 6 250 203.0 203.0 35.0
TPS73533DRBR SON DRB 8 3000 338.0 355.0 50.0
TPS73533DRBT SON DRB 8 250 338.0 355.0 50.0
TPS73533DRVR WSON DRV 6 3000 205.0 200.0 33.0
TPS73533DRVR WSON DRV 6 3000 203.0 203.0 35.0
TPS73533DRVT WSON DRV 6 250 203.0 203.0 35.0
TPS73533DRVT WSON DRV 6 250 205.0 200.0 33.0
TPS73534DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS73534DRBT SON DRB 8 250 210.0 185.0 35.0
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DRV 6 WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A SCALE 5.500
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2.1 A
B
1.9
0.8
0.7 C
SEATING PLANE
0.08 C
(0.2) TYP
1 0.1 0.05
EXPOSED 0.00
THERMAL PAD
3
4
2X
7
1.3 1.6 0.1
6
1
4X 0.65
0.35
6X
PIN 1 ID 0.3 0.25
6X
(OPTIONAL) 0.2 0.1 C A B
0.05 C
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRV0006A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
(1)
1 7
6X (0.3) 6
SYMM (1.6)
(1.1)
4X (0.65)
4
3
( 0.2) VIA
TYP (1.95)
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
DRV0006A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
6X (0.45)
METAL
1 7
6X (0.3) 6
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OUTLINE
DRB0008A SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3.1 B
A
2.9
C
1 MAX
SEATING PLANE
0.05 DIM A
0.00 0.08 C
OPT 1 OPT 2
1.5 0.1 (0.1) (0.2)
4X (0.23)
EXPOSED (DIM A) TYP
THERMAL PAD
4 5
2X
1.95 1.75 0.1
8
1
6X 0.65
0.37
8X
0.25
PIN 1 ID 0.1 C A B
(OPTIONAL)
(0.65) 0.05 C
0.5
8X
0.3
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8X (0.31) 1 8
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
( 0.2) VIA
TYP (0.23)
(0.5)
(2.8)
EXPOSED EXPOSED
METAL METAL
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRB0008A VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
8X (0.6) TYP
4X
(0.725)
8X (0.31) 1 8
(2.674)
SYMM
(1.55)
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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