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    ASIC Design 2010 April (02 Ad)

    Uploaded by

    Anand Raj
    The document is an exam paper for an ASIC Design course. It contains 10 questions about ASIC design flow, types of ASICs, transmission gates, datapath elements, antifuses, EPROM/EEPROM technology, Altera Flex Logic Array Blocks, logic glitches, logic array blocks in Altera MAX 9000 interconnect architecture, CFI design representation, Xilinx LCA interconnect architecture, EDIF, behavioral VHDL programs to implement a 4:1 multiplexer and D flip flop, types of fault simulation, boundary scan test, global and detailed routing, system partitioning algorithms, design rule check, clock routing, and goals of floor planning.

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    Download as PDF, TXT or read online from Scribd

    ASIC Design 2010 April (02 Ad)

    Uploaded by

    Anand Raj
    16 views1 page
    The document is an exam paper for an ASIC Design course. It contains 10 questions about ASIC design flow, types of ASICs, transmission gates, datapath elements, antifuses, EPROM/EEPROM technology, Altera Flex Logic Array Blocks, logic glitches, logic array blocks in Altera MAX 9000 interconnect architecture, CFI design representation, Xilinx LCA interconnect architecture, EDIF, behavioral VHDL programs to implement a 4:1 multiplexer and D flip flop, types of fault simulation, boundary scan test, global and detailed routing, system partitioning algorithms, design rule check, clock routing, and goals of floor planning.

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    ASIC Design 2010 April (02 Ad) cusat Btech question paper

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    ASIC Design 2010 April (02 Ad) -

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    The document is an exam paper for an ASIC Design course. It contains 10 questions about ASIC design flow, types of ASICs, transmission gates, datapath elements, antifuses, EPROM/EEPROM technology, Altera Flex Logic Array Blocks, logic glitches, logic array blocks in Altera MAX 9000 interconnect architecture, CFI design representation, Xilinx LCA interconnect architecture, EDIF, behavioral VHDL programs to implement a 4:1 multiplexer and D flip flop, types of fault simulation, boundary scan test, global and detailed routing, system partitioning algorithms, design rule check, clock routing, and goals of floor planning.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    16 views1 page

    ASIC Design 2010 April (02 Ad)

    Uploaded by

    Anand Raj
    The document is an exam paper for an ASIC Design course. It contains 10 questions about ASIC design flow, types of ASICs, transmission gates, datapath elements, antifuses, EPROM/EEPROM technology, Altera Flex Logic Array Blocks, logic glitches, logic array blocks in Altera MAX 9000 interconnect architecture, CFI design representation, Xilinx LCA interconnect architecture, EDIF, behavioral VHDL programs to implement a 4:1 multiplexer and D flip flop, types of fault simulation, boundary scan test, global and detailed routing, system partitioning algorithms, design rule check, clock routing, and goals of floor planning.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    BTS (C) VIII 10 004 I

    B. Tech Degree VIII Semester Examination, April 2010


    EC/EI 804 (B) ASIC DESIGN (2002 Scheme) Time : 3 Hours Maximum Marks : 100

    I.

    II.

    With neat diagrams, explain about ASIC Design flow. Explain about any four types of ASICS. OR Explain briefly on transmission gates. Realise a 2:1 Mux using transmission gates. What is meant by datapath elements? Explain different types. What are the functions of antifuses? Draw the cross section of actel antifuse and explain how it works. Write about EPROM and EEPROM technology used in ASIC. OR With neat diagrams explain the working of Altera Flex Logic Array Block. What do you mean by Logic Glitch with an example, show how glitches are generated due to supply bounce? With neat figure, explain the logic array blocks within the ALTERA MAX 9000 interconnect architecture. Explain about CFI design representation with an example. OR Describe the salient features of Xilinx LCA interconnect architecture. Write a short note on EDIF. Write a behavioral program in VHDL to implement a 4:1 multiplexer. Explain the different types of fault simulation. OR Explain how Boundary Scan Test is carried out. Write a behavioral program in VHDL to implement a D Flip Flop.

    (10) (10) (10) (10)

    III.

    (10) (10) (10) (10)

    IV.

    V.

    (10) (10) (12) (8)

    VI.

    VII.

    (10) (10) (10) (10)

    VIII.

    IX.

    X.

    (a) (b)

    Distinguish between global routing and detailed routing. What are the goals and objectives of system partitioning? Explain any one algorithm for partitioning. OR Explain about Design Rule Check Clock Routing. Explain about the goals and objectives of floor planning.
    ***

    (8) (12)

    (10) (10)

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