Digital Signal Processing (DSP)

Nowadays, in the field of communications, AEC (acoustic echo cancellation) is truly essential with respect to the quality of multimedia transmission. In this paper, we designed and developed an efficient AEC based on adaptive filters to improve quality of service in telecommunications against the phenomena of acoustic echo, which is indeed a problem in hands-free communications.

The main advantage of the proposed algorithm is its capacity of tracking non-stationary signals such as acoustic echo. In this work the acoustic echo cancellation (AEC) is modeled using a digital signal processing technique especially Simulink Blocksets. The algorithm’s code is generated in Matlab Simulink programming environment. At simulation level, results of simulink implementation prove that module behavior is realistic when it comes to cancellation of echo in hands free communication using adaptive algorithm.

Results obtained with our algorithm in terms of ERLE criteria are confronted to IUT-T recommendation G.168.

In this paper, a novel architecture of RNS based 1D Lifting Integer Wavelet Transform (IWT) has been introduced. Advantage of Residue Number System (RNS) based Lifting Scheme over RNS based Filter Bank and non-binary IWT has been discussed. The performance of traditional predicts and updates stage of binary Lifting Scheme (LS) for Discrete Wavelet Transform (DWT) generates huge carry propagation delay, power and complexity. As a result non binary number system is becoming popular in the field of Digital Signal Processing (DSP) due to its efficient performance. In this paper also a new fixed number ROM based RNS division circuit has been proposed. The proposed architecture has been validated on Xilinx Vertex5 FPGA platform and the corresponding result and reports are shown in here.

The radix (R) used in Multiple-Valued Logic (MVL) circuits goes beyond the binary case (R = 2). MVLRead Only Memory (ROM), Random Access Memory (RAM), and Digital Signal Processing (DSP) systems have been successfully implemented using Complementary Metal Oxide Semiconductor (CMOS) Technology. The complexity of exact synthesis of MVL circuits is prohibitively large. This is because of the enormous solution search space. The Direct Cover (DC) algorithm is a well-known heuristic for synthesis of MVL functions. The algorithm selects the next minterm to be covered and the appropriate implicant to cover it in an iterative manner using a set of synthesis criteria. Evolutionary algorithms, such as Genetic Algorithms (GAs) and Ant Colony (ACO) have also been successfully used in synthesis of MVL functions. In this paper, we introduce and compare synthesis of MVL functions using the GAs and ACO with the corresponding synthesis using the conventional DC algorithm. Our comparison is based on synthesizing a benchmark consisting of 50000 randomly generated 2-variable 4-valued randomly generated functions. The obtained results showed that the average number of product terms (PTs) needed to synthesize a given MVL function using evolutionary techniques outperforms those obtained using conventional DC heuristics. Among the two techniques it is shown that the technique based on the ACO achieves the best results.