research-article

Adaptive wear-leveling algorithm for PRAM main memory with a DRAM buffer

Authors:

Kyu Ho ParkAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 13, Issue 4

Article No.: 88, Pages 1 - 25

https://doi.org/10.1145/2558427

Published: 10 March 2014 Publication History

Abstract

Phase Change RAM (PRAM) is a candidate to replace DRAM main memory due to its low idle power consumption and high scalability. However, its latency and endurance have generated problems in fulfilling its main memory role. The latency can be treated with a DRAM buffer, but the endurance problem remains, with three critical points that need to be improved despite the use of, existing wear-leveling algorithms. First, existing DRAM buffering schemes do not consider write count distribution. Second, swapping and shifting operations are performed statically. Finally, swapping and shifting operations are loosely coupled with a DRAM buffer. As a remedy to these drawbacks, we propose an adaptive wear-leveling algorithm that consists of three novel schemes for PRAM main memory with a DRAM buffer. The PRAM-aware DRAM buffering scheme reduces the write count and prevents skewed writing by considering the write count and clean data based on the least recently used (LRU) scheme. The adaptive multiple swapping and shifting scheme makes the write count even with the dynamic operation timing, the number of swapping pages being based on the workload pattern. Our DRAM buffer-aware swapping and shifting scheme reduces overhead by curbing additional swapping and shifting operations, thus reducing unnecessary write operations. To evaluate the wear-leveling effect, we have implemented a PIN-based wear-leveling simulator. The evaluation confirms that the PRAM lifetime increases from 0.68 years with the previous wear-leveling algorithm to 5.32 years with the adaptive wear-leveling algorithm.

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Cited By

Liu RJin PWu ZWang XWan SHua B(2019)Efficient Wear Leveling for PCM/DRAM-Based Hybrid Memory2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2019.00273(1979-1986)Online publication date: Aug-2019
https://doi.org/10.1109/HPCC/SmartCity/DSS.2019.00273
Wang SYuan JLi XQian ZArena FYou I(2019)Active Data Replica Recovery for Quality-Assurance Big Data Analysis in IC-IoTIEEE Access10.1109/ACCESS.2019.29322597(106997-107005)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2019.2932259
Zhou FWu SJia YGao XJin HLiao XYuan P(2019)VAIL: A Victim-Aware Cache Policy to Improve NVM Lifetime for Hybrid Memory SystemParallel Computing10.1016/j.parco.2018.12.005Online publication date: May-2019
https://doi.org/10.1016/j.parco.2018.12.005
Show More Cited By

Index Terms

Adaptive wear-leveling algorithm for PRAM main memory with a DRAM buffer
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 13, Issue 4

Regular Papers

November 2014

647 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2592905

Editor:
Sandeep K. Shukla
Virginia Tech, USA

Issue’s Table of Contents

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 10 March 2014

Accepted: 01 November 2013

Revised: 01 September 2013

Received: 01 December 2012

Published in TECS Volume 13, Issue 4

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Cited By

Liu RJin PWu ZWang XWan SHua B(2019)Efficient Wear Leveling for PCM/DRAM-Based Hybrid Memory2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2019.00273(1979-1986)Online publication date: Aug-2019
https://doi.org/10.1109/HPCC/SmartCity/DSS.2019.00273
Wang SYuan JLi XQian ZArena FYou I(2019)Active Data Replica Recovery for Quality-Assurance Big Data Analysis in IC-IoTIEEE Access10.1109/ACCESS.2019.29322597(106997-107005)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2019.2932259
Zhou FWu SJia YGao XJin HLiao XYuan P(2019)VAIL: A Victim-Aware Cache Policy to Improve NVM Lifetime for Hybrid Memory SystemParallel Computing10.1016/j.parco.2018.12.005Online publication date: May-2019
https://doi.org/10.1016/j.parco.2018.12.005
Shang FLiu CWang W(2019)Hotness-aware page partition management methodNeural Computing and Applications10.1007/s00521-018-3668-x31:1(133-146)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s00521-018-3668-x
Jia YZhou FGao XWu SJin HLiao XYuan P(2018)VAILProceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores10.1145/3178442.3178451(79-84)Online publication date: 24-Feb-2018
https://dl.acm.org/doi/10.1145/3178442.3178451
Zhao MXue YHu JYang CLiu TJia ZXue C(2017)State Asymmetry Driven State Remapping in Phase Change MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256140836:1(27-40)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2561408
Wu ZJin PYue L(2015)Efficient Space Management and Wear Leveling for PCM-Based Storage SystemsAlgorithms and Architectures for Parallel Processing10.1007/978-3-319-27140-8_54(784-798)Online publication date: 16-Dec-2015
https://doi.org/10.1007/978-3-319-27140-8_54
Yi Wang Min Huang Zili Shao Chan HBathen LDutt N(2014)A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.234792933:11(1623-1631)Online publication date: Nov-2014
https://doi.org/10.1109/TCAD.2014.2347929

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