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Test generation for MOS circuits using D-algorithm

Authors:

Sunil K. Jain,

Vishwani D. AgrawalAuthors Info & Claims

DAC '83: Proceedings of the 20th Design Automation Conference

Pages 64 - 70

Published: 27 June 1983 Publication History

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Abstract

An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both, the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the “memory” state caused by the “open” transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.

References

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K. W. Chiang and Z. G. Vranesic, "Test Generation for MOS Complex Gate Networks," 12th International Symposium on Fault-Tolerant Computing, Santa Monica, CA, June 22-24, 1982, Digest of Papers, pp. 149-157.

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Y. H. Levendel and P. R. Menon, private communication.

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Burchard JErb DReddy SSingh ABecker B(2018)On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277282537:10(2152-2165)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2772825
Burchard JErb DSingh AReddy SBecker B(2017)Fast and waveform-accurate hazard-aware SAT-based TSOF ATPGProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130478(422-427)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130478
Psarakis MGizopoulos DPaschalis A(1998)Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test ToolsJournal of Electronic Testing: Theory and Applications10.1023/A:100838992080613:3(315-319)Online publication date: 1-Dec-1998
https://dl.acm.org/doi/10.1023/A%3A1008389920806
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Test generation for MOS circuits using D-algorithm
1. Hardware

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Published In

DAC '83: Proceedings of the 20th Design Automation Conference

June 1983

700 pages

ISBN:0818600268

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IEEE Press

Publication History

Published: 27 June 1983

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Burchard JErb DReddy SSingh ABecker B(2018)On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277282537:10(2152-2165)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2772825
Burchard JErb DSingh AReddy SBecker B(2017)Fast and waveform-accurate hazard-aware SAT-based TSOF ATPGProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130478(422-427)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130478
Psarakis MGizopoulos DPaschalis A(1998)Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test ToolsJournal of Electronic Testing: Theory and Applications10.1023/A:100838992080613:3(315-319)Online publication date: 1-Dec-1998
https://dl.acm.org/doi/10.1023/A%3A1008389920806
Sachdev M(1997)Open Defects in CMOS RAM Address DecodersIEEE Design & Test10.1109/54.58773814:2(26-33)Online publication date: 1-Apr-1997
https://dl.acm.org/doi/10.1109/54.587738
Sachdev M(1996)Test and Testability Techniques for Open Defects in RAM Address DecodersProceedings of the 1996 European conference on Design and Test10.5555/787259.787560Online publication date: 11-Mar-1996
https://dl.acm.org/doi/10.5555/787259.787560
Jha N(1993)Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail CheckersIEEE Transactions on Computers10.1109/12.20479142:2(179-189)Online publication date: 1-Feb-1993
https://dl.acm.org/doi/10.1109/12.204791
Lee HHa DSmith R(1991)SOPRANOProceedings of the 27th ACM/IEEE Design Automation Conference10.1145/123186.123432(660-666)Online publication date: 3-Jan-1991
https://dl.acm.org/doi/10.1145/123186.123432
Flottes MLandrault CPravossoudovitch SAdshead GJess J(1990)Fault modelling and fault equivalence in CMOS technologyProceedings of the conference on European design automation10.5555/949970.950062(407-412)Online publication date: 12-Mar-1990
https://dl.acm.org/doi/10.5555/949970.950062
Darlay FCourtois BAdshead GJess J(1990)Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networksProceedings of the conference on European design automation10.5555/949970.950048(344-349)Online publication date: 12-Mar-1990
https://dl.acm.org/doi/10.5555/949970.950048
Wang JKuo TLee JThomas D(1989)A new approach to derive robust sets for stuck-open faults in CMOS combinational logic circuitsProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74514(726-729)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74514
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