This paper describes the design, implementation and performance of a fiat edge-based circuit extractor for NMOS circuits. The extractor is able to work on large and complex designs, it can handle arbitrary geometry, and outputs a comprehensive wirelist. ...

This Paper outlines a methodology for design verification of very large networks based on Concurrent Simulation and Clock Suppression. Concurrent Simulation is expected to yield a 30:1 to 600:1 speed advantage over conventional (serial) simulation when ...

A program is described which was designed primarily to automatically place 5000 gate circuits comprising irregular drop-in components onto the UK5000 type gate array. The architecture of this array is unique, having latch cells together with basic logic ...

This paper describes a data structure to represent the driver-load configurations in MOS circuits, which is used universally in the MOTIS simulation environment. In particular, the data structure is used in mixed-mode evaluation including timing, and ...

Edisim and Edicap are new CAD tools that greatly simplify the use of simulation in LSI design. Unlike previous simulator systems which require the user to type in commands textually, the edisim/edicap user works directly from the chip layout displayed ...

Folding is a scheme to reduce the silicon area in Programmable Logic Array (PLA) design. Since optimum folding is an NP-complete problem, methods for estimating potential area saving are desirable. In the case of row folding, both the upper and lower ...

In the past decade significant effort has been devoted to the development of methodologies for design at the register-transfer level. However, effective and versatile procedures are still not available. This paper presents an efficient procedure for the ...

HEX is a general purpose geometric feature extractor with an integrated circuit layout emphasis. It differs from previous extractors in that it is process-independent and has the ability to do a simple or detailed extraction of circuit features ...

The design and verification subsystem (DAV) within IBM's engineering design system (EDS) was developed to significantly increase logic designer productivity. To obtain this gain in productivity, emphasis was placed on creating a system environment which ...

It is becoming increasingly important that the photomasks needed for a VLSI circuit be produced correctly the first time. To obtain good masks, both the design of the chips and their arraying onto masks must be correct. Much attention has been given to ...

Automatic logic synthesis is the generation of system design directly from system specification. It deals almost entirely with digital systems. With Very Large Scale Integration (VLSI), the human system designer is being pushed to his limits, so the ...

This paper describes a program which generates test patterns for scan design circuits with tri-state modules and bidirectional terminals. The test generation procedure uses a path sensitization technique with 14 signal values. The principal features of ...

The paper presents a digital logic modeling system based on MODLAN language. MODLAN, the Hardware Description Language (HDL), is especially useful for hierarchical modeling of microprocessor systems. The modeling system supports both natural design ...

Based on Computer Design Language and Instruction Set Processor Specification, the language CDLM is proposed as a system both for design verification at different levels of abstraction and for dynamic verification of design refinement steps. After ...

The paper presents some aspects of structural, functional and behavioral modeling with MODLAN. MODLAN is especially useful for hierarchical modeling of microprocessor systems. At each design stage a user is provided with MODLAN language constructs ...

This paper describes a method to generate a path between any point of an “input segment” or an “output segment”, appearing inside a topological optimized PLA, and any point of the vicinity of the corresponding input or output terminal node, located on ...

A system that automates Programmable Logic Array optimization and synthesis for VLSI design is described. PLA logic is defined via a high level Hardware Definition Language. After translation to table representation comes the logic optimization phase, ...

The Carnegie-Mellon University Design Automation system (CMU-DA) [2] consists of a set of computer programs whose goal is to produce a complete design in a user-specified device technology, given as input a behavioral description of the piece of ...

This :paper presents the approach of MIT's Placement-Interconnect (PI) Project to routing noncrossing VDD and GND trees in single-layer metal. The input to the power-ground phase is a set of rectangular modules on a rectangular chip. There is one VDD ...

Experiments performed with the SLIM symbolic circuit compactor are described. The experiments were designed to compare SLIM created modules to manually created modules, to attempt to find performance predictors for SLIM, and to determine how well SLIM ...