The paper presents some aspects of structural, functional and behavioral modeling with MODLAN. MODLAN is especially useful for hierarchical modeling of microprocessor systems. At each design stage a user is provided with MODLAN language constructs ...

This paper describes a method to generate a path between any point of an “input segment” or an “output segment”, appearing inside a topological optimized PLA, and any point of the vicinity of the corresponding input or output terminal node, located on ...

A system that automates Programmable Logic Array optimization and synthesis for VLSI design is described. PLA logic is defined via a high level Hardware Definition Language. After translation to table representation comes the logic optimization phase, ...

The Carnegie-Mellon University Design Automation system (CMU-DA) [2] consists of a set of computer programs whose goal is to produce a complete design in a user-specified device technology, given as input a behavioral description of the piece of ...

This :paper presents the approach of MIT's Placement-Interconnect (PI) Project to routing noncrossing VDD and GND trees in single-layer metal. The input to the power-ground phase is a set of rectangular modules on a rectangular chip. There is one VDD ...

Experiments performed with the SLIM symbolic circuit compactor are described. The experiments were designed to compare SLIM created modules to manually created modules, to attempt to find performance predictors for SLIM, and to determine how well SLIM ...

We present algorithms for performing connectivity analysis, transistor identification, and boolean geometric operations with region numbering. Previous methods all require O(n) space where n is the number of edges in the circuit artwork; our method ...

A general algorithm is presented for consistency checking between schematics. A transistor level schematic is partitioned into functional blocks by tracing direct current paths. The first level consistency check is performed on the directed graphs ...

A fast checking algorithm and evaluation of a high-hitting pattern checker (MACH) for VLSI mask data are presented. A two-dimensional-limited searching algorithm has realized O(Nv), where Nv is the number of vectors. The processing speed of MACH is 6,...

This paper describes the design, implementation and performance of a fiat edge-based circuit extractor for NMOS circuits. The extractor is able to work on large and complex designs, it can handle arbitrary geometry, and outputs a comprehensive wirelist. ...

Due to increasing VLSI complexity, logic level simulators have become necessary tools for design verification and test generation. Logic simulators must respond to this increased demand by providing additional functionality in a user-friendly ...

The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test ...

We present a new approach to the production testing of VLSI circuits. By using very structured design for testability, we achieve 100% single stuck-at fault coverage with under 20 test vectors and no search. The approach also detects most multiple ...

This Paper outlines a methodology for design verification of very large networks based on Concurrent Simulation and Clock Suppression. Concurrent Simulation is expected to yield a 30:1 to 600:1 speed advantage over conventional (serial) simulation when ...

We divide microprocessor testing into three distinct phases: verification of the control and data transfer functions; verification of the data-manipulation functions; and verification of the input-output functions. Here we deal in detail only with the ...

This paper describes the design of a topology for array-structured (both Gate-Array and Polycell) semicustom LSI, in the context of a CMOS gate-array fabricated to test both the topology and the unique functional cells. Design emphasis has been placed ...

A new statistical model for routing of gate arrays is described. The model takes into consideration the effect of gate utilization on wiring area requirement. Model computed wiring area estimates suggest that it is better (in terms of area and wire ...

A gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density is described. Logic macros, with fixed intraconnect metal that may span several cell columns, are mapped onto the array producing partially ...

Gate arrays with only one layer of metal have some advantages-notably that they are easier to make than arrays with two or three layers of metal and are correspondingly cheaper. These are countered by the increased difficulty of layout, particularly if ...

A global router which has been developed for the UK5000 gate array is described. The algorithm employed treats all nets in parallel. It solves the problem set by the channels having fixed capacity by using cumulative weighting to direct connections away ...