research-article

Exploiting narrow-width values for thermal-aware register file designs

Authors:

Sotirios G. Ziavras,

Sung Woo ChungAuthors Info & Claims

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 1422 - 1427

Published: 20 April 2009 Publication History

Abstract

Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors. In this paper, we perform a detailed study on the thermal behavior of a low-power value-aware register file (VARF) that is subjected to internal fine-grain hotspots. To further optimize its thermal behavior, we propose and evaluate three thermal-aware control schemes, thermal sensor (TS), access counter (AC), and register-id (ID) based, to balance the access activity and thus the temperature across different partitions in the VARF. The simulation results using SPEC CINT2000 benchmarks show that the register-id controlled VARF (ID-VARF) scheme achieves optimized thermal behavior at minimum cost as compared to the other schemes. We further evaluate the performance impact of the thermal-aware VARF design with the dynamic thermal management (DTM). The experimental results show that the ID-VARF can improve the performance by 26.1% and 7.2% over the conventional register file and the original VARF design, respectively.

References

[1]

S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, no. 4, pp. 23--29, 1999.

Digital Library

[2]

V. Tiwari et al., "Reducing power in high-performance microprocessors," in 35th Design Automation Conference, 1998.

Digital Library

[3]

N. S. Kim et al., "Leakage current: Moore's law meets static power," Computer, no. 12, pp. 68--75, Dec. 2003.

Digital Library

[4]

T. T. Mnatsakanov, M. E. Levinshtein, L. I. Pomortseva, and S. N. Yurkov, "Carrier mobility model for simulation of sic-based electronic devices," Semiconductor Science and Technology, vol. 17, no. 9, pp. 974--977, 2002.

[5]

R. Aitken and B. Hold, "Modeling soft-error susceptibility for ip blocks," in 11th IEEE International On-Line Testing Symposium, 2005, pp. 70--73.

Digital Library

[6]

R. Viswanath, V. Wakharkar, A. Watwe, and V. Lebonheur, "Thermal performance challenges from silicon to systems," Intel Technology Journal, vol. Q3, 2000.

[7]

K. Skadron et al., "Temperature-aware microarchitecture," in Proceedings of the 30th annual international symposium on Computer architecture, San Diego, California, 2003, pp. 2--13.

Digital Library

[8]

O. Ergin, "Exploiting narrow values for energy efficiency in the register files of superscalar microprocessors," in Proc. of 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, 2006, pp. 477--485.

Digital Library

[9]

S. Wang, H. Yang, J. Hu, and S. G. Ziavras, "Asymmetrically banked value-aware register files," in Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007, pp. 363--368.

Digital Library

[10]

S. Wang, H. Yang, J. Hu, and S. G. Ziavras, "Asymmetrically banked value-aware register files for low energy and high performance," Microprocessors and Microsystems, vol. 32, no. 3, pp. 171--182, May 2008.

Digital Library

[11]

J. C. Ku et al., "Thermal management of on-chip caches through power density minimization," in Proc. Micro-38, Nov. 2005, pp. 283--293.

Digital Library

[12]

J. A. Swensen and Y. N. Patt, "Hierarchical registers for scientific computers," in Proc. of ICS'88, 1988, pp. 346--354.

Digital Library

[13]

R. Balasubramonian, S. Dwarkadas, and D. H. Albonesi, "Reducing the complexity of the register file in dynamic superscalar processors," in Proceedings of Micro-34, December 2001, pp. 237--248.

Digital Library

[14]

E. Borch, E. Tune, S. Manne, and J. Emer, "Loose loops sink chips," in Proc. of HPCA-8, February 2002, pp. 270--281.

Digital Library

[15]

J. A. Butts and G. S. Sohi, "Use-based register caching with decoupled indexing," in Proceedings of the 31st annual international symposium on Computer architecture, 2004, pp. 302--313.

Digital Library

[16]

R. E. Kessler, "The alpha 21264 microprocessor," IEEE Micro, vol. 19, no. 2, pp. 24--36, March-April 1999.

Digital Library

[17]

A. Capitanio, N. Dutt, and A. Nicolau, "Partitioned register files for vliws: a preliminary analysis of tradeoffs," in Proc. of Micro-25, 1992, pp. 292--300.

Digital Library

[18]

K. I. Farkas, P. Chow, N. P. Jouppi, and Z. Vranesic, "The multicluster architecture: reducing cycle time through partitioning," in Proc. Micro-30, 1997, pp. 149--159.

Digital Library

[19]

R. Canal, J.-M. Parcerisa, and A. Gonzalez, "Dynamic cluster assignment mechanisms," in Proc. of HPCA-06, 2000, pp. 132--142.

[20]

A. Gonzalez, J. Gonzalez, and M. Valero, "Virtual-physical registers," in Proc. of HPCA-4, 1998, pp. 175--184.

Digital Library

[21]

T. Monreal, A. Gonzalez, M. Valero, J. Gonzalez, and V. Vinals, "Delaying physical register allocation through virtual-physical registers," in Proc. of Micro-32, 1999, pp. 186--192.

Digital Library

[22]

S. Jourdan, R. Ronen, M. Bekerman, B. Shomar, and A. Yoaz, "A novel renaming scheme to exploit value temporal locality through physical register reuse and unification," in Proc. Micro-31, 1998, pp. 216--225.

Digital Library

[23]

J. F. Martinez, J. Renau, M. C. Huang, M. Prvulovic, and J. Torrellas, "Cherry: checkpointed early resource recycling in out-of-order microprocessors," in Proc. fo Micro-35, 2002, pp. 3--14.

Digital Library

[24]

S. Balakrishnan and G. Sohi, "Exploiting value locality in physical register files," in Proc. of Micro-36, 2003, pp. 265--276.

Digital Library

[25]

R. Gonzalez, A. Cristal, D. Ortega, A. Veidenbaum, and M. Valero, "A content aware integer register file organization," in Proceedings of the 31st Annual International Symposium on Computer Architecture, June 2004.

Digital Library

[26]

S. Wallace and N. Bagherzadeh, "A scalable register file architecture for dynamically scheduled processors," in Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques, 1996, p. 179.

Digital Library

[27]

J. Tseng and K. Asanovic, "Banked multiported register files for high-frequency superscalar microprocessors," in 30th International Symposium on Computer Architecture (ISCA-30), San Diego, CA, June 2003.

Digital Library

[28]

I. Park, M. Powell, and T. Vijaykumar, "Reducing register ports for higher speed and lower energy," in Proc. of Micro-35, Dec. 2002.

Digital Library

[29]

M. H. Lipasti, B. R. Mestan, and E. Gunadi, "Physical register inlining," in Proceedings of the 31st Annual International Symposium on Computer Architecture, June 2004, pp. 325--335.

Digital Library

[30]

O. Ergin et al., "Register packing: Exploiting narrow-width operands for reducing register file pressure," in Proc. of MICRO-37, Portland, OR, 2004, pp. 304--315.

Digital Library

[31]

M. Kondo and H. Nakamura, "A small, fast and low-power register file by bit-partitioning," in Proc. of HPCA-11, 2005, pp. 40--49.

Digital Library

[32]

H. Sanchez et al., "Thermal management system for high performance PowerPC microprocessors," in Proceedings of COMPCON 97, San Jose California, 1997.

Digital Library

[33]

S. H. Gunther, F. Binns, D. M. Carmean, and J. C. Hall, "Managing the impact of increasing microprocessor power consumption," Intel Technology Journal, vol. Q1, 2001.

[34]

C. H. Lim, W. R. Daasch, and G. Cai, "A thermal-aware superscalar microprocessor," in Proceedings. International Symposium on Quality Electronic Design, 2002, pp. 517--522.

Digital Library

[35]

D. Brooks and M. Martonosi, "Dynamic thermal management for high-performance microprocessors," in Proc. of HPCA'01, 2001.

Digital Library

[36]

J. K. John, J. S. Hu, and S. G. Ziavras, "Optimizing the thermal behavior of subarrayed data caches," in Proc. of ICCD-2005, 2005, pp. 625--630.

Digital Library

[37]

M. D. Powell, E. Schuchman, and T. N. Vijaykumar, "Balancing resource utilization to mitigate power density in processor pipelines," in Proc. of Micro-38, 2005, pp. 294--304.

Digital Library

[38]

K. Puttaswamy and G. H. Loh, "Thermal herding: Microarchitecture techniques for controlling hotspots in high-performance 3d-integrated processors," in Proc. of HPCA-13, 2007, pp. 193--204.

Digital Library

[39]

X. Zhou, C. Yu, and P. Petrov, "Compiler-driven register re-assignment for register file power-density and temperature reduction," in Proceedings of the 45th annual conference on Design automation, 2008, pp. 750--753.

Digital Library

[40]

D. Brooks and M. Martonosi, "Dynamically exploiting narrow width operands to improve processor power and performance," in Proc. of HPCA-5, 1999.

Digital Library

[41]

G. H. Loh, "Exploiting data-width locality to increase superscalar execution bandwidth," in Proc. of Micro-35, November 18--22 2002, pp. 395--405.

Digital Library

[42]

A. Aggarwal and M. Franklin, "Energy efficient asymmetrically ported register files," in Proc. of ICCD'03, 2003, pp. 2--7.

Digital Library

[43]

L. Villa, M. Zhang, and K. Asanovic, "Dynamic zero compression for cache energy reduction," in Proc. of Micro-33, 2000, pp. 214--220.

Digital Library

[44]

R. Canal, A. Gonzalez, and J. E. Smith, "Very low power pipelines using significance compression," in Proc. of Micro-33, 2000, pp. 181--190.

Digital Library

[45]

R. Canal, A. Gonzalez, and J. E. Smith, "Value compression for efficient computation," in Proceedings of the Euro-Par 2005, 2005, pp. 519--529.

Digital Library

[46]

D. R. Lutz and D. N. Jayasimha, "Early zero detection," in Proc. of ICCD'96, 1996, pp. 545--550.

Digital Library

[47]

M. S. Hrishikesh et al., "The optimal logic depth per pipeline stage is 6 to 8 fo4 inverter delays," in Proceedings of the 29th Annual International Symposium on Computer Architecture, 2002, pp. 14--24.

Digital Library

[48]

D. Burger and T. M. Austin, "The simplescalar tool set, version 2.0," Computer Sciences Department, University of Wisconsin, Tech. Rep. 1342, 1997.

[49]

D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: a framework for architectural-level power analysis and optimizations," in Proc. International Symposium on Computer Architecture, 2000.

Digital Library

[50]

Y. Zhang et al., "Hotleakage: A temperature-aware model of subthresh-old and gate leakage for architects," Dept. of Computer Science, Univ. of Virginia, Tech. Rep., 2003.

[51]

R. P. Preston et al., "Design of an 8-issue superscalar risc microprocessor with simultaneous multithreading," in Proc. IEEE International Solid-State Circuits Conference, 2002.

[52]

T. Sherwood et al., "Automatically characterizing large scale program behavior," in Proc. of ASPLOS X, October 2002.

Digital Library

[53]

D. Tarjan, S. Thoziyoor, and N. P. Jouppi, "Cacti 4.0," HP Laboratories, Tech. Rep., 2006.

Cited By

Imani MPatil SRosing TCoskun AMargala MBehjat LHan J(2016)DCCProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902990(113-116)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902990
Wang SJin TZheng CDuan GRosenstiel WMacii E(2012)Low power aging-aware register file design by duty cycle balancingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492844(546-549)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492844

Exploiting narrow-width values for thermal-aware register file designs
1. General and reference
  1. Cross-computing tools and techniques
2. Hardware

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Published In

cover image ACM Conferences

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

April 2009

1776 pages

ISBN:9783981080155

General Chairs:
Luca Benini
University of Bologna, IT
,
Giovanni De Micheli
EPFL, CH
,
Program Chairs:
Bashir Al-Hashimi
University of Southampton, UK
,
Wolfgang Mueller
University of Paderborn, DE

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
The IEEE Computer Society DATC
The Russian Academy of Sciences: The Russian Academy of Sciences

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 20 April 2009

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DATE '09: Design, Automation and Test in Europe

April 20 - 24, 2009

Nice, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Imani MPatil SRosing TCoskun AMargala MBehjat LHan J(2016)DCCProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902990(113-116)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902990
Wang SJin TZheng CDuan GRosenstiel WMacii E(2012)Low power aging-aware register file design by duty cycle balancingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492844(546-549)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492844

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