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Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Authors:

Federico Angiolini,

Luca BeniniAuthors Info & Claims

Nano-Net '07: Proceedings of the 2nd international conference on Nano-Networks

Article No.: 15, Pages 1 - 5

Published: 24 September 2007 Publication History

Abstract

Three-dimensional (3D) manufacturing technologies are viewed as promising solutions to the bandwidth bottlenecks in VLSI communication. At the architectural level, Networks-on-chip (NoCs) have been proposed to address the complexity of interconnecting an ever-growing number of cores, memories and peripherals. NoCs are a promising choice for implementing scalable 3D interconnect architectures. However, the development of 3D NoCs is still at an early development stage. In this paper, we present a semi-automated design flow for 3D NoCs. Starting from an accurate physical and geometric model of Through-Silicon Vias (TSVs), we extract a circuit-level model for vertical interconnections, and we use it to evaluate the design implications of extending switch architectures with ports in the vertical direction. In addition, we present a design flow allowing for post-layout simulation of NoCs with links in all three physical dimensions.

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Cited By

Bahrebar PStroobandt DEbrahimi MLocatelli R(2015)Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-ChipProceedings of the 8th International Workshop on Network on Chip Architectures10.1145/2835512.2835514(15-20)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2835512.2835514
Ebrahimi MDaneshtalab MLiljeberg PPlosila JTenhunen H(2013)Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architectureJournal of Computer and System Sciences10.1016/j.jcss.2012.09.00579:4(475-491)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1016/j.jcss.2012.09.005
Zhou PYuh PSapatnekar S(2012)Optimized 3D Network-on-Chip Design Using Simulated AllocationACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215954417:2(1-19)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1145/2159542.2159544
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Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
1. Hardware
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Information & Contributors

Information

Published In

cover image Guide Proceedings

Nano-Net '07: Proceedings of the 2nd international conference on Nano-Networks

September 2007

124 pages

ISBN:9789639799103

General Chair:
Salvatore Coffa
STMicroelectronics, Italy

Sponsors

European Nanoelectronics Initiative Advisory Council
IEEE Communications Society
Create-Net

Publisher

ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)

Brussels, Belgium

Publication History

Published: 24 September 2007

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Cited By

Bahrebar PStroobandt DEbrahimi MLocatelli R(2015)Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-ChipProceedings of the 8th International Workshop on Network on Chip Architectures10.1145/2835512.2835514(15-20)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2835512.2835514
Ebrahimi MDaneshtalab MLiljeberg PPlosila JTenhunen H(2013)Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architectureJournal of Computer and System Sciences10.1016/j.jcss.2012.09.00579:4(475-491)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1016/j.jcss.2012.09.005
Zhou PYuh PSapatnekar S(2012)Optimized 3D Network-on-Chip Design Using Simulated AllocationACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215954417:2(1-19)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1145/2159542.2159544
Liu CZhang LHan YLi X(2011)Vertical interconnects squeezing in symmetric 3D mesh network-on-chipProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950892(357-362)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950892
Pasricha SBahirat S(2011)OPALProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950890(345-350)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950890
Daneshtalab MEbrahimi MLiljeberg PPlosila JTenhunen HCascaval CTrancoso PPrasanna V(2011)Cluster-based topologies for 3D stacked architecturesProceedings of the 8th ACM International Conference on Computing Frontiers10.1145/2016604.2016621(1-3)Online publication date: 3-May-2011
https://dl.acm.org/doi/10.1145/2016604.2016621
Camacho JFlich J(2011)HPC-MeshProceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems10.1109/ANCS.2011.17(69-80)Online publication date: 3-Oct-2011
https://dl.acm.org/doi/10.1109/ANCS.2011.17
Loi IBenini LDe Micheli GAl-Hashimi BMueller WMacii E(2010)An efficient distributed memory interface for many-core platform with 3D stacked DRAMProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1870952(99-104)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1870952
Seiculescu CMurali SBenini LDe Micheli GBenini LDe Micheli GAl-Hashimi BMueller W(2009)SunFloor 3DProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874626(9-14)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874626
Murali SSeiculescu CBenini LDe Micheli GWakabayashi K(2009)Synthesis of networks on chips for 3D systems on chipsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509701(242-247)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509701
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