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CERN Document Server 2,044 ჩანაწერია ნაპოვნი  1 - 10შემდეგიდასასრული  ჩანაწერთან გადასვლა: ძიებას დასჭირდა 0.32 წამი. 
1.
Effects of Bias and Temperature on the Dose-Rate Sensitivity of 65-nm CMOS Transistors / Borghello, Giulio (CERN) ; Faccio, Federico (CERN) ; Termo, Gennaro (CERN) ; Michelis, Stefano (CERN) ; Costanzo, Sebastiano (CERN) ; Koch, Henri D (CERN) ; Fleetwood, Daniel M (Vanderbilt U.)
MOS transistors in 65-nm CMOS technology exposed to ultrahigh total ionizing dose (TID) levels show clear evidence of a true dose-rate (DR) dependence. In order to assess the impact of this effect and to understand its origin, an extensive measurement campaign has been carried out at different DRs, different temperatures, and different biases. [...]
2021 - 8 p. - Published in : IEEE Trans. Nucl. Sci. 68 (2021) 573-580
2.
Dose-Rate Sensitivity of 65-nm MOSFETs Exposed to Ultrahigh Doses / Borghello, Giulio (CERN ; U. Udine (main)) ; Faccio, Federico (CERN) ; Lerario, Edoardo (CERN ; U. Salento, Lecce (main)) ; Michelis, Stefano (CERN) ; Kulis, Szymon (CERN) ; Fleetwood, Daniel M (Vanderbilt U. (main)) ; Schrimpf, Ronald D (Vanderbilt U. (main)) ; Gerardin, Simone (U. Padua (main)) ; Paccagnella, Alessandro (U. Padua (main)) ; Bonaldo, Stefano (U. Padua (main))
The radiation response of complementary metal- oxide-semiconductor (CMOS) gate oxides is typically insensitive to true dose-rate effects, but damage in deep-sub-micrometer technologies is dominated by ionization mechanisms in thick isolation oxides surrounding the transistors. Recent results in 65-nm FETs demonstrated that performance degradation in ultrahigh total ionizing dose (TID) experiments is due to defects in the isolation shallow trench isolation oxide or in the materials composing the lightly doped drain spacers. [...]
2018 - 6 p. - Published in : IEEE Trans. Nucl. Sci. 65 (2018) 1482-1487
3.
Degradation and Dose-Rate Dependence in Decananometer MOSFETs Exposed to Ultra-High Levels of Total Ionizing Dose / Costanzo, Sebastiano
The main experiment performed in this thesis is called ``Low Dose-Rate Sensitivity'', an analysis conducted on 65-nm technology node, intended to be implemented in most of the circuitry for CERN HL-LHC (High Luminosity - Large Hadron Collider) upgrade [...]
CERN-THESIS-2019-117 - 100 p.

Full text
4.
Charge Buildup and Spatial Distribution of Interface Traps in 65-nm pMOSFETs Irradiated to Ultrahigh Doses / Bonaldo, Stefano (U. Padua (main)) ; Gerardin, Simone (U. Padua (main)) ; Jin, Xiaoming (Northwest Inst. Nucl. Tech., Xian) ; Paccagnella, Alessandro (U. Padua (main)) ; Faccio, Federico (CERN) ; Borghello, Giulio (CERN) ; Fleetwood, Daniel M (Vanderbilt U. (main))
In this paper, a commercial 65-nm CMOS technology is irradiated at ultrahigh ionizing doses and then annealed at high temperature under different bias conditions. The experimental results demonstrate the high sensitivity of pMOSFETs to radiation-induced short-channel effects, related to the buildup of defects in spacer dielectrics. [...]
2019 - 10 p. - Published in : IEEE Trans. Nucl. Sci. 66 (2019) 1574-1583
In : Conference on Radiation and its Effects on Components and Systems, Gothenburg, Sweden, 16 - 21 Sep 2018, pp.1574-1583
5.
Influence of LDD Spacers and H$^+$ Transport on the Total-Ionizing-Dose Response of 65-nm MOSFETs Irradiated to Ultrahigh Doses / Faccio, Federico (CERN) ; Borghello, Giulio (CERN ; U. Udine (main)) ; Lerario, Edoardo (CERN ; U. Salento, Lecce (main)) ; Fleetwood, Daniel M (Vanderbilt U. (main)) ; Schrimpf, Ronald D (Vanderbilt U. (main)) ; Gong, Huiqi (Vanderbilt U. (main)) ; Zhang, En Xia (Vanderbilt U. (main)) ; Wang, P (Vanderbilt U. (main)) ; Michelis, Stefano (CERN) ; Gerardin, Simone (U. Padua (main)) et al.
The degradation induced by ultrahigh total ionizing dose in 65-nm MOS transistors is strongly gate-length dependent. The current drive decreases during irradiation, and the threshold voltage often shifts significantly during irradiation and/or high-temperature annealing, depending on transistor polarity, applied field, and irradiation/annealing temperature. [...]
2017 - 11 p. - Published in : IEEE Trans. Nucl. Sci. 65 (2018) 164-174
In : 54th Annual IEEE International Nuclear and Space Radiation Effects Conference, New Orleans, LA, USA, 17 - 21 Jul 2017, pp.164-174
6.
65-nm CMOS front-end channel for pixel readout in the HL-LHC radiation environment / Ratti, Lodovico (Pavia U. ; INFN, Pavia) ; Gaioni, Luigi (INFN, Pavia ; Bergamo U.) ; Manghisoni, Massimo (INFN, Pavia ; Bergamo U.) ; Re, Valerio (INFN, Pavia ; Bergamo U.) ; Riceputi, Elisa (INFN, Pavia ; Bergamo U.) ; Traversi, Gianluca (INFN, Pavia ; Bergamo U.)
A charge preamplifier has been developed in a 65-nm CMOS technology for processing the signals from the inner pixel layers of the CMS detector, in view of the experiment upgrade for the High-Luminosity (HL) Large Hadron Collider (LHC). The circuit is part of a readout channel implementing a time-over-threshold method for the analog-to-digital conversion of the input charge signal. [...]
2017 - 11 p. - Published in : IEEE Trans. Nucl. Sci. 64 (2017) 2922-2932
7.
Reliability of Advanced Nanoscale CMOS Technology for High-Radiation Environments / Termo, Gennaro
Ionizing and non-ionizing radiation is known to cause damage to electronic components, resulting in reduced performance and possible failure [...]
CERN-THESIS-2024-267 - https://infoscience.epfl.ch/entities/publication/1b299779-081b-495c-bed3-d9ae1c2e3953/thesisdetails : EPFL, 2024-12-07

8.
Extending a 65nm CMOS process design kit for high total ionizing dose effects / Nikolaou, Aristeidis (Natl. Tech. U., Athens) ; Bucher, Matthias (Natl. Tech. U., Athens) ; Makris, Nikos (Natl. Tech. U., Athens) ; Papadopoulou, Alexia (Natl. Tech. U., Athens) ; Chevas, Loukas (Natl. Tech. U., Athens) ; Borghello, Giulio (Udine U.) ; Koch, Henri D (U. Mons) ; Kloukinas, Kostas (CERN) ; Poikela, Tuomas S (CERN) ; Faccio, Federico (CERN)
Standard CMOS Process Design Kits (PDKs) do not address degradation the technology incurs when exposed to high Total Ionizing Dose (TID). Front-end electronics for the High-Luminosity Large Hadron Collider are expected to be exposed up to ten-fold doses. [...]
2018 - 4 p. - Published in : 10.1109/MOCAST.2018.8376561
In : 7th International Conference on Modern Circuits and Systems Technologies, Thessaloniki, Greece, 7 - 9 May 2018
9.
Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs / Zhang, Chun-Min (Ecole Polytechnique, Lausanne) ; Jazaeri, Farzan (Ecole Polytechnique, Lausanne) ; Borghello, Giulio (CERN ; U. Udine (main)) ; Faccio, Federico (CERN) ; Mattiazzo, Serena (Padua U. ; INFN, Padua) ; Baschirotto, Andrea (Milan Bicocca U. ; INFN, Milan Bicocca) ; Enz, Christian (Ecole Polytechnique, Lausanne)
This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO$_2$) on the drain leakage current of nMOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual nMOSFETs of various sizes provide insight into the TID-induced lateral parasitic devices, which contribute the most to the significant increase up to four orders of magnitude in the drain leakage current. [...]
2018 - 10 p. - Published in : IEEE Trans. Nucl. Sci. 66 (2018) 38-47 Fulltext: PDF;
10.
Investigation of Scaling and Temperature Effects in Total Ionizing Dose (TID) Experiments in 65 nm CMOS / Chevas, Loukas (Natl. Tech. U., Athens) ; Nikolaou, Aristeidis (Natl. Tech. U., Athens) ; Bucher, Matthias (Natl. Tech. U., Athens) ; Makris, Nikolaos (Natl. Tech. U., Athens) ; Papadopoulou, Alexia (Natl. Tech. U., Athens) ; Zografos, Apostolos (Natl. Tech. U., Athens) ; Borghello, Giulio (Udine U.) ; Koch, Henri D (U. Mons) ; Faccio, Federico (CERN)
Ten-fold radiation levels are expected in the upgrade of the High-Luminosity Large Hadron Collider (HL-LHC) at CERN. Bulk silicon CMOS at 65 nm offers appreciable advantages among cost, performance, and resilience to high Total Ionizing Dose (TID). [...]
2018 - 6 p. - Published in : 10.23919/MIXDES.2018.8436809
In : 25th International Conference on Mixed Design of Integrated Circuits and System, Gdynia, Poland, 21 - 23 Jun 2018, pp.313-318

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