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Jesse Allen   (all posts)
Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

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Research Bits: Nov. 11
By Jesse Allen - 11 Nov, 2024 - Comments: 0

Quantum tunneling transistor Researchers from MIT and University of Udine fabricated a transistor that uses ultrathin layers of gallium antimonide and indium arsenide arranged in vertical nanowire heterostructures with a diameter of 6nm. The quantum tunneling effects of the material enable it to simultaneously achieve low-voltage operation and high performance. “This is a technology with ... » read more

Blog Review: Nov. 6
By Jesse Allen - 06 Nov, 2024 - Comments: 0

Cadence's Satish Kumar C explores how the Deferrable Memory Write transaction type in PCIe and CXL can improve latency, efficiency, and performance by delaying certain memory write operations during system bus congestion or until other priority tasks are complete and highlights implementation and verification challenges. Synopsys' Daryl Seitzer and Rahul Thukral point to magnetoresistive RAM... » read more

Research Bits: Nov. 5
By Jesse Allen - 05 Nov, 2024 - Comments: 0

Optical in-memory computing Researchers from the University of Pittsburgh, University of California Santa Barbara, University of Cagliari, and Institute of Science Tokyo propose a resonance-based photonic architecture which leverages the non-reciprocal phase shift in magneto-optical materials to implement photonic in-memory computing. “The materials we use in developing these cells have b... » read more

Blog Review: Oct. 30
By Jesse Allen - 30 Oct, 2024 - Comments: 0

Synopsys' Frank Schirrmeister argues that hardware-assisted verification techniques like emulation and prototyping are essential to help engineers improve design behavior to manage complexity and ensure systems function seamlessly in real-world applications. Siemens’ Stephen V. Chavez finds that ultra high-density interconnect (UHDI) has changed the design and production of PCBs to enable ... » read more

Research Bits: Oct. 29
By Jesse Allen - 29 Oct, 2024 - Comments: 0

Micro-LED DUV maskless lithography Researchers from the University of Science and Technology of China, Anhui GaN Semiconductor, and Wuhan University developed a vertically integrated micro-LED array for deep ultraviolet (DUV) maskless photolithography. The team fabricated a DUV display integrated chip with 564 pixels-per-inch density that uses a three-dimensional vertically integrated devic... » read more

Blog Review: Oct. 23
By Jesse Allen - 23 Oct, 2024 - Comments: 0

Cadence’s Sanjeet Kumar introduces the message bus interface in the PHY Interface for the PCIe, SATA, USB, DisplayPort, and USB4 Architectures (PIPE) specification, which provides a way to initiate and participate in non-latency-sensitive PIPE operations using a small number of wires. Siemens’ Dennis Brophy argues that the recently published Portable Test and Stimulus Standard (PSS) 3.0 ... » read more

Research Bits: Oct. 22
By Jesse Allen - 22 Oct, 2024 - Comments: 0

3D-printed active electronics Researchers from MIT demonstrated fully 3D-printed semiconductor-free resettable fuses. Produced using standard 3D printing hardware and an inexpensive, biodegradable polymer filament doped with copper nanoparticles, the device can perform the same switching functions as the semiconductor-based transistors used for processing operations in active electronics. A... » read more

Startup Funding: Q3 2024
By Jesse Allen - 16 Oct, 2024 - Comments: 0

Numerous new companies burst on the scene in the third quarter of 2024, including startups with plans for customizable RISC-V-based IP for applications from microcontrollers to data centers, high-speed data center interconnects, compute-in-memory LLM inference chips, and surveillance camera SoCs. Although it did not report funding, AheadComputing also launched last quarter to develop RISC-V cor... » read more

Blog Review: Sept. 25
By Jesse Allen - 25 Sep, 2024 - Comments: 0

Cadence’s Mamta Rana digs into how PCIe 6.1 ECN builds on the FLIT-based architecture introduced in PCIe 6.0, further optimizing flow control mechanisms to handle increased data rates and improved efficiency but making verification of shared credit updates essential. Siemens’ Nicolae Tusinschi provides a primer on formal verification, including what makes it different from simulation, pr... » read more

Research Bits: Sept. 24
By Jesse Allen - 24 Sep, 2024 - Comments: 0

Modeling negative capacitance Researchers from Lawrence Berkeley National Laboratory developed an open-source 3D simulation framework capable of modeling the atomistic origins of negative capacitance in ferroelectric thin films at the device level. When a material has negative capacitance, it can store a greater amount of electrical charge at lower voltages. The team believes the FerroX fra... » read more

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