WO2024226968A1

WO2024226968A1 - Package comprising a package substrate that includes an encapsulated portion with interconnection portion blocks

Info

Publication number: WO2024226968A1
Application number: PCT/US2024/026501
Authority: WO
Inventors: Aniket Patil; Hong Bok We; Joan Rey Villarba Buot
Original assignee: Qualcomm Incorporated
Priority date: 2023-04-26
Filing date: 2024-04-26
Publication date: 2024-10-31

Abstract

A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

Description

PACKAGE COMPRISING A PACKAGE SUBSTRATE THAT INCLUDES AN ENCAPSULATED PORTION WITH INTERCONNECTION PORTION BLOCKS

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of U.S. Non-Provisional Application Serial No. 18/646,659 filed in the United States Patent and Trademark Office on April 25, 2024 and U.S. Provisional Application Serial No. 63/498,487 filed in the United States Patent and Trademark Office on April 26, 2023. U.S. Non-Provisional Application Serial No. 18/646,659 claims priority to and the benefit of U.S. Provisional Application Serial No. 63/498,487. The entire content of both applications are incorporated herein by reference as if fully set forth below in its entirety and for all applicable purposes.

Field

[0002] Various features relate to a package comprising an integrated device and a package substrate.

Background

[0003] A package may include a package substrate and an integrated device. These components are coupled together to provide a package that may perform various electrical functions. How the integrated device and the package substrate are coupled together affects how the package performs overall. There is an ongoing need to provide packages with improved performances.

SUMMARY

[0004] Various features relate to a package comprising an integrated device and a package substrate.

[0005] One example provides a package that includes a package substrate and an integrated device. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, a second metallization portion coupled to a second surface of the encapsulated portion, and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block; and a second plurality of pillar interconnects coupled to the second interconnection portion block.

[0006] Another example provides a device that includes a package substrate and an integrated device. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, a second metallization portion coupled to a second surface of the encapsulated portion, and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer that at least partially encapsulates the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

[0007] Another example provides a method for fabricating a package. The method provides a package substrate that comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer that at least partially encapsulates the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block, and a second plurality of pillar interconnects coupled to the second interconnection portion block. The method couples a first integrated device to the package substrate through a first plurality of solder interconnects.

[0008] Another example provides a method for fabricating a package substrate. The method provides a first interconnection portion block. The method provides a second interconnection portion block, wherein the second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block. The method forms a plurality of pillar interconnects, wherein the plurality of pillar interconnects comprises: a first plurality of pillar interconnects coupled to the first interconnection portion block; and a second plurality of pillar interconnects coupled to the second interconnection portion block. The method forms an encapsulation layer that at least partially encapsulates the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects, which forms an encapsulated portion. The method forms a first metallization portion that is coupled to a first surface of the encapsulated portion. The method forms a second metallization portion that is coupled to a second surface of the encapsulated portion.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

[0010] FIG. 1 illustrates a cross sectional profile view of an exemplary package comprising a package substrate with encapsulated portion with several interconnection portion blocks.

[0011] FIG. 2 illustrates a cross sectional profile view of another exemplary package comprising a package substrate with an encapsulated portion with several interconnection portion blocks.

[0012] FIG. 3 illustrates a plan view of an exemplary package substrate with an encapsulated portion with several interconnection portion blocks.

[0013] FIG. 4 illustrates a cross sectional profile view of another exemplary package comprising a package substrate with an encapsulated portion with several interconnection portion blocks.

[0014] FIG. 5 illustrates a cross sectional profile view of an exemplary interconnection portion block. [0015] FIG. 6 illustrates a cross sectional profile view of another exemplary interconnection portion block.

[0016] FIG. 7 illustrates a cross sectional profile view of another exemplary interconnection portion block.

[0017] FIG. 8 illustrates a cross sectional profile view of another exemplary interconnection portion block.

[0018] FIG. 9 illustrates a cross sectional profile view of another exemplary interconnection portion block.

[0019] FIG. 10 illustrates examples of electrical paths for a package comprising a package substrate with an encapsulated portion with several interconnection portion blocks.

[0020] FIG. 11 illustrates examples of electrical paths for another package comprising a package substrate with an encapsulated portion with several interconnection portion blocks.

[0021] FIGS. 12A-12F illustrate an exemplary sequence for fabricating a package comprising a package substrate with an encapsulated portion with several interconnection portion blocks.

[0022] FIG. 13 illustrates an exemplary flow diagram of a method for fabricating a package comprising a package substrate with an encapsulated portion with several interconnection portion blocks.

[0023] FIGS. 14A-14C illustrate an example of a sequence for fabricating a coreless substrate.

[0024] FIG. 15 illustrates an exemplary flow diagram of a method for fabricating a coreless substrate.

[0025] FIGS. 16A-16B illustrate an example of a sequence for fabricating a cored substrate.

[0026] FIG. 17 illustrates an exemplary flow diagram of a method for fabricating a cored substrate.

[0027] FIGS. 18A-18B illustrate an exemplary sequence for fabricating a metallization portion.

[0028] FIG. 19 illustrates an exemplary flow diagram of a method for fabricating a metallization portion. [0029] FIG. 20 illustrates a cross sectional profile view of another exemplary package comprising a package substrate with an encapsulated portion with several interconnection portion blocks.

[0030] FIG. 21 illustrates a cross sectional profile view of another exemplary package comprising a package substrate with an encapsulated portion with several interconnection portion blocks.

[0031] FIG. 22 illustrates a cross sectional profile view of another exemplary package comprising a package substrate with an encapsulated portion with several interconnection portion blocks.

[0032] FIG. 23 illustrates various electronic devices that may integrate a die, an electronic circuit, an integrated device, an integrated passive device (IPD), a passive component, a package, and/or a device package described herein.

DETAILED DESCRIPTION

[0033] In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown as block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure. [0034] The present disclosure describes a package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer that at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block, and a second plurality of pillar interconnects coupled to the second interconnection portion block. As will be further described below, the use of an encapsulated portion that includes different types of interconnection portion blocks provides several technical advantages, including the ability to customize and optimize the interconnects in order to provide a package with improved performance and lower overall fabrication costs.

Exemplary Package Comprising a Package Substrate That Includes an Encapsulated Portion With Interconnection Portion Blocks

[0035] FIG. 1 illustrates a cross sectional profile view of a package 100 that includes a package substrate with an encapsulated portion comprising several interconnection portion blocks. The package 100 is coupled to a board 108 through a plurality of solder interconnects 110. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB). The package 100 includes a package substrate 101 and an integrated device 103. The integrated device 103 is coupled to the package substrate 101 through a plurality of solder interconnects 130. There may be a plurality of pillar interconnects (not shown) between the integrated device 103 and the plurality of solder interconnects 130. In some implementations, the plurality of pillar interconnects (not shown) coupled to the integrated device 103 and the plurality of solder interconnects 130, are considered part of the integrated device 103. The integrated device 103 may be a first integrated device.

[0036] The package substrate 101 includes an encapsulated portion 102, a metallization portion 104 (e.g., first metallization portion) and a metallization portion 106 (e.g., second metallization portion). The metallization portion 104 may be coupled to a first surface (e.g., top surface) of the encapsulated portion 102. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142 (e.g., first plurality of metallization interconnects). The metallization portion 104 may include a redistribution portion. The plurality of metallization interconnects 142 may include a plurality of redistribution interconnects (e.g., first plurality of redistribution interconnects). The integrated device 103 is coupled to the plurality of metallization interconnects 142 through the plurality of solder interconnects 130. A solder resist layer 148 is coupled to the metallization portion 104. The solder resist layer 148 may be part of the metallization portion 104. The metallization portion 104 may help ensure the proper alignment of connections between integrated devices and the package substrate 101.

[0037] The metallization portion 106 may be coupled to a second surface (e.g., bottom surface) of the encapsulated portion 102. The metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallization interconnects 162 (e.g., second plurality of metallization interconnects). The metallization portion 106 may include a redistribution portion. The plurality of metallization interconnects 162 may include a plurality of redistribution interconnects (e.g., second plurality of redistribution interconnects).

[0038] The encapsulated portion 102 is located between the metallization portion 104 and the metallization portion 106. The encapsulated portion 102 includes an interconnection portion block 105 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block), an interconnection portion block 107 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block), an interconnection portion block 109 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block), a plurality of pillar interconnects 122 and an encapsulation layer 120. The encapsulation layer 120 encapsulates the interconnection portion block 105, the interconnection portion block 107, the interconnection portion block 109 and the plurality of pillar interconnects 122. An encapsulation layer (e.g., 120) may include a mold, a resin and/or an epoxy. The encapsulation layer may be a means for encapsulation. The encapsulation layer may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 120 may include a different material than the at least one dielectric layer 140 of the metallization portion 104 and the at least one dielectric layer 160 of the metallization portion 106. In some implementations, the encapsulation layer 120 may include a different material than the at least one dielectric layer 150 of the interconnection portion block 105, the dielectric layers (e.g., 170, 172, 174) of the interconnection portion block 107, and the at least one dielectric layer 190 of the interconnection portion block 109. In some implementations, the dielectric layer 150, the dielectric layer 172, the dielectric layer 174, and/or the dielectric layer 190 may include prepreg and/or poly imide.

[0039] As will be further described below, the interconnection portion block 105, the interconnection portion block 107 and/or the interconnection portion block 109 may include different types of interconnection portion block. Examples of types of interconnection portion blocks include a coreless substrate block, a cored substrate block, a metallization portion block, a redistribution portion block and/or a die block comprising through substrate vias. The different types of interconnection portion blocks may have different properties. For example, different types of interconnection portion blocks may include interconnects with different minimum width (e.g., minimum line width), minimum spacing and/or minimum pitch.

[0040] The interconnection portion block 105 includes at least one dielectric layer 150 and a plurality of interconnects 152. The interconnection portion block 105 may include a coreless substrate block (e.g., embedded trace substrate block).

[0041] The interconnection portion block 107 includes a core layer 170, at least one dielectric layer 172, at least one dielectric layer 174 and a plurality of interconnects 173. The interconnection portion block 107 may include a cored substrate block.

[0042] The interconnection portion block 109 includes at least one dielectric layer 190 and a plurality of interconnects 192. The interconnection portion block 109 may include a metallization portion block (e.g., redistribution portion block).

[0043] The plurality of pillar interconnects 122 may include a first plurality of pillar interconnects 122a, a second plurality of pillar interconnects 122b, a third plurality of pillar interconnects 122c, and a fourth plurality of pillar interconnects 122d.

[0044] The first plurality of pillar interconnects 122a may be coupled to the metallization portion 104 and the interconnection portion block 105. The second plurality of pillar interconnects 122b may be coupled to the metallization portion 104 and the interconnection portion block 107. The third plurality of pillar interconnects 122c may be coupled to the metallization portion 104 and the interconnection portion block 109. The fourth plurality of pillar interconnects 122d may be coupled to the metallization portion 104 and the metallization portion 106.

[0045] The interconnection portion block 105 is coupled to the metallization portion 106. One or more interconnects from the plurality of interconnects 152 may be coupled to and touching metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106. The interconnection portion block 107 is coupled to the metallization portion 106. One or more interconnects from the plurality of interconnects 173 may be coupled to and touching metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106. The interconnection portion block 109 is coupled to the metallization portion 106. One or more interconnects from the plurality of interconnects 192 may be coupled to and touching metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106. [0046] As will be further described below, power, ground and/or different signals (e.g., input/output signals) may extend through the different interconnection portion blocks to and/or from the integrated device 103.

[0047] FIG. 2 illustrates a cross sectional profile view of a package 200 that includes a package substrate with an encapsulated portion comprising several interconnection portion blocks. The package 200 is similar to the package 100, and includes similar components as the package 100. One difference is that the package 200 includes a different combination of types of interconnection portion blocks.

[0048] The package 200 includes a package substrate 201 and the integrated device 103. The integrated device 103 is coupled to the package substrate 201 through a plurality of solder interconnects 130. There may be a plurality of pillar interconnects (not shown) between the integrated device 103 and the plurality of solder interconnects 130. In some implementations, the plurality of pillar interconnects (not shown) coupled to the integrated device 103 and the plurality of solder interconnects 130, are considered part of the integrated device 103.

[0049] The package substrate 201 includes an encapsulated portion 102, a metallization portion 104 (e.g., first metallization portion) and a metallization portion 106 (e.g., second metallization portion). The metallization portion 104 may be coupled to a first surface (e.g., top surface) of the encapsulated portion 102. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142 (e.g., first plurality of metallization interconnects). The metallization portion 104 may include a redistribution portion. The plurality of metallization interconnects 142 may include a plurality of redistribution interconnects (e.g., first plurality of redistribution interconnects). The integrated device 103 is coupled to the plurality of metallization interconnects 142 through the plurality of solder interconnects 130. A solder resist layer 148 is coupled to the metallization portion 104. The solder resist layer 148 may be part of the metallization portion 104.

[0050] The metallization portion 106 may be coupled to a second surface (e.g., bottom surface) of the encapsulated portion 102. The metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallization interconnects 162 (e.g., second plurality of metallization interconnects). The metallization portion 106 may include a redistribution portion. The plurality of metallization interconnects 162 may include a plurality of redistribution interconnects (e.g., second plurality of redistribution interconnects). [0051] The encapsulated portion 102 is located between the metallization portion 104 and the metallization portion 106. The metallization portion 104 may be coupled to a first surface of the encapsulated portion 102. The metallization portion 106 may be coupled to a second surface of the encapsulated portion 102. The encapsulated portion 102 includes an interconnection portion block 105 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block, fourth interconnection portion block), an interconnection portion block 109 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block, fourth interconnection portion block), an interconnection portion block 205 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block, fourth interconnection portion block), an interconnection portion block 207 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block, fourth interconnection portion block), a plurality of pillar interconnects 122 and an encapsulation layer 120. The encapsulation layer 120 encapsulates the interconnection portion block 105, the interconnection portion block 109, the interconnection portion block 205, the interconnection portion block 207 and the plurality of pillar interconnects 122. In some implementations, the encapsulation layer 120 may include a different material than the at least one dielectric layer 140 of the metallization portion 104 and the at least one dielectric layer 160 of the metallization portion 106. In some implementations, the encapsulation layer 120 may include a different material than the at least one dielectric layer 150 of the interconnection portion block 105, the dielectric layers (e.g., 170, 172, 174) of the interconnection portion block 207, and the at least one dielectric layer 190 of the interconnection portion block 109.

[0052] The interconnection portion block 105 includes at least one dielectric layer 150 and a plurality of interconnects 152. The interconnection portion block 105 may include a coreless substrate block (e.g., embedded trace substrate block).

[0053] The interconnection portion block 109 includes at least one dielectric layer 190 and a plurality of interconnects 192. The interconnection portion block 109 may include a metallization portion block (e.g., redistribution portion block).

[0054] The interconnection portion block 205 includes a die substrate 250 (e.g., silicon substrate) and a plurality of interconnects 252. The plurality of interconnects 252 may include through substrate vias (e.g., through silicon vias). The interconnection portion block 205 may include die that includes vias. [0055] The interconnection portion block 207 includes a core layer 170, at least one dielectric layer 172, at least one dielectric layer 174, a plurality of interconnects 173 and a passive device 270. The interconnection portion block 207 may include an embedded passive substrate block. The passive device 270 may be a capacitor that is embedded in a cored substrate. The passive device 270 may be a discrete passive device.

[0056] The plurality of pillar interconnects 122 may include a first plurality of pillar interconnects 122a, a second plurality of pillar interconnects 122b, a third plurality of pillar interconnects 122c, a fourth plurality of pillar interconnects 122d, and a fifth plurality of pillar interconnects 122e.

[0057] The first plurality of pillar interconnects 122a may be coupled to the metallization portion 104 and the interconnection portion block 105. The second plurality of pillar interconnects 122b may be coupled to the metallization portion 104 and the interconnection portion block 207. The third plurality of pillar interconnects 122c may be coupled to the metallization portion 104 and the interconnection portion block 109. The fourth plurality of pillar interconnects 122d may be coupled to the metallization portion 104 and the metallization portion 106. The fifth plurality of pillar interconnects 122e may be coupled to the metallization portion 104 and the interconnection portion block 205.

[0058] The interconnection portion block 105 is coupled to the metallization portion 106. One or more interconnects from the plurality of interconnects 152 may be coupled to and touching metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106. The interconnection portion block 109 is coupled to the metallization portion 106. One or more interconnects from the plurality of interconnects 192 may be coupled to and touching metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106. The interconnection portion block 205 is coupled to the metallization portion 106. One or more interconnects from the plurality of interconnects 252 may be coupled to and touching metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106. The interconnection portion block 207 is coupled to the metallization portion 106. One or more interconnects from the plurality of interconnects 173 may be coupled to and touching metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106.

[0059] FIG. 3 illustrates a plan view of a package substrate 300 that includes various interconnection portion blocks. The package substrate 300 may represent the package substrate 101, the package substrate 201 and/or any of the package substrate described in the disclosure. The package substrate 300 includes an interconnection portion block 301, an interconnection portion block 302, an interconnection portion block 303, an interconnection portion block 304, an interconnection portion block 305, an interconnection portion block 306, an interconnection portion block 307, and an interconnection portion block 308. Each interconnection portion block may be located in an encapsulated portion (e.g., 102) of the package substrate 300. An interconnection portion block may include a coreless substrate block, a cored substrate block, a metallization portion block, a redistribution portion block and/or a die block comprising through substrate vias. A cored substrate block may include a passive device located in the cored substrate block, as described in FIG. 2. Examples of different types of interconnection portion blocks are further described below in at least FIGS. 5-9.

[0060] FIG. 3 illustrates an example of how an integrated device 103 may vertically overlap with the package substrate 300. As shown in FIG. 3, the integrated device 103 may vertically overlap (e.g., partial vertical overlap, complete vertical overlap) with the interconnection portion block 302, the interconnection portion block 303, the interconnection portion block 304 and the interconnection portion block 305. Different implementations may have the integrated device 103 vertically overlap differently with a package substrate and/or interconnection portion blocks of a package substrate.

[0061] Power, ground and/or input/output signals to and/or from the integrated device 103 may extend through one or more electrical paths that include the interconnection portion block 301, the interconnection portion block 302, the interconnection portion block 303, an interconnection portion block 304, the interconnection portion block 305, the interconnection portion block 306, the interconnection portion block 307, and/or the interconnection portion block 308. Examples of electrical paths for packages are further described below in detail in at least FIGS. 10-11.

[0062] In one example, the interconnection portion block 301 may be configured for providing electrical paths for high speed input/output signals to and/from memory of one or more integrated devices, which may require fine line width and spacing, and thin dielectric layers between metal layers. The interconnection portion block 301 may be implemented as a metallization portion block (e.g., redistribution portion block).

[0063] In one example, the interconnection portion block 302 and/or the interconnection portion block 304 may be configured for providing power to one or more integrated devices, which may require thick interconnects for efficient power delivery to the integrated device 103. The interconnection portion block 302 and/or the interconnection portion block 304 may be implemented as a laminate substate block (e.g., coreless substrate block, cored substrate block).

[0064] In one example, the interconnection portion block 303 may be configured to provide electrical paths for a power distribution network (PDN) (e.g., PDN power rails). The interconnection portion block 303 may be implemented as a die block comprising through substrate vias.

[0065] In one example, the interconnection portion block 305 may be configured to provide electrical paths for input/output signals (e.g., I/O signals). The interconnection portion block 305 may be implemented as a partial integrated device shadow block and a peripheral region block for a package. As an example, the interconnection portion block 305 may be implemented as a metallization portion block (e.g., redistribution portion block).

[0066] In one example, the interconnection portion block 306 and/or the interconnection portion block 308 may be configured for providing electrical paths for high speed input/output signals to and/from one or more integrated devices, which may require fine line width and spacing, and thick dielectric layers between metal layers. The interconnection portion block 306 and/or the interconnection portion block 308 may be implemented as a metallization portion block (e.g., redistribution portion block).

[0067] In one example, the interconnection portion block 307 may be configured for providing electrical paths for high speed input/output signals to and/from memory of one or more integrated devices, which may require ultra-fine line width and spacing. The interconnection portion block 307 may be implemented as a die block or a metallization portion block (e.g., redistribution portion block).

[0068] The use of various types of interconnection portion blocks allows a package substrate to be customized and/or optimized in such a way that electrical paths for different portions of one or more integrated device includes interconnects that are fabricated and/or formed using an optimal substrate fabrication technology that provides the best possible performance for the integrated devices. An integrated device may include several cores that are configured for different functions. Different interconnection portion blocks may be used to provide electrical paths for different cores of the integrated device. FIG. 3 illustrates one integrated device. However, in some implementations, two or more integrated device may be coupled to the package substrate 300. In some implementations, one interconnection portion block may be used to provide (i) a first electrical path for a first integrated device and (ii) a second electrical path for a second integrated device. FIG. 3 is merely an example of a possible configuration of a package substrate. Different implementations of a package substrate may include a different number of interconnection portion blocks, a different combination of interconnection portion blocks and/or interconnection portion blocks with different sizes and/or shapes.

[0069] FIG. 4 illustrates a cross sectional profile view of a package 400 that includes a package substrate with an encapsulated portion comprising several interconnection portion blocks. The package 400 is similar to the package 200, and includes similar components as the package 200. One difference is that the package 400 includes several integrated devices coupled to a package substrate.

[0070] The package 400 includes a package substrate 401, an integrated device 103 and an integrated device 403. The integrated device 103 is coupled to the package substrate 401 through a plurality of solder interconnects 130. There may be a plurality of pillar interconnects (not shown) between the integrated device 103 and the plurality of solder interconnects 130. In some implementations, the plurality of pillar interconnects (not shown) coupled to the integrated device 103 and the plurality of solder interconnects 130, are considered part of the integrated device 103.

[0071] The integrated device 403 is coupled to the package substrate 401 through a plurality of solder interconnects 430. There may be a plurality of pillar interconnects (not shown) between the integrated device 403 and the plurality of solder interconnects 430. In some implementations, the plurality of pillar interconnects (not shown) coupled to the integrated device 403 and the plurality of solder interconnects 430, are considered part of the integrated device 403.

[0072] The package substrate 401 includes an encapsulated portion 102, a metallization portion 104 (e.g., first metallization portion) and a metallization portion 106 (e.g., second metallization portion). The metallization portion 104 may be coupled to a first surface (e.g., top surface) of the encapsulated portion 102. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142 (e.g., first plurality of metallization interconnects). The metallization portion 104 may include a redistribution portion. The plurality of metallization interconnects 142 may include a plurality of redistribution interconnects (e.g., first plurality of redistribution interconnects). The integrated device 103 is coupled to the plurality of metallization interconnects 142 through the plurality of solder interconnects 130. The integrated device 403 is coupled to the plurality of metallization interconnects 142 through the plurality of solder interconnects 430. [0073] The metallization portion 106 may be coupled to a second surface (e.g., bottom surface) of the encapsulated portion 102. The metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallization interconnects 162 (e.g., second plurality of metallization interconnects). The metallization portion 106 may include a redistribution portion. The plurality of metallization interconnects 162 may include a plurality of redistribution interconnects (e.g., second plurality of redistribution interconnects). In some implementations, the metallization portion 104 and/or the metallization portion 106 may be optional. Thus, for example, in some implementations, the integrated devices (e.g., 103, 403) may be coupled to the encapsulated portion 102 of the package substrate 101, through a plurality of solder interconnects (e.g., 130, 430). Similarly, in some implementations, the encapsulated portion 102 of the package substrate 101 may be coupled to the board 108 through a plurality of solder interconnects. [0074] The encapsulated portion 102 is located between the metallization portion 104 and the metallization portion 106. The metallization portion 104 may be coupled to a first surface of the encapsulated portion 102. The metallization portion 106 may be coupled to a second surface of the encapsulated portion 102. The encapsulated portion 102 includes an interconnection portion block 105 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block, fourth interconnection portion block), an interconnection portion block 109 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block, fourth interconnection portion block), an interconnection portion block 205 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block, fourth interconnection portion block), an interconnection portion block 207 (e.g., first interconnection portion block, second interconnection portion block, third interconnection portion block, fourth interconnection portion block), a plurality of pillar interconnects 122 and an encapsulation layer 120. The encapsulation layer 120 encapsulates the interconnection portion block 105, the interconnection portion block 109, the interconnection portion block 205, the interconnection portion block 207 and the plurality of pillar interconnects 122. Examples of electrical paths through interconnection portion blocks for the package 400 are further described below in detail in at least FIG. 11.

[0075] In some implementations, one of more of integrated devices (e.g., 103, 403) described in the disclosure may be fabricated using the same technology node or two or more different technology nodes. For example, an integrated device (e.g., 103) may be fabricated using a first technology node, and another chiplet (e.g., 403) may be fabricated using a second technology node that is not as advanced as the first technology node. In such an example, the integrated device (e.g., 103) may include components (e.g., interconnects, transistors) that have a first minimum size, and the other chiplet (e.g., 403) may include components (e.g., interconnects, transistors) that have a second minimum size, where the second minimum size is greater than the first minimum size. In some implementations, the integrated device 103 and the integrated device 403 of a package, may be fabricated using the same technology node or different technology nodes. In some implementations, a chiplet (e.g., 103) and another chiplet (e.g., 403) of a package, may be fabricated using the same technology node or different technology nodes.

[0076] FIGS. 5-9 illustrate various types of interconnection portion blocks that may be implemented in a package substrate. It is noted that the interconnection portion blocks shown are merely examples. Different implementations may include interconnection portion blocks with different sizes, shapes, configurations, and numbers of metal layers. [0077] FIG. 5 illustrates the interconnection portion block 105 that includes at least one dielectric layer 150 and a plurality of interconnects 152. The interconnection portion block 105 may include a coreless substrate block (e.g., embedded trace substrate block). The interconnection portion block 105 may be a laminated substrate block. The interconnection portion block 105 may have different numbers of metal layers. The interconnection portion block 105 includes interconnects that are embedded in the at least one dielectric layer 150 and surface interconnects that are located on a surface of the at least one dielectric layer 150.

[0078] FIG. 6 illustrates the interconnection portion block 107 that includes a core layer 170, at least one dielectric layer 172, at least one dielectric layer 174 and a plurality of interconnects 173. The core layer 170 may be dielectric layer. The core layer 170 may include a different dielectric material or a same dielectric material, as the at least one dielectric layer 172 and/or the at least one dielectric layer 174. The interconnection portion block 107 may include a cored substrate block. The interconnection portion block 107 may be a laminated substrate block. The interconnection portion block 107 may have different numbers of metal layers.

[0079] FIG. 7 illustrates the interconnection portion block 207 that includes a core layer 170, at least one dielectric layer 172, at least one dielectric layer 174, a plurality of interconnects 173 and a passive device 270. The interconnection portion block 207 may be similar to the interconnection portion block 107. The core layer 170 may be dielectric layer. The core layer 170 may include a different dielectric material or a same dielectric material, as the at least one dielectric layer 172 and/or the at least one dielectric layer 174. The passive device 270 may be a capacitor. The passive device 270 may be located in the core layer 170 of the interconnection portion block 207. The passive device 270 may be laterally surrounded by the core layer 170 of the interconnection portion block 207. Terminals of the passive device 270 may be coupled to interconnects of the plurality of interconnects 173. The interconnection portion block 207 may include a cored substrate block. The interconnection portion block 207 may be a laminated substrate block. The interconnection portion block 207 may be a cored substrate block comprising a passive device. The interconnection portion block 207 may be an embedded passive substrate. The interconnection portion block 207 may have different numbers of metal layers.

[0080] FIG. 8 illustrates the interconnection portion block 109 that includes at least one dielectric layer 190 and a plurality of interconnects 192. The interconnection portion block 109 may include a metallization portion block. A metallization portion block may include a redistribution portion that includes redistribution interconnects (e.g., redistribution layer (RDL) interconnects). A redistribution interconnect may include portions that have a U-shape or V-shape. The terms “U-shape” and” V-shape” shall be interchangeable. The terms “U-shape” and “V-shape” may refer to the side profile shape of the interconnects and/or redistribution interconnects. The U-shape interconnect (e.g., U-shape side profile interconnect) and the V-shape interconnect (e.g., V-shape side profile interconnect) may have a top portion and a bottom portion. A bottom portion of a U-shape interconnect (or a V-shape interconnect) may be coupled to a top portion of another U-shape interconnect (or a V-shape interconnect). The interconnection portion block 109 may have different numbers of metal layers. In some implementations, a process for fabricating redistribution interconnects may form the U-shape interconnect (or the V-shape interconnect).

[0081] FIG. 9 illustrates the interconnection portion block 205 that includes a die substrate 250 (e.g., silicon substrate) and a plurality of interconnects 252. The plurality of interconnects 252 may include through substrate vias (e.g., through silicon vias). The interconnection portion block 205 may include die that includes vias. Although not shown, the interconnection portion block 205 may be include interconnects located on the first surface and/or the second surface of the die substrate 250. These interconnects may be pads that may be coupled to the through substrate vias of the interconnection portion block 205. [0082] The above interconnection portion blocks may be fabricated differently and may have different minimum interconnects sizes. The above interconnection portion blocks may be ideally suited for providing interconnects as electrical paths for different types of current, signals, power and/or ground. Different implementations may use different combinations of the above interconnection portion blocks in an encapsulated portion. In some implementations, two or more of the same type of interconnection portion blocks may be implemented in an encapsulated portion of a package substrate. In such instances, the same type of interconnection portion blocks may have different designs, such as having a different number of metal layers, while still considered to be the same type of interconnection portion block.

[0083] Moreover, the above interconnection portion blocks may have different costs associated with them and/or fabrication yields associated with them. Fabrication yields for an interconnection portion blocks affects the overall cost of the interconnection portion block. In some implementations, these costs and/or yields may be taken into account when determining which interconnection portion blocks to implement in the package substrate of a package.

[0084] Different types of interconnection portion blocks may have similar thicknesses or different thicknesses, depending on the design of the interconnection portion blocks. For example, in some implementations, an interconnection portion block that is implemented as a metallization portion block may have more metal layers than another interconnection portion block implemented as a laminate substrate block, but still have an overall thickness that is less than the thickness of the laminate substrate block.

[0085] Table 1 below illustrates exemplary values for interconnects and dielectric layers for different types of interconnection portion blocks.

Table 1 - Exemplary values of features for different interconnection portion blocks.

[0086] As shown above, interconnects from a metallization portion / redistribution portion have the smallest minimum line width and spacing (2/2 means a minimum line width of 2 micrometers and a minimum spacing of 2 micrometers). Thus, interconnection portion blocks that implement metallization layer / redistribution layer properties may be well suited for high density interconnects that are configured to provide electrical paths for input/output signals (VO signals). Laminate coreless substrate technology and/or laminate cored substrate technology have higher minimum line width, minimum spacing and minimum interconnect thickness (e.g., relative to a metallization portion) that may be more suited for interconnects that are configured to provide electrical paths for power and/or ground. A cored substrate that includes a passive device, may include the same features and/or properties as the laminate cored substrate. Thus, an interconnection portion block that is implemented as an embedded passive substrate may have a minimum line width, a minimum spacing and/or a minimum interconnect thickness that are similar to those of the laminate cored substrate.

[0087] The range in minimum dimensions (e.g., 2/2— 5/5) for a particular type of interconnection portion blocks may mean that a type of interconnection portion blocks may be fabricated in several ways and the minimum dimensions may be dependent on the type of fabrication process that is used for that particular type of interconnection portion block. Using the example above, a range of 2/2 - 5/5 means that in some instances, a minimum line width of 2 micrometers and a minimum spacing of 2 micrometers is possible, and in some instances, a minimum line width of 5 micrometers and a minimum spacing of 5 micrometers is possible.

[0088] An interconnection portion block that is implemented as a die block that includes through substrate vias may have a minimum line width in a range of about 5- 150 micrometers and/or a minimum spacing in a range of about 5-150 micrometers. An interconnection portion block that is implemented as a die block with through substrate vias may have a minimum height for the vias in a range of about 20-200 micrometers.

[0089] There are several advantages to using different types of interconnection portion blocks. One, this type of package substrate may provide better yields compared to other package substrates, which helps reduce the overall cost of the package. Two, this type of package substrate enables different substrate technology to be used and/or selected for different regional routing, which also helps provide better yield. Thus, for example, more expensive substrate technology is used for regions where it is needed, and more cost effective substrate technology is used for regions where the more expensive substrate technology is not needed. Three, this type of package substrate can be easily redesigned, by replacing one of more of the interconnection portion blocks with a different type of interconnection portion blocks, thus avoiding the need to completely redesign the package substrate from scratch. Interconnects on the same metal layer of the package substrate can have different thicknesses by using different types of interconnection portion blocks. Using different interconnect technologies enables a package substrate to be highly customizable and still be cost effective (or not cost prohibitive).

[0090] FIGS. 10 and 11 illustrate exemplary electrical paths between (i) one or more integrated devices of a package and (ii) a board. FIG. 10 illustrates exemplary electrical paths for the package 200 that includes the integrated device 103. The integrated device 103 includes a core 1032, a core 1034, a core 1036 and a core 1038. Each core may be configured to perform one or more functions. A core may include a memory, a processing unit (e.g., central processing unit, graphics processing unit), and/or a modem. FIG. 10 illustrates an electrical path 1001, an electrical path 1002, an electrical path 1003, an electrical path 1004, an electrical path 1005 and an electrical path 1006.

[0091] The electrical path 1001 may include an electrical path between the core 1032 of the integrated device 103 and the board 108. However, it is noted that the electrical path 1001 may extend to other components beyond the board 108. The electrical path 1001 between the core 1032 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 152 of the interconnection portion block 105, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0092] The electrical path 1002 may include an electrical path between the core 1032 of the integrated device 103 and the board 108. However, it is noted that the electrical path 1002 may extend to other components beyond the board 108. The electrical path

1002 between the core 1032 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (v) a solder interconnect from the plurality of solder interconnects 110, and (vi) a board interconnect from the plurality of board interconnects 182.

[0093] The electrical path 1003 may include an electrical path between the core 1034 of the integrated device 103 and the board 108. However, it is noted that the electrical path 1003 may extend to other components beyond the board 108. The electrical path

1003 between the core 1034 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0094] The electrical path 1004 may include an electrical path between the integrated device 103 and the board 108. However, it is noted that the electrical path 1004 may extend to other components beyond the board 108. The electrical path 1004 between the integrated device 103 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (v) the passive device 270, (vi) more interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (vii) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (viii) a solder interconnect from the plurality of solder interconnects 110, and (ix) a board interconnect from the plurality of board interconnects 182.

[0095] The electrical path 1005 may include an electrical path between the core 1036 of the integrated device 103 and the board 108. However, it is noted that the electrical path 1005 may extend to other components beyond the board 108. The electrical path

1005 between the core 1036 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) an interconnect from the plurality of interconnects 252 of the interconnection portion block 205, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0096] The electrical path 1006 may include an electrical path between the core 1038 of the integrated device 103 and the board 108. However, it is noted that the electrical path 1006 may extend to other components beyond the board 108. The electrical path

1006 between the core 1038 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 192 of the interconnection portion block 109, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0097] FIG. 11 illustrates exemplary electrical paths for the package 400 that includes the integrated device 103 and the integrated device 403. The integrated device 103 includes a core 1132 and a core 1134. The integrated device 403 includes a core 1142 and a core 1144. Each core may be configured to perform one or more functions. A core may include a memory, a processing unit (e.g., central processing unit, graphics processing unit), and/or a modem. FIG. 11 illustrates an electrical path 1101, an electrical path 1102, an electrical path 1103, an electrical path 1104, an electrical path 1105, an electrical path 1106, and an electrical path 1107.

[0098] The electrical path 1101 may include an electrical path between the core 1132 of the integrated device 103 and the board 108. However, it is noted that the electrical path 1101 may extend to other components beyond the board 108. The electrical path 1101 between the core 1132 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 152 of the interconnection portion block 105, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0099] The electrical path 1102 may include an electrical path between the integrated device 103 and the board 108. However, it is noted that the electrical path 1102 may extend to other components beyond the board 108. The electrical path 1102 between the integrated device 103 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (v) a solder interconnect from the plurality of solder interconnects 110, and (vi) a board interconnect from the plurality of board interconnects 182.

[0100] The electrical path 1103 may include an electrical path between the core 1034 of the integrated device 103 and the board 108. However, it is noted that the electrical path 1103 may extend to other components beyond the board 108. The electrical path 1103 between the core 1134 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0101] The electrical path 1104 may include an electrical path between the integrated device 403 and the board 108. However, it is noted that the electrical path 1104 may extend to other components beyond the board 108. The electrical path 1104 between the integrated device 403 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 430, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (v) the passive device 270,

(vi) more interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (vii) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (viii) a solder interconnect from the plurality of solder interconnects 110, and (ix) a board interconnect from the plurality of board interconnects 182.

[0102] The electrical path 1105 may include an electrical path between the core 1142 of the integrated device 403 and the board 108. However, it is noted that the electrical path 1105 may extend to other components beyond the board 108. The electrical path

1105 between the core 1142 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 430, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) an interconnect from the plurality of interconnects 252 of the interconnection portion block 205, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and

(vii) a board interconnect from the plurality of board interconnects 182.

[0103] The electrical path 1106 may include an electrical path between the core 1144 of the integrated device 403 and the board 108. However, it is noted that the electrical path 1106 may extend to other components beyond the board 108. The electrical path

1106 between the core 1144 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 430, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 192 of the interconnection portion block 109, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0104] The electrical path 1107 may include an electrical path between the integrated device 103 and the integrated device 403. The electrical path 1107 between the integrated device 103 and the integrated device 403 may include (i) a solder interconnect from the plurality of solder interconnects 130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, and (iii) a solder interconnect from the plurality of solder interconnects 430.

[0105] An integrated device (e.g., 103, 403) may include a die (e.g., semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs) based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SiC) based integrated device, a memory, power management processor, and/or combinations thereof. An integrated device (e.g., 103, 403) may include at least one electronic circuit (e.g., first electronic circuit, second electronic circuit, etc...). An integrated device may include an input/output (I/O) hub. An integrated device may include transistors. An integrated device may be an example of an electrical component and/or electrical device.

[0106] In some implementations, an integrated device may be a chiplet. A chiplet may be fabricated using a process that provides better yields compared to other processes used to fabricate other types of integrated devices, which can lower the overall cost of fabricating a chiplet. Different chiplets may have different sizes and/or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different width and/or spacing). In some implementations, several chiplets may be used to perform the functionalities of one or more chips (e.g., one more integrated devices). As mentioned above, using several chiplets that perform several functions may reduce the overall cost of a package relative to using a single chip to perform all of the functions of a package. In some implementations, one or more of the chiplets and/or one of more of integrated devices (e.g., 103, 403) described in the disclosure may be fabricated using the same technology node or two or more different technology nodes. For example, an integrated device (e.g., 103) may be fabricated using a first technology node, and a chiplet may be fabricated using a second technology node that is not as advanced as the first technology node. In such an example, the integrated device (e.g., 103) may include components (e.g., interconnects, transistors) that have a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) that have a second minimum size, where the second minimum size is greater than the first minimum size. In some implementations, the integrated device 103 and the integrated device 403 of a package, may be fabricated using the same technology node or different technology nodes. In some implementations, a chiplet and another chiplet of a package, may be fabricated using the same technology node or different technology nodes.

[0107] A technology node may refer to a specific fabrication process and/or technology that is used to fabricate an integrated device and/or a chiplet. A technology node may specify the smallest possible size (e.g., minimum size) that can be fabricated (e.g., size of a transistor, width of trace, gap with between two transistors). Different technology nodes may have different yield loss. Different technology nodes may have different costs. Technology nodes that produce components (e.g., trace, transistors) with fine details are more expensive and may have higher yield loss, than a technology node that produces components (e.g., trace, transistors) with details that are less fine. Thus, more advanced technology nodes may be more expensive and may have higher yield loss, than less advanced technology nodes. When all of the functions of a package are implemented in single integrated devices, the same technology node is used to fabricate the entire integrated device, even if some of the functions of the integrated devices do not need to be fabricated using that particular technology node. Thus, the integrated device is locked into one technology node. To optimize the cost of a package, some of the functions can be implemented in different integrated devices and/or chiplets, where different integrated devices and/or chiplets may be fabricated using different technology nodes to reduce overall costs. For example, functions that require the use of the most advanced technology node may be implemented in an integrated device, and functions that can be implemented using a less advanced technology node can be implemented in another integrated device and/or one or more chiplets. One example, would be an integrated device, fabricated using a first technology node (e.g., most advanced technology node), that is configured to provide compute applications, and at least one chiplet, that is fabricated using a second technology node, that is configured to provide other functionalities, where the second technology node is not as costly as the first technology node, and where the second technology node fabricates components with minimum sizes that are greater than the minimum sizes of components fabricated using the first technology node. Examples of compute applications may include high performance computing and/or high performance processing, which may be achieved by fabricating and packing in as many transistors as possible in an integrated device, which is why an integrated device that is configured for compute applications may be fabricated using the most advanced technology node available, while other chiplets may be fabricated using less advanced technology nodes, since those chiplets may not require as many transistors to be fabricated in the chiplets. Thus, the combination of using different technology nodes (which may have different associated yield loss) for different integrated devices and/or chiplets, can reduce the overall cost of a package, compared to using a single integrated device to perform all the functions of the package.

[0108] Another advantage of splitting the functions into several integrated devices and/or chiplets, is that it allows improvements in the performance of the package without having to redesign every single integrated device and/or chiplet. For example, if a configuration of a package uses a first integrated device and a first chiplet, it may be possible to improve the performance of the package by changing the design of the first integrated device, while keeping the design of the first chiplet the same. Thus, the first chiplet could be reused with the improved and/or different configured first integrated device. This saves cost by not having to redesign the first chiplet, when packages with improved integrated devices are fabricated.

[0109] Table 2 below illustrates how different chiplets may be paired and/or configured with blocks of a package substrate. It is noted that Table 2 is merely an example of possible chiplets and pairing with blocks of a package substrate, and that other implementations may have different pairings, use different chiplets and/or use different combinations of chiplets.

Table 2 - Chiplet Configurations and Pairing with Blocks

[0110] Table 2 illustrates examples of how different chiplets and/or different pairs of chiplets may be paired with different blocks of a package substrate. For example, a high power consumption chiplet may be paired with a block that has thicker and/or bigger interconnects (e.g., coreless substrate block, cored substrate block), and a medium or low power consumption chiplet may be paired with a block that has thinner and/or smaller interconnects (e.g., coreless substrate block, cored substrate block, redistribution portion block). In another example, a high VO speed chiplet may be paired with a block that has smaller line and spacing interconnects (e.g., redistribution portion block, embedded trace substrate block), and a low speed chiplet may be paired with a block that has larger line and spacing interconnects (e.g., coreless substrate block, cored substrate block, redistribution portion block). In another example, an advanced technology node chiplet may be paired with a block that has smaller line and spacing interconnects (e.g., redistribution portion block, embedded trace substrate block), and a relaxed technology node chiplet may be paired with a block that has larger line and spacing interconnects (e.g., coreless substrate block, cored substrate block, redistribution portion block). The term pairing a chiplet with a block may mean that the block is configured to provide at least one electrical path for the chiplet. A chiplet may be paired with more than one block and/or more than one type of block. As such, when a chiplet is paired with a block of a package substrate, it does not necessarily mean that the chiplet cannot be paired with another block of the package substrate. Similarly, two or more chiplets may be paired with the same block and/or the same type of block. Thus, a block may be configured to provide at least two separate electrical paths for two or more chiplets. Table 2 illustrates how different technology nodes for integrated devices and/or chiplets may be implemented with different technology nodes for package substrates and/or blocks, to reduce costs, improve and/or optimize the performance of the package that includes integrated devices and/or chiplets.

[0111] A metallization portion (e.g., 104, 106) may include a redistribution portion that includes redistribution interconnects (e.g., redistribution layer (RDL) interconnects). A redistribution interconnect may include portions that have a U-shape or V-shape. The terms “U-shape” and” V-shape” shall be interchangeable. The terms “U-shape” and “V- shape” may refer to the side profile shape of the interconnects and/or redistribution interconnects. The U-shape interconnect (e.g., U-shape side profile interconnect) and the V-shape interconnect (e.g., V-shape side profile interconnect) may have a top portion and a bottom portion. A bottom portion of a U-shape interconnect (or a V-shape interconnect) may be coupled to a top portion of another U-shape interconnect (or a V-shape interconnect).

[0112] An encapsulation layer (e.g., 120) may include a mold, a resin and/or an epoxy. The encapsulation layer may be a means for encapsulation. The encapsulation layer may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0113] As mentioned above, a package may include several metallization portions. Any of the metallization portions may be a first metallization portion, and/or any of the metallization portions may be a second metallization portion. For example, in some implementations, the metallization portion 104 may be considered a first metallization portion, and the metallization portion 106 may be considered a second metallization portion. In some implementations, the metallization portion 106 may be considered a first metallization portion, and the metallization portion 104 may be considered a second metallization portion.

Exemplary Sequence for Fabricating a Package Comprising a Package Substrate With an Encapsulated Portion Comprising Interconnection Portion Blocks

[0114] FIGS. 12A-12F illustrate an exemplary sequence for providing or fabricating a package that includes a package substrate with an encapsulated portion with several interconnection portion blocks. In some implementations, the sequence of FIGS. 12A- 12F may be used to provide or fabricate the package 100 of FIG. 1, or any of the packages described in the disclosure.

[0115] It should be noted that the sequence of FIGS. 12A-12F may combine one or more stages in order to simplify and/or clarify the sequence for providing or fabricating the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the scope of the disclosure. The sequence of FIGS. 12A-12F may be used to fabricate one package or several packages at a time (as part of a wafer).

[0116] Stage 1, as shown in FIG. 12A, illustrates a state after several interconnection portion blocks are provided. Examples of interconnection portion blocks include the interconnection portion block 105, the interconnection portion block 107 and the interconnection portion block 109. Different implementations may use different combinations and/or numbers of interconnection portion blocks. Providing interconnection portion blocks may include fabricating interconnection portion blocks. Examples of how different types of interconnection portion blocks may be fabricated are illustrated and described below in at least FIGS. 14A-14C, FIGS. 16A-16B and FIGS. 18A-18B.

[0117] Stage 2 illustrates a state after the interconnection portion block 105, the interconnection portion block 107 and the interconnection portion block 109 are placed on a carrier 1200. In some implementations, an adhesive may be used to place the interconnection portion blocks on the carrier 1200. A carrier may include a substrate, glass, quartz and/or carrier tape.

[0118] Stage 3 illustrates a state after a plurality of pillar interconnects 122 are formed and coupled to the interconnection portion blocks (e.g., 105, 107, 109) and the carrier 1200. A plating process may be used to form the plurality of pillar interconnects 122. Some of the plurality of pillar interconnects 122 may be formed and coupled to interconnects of the interconnection portion blocks.

[0119] Stage 4 illustrates a state after an encapsulation layer 120 is formed over the carrier 1200 and the interconnection portion blocks. The encapsulation layer 120 may encapsulate the interconnection portion block 105, the interconnection portion block 107, the interconnection portion block 109 and the plurality of pillar interconnects 122. The encapsulation layer 120 may include a mold, a resin and/or an epoxy. The encapsulation layer 120 may be a means for encapsulation. The encapsulation layer 120 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0120] Stage 5, as shown in FIG. 12B, illustrates a state after portion of the encapsulation layer 120 and portions of the plurality of pillar interconnects 122 are removed. A grinding process may be used to remove a top portion of the encapsulation layer 120 and a top portion of the plurality of pillar interconnects 122 to reduce the thickness of the encapsulation layer 120 and/or reduce the height of the plurality of pillar interconnects 122. Stage 5 may illustrate an encapsulated portion 102 that includes the encapsulation layer 120, the plurality of pillar interconnects 122 and several interconnection portion blocks.

[0121] Stage 6 illustrates a state after the metallization portion 104 is formed and coupled to the encapsulation layer 120 and the plurality of pillar interconnects 122. The metallization portion 104 is coupled to the encapsulated portion 102. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The plurality of metallization interconnects 142 may include a plurality of redistribution interconnects. The plurality of metallization interconnects 142 may be coupled to the plurality of pillar interconnects 122. In some implementations, the metallization portion 104 may be formed using the sequence shown in at least FIGS 18A- 18B. The metallization portion 104 may have different numbers of metal layers. For example, in some implementations, the metallization portion 104 may have one or two metal layers. In some implementations, the metallization portion 104 may have properties that are the same or similar as described in Table 1 for the redistribution layer.

[0122] Stage 7 illustrates a state after the carrier 1200 is decoupled from the encapsulated portion 102. The carrier 1200 may be removed and/or detached from the encapsulated portion 102. [0123] Stage 8, as shown in FIG. 12C, illustrates a state after the encapsulated portion 102 and the metallization portion 104 are placed on a carrier 1210. In some implementations, an adhesive may be used to place the encapsulated portion 102 and the metallization portion 104 on the carrier 1210. The metallization portion 104 may be coupled to the carrier 1210. The carrier 1210 may be similar to the carrier 1200.

[0124] Stage 9 illustrates a state after the metallization portion 106 is formed and coupled to the encapsulation layer 120, the plurality of pillar interconnects 122 and the interconnection portion blocks (e.g., 105, 107, 109). The metallization portion 106 is coupled to the encapsulated portion 102 such that the encapsulated portion 102 is located between the metallization portion 104 and the metallization portion 106. The metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallization interconnects 162. The plurality of metallization interconnects 162 may include a plurality of redistribution interconnects. The plurality of metallization interconnects 162 may be coupled to the plurality of pillar interconnects 122 and interconnects from the interconnection portion blocks (e.g., 105, 107, 109). In some implementations, the metallization portion 106 may be formed using the sequence shown in at least FIGS 18A-18B. The metallization portion 106 may have different numbers of metal layers. For example, in some implementations, the metallization portion 106 may have one or two metal layers. In some implementations, the metallization portion 106 may have properties that are the same or similar as described in Table 1 for the redistribution layer.

[0125] Stage 10 illustrates a state after the carrier 1210 is decoupled from the metallization portion 104. The carrier 1210 may be removed and/or detached from the metallization portion 104.

[0126] Stage 11, as shown in FIG. 12D, illustrates a state after the encapsulated portion 102, the metallization portion 104 and the metallization portion 106 are placed on a carrier 1220. In some implementations, an adhesive may be used to place the encapsulated portion 102, the metallization portion 104 and the metallization portion 106 on the carrier 1220. The metallization portion 106 may be coupled to the carrier 1220. The carrier 1220 may be similar to the carrier 1200 and/or the carrier 1210.

[0127] Stage 12 illustrates a state after a solder resist layer 148 is formed on the metallization portion 104. The solder resist layer 148 may include several openings over one or more metallization interconnects from the plurality of metallization interconnects 142. A deposition and/or lamination process may be used to form the solder resist layer 148. Stage 12 may illustrate a package substrate 201 that includes the encapsulated portion 102, the metallization portion 104 and the metallization portion 106.

[0128] Stage 13, as shown in FIG. 12E, illustrates a state after an integrated device 103 is coupled to the metallization portion 104 through a plurality of solder interconnects 130. A solder reflow process may be used to couple the plurality of solder interconnects 130 to the metallization interconnects of the metallization portion 104.

[0129] Stage 14 illustrates a state after the carrier 1220 is decoupled from the metallization portion 106. The carrier 1220 may be removed and/or detached from the metallization portion 106.

[0130] Stage 15, as shown in FIG. 12F, illustrates a state after a plurality of solder interconnects 110 are coupled to the package substrate 201. A solder reflow process may be used to couple the plurality of solder interconnects 110 to the plurality of metallization interconnects 162 of the metallization portion 106. Stage 15 may illustrate a package 200 that includes an integrated device 103 and a package substrate 201 that includes an encapsulated portion 102 with several interconnection portion blocks.

Exemplary Flow Diagram of a Method for Fabricating a Package Comprising a Package Substrate With an Encapsulated Portion Comprising Interconnection Portion Blocks

[0131] In some implementations, fabricating a package includes several processes. FIG. 13 illustrates an exemplary flow diagram of a method 1300 for providing or fabricating a package. In some implementations, the method 1300 of FIG. 13 may be used to provide or fabricate any of the packages of the disclosure. For example, the method 1300 of FIG. 13 may be used to fabricate the package 100.

[0132] It should be noted that the method 1300 of FIG. 13 may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the scope of the disclosure. The method 1300 of FIG. 13 may be used to fabricate one package or several packages at a time (as part of a wafer). [0133] The method provides (at 1305) several interconnection portion blocks on a carrier. For example, several interconnection portion blocks may be provided and/or fabricated and placed on a carrier. A carrier may include a substrate, glass, quartz and/or carrier tape. Stage 1 of FIG. 12A, illustrates and describes an example several interconnection portion blocks. Examples of interconnection portion blocks include an interconnection portion block 105, an interconnection portion block 107 and an interconnection portion block 109. Different implementations may use different types of interconnection portion blocks, different combinations interconnection portion blocks and/or numbers of interconnection portion blocks. Providing interconnection portion blocks may include fabricating interconnection portion blocks. Examples of how different types of interconnection portion blocks may be fabricated are illustrated and described below in at least FIGS. 14A-14C, FIGS. 16A-16B and FIGS. 18A-18B.

[0134] Stage 2 of FIG. 12A, illustrates and describes an example of the interconnection portion block 105, the interconnection portion block 107 and the interconnection portion block 109 placed on a carrier 1200. In some implementations, an adhesive may be used to place the interconnection portion blocks on the carrier 1200.

[0135] The method forms and couples (at 1310) a plurality of pillar interconnects to interconnection portion blocks. Stage 3 of FIG. 12A, illustrates and describes an example of a plurality of pillar interconnects 122 that are formed and coupled to the interconnection portion blocks (e.g., 105, 107, 109) and the carrier 1200. A plating process may be used to form the plurality of pillar interconnects 122. Some of the plurality of pillar interconnects 122 may be formed and coupled to interconnects of the interconnection portion blocks.

[0136] The method forms (at 1315) an encapsulation layer that encapsulates the interconnection portion blocks and the plurality of pillar interconnects. Stage 4 of FIG. 12A, illustrates and describes an example of an encapsulation layer 120 that is formed over the carrier 1200 and the interconnection portion blocks. The encapsulation layer 120 may encapsulate the interconnection portion block 105, the interconnection portion block 107, the interconnection portion block 109 and the plurality of pillar interconnects 122. The encapsulation layer 120 may include a mold, a resin and/or an epoxy. The encapsulation layer 120 may be a means for encapsulation. The encapsulation layer 120 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0137] Forming an encapsulation layer may also include removing portion of the encapsulation layer. Stage 5 of FIG. 12B, illustrates and describes an example of portions of the encapsulation layer 120 and portions of the plurality of pillar interconnects 122 that are removed. A grinding process may be used to remove a top portion of the encapsulation layer 120 and a top portion of the plurality of pillar interconnects 122 to reduce the thickness of the encapsulation layer 120 and/or reduce the height of the plurality of pillar interconnects 122. Stage 5 of FIG. 12B, may illustrate an encapsulated portion 102 that includes the encapsulation layer 120, the plurality of pillar interconnects 122 and several interconnection portion blocks. Forming the encapsulation layer that encapsulates the interconnection portion blocks and the plurality of pillars interconnects may form an encapsulated portion 102.

[0138] The method forms (at 1320) a first metallization portion that is coupled to the encapsulation layer and the plurality of pillar interconnects. Stage 6 of FIG. 12B, illustrates and describes an example of the metallization portion 104 that is formed and coupled to the encapsulation layer 120 and the plurality of pillar interconnects 122. The metallization portion 104 is coupled to the encapsulated portion 102. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The plurality of metallization interconnects 142 may include a plurality of redistribution interconnects. The plurality of metallization interconnects 142 may be coupled to the plurality of pillar interconnects 122. In some implementations, the metallization portion 104 may be formed using the sequence shown in at least FIGS 18A- 18B. The metallization portion 104 may have different numbers of metal layers. In some implementations, the metallization portion 104 may have properties that are the same or similar as described in Table 1 for the redistribution layer.

[0139] After the metallization portion 104 is formed, a carrier may be removed. Stage 7 of FIG. 12B, illustrates a state after the carrier 1200 is decoupled from the encapsulated portion 102. The carrier 1200 may be removed and/or detached from the encapsulated portion 102.

[0140] The method forms (at 1325) a second metallization portion that is coupled to the encapsulation layer, the plurality of pillar interconnects and the interconnection portion blocks. The second metallization portion may be formed after the encapsulation layer, the plurality of pillar interconnects and the interconnection portion blocks are placed on another carrier. Stage 8 of FIG. 12C, illustrates and describes an example of the encapsulated portion 102 and the metallization portion 104 that are placed on a carrier 1210. In some implementations, an adhesive may be used to place the encapsulated portion 102 and the metallization portion 104 on the carrier 1210. The metallization portion 104 may be coupled to the carrier 1210.

[0141] Stage 9 of FIG. 12C, illustrates and describes an example of the metallization portion 106 that is formed and coupled to the encapsulation layer 120, the plurality of pillar interconnects 122 and the interconnection portion blocks (e.g., 105, 107, 109). The metallization portion 106 is coupled to the encapsulated portion 102 such that the encapsulated portion 102 is located between the metallization portion 104 and the metallization portion 106. The metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallization interconnects 162. The plurality of metallization interconnects 162 may include a plurality of redistribution interconnects. The plurality of metallization interconnects 162 may be coupled to the plurality of pillar interconnects 122 and interconnects from the interconnection portion blocks (e.g., 105, 107, 109). In some implementations, the metallization portion 106 may be formed using the sequence shown in at least FIGS 18A-18B. The metallization portion 106 may have different numbers of metal layers. In some implementations, the metallization portion 106 may have properties that are the same or similar as described in Table 1 for the redistribution layer.

[0142] After the metallization portion 106 is formed, a carrier may be removed. Stage 10 of FIG. 12C, illustrates a state after the carrier 1210 is decoupled from the metallization portion 104. The carrier 1210 may be removed and/or detached from the metallization portion 104. Forming and/or providing the encapsulated portion 102, the metallization portion 104 and the metallization portion 106 may form a package substrate (e.g., 101, 201, 401).

[0143] After the carrier is removed, the encapsulated portion 102, the metallization portion 104 and the metallization portion 106 may be placed on another carrier. Stage 11 of FIG. 12D, illustrates and describes an example of the encapsulated portion 102, the metallization portion 104 and the metallization portion 106 that are placed on a carrier 1220. In some implementations, an adhesive may be used to place the encapsulated portion 102, the metallization portion 104 and the metallization portion 106 on the carrier 1220. The metallization portion 106 may be coupled to the carrier 1220.

[0144] In some implementations, a solder resist layer may be formed on the metallization portion 104. Stage 12 of FIG. 12D, illustrates and describes an example of a solder resist layer 148 that is formed on the metallization portion 104. The solder resist layer 148 may include several openings over one or more metallization interconnects from the plurality of metallization interconnects 142. Stage 12 of FIG. 12D, may illustrate a package substrate 201 that includes the encapsulated portion 102, the metallization portion 104 and the metallization portion 106.

[0145] The method couples (at 1330) one or more integrated devices to the package substrate. Stage 13 of FIG. 12E, illustrates and describes an example of an integrated device 103 that is coupled to the metallization portion 104 through a plurality of solder interconnects 130. A solder reflow process may be used to couple the plurality of solder interconnects 130 to the metallization interconnects of the metallization portion 104.

[0146] Once the integrated device is coupled to the package substrate, a carrier may be removed. Stage 14 of FIG. 12E, illustrates and describes the carrier 1220 that is decoupled from the metallization portion 106. The carrier 1220 may be removed and/or detached from the metallization portion 106.

[0147] The method couples (at 1335) a plurality of solder interconnects to the package substrate. Stage 15 of FIG. 12F, illustrates and describes an example of a plurality of solder interconnects 110 that are coupled to the package substrate 201. A solder reflow process may be used to couple the plurality of solder interconnects 110 to the plurality of metallization interconnects 162 of the metallization portion 106. Stage 15 of FIG. 12F, may illustrate a package 200 that includes an integrated device 103 and a package substrate 201 that includes an encapsulated portion 102 with several interconnection portion blocks.

Exemplary Sequence for Fabricating a Coreless Substrate

[0148] In some implementations, fabricating a coreless substrate includes several processes. FIGS. 14A-14C illustrate an exemplary sequence for providing or fabricating a coreless substrate. The coreless substrate may be implemented as a coreless substrate block. In some implementations, the sequence of FIGS. 14A-14C may be used to provide or fabricate the interconnection portion block 105. However, the process of FIGS. 14A- 14C may be used to fabricate other interconnection portion blocks described in the disclosure.

[0149] It should be noted that the sequence of FIGS. 14A-14C may combine one or more stages in order to simplify and/or clarify the sequence for providing or fabricating a coreless substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the scope of the disclosure.

[0150] Stage 1, as shown in FIG. 14A, illustrates a state after a carrier 1400 is provided. The carrier 1400 may include a substrate. The carrier 1400 may include a seed layer 1402 located on a first surface of the carrier 1400 and a seed layer 1404 located on a second surface of the carrier 1400. The carrier 1400 may be a dielectric. [0151] Stage 2 illustrates a state after interconnects are formed in and over surfaces of the carrier 1400. A plurality of interconnects 1412 may be formed over (e.g., above) a first surface of the carrier 1400. The seed layer 1402 may be part of the plurality of interconnects 1412. A plurality of interconnects 1414 may be formed over (e.g., below) a second surface of the carrier 1400. The seed layer 1404 may be part of the plurality of interconnects 1414. A masking, a plating and/or an etching process may be used to form the plurality of interconnects 1412 and/or the plurality of interconnects 1414.

[0152] Stage 3 illustrates a state after a dielectric layer 1420 is formed over (e.g., above) the first surface of the carrier 1400 and the plurality of interconnects 1412. Stage 3 also illustrates a state after a dielectric layer 1430 is formed over (e.g., below) the second surface of the carrier 1400 and the plurality of interconnects 1414. A deposition and/or a lamination process may be used to form the dielectric layer 1420 and the dielectric layer 1430. The dielectric layer 1420 and the dielectric layer 1430 may be a different material than the carrier 1400.

[0153] Stage 4 illustrates a state after a plurality of cavities 1421 are formed in the dielectric layer 1420 and a plurality of cavities 1431 are formed in the dielectric layer 1430. The plurality of cavities 1421 and the plurality of cavities 1431 may be formed using an etching process (e.g., photo etching process). A masking, an exposure and/or a development process may be used to form the plurality of cavities 1421 and the plurality of cavities 1431.

[0154] Stage 5, as shown in FIG. 14B, illustrates a state after interconnects are formed in and over surfaces of the dielectric layer 1420 and the dielectric layer 1430. A plurality of interconnects 1422 may be formed over (e.g., above) a first surface of the dielectric layer 1420 and the plurality of cavities 1421. A plurality of interconnects 1432 may be formed over (e.g., below) a second surface of the dielectric layer 1430 and the plurality of cavities 1431. A masking, a plating and/or an etching process may be used to form the plurality of interconnects 1422 and/or the plurality of interconnects 1432.

[0155] Stage 6 illustrates a state after a dielectric layer 1440 is formed over (e.g., above) the first surface of the dielectric layer 1420 and the plurality of interconnects 1422. Stage 6 also illustrates a state after a dielectric layer 1450 is formed over (e.g., below) the second surface of the dielectric layer 1430 and the plurality of interconnects 1432. A deposition and/or a lamination process may be used to form the dielectric layer 1440 and the dielectric layer 1450. The dielectric layer 1440 and/or the dielectric layer 1450 may be the same dielectric layer as the dielectric layer 1420 and/or the dielectric layer 1430. [0156] Stage 7 illustrates a state after a plurality of cavities 1441 are formed in the dielectric layer 1440 (which is shown as being part of the dielectric layer 1425) and a plurality of cavities 1451 are formed in the dielectric layer 1450 (which is shown as being part of the dielectric layer 1427). The plurality of cavities 1441 and the plurality of cavities 1451 may be formed using an etching process (e.g., photo etching process). A masking, an exposure and/or a development process may be used to form the plurality of cavities 1441 and the plurality of cavities 1451. The dielectric layer 1425 may represent the dielectric layer 1420 and/or the dielectric layer 1440. The dielectric layer 1427 may represent the dielectric layer 1430 and/or the dielectric layer 1450.

[0157] Stage 8, as shown in FIG. 14C, illustrates a state after interconnects are formed in and over surfaces of the dielectric layer 1425 and the dielectric layer 1427. A plurality of interconnects 1442 may be formed over (e.g., above) a first surface of the dielectric layer 1425 and the plurality of cavities 1441. A plurality of interconnects 1452 may be formed over (e.g., below) a second surface of the dielectric layer 1427 and the plurality of cavities 1451. A masking, a plating and/or an etching process may be used to form the plurality of interconnects 1442 and/or the plurality of interconnects 1452. The plurality of interconnects 1422 and/or the plurality of interconnects 1442 may be represented by a plurality of interconnects 1424, as shown at stage 9. The plurality of interconnects 1432 and/or the plurality of interconnects 1452 may be represented by a plurality of interconnects 1426, as shown at stage 9.

[0158] Stage 9 illustrates a state after (i) the interconnection portion block 105a is decoupled from the carrier 1400, and (ii) the interconnection portion block 105b is decoupled from the carrier 1400. The interconnection portion block 105a may be implemented as a coreless substrate or a coreless substrate block. The interconnection portion block 105b may be implemented as a coreless substrate or a coreless substrate block.

Exemplary Flow Diagram of a Method for Fabricating a Coreless Substrate

[0159] In some implementations, fabricating a coreless substrate includes several processes. FIG. 15 illustrates an exemplary flow diagram of a method 1500 for providing or fabricating a coreless substrate. In some implementations, the method 1500 of FIG. 15 may be used to provide or fabricate any of the coreless substrate and/or coreless substrate block of the disclosure. For example, the method 1500 of FIG. 15 may be used to fabricate the interconnection portion block 105. [0160] It should be noted that the method 1500 of FIG. 15 may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating a coreless substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the scope of the disclosure. The method 1500 of FIG. 15 may be used to fabricate one substrate or several substrates at a time (as part of a wafer).

[0161] The method provides (at 1505) a carrier with a seed layer. Stage 1 of FIG. 14A illustrates and describes an example of a carrier 1400 that is provided. The carrier 1400 may include a substrate. The carrier 1400 may include a seed layer 1402 located on a first surface of the carrier 1400 and a seed layer 1404 located on a second surface of the carrier 1400. The carrier 1400 may be a dielectric.

[0162] The method forms (at 1510) interconnects on one or both sides of the carrier. Stage 2 of FIG. 14A, illustrates and describes an example of interconnects that are formed in and over surfaces of the carrier 1400. A plurality of interconnects 1412 may be formed over (e.g., above) a first surface of the carrier 1400. The seed layer 1402 may be part of the plurality of interconnects 1412. A plurality of interconnects 1414 may be formed over (e.g., below) a second surface of the carrier 1400. The seed layer 1404 may be part of the plurality of interconnects 1414. A masking, a plating and/or an etching process may be used to form the plurality of interconnects 1412 and/or the plurality of interconnects 1414. [0163] The method forms (at 1515) at least one dielectric layer over the interconnects, the seed layer and the carrier. Stage 3 of FIG. 14A illustrates and describes an example of a dielectric layer 1420 that is formed over (e.g., above) the first surface of the carrier 1400 and the plurality of interconnects 1412. Stage 3 of FIG. 14A also illustrates and describes a dielectric layer 1430 that is formed over (e.g., below) the second surface of the carrier 1400 and the plurality of interconnects 1414. A deposition and/or a lamination process may be used to form the dielectric layer 1420 and the dielectric layer 1430. The dielectric layer 1420 and the dielectric layer 1430 may be a different material than the carrier 1400. Forming the at least one dielectric layer may also include forming cavities in the dielectric layer. Stage 4 of FIG. 14A, illustrates and describes a plurality of cavities 1421 that are formed in the dielectric layer 1420 and a plurality of cavities 1431 that are formed in the dielectric layer 1430. The plurality of cavities 1421 and the plurality of cavities 1431 may be formed using an etching process (e.g., photo etching process). A masking, an exposure and/or a development process may be used to form the plurality of cavities 1421 and the plurality of cavities 1431.

[0164] The method forms (at 1520) interconnects in and over the dielectric layer(s). Stage 5 of FIG. 14B, illustrates and describes an example of interconnects that are formed in and over surfaces of the dielectric layer 1420 and the dielectric layer 1430. A plurality of interconnects 1422 may be formed over (e.g., above) a first surface of the dielectric layer 1420 and the plurality of cavities 1421. A plurality of interconnects 1432 may be formed over (e.g., below) a second surface of the dielectric layer 1430 and the plurality of cavities 1431. A masking, a plating and/or an etching process may be used to form the plurality of interconnects 1422 and/or the plurality of interconnects 1432.

[0165] The method forms (at 1525) at least one dielectric layer over the interconnects and dielectric layer. Stage 6 of FIG. 14B illustrates and describes an example of a dielectric layer 1440 that is formed over (e.g., above) the first surface of the dielectric layer 1420 and the plurality of interconnects 1422. Stage 6 of FIG. 14B also illustrates and describes an example of a dielectric layer 1450 that is formed over (e.g., below) the second surface of the dielectric layer 1430 and the plurality of interconnects 1432. A deposition and/or a lamination process may be used to form the dielectric layer 1440 and the dielectric layer 1450. The dielectric layer 1440 and/or the dielectric layer 1450 may be the same dielectric layer as the dielectric layer 1420 and/or the dielectric layer 1430. Forming the at least one dielectric layer may also include forming cavities in the dielectric layer. Stage 7 of FIG. 14B illustrates and describes an example of a plurality of cavities 1441 that are formed in the dielectric layer 1440 (which is shown as being part of the dielectric layer 1425) and a plurality of cavities 1451 are formed in the dielectric layer 1450 (which is shown as being part of the dielectric layer 1427). The plurality of cavities 1441 and the plurality of cavities 1451 may be formed using an etching process (e.g., photo etching process). A masking, an exposure and/or a development process may be used to form the plurality of cavities 1441 and the plurality of cavities 1451. The dielectric layer 1425 may represent the dielectric layer 1420 and/or the dielectric layer 1440. The dielectric layer 1427 may represent the dielectric layer 1430 and/or the dielectric layer 1450.

[0166] The method forms (at 1530) interconnects in and over the dielectric layer(s). Stage 8 of FIG. 14C, illustrates and describes interconnects that are formed in and over surfaces of the dielectric layer 1440 and the dielectric layer 1450. A plurality of interconnects 1442 may be formed over (e.g., above) a first surface of the dielectric layer 1440 and the plurality of cavities 1441. A plurality of interconnects 1452 may be formed over (e.g., below) a second surface of the dielectric layer 1450 and the plurality of cavities 1451. A masking, a plating and/or an etching process may be used to form the plurality of interconnects 1442 and/or the plurality of interconnects 1452. The plurality of interconnects 1422 and/or the plurality of interconnects 1442 may be represented by a plurality of interconnects 1424, as shown at stage 9. The plurality of interconnects 1432 and/or the plurality of interconnects 1452 may be represented by a plurality of interconnects 1426, as shown at stage 9 of FIG. 14C.

[0167] The method decouples (at 1535) the carrier and removes portions of a seed layer. Stage 9 of FIG. 14C illustrates and describes an example of (i) the interconnection portion block 105a that decoupled from the carrier 1400, and (ii) the interconnection portion block 105b is decoupled from the carrier 1400. The interconnection portion block 105a may be implemented as a coreless substrate or a coreless substrate block. The interconnection portion block 105b may be implemented as a coreless substrate or a coreless substrate block.

Exemplary Sequence for Fabricating a Cored Substrate

[0168] In some implementations, fabricating a cored substrate includes several processes. FIGS. 16A-16B illustrate an exemplary sequence for providing or fabricating a cored substrate. The cored substrate may be implemented as a cored substrate block. In some implementations, the cored substrate may include a passive device. In some implementations, the sequence of FIGS. 16A-16B may be used to provide or fabricate the interconnection portion block 107 and/or the interconnection portion block 207. However, the process of FIGS. 16A-16B may be used to fabricate other interconnection portion blocks described in the disclosure.

[0169] It should be noted that the sequence of FIGS. 16A-16B may combine one or more stages in order to simplify and/or clarify the sequence for providing or fabricating a cored substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the scope of the disclosure.

[0170] Stage 1, as shown in FIG. 16A, illustrates a state after a core layer 1600 is provided. The core layer 1600 may include a seed layer 1602 located on a first surface of the core layer 1600 and a seed layer 1604 located on a second surface of the core layer 1600. The core layer 1600 may be a dielectric. [0171] Stage 2 illustrates a state after a plurality of cavities 1605 are formed through the core layer 1600, the seed layer 1602 and the seed layer 1604. The plurality of cavities 1605 may be formed using an etching process and/or laser process.

[0172] Stage 3 illustrates a state after interconnects are formed in and over surfaces of the core layer 1600. A plurality of core interconnects 1622 may be formed in the plurality of cavities 1605. A plurality of interconnects 1612 may be formed over (e.g., above) a first surface of the core layer 1600. The seed layer 1602 may be part of the plurality of interconnects 1612. A plurality of interconnects 1614 may be formed over (e.g., below) a second surface of the core layer 1600. The seed layer 1604 may be part of the plurality of interconnects 1614. A masking, a plating and/or an etching process may be used to form the plurality of core interconnects 1622, the plurality of interconnects 1612 and/or the plurality of interconnects 1614. In some implementations, a passive device (e.g., 270) may be placed in one of the cavities from the plurality of cavities 1605 before the interconnects are formed. When a passive device is placed in a cavity, a dielectric layer may be formed around the passive device before interconnects are formed. In some implementations, interconnects may be formed such that some interconnects touch terminals of the passive device.

[0173] Stage 4 illustrates a state after a dielectric layer 1620 is formed over (e.g., above) the first surface of the core layer 1600 and the plurality of interconnects 1612. Stage 4 also illustrates a state after a dielectric layer 1630 is formed over (e.g., below) the second surface of the core layer 1600 and the plurality of interconnects 1614. A deposition and/or a lamination process may be used to form the dielectric layer 1620 and the dielectric layer 1630. The dielectric layer 1620 and the dielectric layer 1630 may be a different material than the core layer 1600.

[0174] Stage 5, as shown in FIG. 16B, illustrates a state after a plurality of cavities 1621 are formed in the dielectric layer 1620 and a plurality of cavities 1631 are formed in the dielectric layer 1630. The plurality of cavities 1621 and the plurality of cavities 1631 may be formed using an etching process (e.g., photo etching process). A masking, an exposure and/or a development process may be used to form the plurality of cavities

1621 and the plurality of cavities 1631.

[0175] Stage 6 illustrates a state after interconnects are formed in and over surfaces of the dielectric layer 1620 and the dielectric layer 1630. A plurality of core interconnects

1622 may be formed over (e.g., above) a first surface of the dielectric layer 1620 and the plurality of cavities 1621. A plurality of interconnects 1632 may be formed over (e.g., below) a second surface of the dielectric layer 1630 and the plurality of cavities 1631. A masking, a plating and/or an etching process may be used to form the plurality of core interconnects 1622 and/or the plurality of interconnects 1632.

[0176] Stage 6 may illustrate an interconnection portion block that is implemented as a cored substrate. Stage 6 may illustrate an example of the interconnection portion block 107. Different implementations may use different processes for forming the metal layer(s) and/or interconnects. It is noted that Stages 4-6 of FIGS. 16A-16B may be iteratively repeated to form additional metal layers.

Exemplary Flow Diagram of a Method for Fabricating a Cored Substrate

[0177] In some implementations, fabricating a cored substrate includes several processes. FIG. 17 illustrates an exemplary flow diagram of a method 1700 for providing or fabricating a cored substrate. In some implementations, the method 1700 of FIG. 17 may be used to provide or fabricate any of the cored substrate and/or cored substrate block of the disclosure. For example, the method 1700 of FIG. 17 may be used to fabricate the interconnection portion block 107 and/or the interconnection portion block 207.

[0178] It should be noted that the method 1700 of FIG. 17 may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating a cored substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the scope of the disclosure. The method 1700 of FIG. 17 may be used to fabricate one substrate or several substrates at a time (as part of a wafer).

[0179] The method provides (at 1705) a core layer with at least one seed layer. Stage 1 of FIG. 16 A, illustrates and describes an example of a core layer 1600 is provided. The core layer 1600 may include a seed layer 1602 located on a first surface of the core layer 1600 and a seed layer 1604 located on a second surface of the core layer 1600. The core layer 1600 may be a dielectric.

[0180] The method forms (at 1710) cavities in the core layer. Stage 2 of FIG. 16A illustrates and describes an example of a plurality of cavities 1605 that are formed through the core layer 1600, the seed layer 1602 and the seed layer 1604. The plurality of cavities 1605 may be formed using an etching process and/or laser process.

[0181] The method forms (at 1715) interconnects in/on the core layer. Stage 3 of FIG. 16 A, illustrates and describes an example of interconnects that are formed in and over surfaces of the core layer 1600. A plurality of core interconnects 1622 may be formed in the plurality of cavities 1605. A plurality of interconnects 1612 may be formed over (e.g., above) a first surface of the core layer 1600. The seed layer 1602 may be part of the plurality of interconnects 1612. A plurality of interconnects 1614 may be formed over (e.g., below) a second surface of the core layer 1600. The seed layer 1604 may be part of the plurality of interconnects 1614. A masking, a plating and/or an etching process may be used to form the plurality of core interconnects 1622, the plurality of interconnects 1612 and/or the plurality of interconnects 1614. In some implementations, a passive device (e.g., 270) may be placed in one of the cavities from the plurality of cavities 1605 before the interconnects are formed. When a passive device is placed in a cavity, a dielectric layer may be formed around the passive device before interconnects are formed. In some implementations, interconnects may be formed such that some interconnects touch terminals of the passive device.

[0182] The method forms (at 1720) at least one dielectric layer. Stage 4 of FIG. 16A, illustrates and describes an example of a dielectric layer 1620 that is formed over (e.g., above) the first surface of the core layer 1600 and the plurality of interconnects 1612. Stage 4 of FIG. 16A, also illustrates and describes an example of a dielectric layer 1630 that is formed over (e.g., below) the second surface of the core layer 1600 and the plurality of interconnects 1614. A deposition and/or a lamination process may be used to form the dielectric layer 1620 and the dielectric layer 1630. The dielectric layer 1620 and the dielectric layer 1630 may be a different material than the core layer 1600. Forming the at least one dielectric layer may include forming cavities in the dielectric layer. Stage 5 of FIG. 16B, illustrates and describes an example of a plurality of cavities 1621 that are formed in the dielectric layer 1620 and a plurality of cavities 1631 that are formed in the dielectric layer 1630. The plurality of cavities 1621 and the plurality of cavities 1631 may be formed using an etching process (e.g., photo etching process). A masking, an exposure and/or a development process may be used to form the plurality of cavities 1621 and the plurality of cavities 1631.

[0183] The method forms (at 1725) interconnects. Stage 6 of FIG. 16B, illustrates and describes an example of interconnects that are formed in and over surfaces of the dielectric layer 1620 and the dielectric layer 1630. A plurality of core interconnects 1622 may be formed over (e.g., above) a first surface of the dielectric layer 1620 and the plurality of cavities 1621. A plurality of interconnects 1632 may be formed over (e.g., below) a second surface of the dielectric layer 1630 and the plurality of cavities 1631. A masking, a plating and/or an etching process may be used to form the plurality of core interconnects 1622 and/or the plurality of interconnects 1632. It is noted that additional dielectric layers and additional interconnects on additional metal layers may be formed by iteratively repeating the formation of the dielectric layer (at 1720) and the formation of interconnects (at 1725).

Exemplary Sequence for Fabricating a Metallization Portion

[0184] In some implementations, fabricating a metallization portion includes several processes. FIGS. 18A-18B illustrate an exemplary sequence for providing or fabricating a metallization portion and/or a metallization portion block. In some implementations, the sequence of FIGS. 18A-18B may be used to provide or fabricate a metallization portion block and/or a metallization portion (e.g., 104, 106). The process of FIGS. 18A-18B will be described to fabricate the interconnection portion block 109 (e.g., metallization portion block). However, the process of FIGS. 18A-18B may be used to fabricate any of the metallization portions described in the disclosure.

[0185] It should be noted that the sequence of FIGS. 18A-18B may combine one or more stages in order to simplify and/or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the scope of the disclosure.

[0186] Stage 1, as shown in FIG. 18 A, illustrates a state after a carrier 1800 is provided. A seed layer 1801 and interconnects 1802 may be located over the carrier 1800. The interconnects 1802 may be located over the seed layer 1801. A plating process and etching process may be used to form the interconnects 1802. In some implementations, the carrier 1800 may be provided with the seed layer 1801 and a metal layer that is patterned to form the interconnects 1802. The interconnects 1802 may represent at least some of the interconnects from the plurality of interconnects 192.

[0187] Stage 2 illustrates a state after a dielectric layer 1820 is formed over the carrier 1800, the seed layer 1801 and the interconnects 1802. A deposition and/or lamination process may be used to form the dielectric layer 1820. The dielectric layer 1820 may include prepreg and/or polyimide. The dielectric layer 1820 may include a photo- imageable dielectric. However, different implementations may use different materials for the dielectric layer. [0188] Stage 3 illustrates a state after a plurality of cavities 1810 are formed in the dielectric layer 1820. The plurality of cavities 1810 may be formed using a photolithography process or laser process. A masking, an exposure and/or a development process may be used to form the plurality of cavities 1810.

[0189] Stage 4 illustrates a state after interconnects 1812 are formed in and over the dielectric layer 1820, including in and over the plurality of cavities 1810. For example, a via, pad and/or traces may be formed. A plating process may be used to form the interconnects.

[0190] Stage 5 illustrates a state after a dielectric layer 1822 is formed over the dielectric layer 1820 and the interconnects 1812. A deposition and/or lamination process may be used to form the dielectric layer 1822. The dielectric layer 1822 may include prepreg and/or polyimide. The dielectric layer 1822 may include a photo-imageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0191] Stage 6, as shown in FIG. 18B, illustrates a state after a plurality of cavities 1830 are formed in the dielectric layer 1822. The plurality of cavities 1830 may be formed using a photolithography process or laser process. A masking, an exposure and/or a development process may be used to form the plurality of cavities 1830.

[0192] Stage 7 illustrates a state after interconnects 1814 are formed in and over the dielectric layer 1822, including in and over the plurality of cavities 1830. For example, a via, pad and/or traces may be formed. A plating process may be used to form the interconnects.

[0193] Stage 8 illustrates a state after the carrier 1800 is decoupled (e.g., detached, removed, grinded out) from the dielectric layer 1820 and the seed layer 1801, portions of the seed layer 1801 are removed (e.g., etched out), leaving the interconnection portion block 109 (e.g., metallization portion block) that includes at least one dielectric layer 190 and the plurality of interconnects 192. The at least one dielectric layer 190 may represent the dielectric layer 1820 and/or the dielectric layer 1822. The plurality of interconnects 192 may represent the interconnects 1802, 1812 and/or 1814.

[0194] FIGS. 18A-18B illustrate the metallization portion being formed on a carrier. In some implementations, the metallization portion and/or the metallization portion block may be fabricated on a surface of an encapsulated portion that includes an encapsulation layer and interconnects, thus bypassing the need for a carrier. Exemplary Flow Diagram of a Method for Fabricating a Metallization Portion

[0195] In some implementations, fabricating a metallization portion includes several processes. FIG. 19 illustrates an exemplary flow diagram of a method 1900 for providing or fabricating a metallization portion. The metallization portion may be implemented as a metallization portion block. In some implementations, the method 1900 of FIG. 19 may be used to provide or fabricate the metallization portion of the disclosure. For example, the method 1900 of FIG. 19 may be used to fabricate the metallization portion 104 and/or the metallization portion 106. However, the method 1900 of FIG. 19 will be described to fabricate the interconnection portion block 109.

[0196] It should be noted that the method 1900 of FIG. 19 may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating a metallization portion. In some implementations, the order of the processes may be changed or modified.

[0197] The method provides (at 1905) a carrier (e.g., 1800). Different implementations may use different materials for the carrier 1800. The carrier 1800 may include a seed layer (e.g., 1801). The seed layer 1801 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz and/or carrier tape. Stage 1 of FIG. 18A, illustrates and describes an example of a carrier with a seed layer that is provided.

[0198] The method forms and patterns (at 1910) interconnects over the carrier 1800 and the seed layer 1801. A metal layer may be patterned to form interconnects. A plating process may be used to form the metal layer and interconnects. In some implementations, the carrier and seed layer may include a metal layer. The metal layer is located over the seed layer and the metal layer may be patterned to form interconnects (e.g., 192). Stage 1 of FIG. 18 A, illustrates and describes an example of forming and patterning interconnects over a seed layer and a carrier. It is noted that instead of a carrier, interconnects may be formed over a surface of an encapsulated portion (e.g., 102) that includes an encapsulation layer and interconnects, such as when a metallization portion 104 and/or a metallization portion 106 are fabricated.

[0199] The method forms / provides (at 1915) a dielectric layer 1820 over the seed layer 1801, the carrier 1800 and the interconnects 1802. A deposition and/or lamination process may be used to form the dielectric layer 1820. The dielectric layer 1820 may include prepreg and/or polyimide. The dielectric layer 1820 may include a photo- imageable dielectric. Forming the dielectric layer 1820 may also include forming a plurality of cavities (e.g., 1810) in the dielectric layer 1820. The plurality of cavities may be formed using a photolithography or laser process. A masking, an exposure and/or a development process may be used to form the plurality of cavities 1810. Stages 2-3 of FIG. 18 A, illustrate and describe an example of forming a dielectric layer and cavities in the dielectric layer.

[0200] The method forms (at 1920) interconnects in and over the dielectric layer. For example, the interconnects 1812 may be formed in and over the dielectric layer 1820. A plating process may be used to form the interconnects. Forming interconnects may include providing a patterned metal layer over and/or in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Stage 4 of FIG. 18 A, illustrates and describes an example of forming interconnects in and over a dielectric layer.

[0201] The method forms / provides (at 1925) a dielectric layer 1822 over the dielectric layer 1820 and the interconnects 1812. A deposition and/or lamination process may be used to form the dielectric layer 1822. The dielectric layer 1822 may include prepreg and/or polyimide. The dielectric layer 1822 may include a photo-imageable dielectric. Forming the dielectric layer 1822 may also include forming a plurality of cavities (e.g., 1830) in the dielectric layer 1822. The plurality of cavities may be formed using a photolithography process or laser process. A masking, an exposure and/or a development process may be used to form the plurality of cavities 1830. Stages 5-6 of FIGS. 18A-18B, illustrate and describe an example of forming a dielectric layer and cavities in the dielectric layer.

[0202] The method forms (at 1930) interconnects in and over the dielectric layer. For example, the interconnects 1814 may be formed in and over the dielectric layer 1822. A plating process may be used to form the interconnects. Forming interconnects may include providing a patterned metal layer over and/or in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Stage 7 of FIG. 18B, illustrates and describes an example of forming interconnects in and over a dielectric layer. The method may form additional dielectric layer(s) and additional interconnects as described at 1925 and 1930.

[0203] In some implementations, once all the dielectric layer(s) and additional interconnects are formed, the method may decouple (at 1935) the carrier (e.g., 1800) from the seed layer (e.g., 1801). The carrier 1800 may be detached and/or grinded off. The method may also remove (at 1935) portions of the seed layer (e.g., 1801). An etching process may be used to remove portions of the seed layer 1801. Stage 8 of FIG. 18B, illustrates and describes an example of decoupling a carrier and seed layer removal.

[0204] FIG. 20 illustrates exemplary electrical paths for the package 2000 that includes a package substrate with an encapsulation portion with interconnection portion blocks. The package 2000 is similar to the package 1100 of FIG. 11. The package 2000 includes the integrated device 103, the integrated device 403, the integrated device 2003 and the integrated device 2013. The package 2000 also includes the package substrate 401, as described in at least FIGS. 4 and 11.

[0205] The integrated device 2003 is coupled to the integrated device 403 through a plurality of solder interconnects 2030. The integrated device 2013 is coupled to the integrated device 2003 through a plurality of solder interconnects 2070. In some implementations, the front side of the integrated device 2003 faces the back side of the integrated device 403. In some implementations, the back side of the integrated device 2003 faces the back side of the integrated device 403. In some implementations, the front side of the integrated device 2013 faces the back side of the integrated device 2013. In some implementations, the back side of the integrated device 2013 faces the back side of the integrated device 2013. In some implementations, the front side of the integrated device 2013 faces the front side of the integrated device 2013. In some implementations, the back side of the integrated device 2013 faces the front side of the integrated device 2013. FIG. 20 illustrates stacked integrated devices that may be defined by the integrated device 403, the integrated device 2003 and/or the integrated device 2013.

[0206] FIG. 20 illustrates an electrical path 1101, an electrical path 1102, an electrical path 1103, an electrical path 1104, an electrical path 1105, an electrical path 1106, an electrical path 1107 and an electrical path 2007. The electrical path 1101, the electrical path 1102, the electrical path 1103, the electrical path 1104, the electrical path 1105, the electrical path 1106, and the electrical path 1107 may be similar to the electrical paths illustrated and described in FIG. 11.

[0207] The electrical path 2007 may be an electrical path between the integrated device 403 and the integrated device 2013. The electrical path 2007 between the integrated device 403 and the integrated device 2013 may include (i) a solder interconnect from the plurality of solder interconnects 2030, (ii) interconnects from the integrated device 2003, and (iii) a solder interconnect from the plurality of solder interconnects 2070. Depending on how the integrated device 2003 is coupled to the integrated device 403 and/or how the integrated device 2013 is coupled to the integrated device 2003, the electrical path 2007 may extend through the back side of an integrated device and/or the front side of another integrated device. For example, the electrical path 2007 may extend through the back side of the integrated device 403, through a solder interconnect from the plurality of solder interconnects 2030, through the front side of the integrated device 2003, through the back side of the integrated device 2003, through a solder interconnect from the plurality of solder interconnects 2070 and through the front side of the integrated device 2013. The electrical path 2007 may be configured to be electrically coupled to the electrical path 1104, the electrical path 1105, the electrical path 1106 and/or the electrical path 1107.

[0208] FIG. 21 illustrates exemplary electrical paths for the package 2100 that includes a package substrate with an encapsulation portion with interconnection portion blocks. The package 2100 is similar to the package 1100 of FIG. 11. The package 2100 includes the integrated device 2102, the integrated device 2103 and the integrated device 2105. The package 2100 also includes the package substrate 401, as described in at least FIGS. 4 and 11.

[0209] The integrated device 2102 is coupled to the package substrate 401 through a plurality of solder interconnects 2120. The integrated device 2103 is coupled to the package substrate 401 through a plurality of solder interconnects 2130. The integrated device 2105 is coupled to the package substrate 401 through a plurality of solder interconnects 2150. The integrated device 2102, the integrated device 2103 and the integrated device 2105 are coupled to the metallization portion 104 of the package substrate 401.

[0210] As an example, in some implementations, the integrated device 2102 may be a first chiplet and the integrated device 2105 may be a second chiplet. The integrated device 2103 may include memory, such as a SRAM. In some implementations, an electrical path to the integrated device 2103 may include a cored substrate block and/or a coreless substrate block. In some implementations, the integrated device 2102 may include a relaxed technology node chiplet. In some implementations, an electrical path to the integrated device 2102 may include an embedded trace substrate block and/or a cored substrate block. In some implementations, the integrated device 2105 may include an advanced technology node chiplet. In some implementations, an electrical path to the integrated device 2105 may include a metallization portion block (e.g., redistribution portion block).

[0211] FIG. 21 illustrates an electrical path 2111, an electrical path 2112, an electrical path 2113, an electrical path 2114, an electrical path 2115, an electrical path 2116, an electrical path 2117 and an electrical path 2119.

[0212] The electrical path 2111 may include an electrical path between the integrated device 2103 and the board 108. However, it is noted that the electrical path 2111 may extend to other components beyond the board 108. The electrical path 2111 between the integrated device 2103 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 152 of the interconnection portion block 105, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0213] The electrical path 2112 may include an electrical path between the integrated device 2103 and the board 108. However, it is noted that the electrical path 2112 may extend to other components beyond the board 108. The electrical path 2112 between the integrated device 2103 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2130, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (v) a solder interconnect from the plurality of solder interconnects 110, and (vi) a board interconnect from the plurality of board interconnects 182.

[0214] The electrical path 2113 may include an electrical path between the integrated device 2102 and the board 108. However, it is noted that the electrical path 2113 may extend to other components beyond the board 108. The electrical path 2113 between the integrated device 2102 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2120, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0215] The electrical path 2114 may include an electrical path between the integrated device 2105 and the board 108. However, it is noted that the electrical path 2114 may extend to other components beyond the board 108. The electrical path 2114 between the integrated device 2105 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2150, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (v) the passive device 270, (vi) more interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (vii) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (viii) a solder interconnect from the plurality of solder interconnects 110, and (ix) a board interconnect from the plurality of board interconnects 182.

[0216] The electrical path 2115 may include an electrical path between the integrated device 2105 and the board 108. However, it is noted that the electrical path 2115 may extend to other components beyond the board 108. The electrical path 2115 between the integrated device 2105 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2150, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) an interconnect from the plurality of interconnects 252 of the interconnection portion block 205, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0217] The electrical path 2116 may include an electrical path between the integrated device 2105 and the board 108. However, it is noted that the electrical path 2116 may extend to other components beyond the board 108. The electrical path 2116 between the integrated device 2105 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2150, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (iii) a pillar interconnect from the plurality of pillar interconnects 122, (iv) interconnects from the plurality of interconnects 192 of the interconnection portion block 109, (v) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vi) a solder interconnect from the plurality of solder interconnects 110, and (vii) a board interconnect from the plurality of board interconnects 182.

[0218] The electrical path 2117 may include an electrical path between the integrated device 2102 and the integrated device 2105. The electrical path 2117 between the integrated device 2102 and the integrated device 2105 may include (i) a solder interconnect from the plurality of solder interconnects 2120, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, and (iii) a solder interconnect from the plurality of solder interconnects 2150. [0219] The electrical path 2119 may include an electrical path between the integrated device 2102 and the integrated device 2103. The electrical path 2119 between the integrated device 2102 and the integrated device 2103 may include (i) a solder interconnect from the plurality of solder interconnects 2120, (ii) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, and (iii) a solder interconnect from the plurality of solder interconnects 2130. [0220] FIG. 22 illustrates exemplary electrical paths for the package 2200 that includes a package substrate with an encapsulation portion with interconnection portion blocks. The package 2200 is similar to the package 2100 of FIG. 21. The package 2200 also includes an interposer 2201, an integrated device 2202, an integrated device 2203 and an integrated device 2205. The package 2200 also includes the package substrate 401, as described in at least FIGS. 4 and 11.

[0221] The interposer 2201 is located between the package substrate 401 and the integrated devices (e.g., 2202, 2203, 2205). The interposer 2201 may include interposer substrate 2210 (e.g., silicon substrate, silicon interposer substrate) and a plurality of interconnects 1 (e.g., plurality of interposer interconnects). The plurality of interconnects 1 may include via interconnects. In some implementations, the plurality of interconnects 1 may also include trace interconnects and pad interconnects. The interposer 2201 is coupled to the package substrate 401 through a plurality of solder interconnects 2240. The interposer 2201 may be coupled to the metallization portion 104 of the package substrate 401.

[0222] The integrated device 2202 is coupled to the interposer 2201 through a plurality of solder interconnects 2220. The integrated device 2203 is coupled to the interposer 2201 through a plurality of solder interconnects 2230. The integrated device 2205 is coupled to the interposer 2201 through a plurality of solder interconnects 2250.

[0223] FIG. 22 illustrates an electrical path 2211, an electrical path 2212, an electrical path 2213, an electrical path 2214, an electrical path 2215, an electrical path 2216, an electrical path 2217 and an electrical path 2219.

[0224] The electrical path 2211 may include an electrical path between the integrated device 2203 and the board 108. However, it is noted that the electrical path 2211 may extend to other components beyond the board 108. The electrical path 2211 between the integrated device 2203 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2230, (ii) at least one interconnect from the plurality of interconnects 2222, (iii) a solder interconnect from the plurality of solder interconnects 2240, (iv) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (v) a pillar interconnect from the plurality of pillar interconnects 122, (vi) interconnects from the plurality of interconnects 152 of the interconnection portion block 105, (vii) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (viii) a solder interconnect from the plurality of solder interconnects 110, and (ix) a board interconnect from the plurality of board interconnects 182.

[0225] The electrical path 2212 may include an electrical path between the integrated device 2203 and the board 108. However, it is noted that the electrical path 2212 may extend to other components beyond the board 108. The electrical path 2212 between the integrated device 2203 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2230, (ii) at least one interconnect from the plurality of interconnects 2222, (iii) a solder interconnect from the plurality of solder interconnects 2240, (iv) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (v) a pillar interconnect from the plurality of pillar interconnects 122, (vi) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (vii) a solder interconnect from the plurality of solder interconnects 110, and (viii) a board interconnect from the plurality of board interconnects 182.

[0226] The electrical path 2213 may include an electrical path between the integrated device 2202 and the board 108. However, it is noted that the electrical path 2213 may extend to other components beyond the board 108. The electrical path 2213 between the integrated device 2202 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2220, (ii) at least one interconnect from the plurality of interconnects 2222, (iii) a solder interconnect from the plurality of solder interconnects 2240, (iv) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (v) a pillar interconnect from the plurality of pillar interconnects 122, (vi) interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (vii) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (viii) a solder interconnect from the plurality of solder interconnects 110, and (ix) a board interconnect from the plurality of board interconnects 182.

[0227] The electrical path 2214 may include an electrical path between the integrated device 2205 and the board 108. However, it is noted that the electrical path 2214 may extend to other components beyond the board 108. The electrical path 2214 between the integrated device 2205 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2250, (ii) at least one interconnect from the plurality of interconnects 2222, (iii) a solder interconnect from the plurality of solder interconnects 2240, (iv) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (v) a pillar interconnect from the plurality of pillar interconnects 122, (vi) interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (vii) the passive device 270, (viii) more interconnects from the plurality of interconnects 173 of the interconnection portion block 207, (ix) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (x) a solder interconnect from the plurality of solder interconnects 110, and (xi) a board interconnect from the plurality of board interconnects 182.

[0228] The electrical path 2215 may include an electrical path between the integrated device 2205 and the board 108. However, it is noted that the electrical path 2215 may extend to other components beyond the board 108. The electrical path 2215 between the integrated device 2205 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2250, (ii) at least one interconnect from the plurality of interconnects 2222, (iii) a solder interconnect from the plurality of solder interconnects 2240, (iv) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (v) a pillar interconnect from the plurality of pillar interconnects 122, (vi) an interconnect from the plurality of interconnects 252 of the interconnection portion block 205, (vii) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (viii) a solder interconnect from the plurality of solder interconnects 110, and (ix) a board interconnect from the plurality of board interconnects 182.

[0229] The electrical path 2216 may include an electrical path between the integrated device 2205 and the board 108. However, it is noted that the electrical path 2216 may extend to other components beyond the board 108. The electrical path 2216 between the integrated device 2205 and the board 108 may include (i) a solder interconnect from the plurality of solder interconnects 2250, (ii) at least one interconnect from the plurality of interconnects 2222, (iii) a solder interconnect from the plurality of solder interconnects 2240, (iv) metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104, (v) a pillar interconnect from the plurality of pillar interconnects 122, (vi) interconnects from the plurality of interconnects 192 of the interconnection portion block 109, (vii) metallization interconnects from the plurality of metallization interconnects 162 of the metallization portion 106, (viii) a solder interconnect from the plurality of solder interconnects 110, and (ix) a board interconnect from the plurality of board interconnects 182.

[0230] The electrical path 2217 may include an electrical path between the integrated device 2202 and the integrated device 2205. The electrical path 2217 between the integrated device 2202 and the integrated device 2205 may include (i) a solder interconnect from the plurality of solder interconnects 2220, (ii) at least one interconnect from the plurality of interconnects 2222, and (iii) a solder interconnect from the plurality of solder interconnects 2250.

[0231] The electrical path 2219 may include an electrical path between the integrated device 2202 and the integrated device 2203. The electrical path 2219 between the integrated device 2202 and the integrated device 2203 may include (i) a solder interconnect from the plurality of solder interconnects 2220, (ii) at least one interconnect from the plurality of interconnects 2222, and (iii) a solder interconnect from the plurality of solder interconnects 2230.

[0232] It is noted that the use of the interposer 2201 is not limited to the package 2200. The interposer 2201 may be implemented in other packages, including other packages described and illustrated in the disclosure, in a similar manner.

[0233] It is noted that in some implementations, an integrated device may be coupled to another components, such as a package substrate or another integrated device through a plurality of pillar interconnects and a plurality of solder interconnects. Thus, when an integrated device is shown and described as being coupled to another component through a plurality of solder interconnects, that integrated device may be coupled to another component through a plurality of pillar interconnects and a plurality of solder interconnects.

[0234] It is noted that the electrical paths shown are exemplary. Different implementations may have different electrical paths. Different implementations may have a different number of electrical paths. In some implementations, an electrical path may represent one electrical path from the many electrical paths between two or more components.

Exemplary Electronic Devices

[0235] FIG. 23 illustrates various electronic devices that may be integrated with any of the aforementioned device, integrated device, integrated circuit (IC) package, integrated circuit (IC) device, semiconductor device, integrated circuit, die, interposer, package, package-on-package (PoP), System in Package (SiP), or System on Chip (SoC). For example, a mobile phone device 2302, a laptop computer device 2304, a fixed location terminal device 2306, a wearable device 2308, or automotive vehicle 2310 may include a device 2300 as described herein. The device 2300 may be, for example, any of the devices and/or integrated circuit (IC) packages described herein. The devices 2302, 2304, 2306 and 2308 and the vehicle 2310 illustrated in FIG. 23 are merely exemplary. Other electronic devices may also feature the device 2300 including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (loT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0236] One or more of the components, processes, features, and/or functions illustrated in FIGS. 1-11, 12A-12F, 13, 14A-14C, 15, 16A-16B, 17, 18A-18B and/or 19-23 may be rearranged and/or combined into a single component, process, feature or function or embodied in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be noted FIGS. 1-11, 12A-12F, 13, 14A-14C, 15, 16A-16B, 17, 18A-18B and/or 19-23 and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations, FIGS. 1-11, 12A- 12F, 13, 14A-14C, 15, 16A-16B, 17, 18A-18B and/or 19-23 and its corresponding description may be used to manufacture, create, provide, and/or produce devices and/or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipating device and/or an interposer.

[0237] It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.

[0238] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another — even if they do not directly physically touch each other. An object that is coupled to another object may be coupled to at least part of the another object. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electrical current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electrical current traveling between the two objects. The use of the terms “first”, “second”, “third” and “fourth” (and/or anything above fourth) is arbitrary. Any of the components described may be the first component, the second component, the third component or the fourth component. For example, a component that is referred to a second component, may be the first component, the second component, the third component or the fourth component. The term “encapsulating” means that the object may partially encapsulate or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component that is located on top may be located over a component that is located on a bottom. A top component may be considered a bottom component, and vice versa. As described in the disclosure, a first component that is located “over” a second component may mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component may be located over (e.g., above) a first surface of the second component, and a third component may be located over (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It is further noted that the term “over” as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. A first component that is located “in” a second component may be partially located in the second component or completely located in the second component. The term “about ‘value X’”, or “approximately value X”, as used in the disclosure means within 10 percent of the ‘value X’. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1. A “plurality” of components may include all the possible components or only some of the components from all of the possible components. For example, if a device includes ten components, the use of the term “the plurality of components” may refer to all ten components or only some of the components from the ten components.

[0239] In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and/or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground and/or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and/or sequences for forming the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and/or a plating process may be used to form the interconnects.

[0240] Also, it is noted that various disclosures contained herein may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.

[0241] In the following, further examples are described to facilitate the understanding of the invention.

[0242] Aspect 1: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block; a second interconnection portion block, wherein the second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block; a plurality of pillar interconnects, where the plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block; and a second plurality of pillar interconnects coupled to the second interconnection portion block; and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. [0243] Aspect 2: The package of aspect 1, wherein the first interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias. [0244] Aspect 3: The package of aspects 1 through 2, wherein the second interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias.

[0245] Aspect 4: The package of aspects 1 through 3, wherein the first metallization portion includes a first plurality of metallization interconnects comprising a first minimum width and a first minimum spacing, and wherein the second metallization portion includes a second plurality of metallization interconnects comprising a second minimum width and a second minimum spacing.

[0246] Aspect 5: The package of aspects 1 through 4, wherein the first integrated device is coupled to the first metallization portion of the package substrate through the first plurality of solder interconnects.

[0247] Aspect 6: The package of aspect 5, wherein the first integrated device includes a first core and a second core, wherein a first electrical path for a first signal to the first core of the first integrated device comprises the first interconnection portion block, and wherein a second electrical path for a second signal to the second core of the first integrated device comprises the second interconnection portion block.

[0248] Aspect 7: The package of aspects 5 through 6, further comprising a second integrated device coupled to the first metallization portion of the package substrate through a second plurality of solder interconnects.

[0249] Aspect 8: The package of aspect 7, wherein a first electrical path for a first signal to the first integrated device comprises the first interconnection portion block, and wherein a second electrical path for a second signal to the second integrated device comprises the second interconnection portion block.

[0250] Aspect 9: The package of aspect 7, wherein a first electrical path for a first signal between the second metallization portion and the first integrated device comprises interconnects from the first interconnection portion block, a pillar interconnect from the first plurality of pillar interconnects, metallization interconnects from the first metallization portion, and a first solder interconnect from the first plurality of solder interconnects, and wherein a second electrical path for a second electrical signal between the second metallization portion and the second integrated device comprises interconnects from the second interconnection portion block, a pillar interconnect from the second plurality of pillar interconnects, other metallization interconnects from the first metallization portion, and a second solder interconnect from the second plurality of solder interconnects.

[0251] Aspect 10: The package of aspects 1 through 7, further comprising a third interconnection portion block located in the encapsulated portion, wherein the plurality of pillar interconnects comprises a third plurality of pillar interconnects coupled to the third interconnection portion block.

[0252] Aspect 11 : The package of aspect 10, wherein the first interconnection portion block includes a coreless substrate block, wherein the second interconnection portion block includes a cored substrate block, and wherein the third interconnection portion block includes a metallization portion block.

[0253] Aspect 12: The package of aspects 10 through 11, wherein a first electrical path for a first electrical signal between the second metallization portion and the first integrated device comprises interconnects from the first interconnection portion block, a pillar interconnect from the first plurality of pillar interconnects, first metallization interconnects from the first metallization portion, and a first solder interconnect from the first plurality of solder interconnects, wherein a second electrical path for a second electrical signal between the second metallization portion and the first integrated device comprises interconnects from the second interconnection portion block, a pillar interconnect from the second plurality of pillar interconnects, second metallization interconnects from the first metallization portion, and a second solder interconnect from the first plurality of solder interconnects, and wherein a third electrical path for a third electrical signal between the second metallization portion and the first integrated device comprises interconnects from the third interconnection portion block, a pillar interconnect from the third plurality of pillar interconnects, third metallization interconnects from the first metallization portion, and a third solder interconnect from the first plurality of solder interconnects.

[0254] Aspect 13: The package of aspect 12, wherein interconnects from the metallization portion block are thinner than (i) interconnects from the coreless substrate block, and (ii) interconnects from the cored substrate block.

[0255] Aspect 14: The package of aspects 1 through 13, wherein the first interconnection portion block includes a first number of metal layers, and wherein the second interconnection portion block includes a second number of metal layers that is different than the first number of metal layers. [0256] Aspect 15: The package of aspects 1 through 7, wherein a first electrical path for a first electrical signal between the second metallization portion and the first integrated device comprises interconnects from the first interconnection portion block, a pillar interconnect from the first plurality of pillar interconnects, metallization interconnects from the first metallization portion, and a first solder interconnect from the first plurality of solder interconnects, wherein a second electrical path for a second electrical signal between the second metallization portion and the first integrated device comprises interconnects from the second interconnection portion block, a pillar interconnect from the second plurality of pillar interconnects, other metallization interconnects from the first metallization portion, and a second solder interconnect from the first plurality of solder interconnects.

[0257] Aspect 16: The package of aspects 1 through 7, wherein a first electrical path for a first electrical signal between the second metallization portion and the first integrated device comprises interconnects from the first interconnection portion block, a pillar interconnect from the first plurality of pillar interconnects, metallization interconnects from the first metallization portion, and a first solder interconnect from the first plurality of solder interconnects, wherein a second electrical path for power between the second metallization portion and the first integrated device comprises interconnects from the second interconnection portion block, a pillar interconnect from the second plurality of pillar interconnects, other metallization interconnects from the first metallization portion, and a second solder interconnect from the first plurality of solder interconnects.

[0258] Aspect 17: The package of aspect 16, wherein the second electrical path further includes a passive device located in the second interconnection portion block.

[0259] Aspect 18: The package of aspect 16, wherein the first interconnection portion block includes a metallization portion block, and wherein the second interconnection portion block includes a laminate substrate block.

[0260] Aspect 19: The package of aspect 16, wherein a third electrical path for ground between the second metallization portion and the first integrated device comprises other interconnects from the second interconnection portion block, another pillar interconnect from the second plurality of pillar interconnects, other metallization interconnects from the first metallization portion, and a third solder interconnect from the first plurality of solder interconnects.

[0261] Aspect 20: The package of aspect 1, further comprising a second integrated device coupled to the package through a second plurality of solder interconnects. [0262] Aspect 21: The package of aspect 20, wherein the first integrated device is a first chiplet comprising a first technology node, and wherein the second integrated device is a second chiplet comprising a second technology node.

[0263] Aspect 22: The package of aspect 1, further comprising a second integrated device coupled to the first integrated device through a second plurality of solder interconnects.

[0264] Aspect 23: The package of aspect 22, wherein the first integrated device is a first chiplet comprising a first technology node, wherein the second integrated device is a second chiplet comprising a second technology node, wherein the first interconnection portion block is configured to provide a first electrical path for the first integrated device, and wherein the second interconnection portion block is configured to provide a second electrical path for the second integrated device.

[0265] Aspect 24: The package of aspects 1 through 23, further comprising an interposer coupled to the package substrate through a second plurality of solder interconnects, wherein the first integrated device is coupled to the package substrate through the interposer such that the first plurality of solder interconnects is coupled to the interposer.

[0266] Aspect 25: The package of aspects 1 through 24, wherein the package is implemented in a device is that is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (loT) device, and a device in an automotive vehicle.

[0267] Aspect 26: A method for fabricating a package. The method provides a first interconnection portion block. The method provides a second interconnection portion block, wherein the second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block. The method forms a plurality of pillar interconnects, wherein the plurality of pillar interconnects comprises: a first plurality of pillar interconnects coupled to the first interconnection portion block; and a second plurality of pillar interconnects coupled to the second interconnection portion block. The method forms an encapsulation layer that at least partially encapsulates the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects, which forms an encapsulated portion. The method forms a first metallization portion that is coupled to a first surface of the encapsulated portion. The method forms a second metallization portion that is coupled to a second surface of the encapsulated portion. The encapsulated portion, the first metallization portion and the second metallization portion form a package substrate. The method couples a first integrated device to the package substrate through a first plurality of solder interconnects.

[0268] Aspect 27: The method of aspect 26, wherein the first interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias.

[0269] Aspect 28: The method of aspects 26 through 27, wherein the second interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias.

[0270] Aspect 29: The method of aspects 26 through 28, further comprising coupling a second integrated device to the package substrate through a second plurality of solder interconnects.

[0271] Aspect 30: The method of aspect 29, wherein a first electrical path for a first signal to the first integrated device comprises the first interconnection portion block, and wherein a second electrical path for a second signal to the second integrated device comprises the second interconnection portion block.

[0272] Aspect 31 : A method for fabricating a package substrate. The method provides a first interconnection portion block. The method provides a second interconnection portion block, wherein the second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block. The method forms a plurality of pillar interconnects, wherein the plurality of pillar interconnects comprises: a first plurality of pillar interconnects coupled to the first interconnection portion block; and a second plurality of pillar interconnects coupled to the second interconnection portion block. The method forms an encapsulation layer that at least partially encapsulates the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects, which forms an encapsulated portion. The method forms a first metallization portion that is coupled to a first surface of the encapsulated portion. The method forms a second metallization portion that is coupled to a second surface of the encapsulated portion. [0273] Aspect 32: The method of aspect 31, wherein the first interconnection portion block includes a first coreless substrate block, a first cored substrate block, a first embedded passive substrate block, a first metallization portion block or a first die block comprising through substrate vias, wherein the second interconnection portion block includes a second coreless substrate block, a second cored substrate block, a second embedded passive substrate block, a second metallization portion block or a second die block comprising through substrate vias.

[0274] Aspect 33: A method for fabricating a package. The method provides a package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block; a second interconnection portion block, wherein the second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block; a plurality of pillar interconnects, where the plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block; and a second plurality of pillar interconnects coupled to the second interconnection portion block. The encapsulated portion further comprises an encapsulation layer that at least partially encapsulates the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The method couples a first integrated device to the package substrate through a first plurality of solder interconnects.

[0275] Aspect 34: The method of aspect 33, wherein the first interconnection portion block includes a first coreless substrate block, a first cored substrate block, a first embedded passive substrate block, a first metallization portion block or a first die block comprising through substrate vias, wherein the second interconnection portion block includes a second coreless substrate block, a second cored substrate block, a second embedded passive substrate block, a second metallization portion block or a second die block comprising through substrate vias.

[0276] Aspect 35: The method of aspects 33 through 34, further comprising coupling a second integrated device to the package substrate through a second plurality of solder interconnects.

[0277] Aspect 36: A device comprising the package of aspects 1 through 24, wherein the device is one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (loT) device, and a device in an automotive vehicle.

[0278] Aspect 37: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion. The encapsulated portion comprises a first interconnection portion block; a second interconnection portion block, wherein the second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block; a plurality of pillar interconnects, where the plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block; and a second plurality of pillar interconnects coupled to the second interconnection portion block; and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. [0279] Aspect 38: The package of aspect 37, wherein the first interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias.

[0280] Aspect 39: The package of aspects 37 through 38, wherein the second interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias.

[0281] Aspect 40: The package of aspects 37 through 39, wherein the package substrate further comprises a first metallization portion coupled to a first surface of the encapsulated portion, and/or a second metallization portion coupled to a second surface of the encapsulated portion, wherein the first metallization portion includes a first plurality of metallization interconnects comprising a first minimum width and a first minimum spacing, and wherein the second metallization portion includes a second plurality of metallization interconnects comprising a second minimum width and a second minimum spacing.

[0282] The various features of the disclosure described herein can be implemented in different systems without departing from the disclosure. It should be noted that the foregoing aspects of the disclosure are merely examples and are not to be construed as limiting the disclosure. The description of the aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: a package substrate comprising:

(i) an encapsulated portion comprising: a first interconnection portion block; a second interconnection portion block, wherein the second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block; a plurality of pillar interconnects, wherein the plurality of pillar interconnects comprises: a first plurality of pillar interconnects coupled to the first interconnection portion block; and a second plurality of pillar interconnects coupled to the second interconnection portion block; and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects;

(ii) a first metallization portion coupled to a first surface of the encapsulated portion; and

(iii) a second metallization portion coupled to a second surface of the encapsulated portion; and a first integrated device coupled to the package substrate through a first plurality of solder interconnects.

2. The package of claim 1, wherein the first interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias.

3. The package of claim 1, wherein the second interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias.

4. The package of claim 1, wherein the first metallization portion includes a first plurality of metallization interconnects comprising a first minimum width and a first minimum spacing, and wherein the second metallization portion includes a second plurality of metallization interconnects comprising a second minimum width and a second minimum spacing.

5. The package of claim 1, wherein the first integrated device is coupled to the first metallization portion of the package substrate through the first plurality of solder interconnects.

6. The package of claim 5, wherein the first integrated device includes a first core and a second core, wherein a first electrical path for a first signal to the first core of the first integrated device comprises the first interconnection portion block, and wherein a second electrical path for a second signal to the second core of the first integrated device comprises the second interconnection portion block.

7. The package of claim 5, further comprising a second integrated device coupled to the first metallization portion of the package substrate through a second plurality of solder interconnects.

8. The package of claim 7, wherein a first electrical path for a first signal to the first integrated device comprises the first interconnection portion block, and wherein a second electrical path for a second signal to the second integrated device comprises the second interconnection portion block.

9. The package of claim 7, wherein a first electrical path for a first signal between the second metallization portion and the first integrated device comprises interconnects from the first interconnection portion block, a pillar interconnect from the first plurality of pillar interconnects, metallization interconnects from the first metallization portion, and a first solder interconnect from the first plurality of solder interconnects, and wherein a second electrical path for a second electrical signal between the second metallization portion and the second integrated device comprises interconnects from the second interconnection portion block, a pillar interconnect from the second plurality of pillar interconnects, other metallization interconnects from the first metallization portion, and a second solder interconnect from the second plurality of solder interconnects.

10. The package of claim 1, further comprising a third interconnection portion block located in the encapsulated portion, wherein the plurality of pillar interconnects comprises a third plurality of pillar interconnects coupled to the third interconnection portion block.

11. The package of claim 10, wherein the first interconnection portion block includes a coreless substrate block, wherein the second interconnection portion block includes a cored substrate block, and wherein the third interconnection portion block includes a metallization portion block.

12. The package of claim 10, wherein a first electrical path for a first electrical signal between the second metallization portion and the first integrated device comprises interconnects from the first interconnection portion block, a pillar interconnect from the first plurality of pillar interconnects, first metallization interconnects from the first metallization portion, and a first solder interconnect from the first plurality of solder interconnects, wherein a second electrical path for a second electrical signal between the second metallization portion and the first integrated device comprises interconnects from the second interconnection portion block, a pillar interconnect from the second plurality of pillar interconnects, second metallization interconnects from the first metallization portion, and a second solder interconnect from the first plurality of solder interconnects, and wherein a third electrical path for a third electrical signal between the second metallization portion and the first integrated device comprises interconnects from the third interconnection portion block, a pillar interconnect from the third plurality of pillar interconnects, third metallization interconnects from the first metallization portion, and a third solder interconnect from the first plurality of solder interconnects.

13. The package of claim 12, wherein interconnects from the metallization portion block are thinner than (i) interconnects from the coreless substrate block, and (ii) interconnects from the cored substrate block.

14. The package of claim 1, wherein the first interconnection portion block includes a first number of metal layers, and wherein the second interconnection portion block includes a second number of metal layers that is different than the first number of metal layers.

15. The package of claim 1, wherein a first electrical path for a first electrical signal between the second metallization portion and the first integrated device comprises interconnects from the first interconnection portion block, a pillar interconnect from the first plurality of pillar interconnects, metallization interconnects from the first metallization portion, and a first solder interconnect from the first plurality of solder interconnects, and wherein a second electrical path for a second electrical signal between the second metallization portion and the first integrated device comprises interconnects from the second interconnection portion block, a pillar interconnect from the second plurality of pillar interconnects, other metallization interconnects from the first metallization portion, and a second solder interconnect from the first plurality of solder interconnects.

16. The package of claim 1, wherein a first electrical path for a first electrical signal between the second metallization portion and the first integrated device comprises interconnects from the first interconnection portion block, a pillar interconnect from the first plurality of pillar interconnects, metallization interconnects from the first metallization portion, and a first solder interconnect from the first plurality of solder interconnects, and wherein a second electrical path for power between the second metallization portion and the first integrated device comprises interconnects from the second interconnection portion block, a pillar interconnect from the second plurality of pillar interconnects, other metallization interconnects from the first metallization portion, and a second solder interconnect from the first plurality of solder interconnects.

17. The package of claim 16, wherein the second electrical path further includes a passive device located in the second interconnection portion block.

18. The package of claim 16, wherein the first interconnection portion block includes a metallization portion block, and wherein the second interconnection portion block includes a laminate substrate block.

19. The package of claim 16, wherein a third electrical path for ground between the second metallization portion and the first integrated device comprises other interconnects from the second interconnection portion block, another pillar interconnect from the second plurality of pillar interconnects, other metallization interconnects from the first metallization portion, and a third solder interconnect from the first plurality of solder interconnects.

20. The package of claim 1, further comprising a second integrated device coupled to the package through a second plurality of solder interconnects.

21. The package of claim 20, wherein the first integrated device is a first chiplet comprising a first technology node, and wherein the second integrated device is a second chiplet comprising a second technology node.

22. The package of claim 1, further comprising a second integrated device coupled to the first integrated device through a second plurality of solder interconnects.

23. The package of claim 22, wherein the first integrated device is a first chiplet comprising a first technology node, wherein the second integrated device is a second chiplet comprising a second technology node, wherein the first interconnection portion block is configured to provide a first electrical path for the first integrated device, and wherein the second interconnection portion block is configured to provide a second electrical path for the second integrated device.

24. The package of claim 1, further comprising an interposer coupled to the package substrate through a second plurality of solder interconnects, wherein the first integrated device is coupled to the package substrate through the interposer such that the first plurality of solder interconnects is coupled to the interposer.

25. The package of claim 1, wherein the package is implemented in a device is that is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (loT) device, and a device in an automotive vehicle.

26. A method for fabricating a package, the method comprising: providing a first interconnection portion block; providing a second interconnection portion block, wherein the second interconnection portion block is a different type of interconnection portion block from the first interconnection portion block; forming a plurality of pillar interconnects, wherein the plurality of pillar interconnects comprises: a first plurality of pillar interconnects coupled to the first interconnection portion block; and a second plurality of pillar interconnects coupled to the second interconnection portion block; and forming an encapsulation layer that at least partially encapsulates the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects, which forms an encapsulated portion; forming a first metallization portion that is coupled to a first surface of the encapsulated portion; and forming a second metallization portion that is coupled to a second surface of the encapsulated portion, wherein the encapsulated portion, the first metallization portion and the second metallization portion form a package substrate; and coupling a first integrated device to the package substrate through a first plurality of solder interconnects.

27. The method of claim 26, wherein the first interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias.

28. The method of claim 26, wherein the second interconnection portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallization portion block or a die block comprising through substrate vias.

29. The method of claim 26, further comprising coupling a second integrated device to the package substrate through a second plurality of solder interconnects.

30. The method of claim 29, wherein a first electrical path for a first signal to the first integrated device comprises the first interconnection portion block, and wherein a second electrical path for a second signal to the second integrated device comprises the second interconnection portion block.