WO2024128448A1

WO2024128448A1 - Electronic device having display with adaptive synchronization technology

Info

Publication number: WO2024128448A1
Application number: PCT/KR2023/010169
Authority: WO
Inventors: 조광래; 박준영; 김승진
Original assignee: 삼성전자 주식회사
Priority date: 2022-12-12
Filing date: 2023-07-17
Publication date: 2024-06-20

Abstract

An electronic device comprising a display and a processor operatively connected to the display is provided. The processor may be configured to: while the display is configured to periodically generate a synchronization signal having a high voltage level in a first time interval in a state where the frame rate of the display is configured to be a first frame rate, start a transmission operation of transmitting a frame to the display in the first time interval; on the basis of occurrence of an event to change from the first frame rate to a second frame rate, request the display to refresh the frame rate to the second frame rate; and start the transmission operation in a second time interval shorter than the first time interval.

Description

Electronic device having a display with adaptive synchronization technology

Various embodiments relate to an electronic device having a display to which Adaptive Sync technology is applied.

The electronic device may combine images to be displayed on the display into one frame and display the frame on the display in accordance with a synchronization signal (eg, a tearing effect (TE) synchronization signal). For example, based on the synchronization signal, an operation to write a frame to the graphic memory and a scan operation to read the frame recorded in the graphic memory to draw the frame on the display may be started. Write and scan can be started sequentially according to the frequency of the synchronization signal. If the frequency (e.g., frame rate) of the synchronization signal is, for example, 60 Hz, the number of frames displayed on the display per second may be 60 frames per second (FPS).

If rendering (e.g. image compositing) is delayed, the recording operation may be delayed and the frames that need to be read may not be in the graphics memory. In this case, a so-called frame drop may occur, in which the number of frames displayed on the display per second is reduced.

According to various embodiments, adaptive synchronization technology that adjusts the timing of occurrence of a synchronization signal so that frame drops can be prevented or suppressed may be implemented in an electronic device. For example, the electronic device may generate a synchronization signal earlier than a specified point in time. Accordingly, the time for rendering a frame is increased by the time when the synchronization signal was generated earlier, so frame drops can be prevented or suppressed.

The frame rate may be changed in the electronic device. For example, the frame rate may change from 60Hz to 120Hz as an application that requires high performance (e.g., a game) is executed. While the frame rate is changing, there may be a temporary pause on the display while adaptive synchronization technology is performed on the processor. At this time, because the scan operation is performed before the write operation, tearing of the screen may occur.

In various embodiments, an electronic device may provide a solution to prevent screen tearing when the frame rate changes while adaptive synchronization is performed. The technical problem to be achieved in the present disclosure is not limited to the technical problem mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the description below. There will be.

According to one embodiment, a display; a processor operatively coupled to the display; and a memory operatively coupled to the processor. The memory is configured to, when executed, cause the processor to periodically generate a synchronization signal with the high voltage level in a first time period with the display having the frame rate of the display set to a first frame rate. During this time, instructions for starting a transmission operation for transmitting a frame to the display in the first time period may be stored. The instructions cause the processor to request the display to refresh a frame at the second frame rate based on an event occurring that causes the processor to change from the first frame rate to the second frame rate, and to display the first pitch. The transmission operation may be started in a second time period shorter than the time interval.

According to one embodiment, a display; and a processor operatively connected to the display. The processor is configured to send a frame to the display while the display is configured to periodically generate a synchronization signal with the high voltage level in a first time period while the frame rate of the display is set to a first frame rate. It may be configured to start a transmission operation in the first time period. The processor requests the display to refresh a frame at the second frame rate based on an event occurring that causes a change from the first frame rate to the second frame rate, and displays a frame rate shorter than the first time period. It may be configured to start the transmission operation in a second time period.

According to one embodiment, a method of operating an electronic device is provided. The method includes, while the display of the electronic device is configured to periodically generate a synchronization signal having the high voltage level in a first time period, while the frame rate of the display is set to a first frame rate, and the frame rate is set to a first frame rate. It may include starting a transmission operation to transmit to the display in the first time period. The method requests the display to refresh frames at the second frame rate based on the occurrence of an event that causes a change from the first frame rate to the second frame rate, and displays a frame rate shorter than the first time period. It may include starting the transmission operation in a second time period.

According to one embodiment, a recording medium storing instructions readable by a processor of an electronic device is provided. The instructions, when executed by the processor, cause the processor to cause the display of the electronic device to send a synchronization signal having the high voltage level in a first time period while the frame rate of the display is set to a first frame rate. While configured to occur periodically, a transmission operation for transmitting a frame to the display may be performed starting from the first time period. The instructions cause the processor to request the display to refresh a frame at the second frame rate based on an event occurring that causes the processor to change from the first frame rate to the second frame rate, and to display the first pitch. The operation of starting the transmission operation may be performed in a second time period shorter than the time interval.

According to various embodiments, an electronic device can prevent screen tearing when the frame rate is changed while an adaptive synchronization operation is performed. In addition, various effects that can be directly or indirectly identified through this document may be provided.

1 is a block diagram of an electronic device in a network environment, according to various embodiments.

Figure 2 is a block diagram 200 of the display module 160, according to various embodiments.

Figure 3 shows a configuration of an electronic device for generating and displaying a frame, according to one embodiment.

Figures 4 to 8 are diagrams illustrating situations in which frame drops and screen tearing may occur.

FIG. 9 is a diagram illustrating processor operations to prevent screen tearing when the frame rate is changed while an adaptive synchronization operation is performed, according to an embodiment.

FIG. 10 is a flowchart illustrating operations of a compositing module, a processor, and a display to prevent screen tearing when a frame rate is changed while an adaptive synchronization operation is performed, according to an embodiment.

FIG. 11 is a flowchart illustrating processor operations to prevent screen tearing when the frame rate is changed while an adaptive synchronization operation is performed, according to an embodiment.

1 is a block diagram of an electronic device 101 in a network environment 100, according to various embodiments. Referring to FIG. 1, in the network environment 100, the electronic device 101 communicates with the electronic device 102 through a first network 198 (e.g., a short-range wireless communication network) or a second network 199. It is possible to communicate with at least one of the electronic device 104 or the server 108 through (e.g., a long-distance wireless communication network). According to one embodiment, the electronic device 101 may communicate with the electronic device 104 through the server 108. According to one embodiment, the electronic device 101 includes a processor 120, a memory 130, an input module 150, an audio output module 155, a display module 160, an audio module 170, and a sensor module ( 176), interface 177, connection terminal 178, haptic module 179, camera module 180, power management module 188, battery 189, communication module 190, subscriber identification module 196 , or may include an antenna module 197. In some embodiments, at least one of these components (eg, the connection terminal 178) may be omitted or one or more other components may be added to the electronic device 101. In some embodiments, some of these components (e.g., sensor module 176, camera module 180, or antenna module 197) are integrated into one component (e.g., display module 160). It can be.

The processor 120, for example, executes software (e.g., program 140) to operate at least one other component (e.g., hardware or software component) of the electronic device 101 connected to the processor 120. It can be controlled and various data processing or calculations can be performed. According to one embodiment, as at least part of data processing or computation, the processor 120 stores commands or data received from another component (e.g., sensor module 176 or communication module 190) in volatile memory 132. The commands or data stored in the volatile memory 132 can be processed, and the resulting data can be stored in the non-volatile memory 134. According to one embodiment, the processor 120 includes a main processor 121 (e.g., a central processing unit or an application processor) or an auxiliary processor 123 that can operate independently or together (e.g., a graphics processing unit, a neural network processing unit ( It may include a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor). For example, if the electronic device 101 includes a main processor 121 and a secondary processor 123, the secondary processor 123 may be set to use lower power than the main processor 121 or be specialized for a designated function. You can. The auxiliary processor 123 may be implemented separately from the main processor 121 or as part of it.

The auxiliary processor 123 may, for example, act on behalf of the main processor 121 while the main processor 121 is in an inactive (e.g., sleep) state, or while the main processor 121 is in an active (e.g., application execution) state. ), together with the main processor 121, at least one of the components of the electronic device 101 (e.g., the display module 160, the sensor module 176, or the communication module 190) At least some of the functions or states related to can be controlled. According to one embodiment, co-processor 123 (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module 180 or communication module 190). there is. According to one embodiment, the auxiliary processor 123 (eg, neural network processing device) may include a hardware structure specialized for processing artificial intelligence models. Artificial intelligence models can be created through machine learning. For example, such learning may be performed in the electronic device 101 itself on which the artificial intelligence model is performed, or may be performed through a separate server (e.g., server 108). Learning algorithms may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but It is not limited. An artificial intelligence model may include multiple artificial neural network layers. Artificial neural networks include deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), restricted boltzmann machine (RBM), belief deep network (DBN), bidirectional recurrent deep neural network (BRDNN), It may be one of deep Q-networks or a combination of two or more of the above, but is not limited to the examples described above. In addition to hardware structures, artificial intelligence models may additionally or alternatively include software structures.

The memory 130 may store various data used by at least one component (eg, the processor 120 or the sensor module 176) of the electronic device 101. Data may include, for example, input data or output data for software (e.g., program 140) and instructions related thereto. Memory 130 may include volatile memory 132 or non-volatile memory 134.

The program 140 may be stored as software in the memory 130 and may include, for example, an operating system 142, middleware 144, or application 146.

The input module 150 may receive commands or data to be used in a component of the electronic device 101 (e.g., the processor 120) from outside the electronic device 101 (e.g., a user). The input module 150 may include, for example, a microphone, mouse, keyboard, keys (eg, buttons), or digital pen (eg, stylus pen).

The sound output module 155 may output sound signals to the outside of the electronic device 101. The sound output module 155 may include, for example, a speaker or a receiver. Speakers can be used for general purposes such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part of it.

The display module 160 can visually provide information to the outside of the electronic device 101 (eg, a user). The display module 160 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling the device. According to one embodiment, the display module 160 may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of force generated by the touch.

The audio module 170 can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module 170 acquires sound through the input module 150, the sound output module 155, or an external electronic device (e.g., directly or wirelessly connected to the electronic device 101). Sound may be output through the electronic device 102 (e.g., speaker or headphone).

The sensor module 176 detects the operating state (e.g., power or temperature) of the electronic device 101 or the external environmental state (e.g., user state) and generates an electrical signal or data value corresponding to the detected state. can do. According to one embodiment, the sensor module 176 includes, for example, a gesture sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, It may include a temperature sensor, humidity sensor, or light sensor.

The interface 177 may support one or more designated protocols that can be used to connect the electronic device 101 directly or wirelessly with an external electronic device (eg, the electronic device 102). According to one embodiment, the interface 177 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

The connection terminal 178 may include a connector through which the electronic device 101 can be physically connected to an external electronic device (eg, the electronic device 102). According to one embodiment, the connection terminal 178 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

The haptic module 179 can convert electrical signals into mechanical stimulation (e.g., vibration or movement) or electrical stimulation that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module 179 may include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

The camera module 180 can capture still images and moving images. According to one embodiment, the camera module 180 may include one or more lenses, image sensors, image signal processors, or flashes.

The power management module 188 can manage power supplied to the electronic device 101. According to one embodiment, the power management module 188 may be implemented as at least a part of, for example, a power management integrated circuit (PMIC).

The battery 189 may supply power to at least one component of the electronic device 101. According to one embodiment, the battery 189 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

Communication module 190 is configured to provide a direct (e.g., wired) communication channel or wireless communication channel between electronic device 101 and an external electronic device (e.g., electronic device 102, electronic device 104, or server 108). It can support establishment and communication through established communication channels. Communication module 190 operates independently of processor 120 (e.g., an application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module 190 may be a wireless communication module 192 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 194 (e.g., : LAN (local area network) communication module, or power line communication module) may be included. Among these communication modules, the corresponding communication module is a first network 198 (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network 199 (e.g., legacy It may communicate with an external electronic device 104 through a telecommunication network such as a cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., LAN or WAN). These various types of communication modules may be integrated into one component (e.g., a single chip) or may be implemented as a plurality of separate components (e.g., multiple chips). The wireless communication module 192 uses subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module 196 to communicate within a communication network such as the first network 198 or the second network 199. The electronic device 101 can be confirmed or authenticated.

The wireless communication module 192 may support 5G networks after 4G networks and next-generation communication technologies, for example, NR access technology (new radio access technology). NR access technology provides high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and access to multiple terminals (massive machine type communications (mMTC)), or ultra-reliable and low-latency (URLLC). -latency communications)) can be supported. The wireless communication module 192 may support high frequency bands (eg, mmWave bands), for example, to achieve high data rates. The wireless communication module 192 uses various technologies to secure performance in high frequency bands, for example, beamforming, massive array multiple-input and multiple-output (MIMO), and full-dimensional multiplexing. It can support technologies such as input/output (FD-MIMO: full dimensional MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module 192 may support various requirements specified in the electronic device 101, an external electronic device (e.g., electronic device 104), or a network system (e.g., second network 199). According to one embodiment, the wireless communication module 192 supports Peak data rate (e.g., 20 Gbps or more) for realizing eMBB, loss coverage (e.g., 164 dB or less) for realizing mmTC, or U-plane latency (e.g., 164 dB or less) for realizing URLLC. Example: Downlink (DL) and uplink (UL) each of 0.5 ms or less, or round trip 1 ms or less) can be supported.

The antenna module 197 may transmit or receive signals or power to or from the outside (eg, an external electronic device). According to one embodiment, the antenna module 197 may include an antenna including a radiator made of a conductor or a conductive pattern formed on a substrate (eg, PCB). According to one embodiment, the antenna module 197 may include a plurality of antennas (eg, an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network such as the first network 198 or the second network 199 is, for example, connected to the plurality of antennas by the communication module 190. can be selected. Signals or power may be transmitted or received between the communication module 190 and an external electronic device through the at least one selected antenna. According to some embodiments, in addition to the radiator, other components (eg, radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module 197.

According to various embodiments, the antenna module 197 may form a mmWave antenna module. According to one embodiment, a mmWave antenna module includes a printed circuit board, an RFIC disposed on or adjacent to a first side (e.g., bottom side) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., mmWave band); And a plurality of antennas (e.g., array antennas) disposed on or adjacent to the second side (e.g., top or side) of the printed circuit board and capable of transmitting or receiving signals in the designated high frequency band. can do.

At least some of the components are connected to each other through a communication method between peripheral devices (e.g., bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)) and signal ( (e.g. commands or data) can be exchanged with each other.

According to one embodiment, commands or data may be transmitted or received between the electronic device 101 and the external electronic device 104 through the server 108 connected to the second network 199. Each of the external

electronic devices

102 or 104 may be of the same or different type as the electronic device 101. According to one embodiment, all or part of the operations performed in the electronic device 101 may be executed in one or more of the external

electronic devices

102, 104, or 108. For example, when the electronic device 101 must perform a certain function or service automatically or in response to a request from a user or another device, the electronic device 101 may perform the function or service instead of executing the function or service on its own. Alternatively, or additionally, one or more external electronic devices may be requested to perform at least part of the function or service. One or more external electronic devices that have received the request may execute at least part of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device 101. The electronic device 101 may process the result as is or additionally and provide it as at least part of a response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology can be used. The electronic device 101 may provide an ultra-low latency service using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device 104 may include an Internet of Things (IoT) device. Server 108 may be an intelligent server using machine learning and/or neural networks. According to one embodiment, the external electronic device 104 or server 108 may be included in the second network 199. The electronic device 101 may be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

Figure 2 is a block diagram 200 of the display module 160, according to various embodiments. Referring to FIG. 2, the display module 160 may include a display 210 and a display driver IC (DDI) 230 for controlling the display 210. The DDI 230 may include an interface module 231, a memory 233 (eg, buffer memory), an image processing module 235, or a mapping module 237. For example, the DDI 230 receives image information including image data or an image control signal corresponding to a command for controlling the image data from other components of the electronic device 101 through the interface module 231. can do. For example, image information may be stored in the processor 120 (e.g., main processor 121 (e.g., application processor) or a secondary processor 123 (e.g., graphics processing unit) that operates independently of the functions of the main processor 121. The DDI 230 may communicate with the touch circuit 250 or the sensor module 176 through the interface module 231. The image processing module 235 may store a portion of the image data in the memory 233, for example, in units of frames, for example, the characteristics of the image data or the characteristics of the display 210. The mapping module 237 may perform pre-processing or post-processing (e.g., resolution, brightness, or size adjustment) based on the image data corresponding to the pre-processing or post-processing. According to one embodiment, the voltage value or current value may be generated by, for example, a property of the pixels of the display 210 (e.g., an array of pixels (RGB stripe or pentile structure)). , or the size of each subpixel), at least some pixels of the display 210 may be driven, for example, at least in part based on the voltage value or the current value. Corresponding visual information (e.g., text, images, or icons) may be displayed via display 210.

According to one embodiment, the display module 160 may further include a touch circuit 250. The touch circuit 250 may include a touch sensor 251 and a touch sensor IC 253 for controlling the touch sensor 251. For example, the touch sensor IC 253 may control the touch sensor 251 to detect a touch input or a hovering input for a specific position of the display 210. For example, the touch sensor IC 253 may detect a touch input or a hovering input by measuring a change in a signal (eg, voltage, light amount, resistance, or charge amount) for a specific position of the display 210. The touch sensor IC 253 may provide information (e.g., location, area, pressure, or time) about the detected touch input or hovering input to the processor 120. According to one embodiment, at least a portion of the touch circuit 250 (e.g., touch sensor IC 253) is disposed as part of the display driver IC 230, the display 210, or outside the display module 160. It may be included as part of other components (e.g., auxiliary processor 123).

According to one embodiment, the display module 160 may further include at least one sensor (eg, a fingerprint sensor, an iris sensor, a pressure sensor, or an illumination sensor) of the sensor module 176, or a control circuit therefor. In this case, the at least one sensor or a control circuit therefor may be embedded in a part of the display module 160 (eg, the display 210 or the DDI 230) or a part of the touch circuit 250. For example, when the sensor module 176 embedded in the display module 160 includes a biometric sensor (e.g., a fingerprint sensor), the biometric sensor records biometric information associated with a touch input through a portion of the display 210. (e.g. fingerprint image) can be obtained. For another example, when the sensor module 176 embedded in the display module 160 includes a pressure sensor, the pressure sensor may acquire pressure information associated with a touch input through part or the entire area of the display 210. You can. According to one embodiment, the touch sensor 251 or the sensor module 176 may be disposed between pixels of a pixel layer of the display 210, or above or below the pixel layer.

Electronic devices according to various embodiments disclosed in this document may be of various types. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to embodiments of this document are not limited to the above-described devices.

The various embodiments of this document and the terms used herein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various changes, equivalents, or replacements of the embodiments. In connection with the description of the drawings, similar reference numbers may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the above items, unless the relevant context clearly indicates otherwise. As used herein, “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B or C”, “at least one of A, B and C”, and “A Each of phrases such as “at least one of , B, or C” may include any one of the items listed together in the corresponding phrase, or any possible combination thereof. Terms such as "first", "second", or "first" or "second" may be used simply to distinguish one element from another, and may be used to distinguish such elements in other respects, such as importance or order) is not limited. One (e.g. first) component is said to be "coupled" or "connected" to another (e.g. second) component, with or without the terms "functionally" or "communicatively". Where mentioned, it means that any of the components can be connected to the other components directly (e.g. wired), wirelessly, or through a third component.

The term “module” used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and is interchangeable with terms such as logic, logic block, component, or circuit, for example. It can be used as A module may be an integrated part or a minimum unit of the parts or a part thereof that performs one or more functions. According to one embodiment, the module may be implemented in the form of an application-specific integrated circuit (ASIC).

Various embodiments of the present document are one or more instructions stored in a storage medium (e.g., built-in memory 136 or external memory 138) that can be read by a machine (e.g., electronic device 101). It may be implemented as software (e.g., program 140) including these. For example, a processor (e.g., processor 120) of a device (e.g., electronic device 101) may call at least one command among one or more commands stored from a storage medium and execute it. This allows the device to be operated to perform at least one function according to the at least one instruction called. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. A storage medium that can be read by a device may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' only means that the storage medium is a tangible device and does not contain signals (e.g. electromagnetic waves). This term refers to cases where data is stored semi-permanently in the storage medium. There is no distinction between temporary storage cases.

According to one embodiment, methods according to various embodiments disclosed in this document may be provided and included in a computer program product. Computer program products are commodities and can be traded between sellers and buyers. The computer program product may be distributed in the form of a machine-readable storage medium (e.g. compact disc read only memory (CD-ROM)) or via an application store (e.g. Play Store ^TM ) or on two user devices (e.g. It can be distributed (e.g. downloaded or uploaded) directly between smart phones) or online. In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored or temporarily created in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store server, or a relay server.

According to various embodiments, each component (e.g., module or program) of the above-described components may include a single or plural entity, and some of the plurality of entities may be separately placed in other components. there is. According to various embodiments, one or more of the components or operations described above may be omitted, or one or more other components or operations may be added. Alternatively or additionally, multiple components (eg, modules or programs) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each component of the plurality of components identically or similarly to those performed by the corresponding component of the plurality of components prior to the integration. . According to various embodiments, operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, or omitted. Alternatively, one or more other operations may be added.

FIG. 3 shows the configuration of an electronic device 300 for generating and displaying a frame, according to one embodiment. The electronic device 300 may include any electronic device including a display.

Referring to FIG. 3, the electronic device 300 may include an application 310, a composition module 320, a display driver 330, a display 340, an image memory 345, and a processor 399. . The application 310, composition module 320, and display driver 330 may be stored as software in memory (eg, memory 130 in FIG. 1) and executed by the processor 399.

The application 310 may create images (in other words, surfaces) to be displayed through the display 340 and store them in the image memory 345. For example, the image memory 345 may be a memory area allocated to the application 310 in the volatile memory 130 of FIG. 1 . The processor 399 may allocate a portion of the volatile memory 130 to the application 310 as a buffer (eg, BufferQueue) for storing images generated by the application 310. The application 310 can create an image using a graphics engine (eg, skia, GLES) and store it in the image memory 345. For example, the application 310 may create a status bar, background, widgets, and navigation bar as elements constituting the home screen. The application 310 may store the components of the above-described home screen in the image memory 345.

The compositing module 320 can composite images received from the application 310 through the image memory 345 into one frame. The composition module 320 may include a surface flinger (321), a hardware composer (HWC) 322, and a graphic processing unit (GSL) system layer (GSL) 323.

Surface Flinger 321 can manage image composition. For example, the compositing module 320 can specify a layer and location for images to be composited. For example, the surface flinger 321 may designate the background as the lower layer and the status bar, widgets, and navigation bar as the upper layer. The surface flinger 321 can specify the display position of the status bar at the top of the screen, the display position of the widget at the center of the screen, and the display position of the navigation bar at the bottom of the screen.

The processor 399 may include a number of

processors

350 and 360 to be used for image synthesis. The surface flinger 321 can determine the processor to be used for image compositing. For example, if the application 310 that provides the images is a game application that requires relatively high performance, the surface flinger 321 uses a second processor ( 360) (e.g. GPU) can be determined as the processor to be used for image synthesis. If the first processor 350 is determined to be the unit used for image synthesis, the surface linger 321 may transmit a list of images to be synthesized and information indicating the hierarchy and location of each image to the HWC 322. The HWC 322 can generate a frame to be displayed on the display 340 by combining images using the first processor 350 through the first display driver 331 configured to drive the first processor 350. there is. The HWC 322 may send a frame generated using the first processor 350 to the display 340. If the second processor 360 is determined to be the unit used for image synthesis, the surface slinger 321 may transmit a list of images to be synthesized and information indicating the hierarchy and location of each image to the GSL 323. The GSL 323 may generate a frame to be displayed on the display 340 by combining images using the second processor 360 through the second display driver 332 configured to drive the second processor 360. there is. The GSL 323 may send a frame generated using the second processor 360 to the display 340.

The display 340 may be provided with a frame memory 341 (e.g., memory 233 in FIG. 2) (aka Gram) as a buffer for storing frames received from the processor 399. In the display 340, the DDI (eg, DDI 230 in FIG. 2) may write a frame received from the processor 399 to the frame memory 341. In the display 340, a panel (e.g., the display panel 210 of FIG. 2) may scan the frame memory 341 to obtain a frame and display visual information corresponding to the obtained frame.

Frame rate (or refresh rate) refers to the number of frames displayed through the display 340 per second. For example, if the frame rate is 60Hz (or 60FPS), the number of frames refreshed on the display 340 may be 60 per second. In one example, the frame rate may be determined by the application 310 that provides images as a source of frames to be displayed on the display 340. As another example, it may be determined by the middleware 144 or the operating system 142 that supports execution of the application 310. The processor 399 may control the display 399 at a specified frame rate.

The display 340 may generate a synchronization signal as a pulse in which a high voltage level (or ON state) and a low voltage level (or OFF state) are periodically repeated. For example, referring to FIG. 4 , the display 340 may periodically generate a synchronization signal by matching the frequency of a synchronization signal (e.g., a tearing effect (TE) synchronization signal) to the determined frame rate. The display 340 may periodically generate a synchronization signal according to the frame rate. For example, if the frame rate is 60Hz, the generation period “T1” of the synchronization signal may be 16.6ms (1/60). “(t2-t1)/T1” as the duty ratio of the synchronization signal may be determined by the processor 399 (or display 340). Here, the duty ratio may mean the ratio of the time when the synchronization signal has a high voltage level (in other words, the time when the synchronization signal is in the On state) for one cycle. The processor 399 may transmit a rendering trigger event (eg, a vertical synchronization (VSYNC) signal) corresponding to a synchronization signal generated by the display 340 to the synthesis module 320. Based on the received rendering trigger event, the composition module 320 determines the period of the synchronization signal, the duty ratio, and the time when the synchronization signal changes from a low voltage level to a high voltage level (in other words, the synchronization signal changes from an Off state to an On state). (hereinafter referred to as rising timing), and the timing at which the synchronization signal changes from a high voltage level to a low voltage level (in other words, the timing at which the synchronization signal switches from the On state to the Off state) (hereinafter referred to as the rising timing). The falling timing can be recognized. The synthesis module 320 starts rendering 401 at a time period (t2-t1) in which the first synchronization signal 410 has a high voltage level, and the rising point of the second synchronization signal 420 ( Rendering 401 may be completed before t3) and the frame generated as a result of rendering may be transmitted to the processor 399. The processor 320 performs a frame transmission 402 (an operation of transmitting a frame received from the composition module 320 to the display 340) in a time period (t4-t3) in which the second synchronization signal 420 has a high voltage level. ) can be started. The display 340 records (403) (e.g., Gram write) the frame received from the processor 399 in the frame memory 341 and records the frame memory 341 at the falling point (t4) of the second synchronization signal 420. You can start a scan 404 (e.g. Gram scan).

The processor 399 may perform tasks other than rendering. If the number of tasks to be performed by the processor 399 increases, rendering delays may occur in the compositing module 320.

Referring to FIG. 5 , the composition module 320 may start rendering 501 in a time period (t2-t1) in which the first synchronization signal 410 has a high voltage level. Due to the increased number of tasks to be performed by the processor 399, the composition module 320 may complete the rendering 501 after the rising time t3 of the second synchronization signal 520. As a result, frame transmission 502 and recording 503 start in the time period (t6-t5) when the third synchronization signal 530 has a high voltage level, and the falling point of the third synchronization signal 530 (t6) A scan 504 may begin.

The electronic device 300 may perform an adaptive synchronization operation as a function to suppress frame drops due to rendering delay as illustrated in FIG. 5 . Based on the control of the processor 399, the display 340 may advance the synchronization signal to a high voltage level by a specified threshold time ‘T_th’. In other words, the display 340 can increase the time period during which the synchronization signal has a high voltage level (the time when the synchronization signal is in the ON state) by a given amount of ‘T_th’. In this way, if the synchronization signal is generated as early as ‘T_th’, an additional time for starting frame transmission as ‘T_th’ is given to the processor 399, and frame drops can be prevented or suppressed accordingly.

Referring to FIG. 6, the display 340 causes the first synchronization signal 610 to have a high voltage level at the first time 611, which is “T_th” ahead of the time ‘t1’, and sets the first synchronization signal 610 to a high voltage level at the time ‘t2’. The voltage level of the signal 610 can be changed to a low voltage level. The display 340 causes the second synchronization signal 620 to have a high voltage level at a second time 621, which is 'T_th' ahead of the time 't3', and the voltage of the second synchronization signal 620 at time 't4'. The level can be changed to a low voltage level. Accordingly, the compositing module 320 can start rendering 601 as fast as ‘T_th’. The processor 399 is given an additional time of ‘T_th’ to start the frame transmission 602, so that the frame drop illustrated in FIG. 5 may not occur. The processor 399 may start frame transmission 602 at a time period (t4 - second time point 621) when the second synchronization signal 620 has a high voltage level. The display 340 records the frame received from the processor 399 in the frame memory 341 (603) and scans the frame memory 341 (604) at the falling point (t4) of the second synchronization signal 620. You can start. When performing an adaptive synchronization task, the generation period T2 of the synchronization signal may be set by the processor 399. For example, the processor 399 may set T2 to the same value as T1 (see FIG. 4).

While an adaptive synchronization operation is performed, the frame rate may change, for example, from 30 Hz to 60 Hz, from 60 Hz to 120 Hz, or vice versa. The processor 399 may instruct the display 340 to change the frame rate. In response to the instruction, display 340 may perform an operation to change the frame rate. Display 340 has the characteristic of breaking adaptive synchronization while changing frame rates. Processor 399 may be unaware of this characteristic of display 340 and may continue to perform adaptive synchronization operations. In this way, while the adaptive synchronization operation is stopped on one side (display 340) and the adaptive synchronization operation is performed on the other side (processor 399), screen tearing may occur on the display 340.

Referring to FIGS. 7 and 8, the display 340 may cause the synchronization signal 710 to have a high voltage level at time t0 and change the voltage level of the synchronization signal 710 to a low voltage level at time t1. Accordingly, the display 340 may start the scan 703 at time t1. The processor 399 may mistakenly believe that the voltage level of the synchronization signal 710 changes to a low voltage level at time t4, after the threshold time (T_th) designated for adaptive synchronization has elapsed. As a result of this misperception, frame transmission 701 may begin at time t2 during the time period (t4-t0) in which the synchronization signal 610 has a high voltage level, and then recording 702 may begin at time t3. In Figure 8, the X-axis represents time and the Y-axis represents each line on the screen. Reference numeral 801 denotes scan speed and reference numeral 802 denotes recording speed. Relatively, the recording speed (802) is faster than the scan speed (801). Therefore, if recording starts first, the so-called ASYNC problem where scanning and recording overlap may not occur. However, as illustrated in FIGS. 7 and 8, when the scan 703 starts before the recording 702, the recording 702 and the scan 703 overlap at time t5, a so-called ASYNC problem. occurs, and at this moment, screen tearing may occur. For example, the screen may appear broken at the line corresponding to point t5.

FIG. 9 is a diagram illustrating operations of the processor 399 to prevent screen tearing when the frame rate is changed while an adaptive synchronization operation is performed, according to an embodiment.

Processor 399 may request display 340 to change the frame rate, for example, from 60 Hz to 120 Hz. In response, display 340 may change the frame rate. Display 340 may not apply adaptive synchronization to timing control for generating a synchronization signal while changing the frame rate. For example, referring to FIG. 9, the display 340 may have the first synchronization signal 910 have a high voltage level at time t0 and change the voltage level of the first synchronization signal 910 to a low voltage level at time t1. there is.

The processor 399 performs an operation for frame transmission from the time it requests the display 340 to change the frame rate until it receives a message from the display 340 indicating that the frame rate change has been completed (or during a designated time period). You can set it to not apply adaptive synchronization operations. For example, referring to FIG. 9, when adaptive synchronization is set to be applied to timing control, the time period in which the first synchronization signal 910 has a high voltage level is the first time period including the first threshold time (T_th1). (931; t2-t0), and if adaptive synchronization is set not to apply to timing control, the time period in which the first synchronization signal 910 has a high voltage level does not include the first threshold time (T_th1). It may be the second time period (932; t1-t0). The processor 399 may request the display 340 to change the frame rate and then begin frame transmission 901 in the second time period 932. The display 340 records the frame received from the processor 399 in the frame memory 341 (902) and scans the frame memory 341 (903) at the falling point (t1) of the first synchronization signal 910. You can start.

The display 340 may complete the frame rate change and transmit a change completion message to the processor 399. Additionally, after the change is completed, the display 340 can be set to apply adaptive synchronization to timing control. For example, referring to FIG. 9, when adaptive synchronization is set to be applied to timing control, the time period in which the second synchronization signal 920 has a high voltage level is the third time period including the second threshold time (T_th2). (941; t5-t3), and when adaptive synchronization is set not to be applied to timing control, the time period in which the second synchronization signal 920 has a high voltage level is the fourth time period that does not include the second threshold time (T_th2). It may be a time period (942; t4-t3). The display 340 may cause the second synchronization signal 920 to have a high voltage level at time t3 and change the voltage level of the second synchronization signal 920 to a low voltage level at time t5.

Based on receiving a message indicating that the frame rate change has been completed from the display 340, the processor 399 divides the time period in which the second synchronization signal 920 has a high voltage level into the third time period 941. It is possible to determine and start frame transmission (904) in the third time period (941). The display 340 records the frame received from the processor 399 in the frame memory 341 (905) and scans the frame memory 341 (906) at the falling point (t5) of the second synchronization signal 920. You can start.

According to the operations of the processor 399 described with reference to FIG. 9, the electronic device 300 implements the method so that recording occurs before scanning, although frame drops may occur due to rendering delay while the frame rate is changed. This prevents screen tearing.

FIG. 10 illustrates operations of the compositing module 320, processor 399, and display 340 to prevent screen tearing when the frame rate is changed while an adaptive synchronization operation is performed, according to one embodiment. This is a flow chart to do this.

In operation 1011, the processor 399 may receive an initialization request from the composition module 320. For example, initialization may be a format for the image memory 345 and the frame memory 341. Here, formatting may include, for example, allocating part of the volatile memory as a buffer for storing images created by the application 310 and/or deleting existing frames recorded in the frame memory 341. . According to one embodiment, initialization may include configuring the processor 399 and the display 340 to perform an adaptive synchronization operation.

In operation 1021, the processor 399 may request the display 340 to perform an adaptive synchronization operation based on an event requesting initialization being generated by the composition module 320. Additionally, in operation 1022, the processor 399 may configure adaptive synchronization to be applied to frame transmission. In operation 1031, the display 340 may be configured to apply adaptive synchronization to timing control for generating a synchronization signal based on a message requesting an adaptive synchronization operation being received from the processor 399. The display 340 may periodically generate a synchronization signal with a high voltage level in a first time period (e.g., first time period 931) or a second time period (e.g., second time period 932). . Here, the first time period includes the second time period and the designated first threshold time. Display 340 may receive a request from processor 399 to perform an adaptive synchronization operation. In response to receiving the request, display 340 may periodically generate a synchronization signal having a high voltage level in a first time period. The processor 399 may start transmitting the frame in the first time period. The display 340 may record the frames received from the processor 399 in the frame memory 341 and start scanning the frames recorded in the frame memory 341 when the first time period ends.

In operation 1023, the processor 399 may transmit a completion message to the composition module 320 after initialization is completed. Based on receipt of the completion message, composition module 320 may begin rendering the frame. Operation 1023 can be omitted, and the compositing module 320 can start rendering frames after an initialization request.

While the adaptive synchronization operation is performed, processor 399 may receive a request from composition module 320 to change the frame rate at operation 1012.

In operation 1024, the processor 399 may request a change in the frame rate from the display 340 based on an event requesting a change in the frame rate being generated by the composition module 320. For example, the processor 399 may transmit a command to change the frame rate to the display 340 through MIPI (mobile industry processor interface). Additionally, in operation 1025, the processor 399 may configure not to apply adaptive synchronization to frame transmission based on event occurrence. In operation 1032, the display 340 may configure not to apply adaptive synchronization to timing control based on a message requesting a frame rate change being received from the processor 399. According to this setting, the display 340 may periodically generate a synchronization signal with a high voltage level in the second time period.

While configured not to apply adaptive synchronization to frame transmission, processor 399 may receive a frame from composition module 320 in operation 1013 . In operation 1026, the processor 399 may begin transmitting the received frame to the display 340 in the second time period. The display 340 may record the frames received from the processor 399 in the frame memory 341 and start scanning the frames recorded in the frame memory 341 when the second time period ends.

At the request of the processor 399, the display 340 may complete the frame rate change and transmit a message indicating that the frame rate change has been completed to the processor 399 in operation 1033. In operation 1034, the display 340 may be configured to apply adaptive synchronization to timing control based on the frame rate change being completed. Based on the frame rate change, the display 340 has a high voltage level in the third time period (e.g., the third time period 941) or the fourth time period (e.g., the fourth time period 942). A synchronization signal may be generated periodically. Here, the third time period includes the fourth time period and the designated second threshold time. Based on being configured to apply adaptive synchronization to timing control, the display 340 may periodically generate a synchronization signal with a high voltage level in the third time period.

While adaptive synchronization is not applied to frame transmission, processor 399 may receive a message from display 340 indicating that the frame rate change is complete. Based on receipt of the completion message, processor 399 may configure to apply adaptive synchronization to frame transmission in operation 1027. Operation 1033 can be omitted, and the processor 399 may perform operation 1027 when a specified time has elapsed from the time of requesting a change in frame rate.

While configured to apply adaptive synchronization to frame transmission after a frame rate change, processor 399 may receive a frame from composition module 320 at operation 1014 . In operation 1028, the processor 399 may begin transmitting the received frame to the display 340 in the third time period. The display 340 may record the frames received from the processor 399 in the frame memory 341 and start scanning the frames recorded in the frame memory 341 when the third time period ends.

FIG. 11 is a flowchart illustrating operations of the processor 399 to prevent screen tearing when the frame rate is changed while an adaptive synchronization operation is performed, according to an embodiment.

The display 340 may periodically generate a synchronization signal having a low voltage level and a high voltage level to refresh the screen. When the frame rate for refresh is set to the first frame rate, the display 340 displays the first time period (e.g., the first time period 931) or the second time period (e.g., the second time period set to the default value). It may be configured to periodically generate a synchronization signal with a high voltage level in a time period 932). When the frame rate for refresh is set to the second frame rate, the display 340 displays the third time period (e.g., the third time period 941) or the fourth time period (e.g., the fourth time period set to the default value). It may be configured to periodically generate a synchronization signal with a high voltage level in a time period 942).

While the display 340 is set to periodically generate a synchronization signal with a high voltage level in the first time period, the processor 399 may start frame transmission in the first time period in operation 1110.

An event that causes a change from the first frame rate to the second frame rate may occur, for example, in the compositing module 320. Based on the event occurrence, in operation 1120, the processor 399 may request the display 340 to refresh the screen at a second frame rate and start frame transmission in a second time period set as a default value.

While frame transmission is starting in the second time period, in operation 1130, the processor 399 may receive a message from the display 340 indicating that the frame rate has been completely changed to the second frame rate.

Based on receipt of the completion message, in operation 1140, the processor 399 may start frame transmission in a third time period that is longer than the fourth time period set as a default value. Operation 1130 can be omitted, and the processor 399 may perform operation 1140 when a specified time has elapsed from the time of requesting a change in frame rate.

According to one embodiment, a display (e.g., display 340); a processor operatively coupled to the display (e.g., processor 399); and an electronic device (eg, electronic device 300) including a memory operatively connected to the processor. The memory is configured to, when executed, cause the processor to periodically generate a synchronization signal with the high voltage level in a first time period with the display having the frame rate of the display set to a first frame rate. During this time, instructions for starting a transmission operation for transmitting a frame to the display in the first time period may be stored. The instructions cause the processor to request the display to refresh a frame at the second frame rate based on an event occurring that causes the processor to change from the first frame rate to the second frame rate, and to display the first pitch. The transmission operation may be started in a second time period shorter than the time interval.

The display is configured to periodically generate a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period while the frame rate of the display is set to the second frame rate. It can be configured. The instructions may cause the processor to start the transmission operation in the third time period based on receiving a message from the display indicating that the change from the first frame rate to the second frame rate has been completed. .

The display periodically sends a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period while the frame rate for refreshing is set to the second frame rate. It can be configured to occur. The instructions may cause the processor to start the transmission operation in the third time period after a specified time has elapsed from the time the display is requested to refresh the frame at the second frame rate.

The first frame rate may be 60Hz and the second frame rate may be 120Hz.

The processor may include an application processor and/or GPU (graphic processing unit).

The display may be configured to record frames received from the processor in a frame memory and scan the frames recorded in the frame memory at a falling point when a synchronization signal switches from the high voltage level to the low voltage level.

The frame memory may be configured in a display driver integrated circuit (IC) of the display.

According to one embodiment, a display (e.g., display 340); and an electronic device (e.g., electronic device 300) including a processor (e.g., processor 399) operatively connected to the display. The processor is configured to send a frame to the display while the display is configured to periodically generate a synchronization signal with the high voltage level in a first time period while the frame rate of the display is set to a first frame rate. It may be configured to start a transmission operation in the first time period. The processor requests the display to refresh a frame at the second frame rate based on an event occurring that causes a change from the first frame rate to the second frame rate, and displays a frame rate shorter than the first time period. It may be configured to start the transmission operation in a second time period.

The display is configured to periodically generate a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period while the frame rate of the display is set to the second frame rate. It can be configured. The processor may be configured to start the transmission operation in the third time period based on a message indicating that the change from the first frame rate to the second frame rate has been completed is received from the display.

The display periodically sends a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period while the frame rate for refreshing is set to the second frame rate. It can be configured to occur. The processor may be configured to start the transmission operation in the third time period after a specified time has elapsed from the time of requesting the display to refresh the frame at the second frame rate.

According to one embodiment, a method of operating an electronic device (eg, electronic device 300) is provided. The method includes, while the display of the electronic device is configured to periodically generate a synchronization signal having the high voltage level in a first time period, while the frame rate of the display is set to a first frame rate, and the frame rate is set to a first frame rate. It may include an operation (eg, operation 1110) of starting a transmission operation to transmit to the display in the first time period. The method requests the display to refresh at the second frame rate based on an event occurring that causes the change from the first frame rate to the second frame rate, and refreshes the display at the second frame rate, and refreshes the display at a second frame rate shorter than the first time period. It may include an operation (e.g., operation 1120) of starting the transmission operation in a 2-time period.

The display is configured to periodically generate a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period while the frame rate of the display is set to the second frame rate. It can be configured. The method includes starting the transmission operation in the third time period based on a message indicating that the change from the first frame rate to the second frame rate has been completed is received from the display (e.g., operation 1140 ) may further be included.

The display periodically sends a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period while the frame rate for refreshing is set to the second frame rate. It can be configured to occur. The method may further include starting the transmission operation in the third time period after a specified time has elapsed from the time of requesting the display to refresh the frame at the second frame rate.

According to one embodiment, a recording medium storing instructions readable by a processor of an electronic device is provided. The instructions, when executed by the processor, cause the processor to cause the display of the electronic device to send a synchronization signal having the high voltage level in a first time period while the frame rate of the display is set to a first frame rate. While configured to occur periodically, a transmission operation for transmitting a frame to the display may be performed starting in the first time period (eg, operation 1110). The instructions cause the processor to request the display to refresh a frame at the second frame rate based on an event occurring that causes the processor to change from the first frame rate to the second frame rate, and to display the first pitch. An operation to start the transmission operation (eg, operation 1120) may be performed in a second time period shorter than the time period.

The display is configured to periodically generate a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period while the frame rate of the display is set to the second frame rate. It can be configured. The instructions include, by the processor, starting the transmission operation in the third time period based on a message indicating that the change from the first frame rate to the second frame rate has been completed is received from the display (e.g. : Operation 1140) can be performed.

The display periodically sends a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period while the frame rate for refreshing is set to the second frame rate. It can be configured to occur. The instructions may cause the processor to perform an operation to start the transmission operation in the third time period after a specified time has elapsed from the time of requesting the display to refresh the frame at the second frame rate. .

Claims

In electronic devices,

display;

a processor operatively coupled to the display; and

a memory operatively coupled to the processor,

The memory, when executed, causes the processor to:

A transmission operation of transmitting a frame to the display while the display is configured to periodically generate a synchronization signal with the high voltage level in a first time period while the frame rate of the display is set to a first frame rate. Starting from the first time period,

Based on the occurrence of an event causing a change from the first frame rate to the second frame rate, requesting the display to refresh the frame at the second frame rate, and a second time period shorter than the first time period An electronic device that stores instructions for starting the transmission operation.
The method of claim 1, wherein when the frame rate of the display is set to the second frame rate, the display displays a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period. configured to occur periodically, wherein the instructions are such that the processor,

An electronic device that starts the transmission operation in the third time period based on a message indicating that the change from the first frame rate to the second frame rate has been completed is received from the display.
The method of claim 1, wherein when the frame rate for refresh is set to the second frame rate, the display has the high voltage level in a third time period or a fourth time period shorter than the third time period. Configured to periodically generate a synchronization signal, the instructions include the processor,

An electronic device that starts the transmission operation in the third time period after a specified time has elapsed from the time of requesting the display to refresh the frame at the second frame rate.
According to any one of claims 1 to 3,

The electronic device wherein the first frame rate is 60Hz and the second frame rate is 120Hz.
The method of any one of claims 1 to 3, wherein the processor:

An electronic device that includes an application processor and/or graphics processing unit (GPU).
The method according to any one of claims 1 to 3, wherein the display,

Recording the frame received from the processor in a frame memory,

An electronic device configured to scan frames written to the frame memory at a falling point when a synchronization signal transitions from the high voltage level to the low voltage level.
The electronic device of claim 6, wherein the frame memory is configured in a display driver integrated circuit (IC) of the display.
In electronic devices,

display; and

a processor operatively coupled to the display, the processor comprising:

A transmission operation of transmitting a frame to the display while the display is configured to periodically generate a synchronization signal with the high voltage level in a first time period while the frame rate of the display is set to a first frame rate. Starting from the first time period,

Based on the occurrence of an event causing a change from the first frame rate to the second frame rate, requesting the display to refresh the frame at the second frame rate, and a second time period shorter than the first time period An electronic device configured to initiate the transmission operation.
The method of claim 8, wherein when the frame rate of the display is set to the second frame rate, the display displays a synchronization signal having the high voltage level in a third time period or a fourth time period shorter than the third time period. configured to occur periodically, where the processor:

The electronic device is configured to start the transmission operation in the third time period based on receiving a message from the display indicating that the change from the first frame rate to the second frame rate is complete.
The method of claim 8, wherein when the frame rate for refresh is set to the second frame rate, the display has the high voltage level in a third time period or a fourth time period shorter than the third time period. Configured to periodically generate a synchronization signal, wherein the processor:

The electronic device configured to start the transmission operation in the third time period after a specified time has elapsed from the time of requesting the display to refresh the frame at the second frame rate.
The method according to any one of claims 8 to 10,

The electronic device wherein the first frame rate is 60Hz and the second frame rate is 120Hz.
The method of any one of claims 8 to 10, wherein the processor:

An electronic device that includes an application processor and/or graphic processing unit (GPU).
In a method of operating an electronic device,

Transmitting a frame to the display while the display of the electronic device is configured to periodically generate a synchronization signal having the high voltage level in a first time period while the frame rate of the display is set to a first frame rate starting a transmission operation in the first time period; and

Based on the occurrence of an event causing a change from the first frame rate to the second frame rate, requesting the display to refresh the frame at the second frame rate, and a second time period shorter than the first time period A method comprising initiating the transmission operation.
14. The method of claim 13, wherein the display has the high voltage level in a third time period or a fourth time period shorter than the third time period, with the frame rate of the display set to the second frame rate. It is configured to generate a signal periodically,

The method further includes starting the transmission operation in the third time period based on a message indicating completion of the change from the first frame rate to the second frame rate being received from the display.
The method of claim 13 or 14, wherein the display displays the display in a third time period or a fourth time period shorter than the third time period, with the frame rate for refreshing being set to the second frame rate. Configured to periodically generate a synchronization signal with a high voltage level,

The method further includes starting the transmission operation in the third time period after a specified time has elapsed from the time of requesting the display to refresh at the second frame rate.