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WO2024198763A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024198763A1
WO2024198763A1 PCT/CN2024/077544 CN2024077544W WO2024198763A1 WO 2024198763 A1 WO2024198763 A1 WO 2024198763A1 CN 2024077544 W CN2024077544 W CN 2024077544W WO 2024198763 A1 WO2024198763 A1 WO 2024198763A1
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WO
WIPO (PCT)
Prior art keywords
layer
isolation
isolation portion
substrate
film
Prior art date
Application number
PCT/CN2024/077544
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English (en)
French (fr)
Inventor
张静丽
宋二龙
张锴
储小东
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024198763A1 publication Critical patent/WO2024198763A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device.
  • OLED display products have gradually become mainstream products in the display field due to their advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed.
  • reliability has always been a test for OLED display products.
  • the high-temperature and high-humidity operation test is to place the display screen in a high-temperature and high-humidity environment when powered on, and observe the display screen after 672 hours to see if there is any poor reliability.
  • OLED display products designed with openings since the frame of the hole area is very narrow, the area near the hole area is a place with weak reliability.
  • OLED light-emitting elements include anodes, light-emitting functional layers, and cathode layers stacked in sequence
  • some technologies set isolation columns in the frame of the hole area to separate the light-emitting functional layer and the cathode layer to block the channel for water and oxygen to invade.
  • the conductive glue of the display screen or the conductive ions in the polarizer will be freed to the display area under the action of the electric field, causing product reliability failure.
  • An embodiment of the present disclosure provides a display substrate, comprising a hole area, a transition area surrounding the hole area, and a display area surrounding the transition area; the transition area is provided with an isolation column surrounding the hole area, the isolation column comprising a first isolation portion and a first coating layer;
  • the display substrate comprises a base, the first isolation portion comprises a second conductive layer, the first side of the first isolation portion faces the display area, and the second side of the first isolation portion faces the hole area;
  • the first coating layer is arranged on a side of the first isolation portion away from the base, and covers one of the first side and the second side of the first isolation portion, and on the other side of the first side and the second side of the first isolation portion, the second conductive layer is set back compared to the first coating layer;
  • the material of the first coating layer is an insulating material.
  • the embodiment of the present disclosure also provides a display device, comprising the display substrate.
  • the present disclosure also provides a method for preparing the display substrate, comprising:
  • first isolation layer on the substrate of the transition region, the first isolation layer comprising a first film layer, a second film layer and a third film layer stacked in sequence in a direction away from the substrate, and edges of the first film layer, the second film layer and the third film layer are flush on a side of the first isolation layer facing the display region and a side facing the hole region;
  • a first covering layer is formed on a surface of the second film layer away from the substrate, and the first covering layer covers a side of the first isolation layer facing the display area or the hole area, and on a side of the first isolation layer not covered by the first covering layer, edges of the second film layer and the first film layer protrude from an edge of the first covering layer;
  • the second film layer is etched by an etching process, so that on the side of the first isolation layer not covered by the first covering layer, the edge of the second film layer is retracted compared to the edge of the first covering layer and the edge of the first film layer, so that the first film layer and the second film layer of the first isolation layer become the first conductive layer and the second conductive layer of the first isolation part respectively.
  • FIG. 1 is a schematic diagram of a planar structure of a display substrate according to some exemplary embodiments
  • Fig. 2 is a schematic diagram of the A-A cross-sectional structure in Fig. 1 in some exemplary embodiments;
  • FIG3 is a schematic diagram of a structure in which a light-emitting functional layer is separated by an isolation column in some technologies
  • FIG4 is a schematic diagram of a structure in which a light-emitting functional layer is separated by an isolation column in some other technologies
  • FIG5 is a schematic structural diagram of the third metal conductive layer of the isolation column in FIG4 being warped and overlapping the light-emitting functional layer;
  • FIG6 is a schematic structural diagram of the light-emitting functional layer in FIG4 being bent downward and overlapped with the third metal conductive layer of the isolation column;
  • FIG. 7 a is a schematic cross-sectional structure diagram of an isolation column of a display substrate according to some exemplary embodiments.
  • FIG. 7 b is a schematic cross-sectional structure diagram of an isolation column of a display substrate according to some other exemplary embodiments.
  • FIG. 7c is a schematic cross-sectional structure diagram of an isolation column of a display substrate according to some other exemplary embodiments.
  • FIG8 is a schematic cross-sectional structure diagram of an isolation column of a display substrate according to some other exemplary embodiments.
  • FIG9 is a schematic cross-sectional view of an isolation column of a display substrate according to some further exemplary embodiments.
  • FIG10 is a schematic cross-sectional view of an isolation column of a display substrate according to some further exemplary embodiments.
  • FIG11 is a schematic cross-sectional view of a spacer column of a display substrate according to some further exemplary embodiments.
  • FIG. 12 a is a schematic structural diagram of a display substrate after a fourth insulating layer is formed according to some exemplary embodiments
  • FIG12 b is a schematic structural diagram of a display substrate after forming a first source-drain metal layer according to some exemplary embodiments
  • FIG12c is a schematic structural diagram of a display substrate after the third metal layer of the first isolation layer is removed according to some exemplary embodiments;
  • FIG12d is a schematic structural diagram of a display substrate after a passivation layer is formed according to some exemplary embodiments.
  • FIG12e is a schematic structural diagram of a display substrate after forming a second source-drain metal layer according to some exemplary embodiments
  • FIG12f is a schematic structural diagram of a display substrate after a pixel defining layer is formed according to some exemplary embodiments.
  • FIG12g is a schematic structural diagram of a display substrate after etching the second metal layer of the first isolation layer according to some exemplary embodiments;
  • FIG13a is a schematic structural diagram of a display substrate after forming a second source-drain metal layer according to some other exemplary embodiments
  • FIG13 b is a schematic structural diagram of a display substrate of some other exemplary embodiments after the sixth metal layer of the first isolation layer is removed;
  • FIG13c is a schematic structural diagram of a display substrate after forming a second planar layer according to some other exemplary embodiments.
  • FIG13d is a schematic structural diagram of a display substrate after forming a first electrode according to some other exemplary embodiments.
  • FIG13e is a schematic structural diagram of a display substrate after forming a pixel defining layer according to some other exemplary embodiments.
  • FIG13f is a schematic structural diagram of a display substrate after etching the fifth metal layer of the first isolation layer according to some other exemplary embodiments;
  • FIG14a is a schematic structural diagram of a display substrate after forming a fourth insulating layer according to some further exemplary embodiments.
  • FIG14 b is a schematic structural diagram of a display substrate after forming a first source-drain metal layer according to some further exemplary embodiments;
  • FIG. 14c is a schematic structural diagram of a display substrate according to some further exemplary embodiments after a portion of the third metal layer of the first isolation layer is etched;
  • FIG14d is a schematic structural diagram of a display substrate after a passivation layer is formed according to some other exemplary embodiments.
  • FIG14e is a schematic structural diagram of a display substrate after forming a second source-drain metal layer according to some other exemplary embodiments.
  • FIG. 14f is a schematic structural diagram of a display substrate after forming a pixel defining layer according to some other exemplary embodiments.
  • FIG14g is a schematic structural diagram of a display substrate according to some further exemplary embodiments after etching the second metal layer of the first isolation layer;
  • FIG15 a is a schematic structural diagram of a display substrate after forming a fourth insulating layer according to some further exemplary embodiments
  • FIG15 b is a schematic structural diagram of a display substrate after forming a first source-drain metal layer according to some further exemplary embodiments;
  • FIG15c is a schematic structural diagram of a display substrate after a passivation layer is formed according to some other exemplary embodiments.
  • FIG15d is a schematic structural diagram of a display substrate after forming a second source-drain metal layer according to some other exemplary embodiments.
  • FIG15e is a schematic structural diagram of a display substrate according to some further exemplary embodiments after a portion of the third metal layer of the first isolation layer is etched;
  • FIG. 15f is a schematic diagram of the structure of the display substrate after etching the second metal layer of the first isolation layer according to some further exemplary embodiments.
  • Figure 1 is a schematic diagram of the planar structure of a display substrate of some exemplary embodiments
  • Figure 2 is a schematic diagram of the A-A cross-sectional structure in Figure 1 in some exemplary embodiments.
  • the display substrate includes a hole area 200, a transition area 300 surrounding the hole area 200, and a display area 100 surrounding the transition area 300.
  • the display area 100 includes a driving structure layer 20 , a light emitting structure layer 30 and a packaging structure layer 40 which are sequentially stacked on the substrate 10 .
  • the driving structure layer 20 includes a plurality of pixel driving circuits, and the pixel driving circuits include a plurality of transistors (T) 201 and storage capacitors (C) 202.
  • the pixel driving circuits may adopt a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure, which is not limited in the present disclosure.
  • the light emitting structure layer 30 includes a plurality of light emitting elements, and the light emitting elements may be OLED (organic light emitting diode) Or QLED (quantum dot light emitting diode) device.
  • the light emitting structure layer 30 includes a first electrode layer, a pixel defining layer 32, a light emitting functional layer and a second electrode layer 34 arranged in sequence;
  • the first electrode layer includes a plurality of first electrodes 31,
  • the pixel defining layer 32 is arranged on the side of the plurality of first electrodes 31 away from the substrate 10 and is provided with a plurality of pixel openings, the pixel openings expose the first electrodes 31, and the light emitting functional layer and the second electrode layer 34 are stacked in sequence on the side of the first electrode 31 away from the substrate 10.
  • the light emitting element includes a first electrode 31, a light emitting functional layer 33 and a second electrode layer 34.
  • the light emitting functional layer 33 includes an organic light emitting layer, and may also include any one or more film layers of a hole injection layer, a hole transport layer and an electron blocking layer located between the first electrode 31 and the organic light emitting layer, and any one or more film layers of an electron injection layer, an electron transport layer and a hole blocking layer located between the second electrode layer 34 and the organic light emitting layer.
  • the first electrode 31 of the light emitting element is connected to the pixel driving circuit, and the light emitting element emits light under the drive of the pixel driving circuit.
  • the encapsulation structure layer 40 may include a first encapsulation layer 41, a second encapsulation layer 42, and a third encapsulation layer 43 stacked in sequence in a direction away from the substrate 10.
  • the main material of the first encapsulation layer 41 and the third encapsulation layer 43 (the material with the largest component in the film layer) is an inorganic material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the main material of the second encapsulation layer 42 may be an organic material, such as epoxy resin, which helps to achieve encapsulation and avoid erosion by water vapor.
  • the first encapsulation layer 41 and the third encapsulation layer 43 may be formed by a chemical vapor deposition (CVD) process, and the second encapsulation layer 42 may be formed by an inkjet printing (IJP) process.
  • CVD chemical vapor deposition
  • IJP inkjet printing
  • the transition region 300 is provided with an isolation dam 60 and an isolation column 50, and the isolation dam 60 and the isolation column 50 are both arranged around the hole region 200.
  • the surface of the isolation dam 60 away from the substrate 10 is higher than the surface of the isolation column 50 away from the substrate 10.
  • the number of the isolation dam 60 and the isolation column 50 may be unlimited.
  • the inkjet printing material may overflow, and the isolation dam 60 may prevent the inkjet printing material from overflowing.
  • the isolation column 50 may serve to isolate the light-emitting functional layer 33 and the second electrode layer 34, so as to prevent water and oxygen from corroding from the hole region 200 along the light-emitting functional layer 33 and the second electrode layer 34 to the display region 100, and protect the light-emitting functional layer 33 and the second electrode layer 34 of the display region 100 from being corroded by water and oxygen.
  • Figure 3 is a schematic diagram of the structure of the isolation column separating the light-emitting functional layer in some technologies, the isolation column includes a first metal conductive layer 1', a second metal conductive layer 2' and a third metal conductive layer 3' stacked in sequence along the direction away from the substrate.
  • the first metal conductive layer 1', the second metal conductive layer 2' and the third metal conductive layer 3' are roughly in the shape of an "I".
  • the light-emitting functional layer 33 located on both sides of the isolation column are overlapped on the first metal conductive layer 1' and connected to form a conductive path through the first metal conductive layer 1'.
  • the conductive glue or polarizer of the display screen will adhere to the light-emitting functional layer 33 at the edge of the hole area.
  • the conductive ions in the conductive glue or polarizer will be freed to the display area through the conductive path, causing product reliability failure.
  • one side of the isolation column is covered with an insulating layer 4' to block the conductive path.
  • the insulating layer 4' covers one side (the first side) of the isolation column, it is also partially located on the surface of the third metal conductive layer 3' away from the substrate. The portion of the third metal conductive layer 3' close to the other side (the second side) of the isolation column is not covered by the insulating layer 4'.
  • the light-emitting functional layer 33 located on the first side of the isolation column is partially located on the insulating layer 4' on the surface of the third metal conductive layer 3' away from the substrate, and the light-emitting functional layer 33 located on the second side of the isolation column is partially located on the first metal conductive layer 1'.
  • the portion of the third metal conductive layer 3' that is not covered by the insulating layer 4' near the second side of the isolation column will bend up and can overlap with the light-emitting functional layer 33 on the insulating layer 4' located on the surface of the third metal conductive layer 3' away from the substrate, or, as shown in FIG6 , the light-emitting functional layer 33 on the insulating layer 4' located on the surface of the third metal conductive layer 3' away from the substrate will bend down and can overlap with the portion of the third metal conductive layer 3' that is not covered by the insulating layer 4' near the second side of the isolation column, so that the light-emitting functional layer 33 located on the first side of the isolation column is still connected to the light-emitting functional layer 33 located on the second side of the isolation column through the third metal conductive layer 3', the second metal conductive layer 2' and the first metal conductive layer 1' to form a conductive path.
  • Fig. 7a is a schematic diagram of the cross-sectional structure of the isolation column of the display substrate of some exemplary embodiments
  • Fig. 8 is a schematic diagram of the cross-sectional structure of the isolation column of the display substrate of some other exemplary embodiments.
  • the embodiment of the present disclosure provides a display substrate, the display substrate includes a hole area 200, a transition area 300 surrounding the hole area 200, and a display area 100 surrounding the transition area 300; the transition area 300 is provided with an isolation column 50 surrounding the hole area 200, and the isolation column 50 includes a first isolation portion 51 and a first cladding layer 52; the display substrate includes The substrate 10, the first isolation part 51 includes a second conductive layer 512, the first side of the first isolation part 51 faces the display area 100, and the second side of the first isolation part 51 faces the hole area 200; the first covering layer 52 is arranged on the side of the first isolation part 51 away from the substrate 10, and covers one of the first side and the second side of the first isolation part 51, and on the other side of the first side and the second side of the first isolation part 51, the second conductive layer 512 is retracted compared to the first covering layer 52; the material of the first covering layer 52 is an insulating material.
  • a first coating layer 52 of an insulating material is provided, and one of the first side and the second side of the first isolation portion 51 is coated.
  • the second conductive layer 512 is set inwardly compared with the first coating layer 52 (that is, the first coating layer 52 is set protrudingly compared with the second conductive layer 512). In this way, the light-emitting functional layer 33 of the display substrate can be disconnected on the side of the first side and the second side of the first isolation portion 51 that is not coated by the first coating layer 52.
  • the first coating layer 52 is provided on the second side of the first isolation portion 51.
  • the light-emitting functional layer 33 located on the first covering layer 52 will not overlap with the second conductive layer 512. Therefore, the light-emitting functional layer 33 located on the side of the isolation column 50 facing the display area 100 and the light-emitting functional layer 33 located on the side of the isolation column 50 facing the hole area 200 will not be connected to form a conductive path through the first isolation portion 51 with a conductive function. This can avoid the problem in some technologies that when the display screen is powered on, the conductive glue of the display screen or the conductive ions in the polarizer are liberated to the display area 100 through the conductive path under the action of the electric field, causing product reliability failure.
  • the first isolation portion 51 further includes a first conductive layer 511 disposed on a side of the second conductive layer 512 close to the substrate 10, the first coating layer 52 is disposed on a surface of the second conductive layer 512 away from the substrate 10, and covers one of the first side and the second side of the first isolation portion 51, and on the other side of the first side and the second side of the first isolation portion 51, the second conductive layer 512 is further retracted relative to the first conductive layer 511.
  • the first isolation portion 51 may include only the first conductive layer 511 and the second conductive layer 512.
  • the second conductive layer 512 can be retracted by approximately 0.35 microns to 0.4 microns compared to the first encapsulating layer 52, which helps the isolation column 50 to isolate the light-emitting functional layer 33, and when the light-emitting functional layer 33 is disconnected at the isolation column 50, the light-emitting functional layer 33 located on the first encapsulating layer 52 will not overlap with the second conductive layer 512 on the other side of the first side and the second side of the first isolation portion 51.
  • Figure 7b is a schematic diagram of the cross-sectional structure of the isolation column of the display substrate of other exemplary embodiments, on the other side of the first side and the second side of the first isolation portion 51 (the side not covered by the first covering layer 52), the thickness of the portion close to the edge of the first covering layer 52 is smaller than that of the rest of the first covering layer 52, and the portion close to the edge of the first covering layer 52 can have a slope angle ⁇ of approximately 20 degrees to 45 degrees.
  • the first isolation portion 51 may also include a third conductive layer 513 arranged on the side of the second conductive layer 512 away from the substrate 10, and the first coating layer 52 is arranged on the surface of the third conductive layer 513 away from the substrate 10, and covers one of the first side and the second side of the first isolation portion 51; on the other side of the first side and the second side of the first isolation portion 51, the second conductive layer 512 is also retracted compared to the third conductive layer 513.
  • the first coating layer 52 also includes the third conductive layer 513
  • the surface of the other side (the side not covered by the first covering layer 52) of the first isolation portion 51 and the second side is covered, and the orthographic projection of the third conductive layer 513 on the substrate 10 falls within the orthographic projection of the first covering layer 52 on the substrate 10.
  • the first coating layer 52 also coats the surface of the third conductive layer 513 located on the other side of the first side and the second side of the first isolation portion 51, when the light-emitting functional layer 33 is disconnected at the isolation column 50, the light-emitting functional layer 33 located on the first coating layer 52 will not overlap with the third conductive layer 513 on the other side of the first side and the second side of the first isolation portion 51.
  • the light-emitting functional layer 33 located on the side of the isolation column 50 facing the display area 100 and the light-emitting functional layer 33 located on the side of the isolation column 50 facing the hole area 200 will not be connected to form a conductive path through the first isolation portion 51 with a conductive function, thereby avoiding the problem in some technologies that when the display screen is powered on, the conductive glue of the display screen or the conductive ions in the polarizer are freed to the display area 100 through the conductive path under the action of the electric field, causing product reliability failure.
  • the second conductive layer 512 may be retracted by about 0.35 micrometers to 0.4 micrometers compared to the first cladding layer 52 .
  • a portion of the first cladding layer 52 close to the edge may have a slope of approximately 50 to 75 degrees, and reference may be made to the slope angle ⁇ in FIG. 7b .
  • FIG. 9 is a schematic diagram of the cross-sectional structure of the isolation column of the display substrate of some other exemplary embodiments, the isolation column may also include a second isolation portion 53, the second isolation portion 53 is arranged on the side of the first isolation portion 51 facing the substrate 10, the second isolation portion 53 includes a fourth conductive layer 531, a fifth conductive layer 532 and a sixth conductive layer 533 stacked in sequence in a direction away from the substrate 10; the first side of the second isolation portion 53 faces the display area 100, and the second side of the second isolation portion 53 faces the hole area 200; the first coating layer 52 also covers one of the first side and the second side of the second isolation portion 53, and on the other side of the first side and the second side of the second isolation portion 53, the fifth conductive layer 532 is set inward compared with the fourth conductive layer 531 and the sixth conductive layer 533.
  • the second isolation portion 53 may only include a fourth conductive layer 531 and a fifth conductive
  • the light-emitting functional layer 33 can be disconnected on the first side and the second side of the second isolation portion 53 that are not covered by the first covering layer 52 , thereby improving the isolation effect of the isolation column on the light-emitting functional layer 33 .
  • the first side and the second side of the first isolation part 51, which are covered by the first covering layer 52, and the first side and the second side of the second isolation part 53, which are covered by the first covering layer 52, are located on the same side of the isolation column.
  • they may both be located on the side of the isolation column facing the display area 100, or they may both be located on the side of the isolation column facing the hole area 200.
  • the first conductive layer 511 may be disposed on a surface of the sixth conductive layer 533 away from the substrate 10.
  • the materials of the first conductive layer 511 and the sixth conductive layer 533 may be the same or different.
  • FIG. 10 is a schematic diagram of the cross-sectional structure of the isolation column of the display substrate of some other exemplary embodiments, and the isolation column includes a first isolation portion 51, a first coating layer 52, and a second isolation portion 53.
  • the structure of the first isolation portion 51 may be the same as the structure of the first isolation portion 51 of FIG.
  • the first isolation portion 51 includes a first conductive layer 511 and a second conductive layer 512 stacked in sequence in a direction away from the substrate 10, and the first coating layer 52 is provided on the surface of the second conductive layer 512 away from the substrate 10, and covers the first isolation portion 51 and the second isolation portion 53 on one side facing the display area 100 or the hole area 200, and the first isolation portion 51 is not covered by the first covering layer 52, and the second conductive layer 512 is set back compared with the first conductive layer 511 and the first covering layer 52.
  • the structure of the first isolation part 51 can be the same as the structure of the first isolation part 51 of FIG8, the first isolation part 51 includes a first conductive layer 511, a second conductive layer 512 and a third conductive layer 513 stacked in sequence in a direction away from the substrate 10, the first covering layer 52 is provided on the surface of the third conductive layer 513 away from the substrate 10, and covers the first isolation part 51 and the second isolation part 53 on the side facing the display area 100 or the hole area 200, and covers the surface of the third conductive layer 513 located on the side of the first isolation part 51 not covered by the first covering layer 52; on the side of the first isolation part 51 not covered by the first covering layer 52, the second conductive layer 512 is set back compared with the first conductive layer 511 and the third conductive layer 513.
  • FIG. 11 is a schematic diagram of the cross-sectional structure of the isolation column of the display substrate of some other exemplary embodiments, the isolation column 50 includes a first isolation portion 51 and a first cladding layer 52; the first isolation portion 51 includes a first conductive layer 511 and a second conductive layer 512 sequentially stacked in a direction away from the substrate 10, the first side of the first isolation portion 51 faces the display area 100, and the second side of the first isolation portion 51 faces the hole area 200; the first cladding layer 52 is provided on the side of the first isolation portion 51 away from the substrate 10, and covers one of the first side and the second side of the first isolation portion 51, and on the other side of the first side and the second side of the first isolation portion 51, the second conductive layer 512 is set inward compared with the first conductive layer 511 and the first cladding layer 52; the material of the first cladding layer 52 is an insulating material;
  • the isolation column 50 may also include a second isolation portion 53 and a second coating layer 54; the second isolation portion 53 is arranged on the side of the first isolation portion 51 facing the substrate 10, the first side of the second isolation portion 53 faces the display area 100, and the second side of the second isolation portion 53 faces the hole area 200; the second coating layer 54 is arranged between the second isolation portion 53 and the first isolation portion 51, and covers one of the first side and the second side of the second isolation portion 53; the material of the second isolation portion 53 is a conductive material, and the material of the second coating layer 54 is an insulating material.
  • the second isolation portion 53 may include a fourth conductive layer 531, a fifth conductive layer 532 and a sixth conductive layer 533 stacked in sequence in a direction away from the substrate 10; on the other side of the first side and the second side of the second isolation portion 53 (the side not covered by the second covering layer 54), the fifth conductive layer 532 is retracted compared to the fourth conductive layer 531 and the sixth conductive layer 533.
  • the first side and the second side of the first isolating portion 51, which are covered by the first coating layer 52, and the first side and the second side of the second isolating portion 53, which are covered by the second coating layer 54, may be located on different sides of the isolating column 50.
  • the first side and the second side of the first isolating portion 51, which are covered by the first coating layer 52, are located on the side of the isolating column 50 facing the display area 100, and the first side and the second side of the second isolating portion 53, which are covered by the second coating layer 54, are located on the side of the isolating column 50 facing the hole area 200; or, the first side and the second side of the first isolating portion 51, which are covered by the first coating layer 52, are located on the side of the isolating column 50 facing the hole area 200, and the first side and the second side of the second isolating portion 53, which are covered by the second coating layer 54, are located on the side of the isolating column 50 facing the display area 100.
  • first side and the second side of the first isolation portion 51 which is covered by the first coating layer 52
  • first side and the second side of the second isolation portion 53 which is covered by the second coating layer 54
  • they may both be located on the side of the isolation column 50 facing the display area 100, or they may both be located on the side of the isolation column 50 facing the hole area 200.
  • the number of the isolation parts of the isolation column may be one or more, for example, in the examples of FIG. 7a and FIG. 8 , there may be only one isolation part (i.e., the first isolation part), and in the examples of FIG. 9 , FIG. 10 and FIG. 11 , there may be two isolation parts (i.e., the first isolation part and the second isolation part), and in other embodiments, the number of isolation parts may be three or four, etc.
  • the embodiment of the present disclosure does not limit the number of isolation parts of the isolation column.
  • the isolation column 50 may further include a column base 55 disposed on a side of the first isolation portion 51 facing the substrate 10 , and the column base 55 may include one or more film layers.
  • the column base 55 may include one inorganic insulating layer or a plurality of stacked inorganic insulating layers.
  • the column base 55 may include at least one inorganic insulating layer and at least one metal layer, and the metal layer may be coated by the inorganic insulating layer.
  • FIG. 7c is a schematic diagram of the cross-sectional structure of the isolation column of the display substrate of other exemplary embodiments
  • the column base 55 may include a seventh metal layer 555, a first inorganic insulating layer 553, an eighth metal layer 556 and a second inorganic insulating layer 554 stacked in sequence in a direction away from the substrate, the first inorganic insulating layer 553 covers the seventh metal layer 555, and the second inorganic insulating layer 554 covers the eighth metal layer 556.
  • the first isolation portion 51 may be provided on a surface of the second inorganic insulating layer 554 away from the substrate.
  • the first conductive layer 511 of the first isolation portion 51 may be disposed on a surface of the column base 55 away from the substrate 10 .
  • the isolation column 50 when the isolation column 50 includes the second isolation portion 53, the column base 55 is arranged on the side of the second isolation portion 53 facing the substrate 10, and the fourth conductive layer 531 of the second isolation portion 53 can be arranged on the surface of the column base 55 away from the substrate 10.
  • the display area 100 includes a driving structure layer 20 and a light-emitting structure layer 30 sequentially stacked on the substrate 10
  • the driving structure layer 20 includes a pixel driving circuit
  • the pixel driving circuit includes a plurality of transistors 201 and a storage capacitor 202
  • the light-emitting structure layer 30 includes a plurality of light-emitting elements
  • the light-emitting elements include a first electrode 31, a light-emitting functional layer 33 and a second electrode layer 34 sequentially stacked in a direction away from the substrate 10.
  • the driving structure layer 20 may include a first source-drain metal layer, a fifth insulating layer 25, a second source-drain metal layer and a second flat layer 26 arranged in sequence along a direction away from the substrate 10;
  • the first source-drain metal layer includes a source electrode 2013 and a drain electrode 2014 of at least one of the transistors 201, and the second source-drain metal layer includes a connecting electrode 203 connected to the source electrode 2013 or the drain electrode 2014 of the transistor 201, and the connecting electrode 203 is also connected to the first electrode 31.
  • the first source-drain metal layer may include a plurality of stacked metal layers, and the first isolation portion 51 is disposed in the same layer as the source electrode 2013 and the drain electrode 2014 of the transistor 201.
  • the film layer of the first isolation portion 51 may be the same as the film layer of the source electrode 2013 and the drain electrode 2014 of the transistor 201, or the number of film layers of the first isolation portion 51 may be less than the number of film layers of the source electrode 2013 and the drain electrode 2014 of the transistor 201.
  • a and B are arranged in the same layer means that the film layer of A and the film layer of B are from the same thin film, which can be a single-layer structure or a multi-layer composite structure, and the film layer of A and the film layer of B can be the same or different.
  • “A and B are arranged in the same layer” can be understood as that the same thin film is subjected to the same patterning process to form A and B at the same time, or that the same thin film is subjected to the same patterning process to form A’ and B’ at the same time, and A’ is further processed (such as etching, etc.) to obtain A, and B’ is further processed (such as etching, etc.) to obtain B.
  • the first source-drain metal layer may include a first metal layer 301, a second metal layer 302, and a third metal layer 303 stacked in sequence in a direction away from the substrate 10.
  • the first metal layer 301 and the third metal layer 303 may be titanium layers
  • the second metal layer 302 may be an aluminum layer.
  • the film layer of the source electrode 2013 and the drain electrode 2014 of the transistor 201 is the same as the film layer of the first source-drain metal layer, that is, both include the stacked first metal layer 301, the second metal layer 302, and the third metal layer 303. In some examples, as shown in FIG.
  • the first isolation portion 51 includes two film layers, namely the first conductive layer 511 and the second conductive layer 512, wherein the first conductive layer 511 is made of the same material as the first metal layer 301, and the second conductive layer 512 is made of the same material as the second metal layer 302.
  • the first isolation portion 51 includes three film layers, namely the first conductive layer 511, the second conductive layer 512 and the third conductive layer 513, wherein the first conductive layer 511 is made of the same material as the first metal layer 301, the second conductive layer 512 is made of the same material as the second metal layer 302, and the third conductive layer 513 is made of the same material as the third metal layer 303.
  • the first coating layer 52 may be disposed on the same layer as the fifth insulating layer 25, and the fifth insulating layer 25 may be a single-layer structure or a multi-layer structure.
  • the material of the first coating layer 52 is the same as that of the fifth insulating layer 25; when the fifth insulating layer 25 is a multi-layer structure, the material of the first coating layer 52 is the same as that of any one of the film layers in the fifth insulating layer 25, or the first coating layer 52 may include a plurality of film layers, and the materials of the plurality of film layers of the first coating layer 52 are the same as those of the plurality of film layers in the fifth insulating layer 25.
  • the fifth insulating layer 25 may include a passivation layer 251 and a first flat layer 252 stacked in sequence in a direction away from the substrate 10, and the material of the first coating layer 52 may be the same as that of the passivation layer 251 or the first flat layer 252, or the first coating layer 52 may include two film layers, and the materials of the two film layers are the same as those of the passivation layer 251 and the first flat layer 252, respectively.
  • the fifth insulating layer 25 may only include the first planar layer 252 , and the material of the first cladding layer 52 is the same as the material of the first planar layer 252 .
  • the second source-drain metal layer may include a plurality of stacked metal layers, and the first isolation portion 51 is provided in the same layer as the connection electrode 203.
  • the film layer of the first isolation portion 51 may be the same as the film layer of the connection electrode 203, or the number of film layers of the first isolation portion 51 may be less than the number of film layers of the connection electrode 203.
  • the second source-drain metal layer may include a fourth metal layer 401, a fifth metal layer 402, and a sixth metal layer 403 stacked in sequence in a direction away from the substrate 10.
  • the fourth metal layer 401 and the sixth metal layer 403 may be titanium layers
  • the fifth metal layer 402 may be an aluminum layer.
  • the film layer of the connecting electrode 203 is the same as the film layer of the second source-drain metal layer, that is, both include the stacked fourth metal layer 401, the fifth metal layer 402, and the sixth metal layer 403. In some examples, as shown in FIG.
  • the first isolation portion 51 includes two film layers, namely, the first conductive layer 511 and the second conductive layer 512, wherein the first conductive layer 511 is made of the same material as the fourth metal layer 401, and the second conductive layer 512 is made of the same material as the fifth metal layer 402.
  • the first isolation portion 51 includes three film layers, namely the first conductive layer 511, the second conductive layer 512 and the third conductive layer 513, wherein the first conductive layer 511 is made of the same material as the fourth metal layer 401, the second conductive layer 512 is made of the same material as the fifth metal layer 402, and the third conductive layer 513 is made of the same material as the sixth metal layer 403.
  • the first cladding layer 52 can be disposed on the same layer as the second flat layer 26 and made of the same material.
  • the isolation column 50 includes a first isolation portion 51, a first cladding layer 52, and a second isolation portion 53.
  • the first isolation portion 51 can be disposed in the same layer as the connection electrode 203
  • the first cladding layer 52 can be disposed in the same layer as the second planar layer 26 and made of the same material
  • the second isolation portion 53 can be disposed in the same layer as the source electrode 2013 and the drain electrode 2014 of the transistor 201.
  • the first source-drain metal layer may include a first metal layer 301, a second metal layer 302, and a third metal layer 303 stacked in sequence in a direction away from the substrate 10.
  • the first metal layer 301 and the third metal layer 303 may be titanium layers
  • the second metal layer 302 may be an aluminum layer.
  • the film layers of the source electrode 2013 and the drain electrode 2014 of the transistor 201 are the same as the film layers of the first source-drain metal layer, that is, both include the stacked first metal layer 301, the second metal layer 302, and the third metal layer 303.
  • the second isolation portion 53 includes a fourth conductive layer 531, a fifth conductive layer 532, and a sixth conductive layer 533 stacked in sequence in a direction away from the substrate 10.
  • the material of the fourth conductive layer 531 is the same as that of the first metal layer 301
  • the material of the fifth conductive layer 532 is the same as that of the second metal layer 302
  • the material of the sixth conductive layer 533 is the same as that of the third metal layer 303.
  • the second source-drain metal layer may include a fourth metal layer 401, a fifth metal layer 402, and a sixth metal layer 403 stacked in sequence in a direction away from the substrate 10.
  • the fourth metal layer 401 and the sixth metal layer 403 may be titanium layers
  • the fifth metal layer 402 may be an aluminum layer.
  • the film layer of the connecting electrode 203 is the same as the film layer of the second source-drain metal layer, that is, both include the stacked fourth metal layer 401, the fifth metal layer 402, and the sixth metal layer 403. In some examples, as shown in FIG.
  • the first isolation portion 51 includes two film layers, namely the first conductive layer 511 and the second conductive layer 512, wherein the first conductive layer 511 is made of the same material as the fourth metal layer 401, and the second conductive layer 512 is made of the same material as the fifth metal layer 402.
  • the first isolation portion 51 includes three film layers, namely the first conductive layer 511, the second conductive layer 512 and the third conductive layer 513, wherein the first conductive layer 511 is made of the same material as the fourth metal layer 401, the second conductive layer 512 is made of the same material as the fifth metal layer 402, and the third conductive layer 513 is made of the same material as the sixth metal layer 403.
  • the isolation column 50 includes a first isolation portion 51 and a first cladding layer 52, and a second isolation portion 53 and a second cladding layer 54.
  • the first isolation portion 51 can be disposed in the same layer as the connection electrode 203
  • the first cladding layer 52 can be disposed in the same layer as the second flat layer 26 and made of the same material
  • the second isolation portion 53 can be disposed in the same layer as the source electrode 2013 and the drain electrode 2014 of the transistor 201
  • the second cladding layer 54 can be disposed in the same layer as the fifth insulating layer 25.
  • the film layer structure of the first isolation portion 51 and the second isolation portion 53 can refer to the example of FIG10
  • the film layer structure of the second cladding layer 54 can refer to the film layer structure of the first cladding layer 52 in the above example when the first cladding layer 52 and the fifth insulating layer 25 are disposed in the same layer.
  • the driving structure layer 20 may also include a semiconductor layer, a first gate metal layer and a second gate metal layer arranged on the side of the first source and drain metal layer facing the substrate 10, the semiconductor layer includes the active layer 2011 of the transistor 201, the first gate metal layer may include the gate electrode 2012 of the transistor 201 and one plate of the storage capacitor 202, and the second gate metal layer may include another plate of the storage capacitor 202.
  • the column base 55 may include an inorganic insulating layer or multiple inorganic insulating layers stacked. Alternatively, the column base 55 may include at least one inorganic insulating layer and at least one metal layer, and the metal layer may be coated by the inorganic insulating layer. Exemplarily, one of the inorganic insulating layers of the column base 55 may be arranged in the same layer and made of the same material as the insulating layer located between the first source and drain metal layer and the second gate metal layer. The metal layer in the column base 55 may be arranged in the same layer and made of the same material as the first gate metal layer or/and the second gate metal layer. Exemplarily, as shown in FIG.
  • the column base 55 may include a seventh metal layer 555, a first inorganic insulating layer 553, an eighth metal layer 556, and a second inorganic insulating layer 554 stacked in sequence in a direction away from the substrate, the first inorganic insulating layer 553 coating the seventh metal layer 555, and the second inorganic insulating layer 554 coating the eighth metal layer 556.
  • the seventh metal layer 555 may be disposed in the same layer as the first gate metal layer and may be made of the same material
  • the eighth metal layer 556 may be disposed in the same layer as the second gate metal layer and may be made of the same material.
  • the driving structure layer 20 includes a first insulating layer 21, a semiconductor layer, a second insulating layer 22, a first gate metal layer, a third insulating layer 23, a second gate metal layer, a fourth insulating layer 24, a first source-drain metal layer, a fifth insulating layer 25, a second source-drain metal layer, and a sixth insulating layer stacked sequentially on the substrate 10; wherein the fifth insulating layer 25 may include a passivation layer 251 and a first flat layer 252 stacked sequentially in a direction away from the substrate 10, or the fifth insulating layer 25 may only include the first flat layer 252; the sixth insulating layer is the second flat layer 26.
  • the first electrode 31 may be disposed on a surface of the second flat layer 26 away from the substrate 10.
  • the substrate 10 may be a flexible substrate 10, such as a polyimide (PI) material.
  • the substrate 10 may be a rigid substrate 10, such as glass.
  • the first insulating layer 21, the second insulating layer 22, the third insulating layer 23, the fourth insulating layer 24 and the passivation layer 251 may be inorganic insulating layers, such as any one or more of silicon oxide (SiO X ), silicon nitride (SiN X ) and silicon oxynitride (SiO X N Y ), and may be a single layer or a multilayer structure.
  • the first insulating layer 21 may be referred to as The buffer layer is used to improve the water and oxygen resistance of the substrate 10.
  • the second insulating layer 22 and the third insulating layer 23 can be called gate insulating (GI) layers, and the fourth insulating layer 24 can be called an interlayer insulating (ILD) layer.
  • GI gate insulating
  • ILD interlayer insulating
  • the first flat layer 252 and the second flat layer 26 are organic insulating layers, and organic insulating materials such as resin can be used.
  • the first gate metal layer, the second gate metal layer, the first source and drain metal layer and the second source and drain metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer structure, such as Ti/Al/Ti stacking.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (
  • the semiconductor layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors 201 manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene polythiophene and other materials
  • FIG. 2 illustrates four isolation columns, namely, isolation column 50a, isolation column 50b, isolation column 50c and isolation column 50d.
  • the number of the isolation columns 50 may be unlimited, for example, it may be set to one or more, and the isolation column 50 may be set on the side of the isolation dam 60 facing the display area 100 or/and the side facing the hole area 200.
  • the structures of the multiple isolation columns 50 may be the same or different, and the multiple isolation columns 50 may be any one or more of the isolation columns 50 illustrated in FIG. 7a , FIG. 8 , FIG. 9 , FIG. 10 , and FIG. 11 .
  • the side of the first isolation portion in the multiple isolation columns 50 covered by the first coating layer may all face the display area or the hole area, or the side of the first isolation portion in at least one of the isolation columns 50 covered by the first coating layer faces the hole area, and the side of the first isolation portion in at least one of the isolation columns 50 covered by the first coating layer faces the display area.
  • the isolation dam 60 may include a first dam layer, a second dam layer, and a third dam layer sequentially stacked in a direction away from the substrate 10, the first dam layer may be disposed in the same layer and made of the same material as the first planar layer 252, the second dam layer may be disposed in the same layer and made of the same material as the second planar layer 26, and the third dam layer may be disposed in the same layer and made of the same material as the pixel defining layer 32.
  • the isolation dam 60 may further include a dam base disposed on a side of the first dam layer facing the substrate 10, and the dam base may include at least one inorganic insulating layer.
  • the structure of the display substrate is exemplified below by the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes the coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A contains the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the first isolation portion 51 is disposed in the same layer as the source electrode 2013 and the drain electrode 2014 of the transistor 201, and the first cladding layer 52 is disposed in the same layer as the passivation layer 251 in the fifth insulating layer 25.
  • the preparation process of the display substrate may include the following operations:
  • a first insulating film and a semiconductor film are sequentially deposited on the substrate 10, and the semiconductor film is patterned by a patterning process.
  • the substrate 10 is patterned to form a first insulating layer 21 covering the substrate 10, and a semiconductor layer pattern disposed on the first insulating layer 21, wherein the semiconductor layer pattern includes a plurality of active layers 2011 located in the display area 100.
  • the transition area 300 includes the first insulating layer 21 disposed on the substrate 10, as shown in FIG. 12a.
  • the transition area 300 includes a first insulating layer 21 and a second insulating layer 22 sequentially stacked on the substrate 10, as shown in FIG. 12a.
  • a third insulating film and a second gate metal film are sequentially deposited, and the second gate metal film is patterned by a patterning process to form a third insulating layer 23 covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer 23, wherein the second gate metal layer pattern includes a plurality of second electrodes 2022 located in the display area 100.
  • the plurality of second electrodes 2022 are disposed opposite to the plurality of first electrodes 2021 and form a plurality of storage capacitors 202.
  • the transition region 300 includes a first insulating layer 21, a second insulating layer 22, and a third insulating layer 23 sequentially stacked on the substrate 10. As shown in FIG. 12a.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer 24 pattern covering the second gate metal layer pattern, wherein the fourth insulating layer 24 pattern includes a first pillar base layer 551 located in the transition region 300, and the fourth insulating layer 24 in the display region 100 is provided with a plurality of first via holes V1 and a plurality of second via holes V2, wherein the plurality of first via holes V1 expose one end of the plurality of active layers 2011, and the plurality of second via holes V2 expose the other end of the plurality of active layers 2011.
  • the transition region 300 includes a first insulating layer 21, a second insulating layer 22, and a third insulating layer 23 sequentially stacked on the substrate 10, and a first pillar base layer 551 disposed on the third insulating layer 23. As shown in FIG. 12a.
  • the first source-drain metal layer pattern includes a plurality of source electrodes 2013 and a plurality of drain electrodes 2014 located in the display area 100, and a first isolation layer located on the first pillar base layer 551 in the transition area 300.
  • the source electrode 2013 is connected to one end of the active layer 2011 through the first via hole V1
  • the drain electrode 2014 is connected to the other end of the active layer 2011 through the second via hole V2.
  • the plurality of active layers 2011, the plurality of gate electrodes 2012, the plurality of source electrodes 2013, and the plurality of drain electrodes 2014 in the display area 100 form a plurality of transistors 201. As shown in FIG. 12b.
  • the first source-drain metal layer may include a first metal layer 301, a second metal layer 302 and a third metal layer 303 stacked in sequence in a direction away from the substrate 10.
  • the first metal layer 301 and the third metal layer 303 may be titanium layers
  • the second metal layer 302 may be an aluminum layer.
  • the source electrode 2013, the drain electrode 2014 and the first isolation layer all include a first metal layer 301 (Ti), a second metal layer 302 (Al) and a third metal layer 303 (Ti) stacked in sequence in a direction away from the substrate 10.
  • the edges of the first metal layer 301, the second metal layer 302 and the third metal layer 303 of the first isolation layer may be substantially flush. As shown in FIG. 12b.
  • edges of A and B are flush means that the edges of A and B are flush within the range of process error, not absolutely flush.
  • the third metal layer 303 of the first isolation layer located in the transition region 300 is completely etched away by an etching process using a mask, as shown in FIG. 12c.
  • a passivation film is deposited, and the passivation film is patterned by a patterning process to form a passivation layer 251 pattern covering the first source and drain metal layer pattern, wherein the passivation layer 251 pattern includes a first coating layer 52 located in the transition region 300, and the first coating layer 52 is arranged on a surface of the second metal layer 302 of the first isolation layer away from the substrate 10 and covers one side of the first isolation layer (for example, a side facing the display region 100), and the second metal layer 302 of the first isolation layer away from the substrate The portion of the surface of the substrate 10 close to the other side of the first isolation layer (for example, the side facing the hole area 200) may not be covered by the first coating layer 52. As shown in FIG. 12d.
  • a first flat film is coated, and the first flat film is patterned by a patterning process to form a first flat layer 252 pattern disposed on the passivation layer 251, and the first flat layer 252 is formed with a plurality of third via holes V3 located in the display area 100, and the first flat layer 252 and the passivation layer 251 in the third via holes V3 are removed and the surface of the drain electrode 2014 is exposed.
  • the passivation layer 251 and the first flat layer 252 as a whole can be referred to as the fifth insulating layer 25, the passivation layer 251 can be an inorganic insulating material, and the first flat layer 252 can be an organic insulating material.
  • the passivation layer 251 may not be provided, and the fifth insulating layer 25 may only include the first flat layer 252.
  • the first coating layer 52 may be formed simultaneously during the process of patterning the first flat layer 252 pattern.
  • the second source-drain metal layer pattern includes a plurality of anode connection electrodes 203 located in the display area 100.
  • the anode connection electrode 203 is connected to the drain electrode 2014 through the third via hole V3, as shown in FIG. 12e.
  • the film structure and material of the second source-drain metal layer may be the same as those of the first source-drain metal layer.
  • the second source-drain metal layer may include a fourth metal layer 401, a fifth metal layer 402, and a sixth metal layer 403 stacked in sequence in a direction away from the substrate 10.
  • the fourth metal layer 401 and the sixth metal layer 403 may be titanium layers
  • the fifth metal layer 402 may be an aluminum layer.
  • the portion of the second metal layer 302 of the first isolation layer of the transition region 300 that is not covered by the first cladding layer 52 is etched away.
  • the edge of the second metal layer 302 of the first isolation layer is roughly flush with the edge of the first cladding layer 52, and the edge of the first metal layer 301 of the first isolation layer protrudes from the edge of the second metal layer 302.
  • the edge of the first metal layer 301 of the first isolation layer made of titanium is more difficult to etch than the second metal layer 302 made of aluminum, after the patterning process is completed, on the side of the first isolation layer not covered by the first covering layer 52, the edge of the first metal layer 301 of the first isolation layer protrudes beyond the edge of the second metal layer 302, as shown in FIG. 12e.
  • a second flat film is coated and patterned by a patterning process to form a second flat layer 26 pattern covering the second source-drain metal layer pattern, and the second flat layer 26 is formed with a plurality of fourth via holes V4 located in the display area 100, and the second flat layer 26 in the fourth via holes V4 is removed to expose the surface of the anode connection electrode 203, as shown in FIG. 12f.
  • the driving structure layer 20 and the film layer of the isolation column 50 are prepared.
  • Forming the light emitting structure layer 30 may include:
  • a first electrode film is deposited on the substrate 10 with the aforementioned pattern formed thereon, and the first electrode film is patterned by a patterning process to form a first electrode layer pattern, wherein the first electrode layer pattern includes a plurality of first electrodes 31 (anodes) located in the display area 100, and the first electrode 31 is connected to the anode connection electrode 203 through the fourth via hole V4 on the second flat layer 26, so that the first electrode 31 is connected to the drain electrode 2014 through the anode connection electrode 203, as shown in FIG. 12f.
  • a pixel defining film is coated on the substrate 10 with the aforementioned pattern, and the pixel defining film is patterned by a patterning process to form a pixel defining layer 32 pattern, wherein the pixel defining layer 32 is provided with a plurality of pixel openings, and the pixel openings expose the surface of the first electrode 31 of the display area 100, as shown in FIG12f.
  • the second metal layer 302 of the first isolation layer of the transition region 300 can be laterally etched using a mask and a wet etching process, so that the second metal layer 302 of the first isolation layer is partially retracted relative to the first cladding layer 52 on the side of the first isolation layer not covered by the first cladding layer 52.
  • the final isolation column 50 structure is formed, and the first metal layer 301 and the second metal layer 302 of the first isolation layer become the first conductive layer of the first isolation portion 51 of the isolation column 50.
  • the conductive layer 511, the second conductive layer 512, and the first column base layer 551 form a column base 55. As shown in FIG12g.
  • a spacer column film is coated on the substrate 10 with the aforementioned pattern formed thereon, and the spacer column film is patterned through a patterning process to form a spacer column layer pattern, wherein the spacer column layer pattern includes a plurality of spacer columns (not shown in the figure) located on the pixel defining layer 32 of the display area 100 .
  • a plurality of film layers of the light-emitting functional layer 33 can be sequentially formed by an evaporation process, and the light-emitting functional layer 33 can include a hole injection layer, a hole transport layer, an electron blocking layer, an organic light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer sequentially arranged in a direction away from the substrate.
  • the remaining film layers of the light-emitting functional layer 33 can all be an integrated whole-surface structure, that is, the remaining film layers of the light-emitting functional layer 33 can be common layers of sub-pixels of different colors, and these common layers can be formed in the display area 100 and the transition area 300 during evaporation. Since the isolation column 50 is provided in the transition area 300, these common layers will be disconnected at the isolation column 50, blocking the path of water and oxygen being transmitted from the hole area 200 through the light-emitting functional layer 33 to the display area 100, and water and oxygen can be prevented from corroding the light-emitting functional layer 33 of the display area 100. As shown in FIG. 2 .
  • a second electrode (cathode) layer is formed by an evaporation process.
  • the second electrode layer 34 of sub-pixels of different colors is a common layer connected as an integrated structure.
  • the second electrode layer 34 can be formed in the display area 100 and the transition area 300.
  • the second electrode layer 34 can be disconnected at the isolation column 50, blocking the path of water and oxygen being transmitted from the hole area 200 through the second electrode layer 34 to the display area 100, thereby preventing water and oxygen from corroding the second electrode layer 34 in the display area 100. As shown in FIG. 2 .
  • Forming the encapsulation structure layer 40 may include:
  • the first encapsulation film is first deposited by deposition using an open mask to form a first encapsulation layer 41 located in the display area 100 and the transition area 300.
  • the second encapsulation material is printed by inkjet printing process using an open mask to form a second encapsulation layer 42 located in the display area 100 and the transition area 300, wherein the isolation dam 60 of the transition area 300 can prevent ink overflow during the inkjet printing process.
  • the third encapsulation film is deposited by deposition using an open mask to form a third encapsulation layer 43 located in the display area 100 and the transition area 300.
  • the materials of the first encapsulation layer 41 and the third encapsulation layer 43 can be inorganic materials, and the materials of the second encapsulation layer 42 can be organic materials. As shown in FIG. 2 .
  • film layers such as a touch control structure layer and a color filter layer may be formed in sequence on the side of the encapsulation structure layer 40 away from the substrate 10 .
  • the display substrate shown in FIG. 2 and the isolation column shown in FIG. 7 a are taken as examples, and the first isolation portion 51 is disposed on the same layer as the connection electrode 203, and the first coating layer 52 is disposed on the same layer as the second planar layer 26.
  • the preparation process of the display substrate may include the following operations:
  • a first insulating film and a semiconductor film are sequentially deposited on the substrate 10, and the semiconductor film is patterned by a patterning process to form a first insulating layer 21 covering the substrate 10, and a semiconductor layer pattern disposed on the first insulating layer 21, wherein the semiconductor layer pattern includes a plurality of active layers 2011 located in the display area 100.
  • the transition area 300 includes the first insulating layer 21 disposed on the substrate 10, as shown in FIG. 13a.
  • the transition area 300 includes a first insulating layer 21 and a second insulating layer 22 sequentially stacked on the substrate 10, as shown in FIG. 13a.
  • a third insulating film and a second gate metal film are sequentially deposited, and the second gate metal film is patterned by a patterning process to form a third insulating layer 23 covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer 23, wherein the second gate metal layer pattern includes a plurality of second electrodes 2022 located in the display area 100.
  • the plurality of second electrodes 2022 are disposed opposite to the plurality of first electrodes 2021 and form a plurality of storage capacitors 202.
  • the transition region 300 includes a first insulating layer 21, a second insulating layer 22, and a third insulating layer 23 sequentially stacked on the substrate 10. As shown in FIG. 13a.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer 24 pattern covering the second gate metal layer pattern, wherein the fourth insulating layer 24 pattern includes a first pillar base layer 551 located in the transition region 300, and the fourth insulating layer 24 in the display region 100 is provided with a plurality of first via holes and a plurality of second via holes, wherein the plurality of first via holes expose one end of the plurality of active layers 2011, and the plurality of second via holes expose the other end of the plurality of active layers 2011.
  • the transition region 300 includes a first insulating layer 21, a second insulating layer 22, and a third insulating layer 23 sequentially stacked on the substrate 10, and a first pillar base layer 551 disposed on the third insulating layer 23. As shown in FIG. 13a.
  • the first source-drain metal layer pattern includes a plurality of source electrodes 2013 and a plurality of drain electrodes 2014 located in the display area 100.
  • the source electrode 2013 is connected to one end of the active layer 2011 through a first via hole
  • the drain electrode 2014 is connected to the other end of the active layer 2011 through a second via hole.
  • the plurality of active layers 2011, the plurality of gate electrodes 2012, the plurality of source electrodes 2013, and the plurality of drain electrodes 2014 in the display area 100 form a plurality of transistors 201. As shown in FIG. 13a.
  • a passivation film is deposited and patterned by a patterning process to form a passivation layer 251 pattern covering the first source and drain metal layer pattern, wherein the passivation layer 251 pattern includes a second column base layer 552 located on the first column base layer 551 in the transition region 300, as shown in FIG. 13a.
  • a first flat film is coated and patterned by a patterning process to form a first flat layer 252 pattern disposed on the passivation layer 251.
  • the first flat layer 252 is formed with a plurality of third via holes located in the display area 100.
  • the first flat layer 252 and the passivation layer 251 in the third via holes are removed to expose the surface of the drain electrode 2014. As shown in FIG. 13a.
  • the second source-drain metal layer pattern includes a plurality of anode connection electrodes 203 located in the display area 100, and a first isolation layer located on the second pillar base layer 552 in the transition area 300.
  • the anode connection electrode 203 is connected to the drain electrode 2014 through a third via hole, as shown in FIG. 13a.
  • the second source-drain metal layer may include a fourth metal layer 401, a fifth metal layer 402 and a sixth metal layer 403 stacked in sequence in a direction away from the substrate 10.
  • the fourth metal layer 401 and the sixth metal layer 403 may be titanium layers
  • the fifth metal layer 402 may be an aluminum layer.
  • the film layer of the anode connection electrode 203 and the film layer of the first isolation layer are the same as the film layer of the second source-drain metal layer, that is, they all include the stacked fourth metal layer 401, the fifth metal layer 402 and the sixth metal layer 403.
  • the edges of the fourth metal layer 401, the fifth metal layer 402 and the sixth metal layer 403 of the first isolation layer on the side facing the display area 100 and the side facing the hole area 200 may be roughly flush. As shown in Figure 13a.
  • the sixth metal layer 403 of the first isolation layer located in the transition region 300 is completely etched away by using a mask and an etching process, as shown in FIG. 13 b .
  • a second flat film is coated and patterned using a patterning process to form a second flat layer 26 pattern covering the second source-drain metal layer pattern.
  • the second flat layer 26 is formed with a plurality of fourth via holes V4 located in the display area 100, and the second flat layer 26 in the fourth via holes V4 is removed to expose the surface of the anode connection electrode 203;
  • the second flat layer 26 pattern includes a first cladding layer 52 located in the transition area 300, the first cladding layer 52 is disposed on the surface of the fifth metal layer 402 of the first isolation layer away from the substrate 10 and covers one side of the first isolation layer (for example, the side facing the display area 100), and the portion of the surface of the fifth metal layer 402 of the first isolation layer away from the substrate 10 and close to the other side of the first isolation layer (for example, the side facing the hole area 200) may not be covered by the first cladding layer 52. As shown in FIG. 13c.
  • the driving structure layer 20 and the film layer of the isolation column 50 are prepared.
  • Forming the light emitting structure layer 30 may include:
  • a first electrode film is deposited on the substrate 10 with the aforementioned pattern formed thereon, and the first electrode film is patterned by a patterning process to form a first electrode layer pattern, wherein the first electrode layer pattern includes a plurality of first electrodes 31 (anodes) located in the display area 100, and the first electrodes 31 are connected to the anode connection electrode 203 through the fourth via hole on the second planar layer 26, so that the first electrodes 31 are connected to the drain electrode 2014 through the anode connection electrode 203, as shown in FIG. 13d.
  • the portion of the first isolation layer of the transition region 300 that is not covered by the first cladding layer 52 will also be etched.
  • the portion of the fifth metal layer 402 of the first isolation layer of the transition region 300 that is not covered by the first cladding layer 52 can be etched away.
  • the edge of the fifth metal layer 402 of the first isolation layer can be roughly flush with the edge of the first cladding layer 52, and the edge of the fourth metal layer 401 of the first isolation layer protrudes from the edge of the fifth metal layer 402.
  • the edge of the fourth metal layer 401 of the first isolation layer made of titanium is more difficult to etch than the fifth metal layer 402 made of aluminum, after the patterning process is completed, on the side of the first isolation layer that is not covered by the first cladding layer 52, the edge of the fourth metal layer 401 of the first isolation layer can protrude from the edge of the fifth metal layer 402. As shown in FIG. 13d.
  • a pixel defining film is coated on the substrate 10 with the aforementioned pattern, and the pixel defining film is patterned by a patterning process to form a pixel defining layer 32 pattern, wherein the pixel defining layer 32 is provided with a plurality of pixel openings, and the pixel openings expose the surface of the first electrode 31 of the display area 100, as shown in FIG13e.
  • the fifth metal layer 402 of the first isolation layer of the transition region 300 can be laterally etched by using a mask and a wet etching process, so that the fifth metal layer 402 of the first isolation layer is partially retracted relative to the first cladding layer 52 on the side of the first isolation layer not covered by the first cladding layer 52.
  • the final isolation column 50 structure is formed, and the fourth metal layer 401 and the fifth metal layer 402 of the first isolation layer become the first conductive layer 511 and the second conductive layer 512 of the first isolation portion 51 of the isolation column 50, and the first column base layer 551 and the second column base layer 552 form a column base 55. As shown in FIG. 13f.
  • a spacer column film is coated on the substrate 10 with the aforementioned pattern formed thereon, and the spacer column film is patterned through a patterning process to form a spacer column layer pattern, wherein the spacer column layer pattern includes a plurality of spacer columns (not shown in the figure) located on the pixel defining layer 32 of the display area 100 .
  • a plurality of film layers of the light-emitting functional layer 33 can be sequentially formed by an evaporation process, and the light-emitting functional layer 33 can include a hole injection layer, a hole transport layer, an electron blocking layer, an organic light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer sequentially arranged in a direction away from the substrate.
  • the remaining film layers of the light-emitting functional layer 33 can all be an integrated whole-surface structure, that is, the remaining film layers of the light-emitting functional layer 33 can be common layers of sub-pixels of different colors, and these common layers can be formed in the display area 100 and the transition area 300 during evaporation. Since the isolation column 50 is provided in the transition area 300, these common layers will be disconnected at the isolation column 50, blocking the path of water and oxygen being transmitted from the hole area 200 through the light-emitting functional layer 33 to the display area 100, and water and oxygen can be prevented from corroding the light-emitting functional layer 33 of the display area 100. As shown in FIG. 2 .
  • a second electrode (cathode) layer is formed on the substrate 10 formed with the aforementioned pattern by an evaporation process.
  • the second electrode layer 34 of the sub-pixels of different colors is a common layer connected into an integrated structure.
  • the second electrode layer 34 can be formed on the display
  • the second electrode layer 34 can be disconnected at the isolation column 50, blocking the path of water and oxygen from the hole area 200 to the display area 100 through the second electrode layer 34, thereby preventing water and oxygen from corroding the second electrode layer 34 in the display area 100. As shown in FIG. 2 .
  • film layers such as an encapsulation structure layer 40 , a touch structure layer and a color filter layer may be formed in sequence on the side of the light emitting structure layer 30 away from the substrate 10 .
  • the embodiment of the present disclosure provides a method for preparing a display substrate, including preparing the isolation column of FIG. 7a .
  • the preparation process of the isolation column of FIG. 7a may include:
  • first isolation layer on the substrate of the transition region, the first isolation layer comprising a first film layer, a second film layer and a third film layer stacked in sequence in a direction away from the substrate, and edges of the first film layer, the second film layer and the third film layer are flush on a side of the first isolation layer facing the display region and a side facing the hole region;
  • a first covering layer is formed on a surface of the second film layer away from the substrate, and the first covering layer covers a side of the first isolation layer facing the display area or the hole area, and on a side of the first isolation layer not covered by the first covering layer, edges of the second film layer and the first film layer protrude from an edge of the first covering layer;
  • the second film layer is etched by an etching process, so that on the side of the first isolation layer not covered by the first covering layer, the edge of the second film layer is retracted compared to the edge of the first covering layer and the edge of the first film layer, so that the first film layer and the second film layer of the first isolation layer become the first conductive layer and the second conductive layer of the first isolation part respectively.
  • the display substrate shown in FIG. 2 and the isolation column shown in FIG. 8 are taken as examples, and the first isolation portion 51 is disposed in the same layer as the source electrode 2013 and the drain electrode 2014 of the transistor 201, and the first cladding layer 52 is disposed in the same layer as the passivation layer 251 in the fifth insulating layer 25.
  • the preparation process of the display substrate may include the following operations:
  • a first insulating layer 21, a semiconductor layer, a second insulating layer 22, a first gate metal layer, a third insulating layer 23, a second gate metal layer and a fourth insulating layer 24 are sequentially formed on the substrate 10;
  • the first column base layer 551 is formed on the third insulating layer 23 of the transition area 300, that is, the first column base layer 551 is arranged on the same layer and made of the same material as the fourth insulating layer 24.
  • the fourth insulating layer 24 of the display area 100 is provided with a plurality of first via holes V1 and a plurality of second via holes V2, the plurality of first via holes V1 expose one end of the plurality of active layers 2011, and the plurality of second via holes V2 expose the other end of the plurality of active layers 2011. As shown in FIG. 14a.
  • the first source-drain metal layer pattern includes a plurality of source electrodes 2013 and a plurality of drain electrodes 2014 located in the display area 100, and a first isolation layer located on the first pillar base layer 551 in the transition area 300.
  • the source electrode 2013 is connected to one end of the active layer 2011 through a first via hole
  • the drain electrode 2014 is connected to the other end of the active layer 2011 through a second via hole.
  • the plurality of active layers 2011, the plurality of gate electrodes 2012, and the plurality of source electrodes 2014 in the display area 100 are connected to each other.
  • the electrode 2013 and the plurality of drain electrodes 2014 form a plurality of transistors 201, as shown in FIG14b.
  • the first source-drain metal layer may include a first metal layer 301, a second metal layer 302 and a third metal layer 303 stacked in sequence in a direction away from the substrate 10.
  • the first metal layer 301 and the third metal layer 303 may be titanium layers
  • the second metal layer 302 may be an aluminum layer.
  • the source electrode 2013, the drain electrode 2014 and the first isolation layer all include a first metal layer 301 (Ti), a second metal layer 302 (Al) and a third metal layer 303 (Ti) stacked in sequence in a direction away from the substrate 10.
  • the edges of the first metal layer 301, the second metal layer 302 and the third metal layer 303 of the first isolation layer may be substantially flush. As shown in FIG. 14b.
  • a mask is used to etch away a portion of the third metal layer 303 of the first isolation layer in the transition region 300 close to the display region 100 or the hole region 200 (in the example of FIG. 14c , a portion close to the hole region 200), as shown in FIG. 14c .
  • a passivation film is deposited, and the passivation film is patterned by a patterning process to form a passivation layer 251 pattern covering the first source-drain metal layer pattern, wherein the passivation layer 251 pattern includes a first cladding layer 52 located in the transition region 300, and the first cladding layer 52 is disposed on the surface of the third metal layer 303 of the first isolation layer away from the substrate 10, and covers the side of the first isolation layer facing the display region 100, and covers the surface of the third metal layer 303 away from the substrate 10 and the surface of the third metal layer 303 located on the side of the first isolation layer facing the hole region 200 (i.e., the surface of the third metal layer 303 facing the hole region 200).
  • a portion of the surface of the second metal layer 302 of the first isolation layer away from the substrate 10 and close to the hole region 200 may not be covered by the first cladding layer 52, that is, on the side of the first isolation layer not covered by the first cladding layer 52, the edge of the second metal layer 302 of the first isolation layer may protrude from the edge of the first cladding layer 52. As shown in FIG. 14d.
  • a first flat film is coated, and the first flat film is patterned by a patterning process to form a first flat layer 252 pattern disposed on the passivation layer 251, wherein the first flat layer 252 is formed with a plurality of third via holes V3 located in the display area 100, and the first flat layer 252 and the passivation layer 251 in the third via holes V3 are removed and the surface of the drain electrode 2014 is exposed.
  • the passivation layer 251 and the first flat layer 252 as a whole can be referred to as the fifth insulating layer 25, the passivation layer 251 can be an inorganic insulating material, and the first flat layer 252 can be an organic insulating material.
  • the passivation layer 251 may not be provided, and the fifth insulating layer 25 may only include the first flat layer 252.
  • the first encapsulation layer 52 may be formed simultaneously during the process of patterning the first flat layer 252 pattern.
  • the second source-drain metal layer pattern includes a plurality of anode connection electrodes 203 located in the display area 100.
  • the anode connection electrode 203 is connected to the drain electrode 2014 through a third via hole V3, as shown in FIG. 14e.
  • the film structure and material of the second source-drain metal layer may be the same as those of the first source-drain metal layer.
  • the second source-drain metal layer may include a fourth metal layer 401, a fifth metal layer 402, and a sixth metal layer 403 stacked in sequence in a direction away from the substrate 10.
  • the fourth metal layer 401 and the sixth metal layer 403 may be titanium layers
  • the fifth metal layer 402 may be an aluminum layer.
  • the portion of the second metal layer 302 of the first isolation layer of the transition region 300 that is not covered by the first cladding layer 52 is etched away.
  • the edge of the second metal layer 302 of the first isolation layer is roughly flush with the edge of the first cladding layer 52, and the edge of the first metal layer 301 of the first isolation layer protrudes from the edge of the second metal layer 302.
  • the edge of the first metal layer 301 of the first isolation layer made of titanium is more difficult to etch than the second metal layer 302 made of aluminum, after the patterning process is completed, on the side of the first isolation layer not covered by the first covering layer 52, the edge of the first metal layer 301 of the first isolation layer protrudes beyond the edge of the second metal layer 302, as shown in FIG. 14e.
  • a second flat film is coated and patterned by a patterning process to form a second flat layer 26 pattern covering the second source and drain metal layer pattern.
  • the second flat layer 26 is formed with a plurality of first The fourth via hole V4, the second flat layer 26 in the fourth via hole V4 is removed and the surface of the anode connection electrode 203 is exposed, as shown in FIG. 14f.
  • the driving structure layer 20 and the film layer of the isolation column 50 are prepared.
  • Forming the light emitting structure layer 30 may include:
  • a first electrode film is deposited on the substrate 10 with the aforementioned pattern formed thereon, and the first electrode film is patterned by a patterning process to form a first electrode layer pattern, wherein the first electrode layer pattern includes a plurality of first electrodes 31 (anodes) located in the display area 100, and the first electrode 31 is connected to the anode connection electrode 203 through the fourth via hole V4 on the second flat layer 26, so that the first electrode 31 is connected to the drain electrode 2014 through the anode connection electrode 203, as shown in FIG. 14f.
  • a pixel defining film is coated on the substrate 10 with the aforementioned pattern, and the pixel defining film is patterned by a patterning process to form a pixel defining layer 32 pattern, wherein the pixel defining layer 32 is provided with a plurality of pixel openings, and the pixel openings expose the surface of the first electrode 31 of the display area 100, as shown in FIG. 14f.
  • the second metal layer 302 of the first isolation layer of the transition region 300 can be laterally etched by using a mask and a wet etching process, so that the second metal layer 302 of the first isolation layer is partially retracted relative to the third metal layer 303 on the side of the first isolation layer not covered by the first covering layer 52.
  • the final isolation column 50 structure is formed, and the first metal layer 301, the second metal layer 302 and the third metal layer 303 of the first isolation layer become the first conductive layer 511, the second conductive layer 512 and the third conductive layer 513 of the first isolation part 51 of the isolation column 50, and the first column base layer 551 forms a column base 55. As shown in FIG. 14g.
  • the process of Figures 14a to 14g above forms the isolation column 50 shown in Figure 8, and the first isolation part 51 is arranged in the same layer as the source electrode 2013 and the drain electrode 2014 of the transistor 201, and the first encapsulation layer 52 is arranged in the same layer as the passivation layer 251 in the fifth insulating layer 25.
  • the first isolation portion 51 is disposed in the same layer as the connecting electrode 203, and the first coating layer 52 is disposed in the same layer as the second flat layer 26.
  • the formation method of the isolation column 50 may be the same as the formation method of the isolation column 50 in FIG14a to FIG14g.
  • the connecting electrode 203 may be formed in the display area 100, and the first isolation layer may be formed in the transition area 300, wherein the second source-drain metal layer may include a fourth metal layer 401, a fifth metal layer 402, and a sixth metal layer 403 stacked in sequence in a direction away from the substrate 10.
  • the fourth metal layer 401 and the sixth metal layer 403 may be a titanium layer
  • the fifth metal layer 402 may be an aluminum layer.
  • the first isolation layer includes a fourth metal layer 401, a fifth metal layer 402, and a sixth metal layer 403 stacked in sequence in a direction away from the substrate 10.
  • the etching process is performed using a mask to remove the fourth metal layer 401, the fifth metal layer 402, and the sixth metal layer 403 located in the transition area 300.
  • a portion of the sixth metal layer 403 of the first isolation layer close to the display area 100 or the hole area 200 is etched away; then, while patterning the second flat layer 26 pattern, a first encapsulation layer 52 is formed on the sixth metal layer 403 of the first isolation layer in the transition zone 300; then, while patterning the first electrode 31, a portion of the fifth metal layer 402 of the first isolation layer not covered by the first encapsulation layer 52 is etched away, and on the side of the first isolation layer not covered by the first encapsulation layer 52, the edge of the fifth metal layer 402 of the first isolation layer can be roughly flush with the edge of the first encapsulation layer 52, and the edge of the fourth metal layer 401 protrudes from the edge of the fifth metal layer 402; then, a mask can be used to laterally etch the fifth metal layer 402 of the first isolation layer close
  • the final isolation column 50 structure is formed, and the fourth metal layer 401, the fifth metal layer 402 and the sixth metal layer 403 of the first isolation layer become the first conductive layer 511, the second conductive layer 512 and the third conductive layer 513 of the first isolation part 51 of the isolation column 50.
  • the embodiment of the present disclosure provides a method for preparing a display substrate, including preparing the isolation column shown in FIG. 8.
  • the preparation process of the isolation column shown in FIG. 8 may include:
  • first isolation layer on the substrate of the transition region, the first isolation layer comprising a first film layer, a second film layer and a third film layer stacked in sequence in a direction away from the substrate, and edges of the first film layer, the second film layer and the third film layer are flush on a side of the first isolation layer facing the display region and a side facing the hole region;
  • first coating layer on the surface of the third film layer away from the substrate, wherein the first coating layer covers the second side of the first isolation layer, and covers the surface of the third film layer away from the substrate and the surface of the third film layer located on the first side of the first isolation layer;
  • the first isolation layer is etched by an etching process, so that on a side of the first isolation layer not covered by the first covering layer (i.e., the first side of the first isolation layer), an edge of the second film layer is flush with an edge of the first covering layer, and an edge of the first film layer protrudes from or is flush with an edge of the second film layer;
  • the second film layer is etched by an etching process, so that on the side of the first isolation layer not covered by the first covering layer, the edge of the second film layer is retracted compared to the edge of the third film layer and the edge of the first film layer, so that the first film layer, the second film layer and the third film layer of the first isolation layer become the first conductive layer, the second conductive layer and the third conductive layer of the first isolation part respectively.
  • the display substrate shown in FIG. 2 and the isolation column shown in FIG. 8 are taken as examples, and the first isolation portion 51 is disposed in the same layer as the source electrode 2013 and the drain electrode 2014 of the transistor 201, and the first cladding layer 52 is disposed in the same layer as the passivation layer 251 in the fifth insulating layer 25.
  • the preparation process of the display substrate may include the following operations:
  • a first insulating layer 21, a semiconductor layer, a second insulating layer 22, a first gate metal layer, a third insulating layer 23, a second gate metal layer and a fourth insulating layer 24 are sequentially formed on the substrate 10;
  • the first column base layer 551 is formed on the third insulating layer 23 of the transition area 300, that is, the first column base layer 551 is arranged in the same layer and made of the same material as the fourth insulating layer 24.
  • the fourth insulating layer 24 of the display area 100 is provided with a plurality of first via holes V1 and a plurality of second via holes V2, the plurality of first via holes V1 expose one end of the plurality of active layers 2011, and the plurality of second via holes V2 expose the other end of the plurality of active layers 2011. As shown in FIG. 15a.
  • the first source-drain metal layer pattern includes a plurality of source electrodes 2013 and a plurality of drain electrodes 2014 located in the display area 100, and a first isolation layer located on the first pillar base layer 551 in the transition area 300.
  • the source electrode 2013 is connected to one end of the active layer 2011 through a first via hole
  • the drain electrode 2014 is connected to the other end of the active layer 2011 through a second via hole.
  • the plurality of active layers 2011, the plurality of gate electrodes 2012, the plurality of source electrodes 2013, and the plurality of drain electrodes 2014 in the display area 100 form a plurality of transistors 201. As shown in FIG. 15b .
  • the first source-drain metal layer may include a first metal layer 301, a second metal layer 302 and a third metal layer 303 stacked in sequence in a direction away from the substrate 10.
  • the first metal layer 301 and the third metal layer 303 may be titanium layers
  • the second metal layer 302 may be an aluminum layer.
  • the source electrode 2013, the drain electrode 2014 and the first isolation layer all include a first metal layer 301 (Ti), a second metal layer 302 (Al) and a third metal layer 303 (Ti) stacked in sequence in a direction away from the substrate 10.
  • the edges of the first metal layer 301, the second metal layer 302 and the third metal layer 303 of the first isolation layer may be substantially flush. As shown in FIG. 15b.
  • a passivation film is deposited and patterned by a patterning process to form a passivation layer 251 pattern covering the first source and drain metal layer pattern.
  • the passivation layer 251 pattern includes a first cladding layer 52 located in the transition region 300, a first cladding layer 53 located in the transition region 300, and a second cladding layer 54 located in the transition region 300.
  • a coating layer 52 is disposed on the surface of the third metal layer 303 of the first isolation layer away from the substrate 10, and covers the side of the first isolation layer facing the display area 100 or the hole area 200 (the side facing the display area 100 in the example of FIG.
  • a first flat film is coated, and the first flat film is patterned by a patterning process to form a first flat layer 252 pattern disposed on the passivation layer 251, wherein the first flat layer 252 is formed with a plurality of third via holes V3 located in the display area 100, and the first flat layer 252 and the passivation layer 251 in the third via holes V3 are removed and the surface of the drain electrode 2014 is exposed.
  • the passivation layer 251 and the first flat layer 252 as a whole can be referred to as the fifth insulating layer 25, the passivation layer 251 can be an inorganic insulating material, and the first flat layer 252 can be an organic insulating material.
  • the passivation layer 251 may not be provided, and the fifth insulating layer 25 may only include the first flat layer 252.
  • the first encapsulation layer 52 may be formed simultaneously during the process of patterning the first flat layer 252 pattern.
  • a second source-drain metal film is deposited and patterned by a patterning process to form a second source-drain metal layer pattern on the first planar layer 252.
  • the second source-drain metal layer pattern includes a plurality of anode connection electrodes 203 located in the display area 100.
  • the anode connection electrode 203 is connected to the drain electrode 2014 through a third via hole V3, as shown in FIG. 15d.
  • the film structure and material of the second source-drain metal layer may be the same as those of the first source-drain metal layer.
  • the second source-drain metal layer may include a fourth metal layer 401, a fifth metal layer 402, and a sixth metal layer 403 stacked in sequence in a direction away from the substrate 10.
  • the fourth metal layer 401 and the sixth metal layer 403 may be titanium layers
  • the fifth metal layer 402 may be an aluminum layer.
  • the portion of the third metal layer 303 and the second metal layer 302 of the first isolation layer of the transition region 300 that is not covered by the first cladding layer 52 is etched away.
  • the edges of the third metal layer 303 and the second metal layer 302 of the first isolation layer are substantially flush with the edges of the first cladding layer 52, and the edge of the first metal layer 301 of the first isolation layer protrudes from the edges of the third metal layer 303 and the second metal layer 302.
  • the edge of the first metal layer 301 of the first isolation layer made of titanium is more difficult to etch than the second metal layer 302 made of aluminum, after the patterning process is completed, on the side of the first isolation layer not covered by the first covering layer 52, the edge of the first metal layer 301 of the first isolation layer protrudes beyond the edge of the second metal layer 302, as shown in FIG. 15d.
  • an etching process is used to etch away a portion of the third metal layer 303 of the first isolation layer located in the transition zone 300, which is close to the first isolation layer and not covered by the first cladding layer 52.
  • a portion of the first cladding layer 52 which is close to the first isolation layer and not covered by the first cladding layer 52, will sag without the support of the third metal layer 303, and cover the surface of the third metal layer 303 located on the side of the first isolation layer that is not covered by the first cladding layer 52. As shown in FIG. 15e.
  • the second metal layer 302 of the first isolation layer of the transition region 300 can be laterally etched by using a mask and a wet etching process, so that the second metal layer 302 of the first isolation layer is retracted inwards compared to the third metal layer 303 and the first metal layer 301 on the side of the first isolation layer not covered by the first covering layer 52.
  • the final isolation column 50 structure is formed, and the first metal layer 301, the second metal layer 302 and the third metal layer 303 of the first isolation layer become the first conductive layer 511, the second conductive layer 512 and the third conductive layer 513 of the first isolation part 51 of the isolation column 50, and the first column base layer 551 forms the column base 55.
  • FIG. 15f As shown in FIG. 15f.
  • the embodiment of the present disclosure provides a method for preparing a display substrate, including preparing the isolation column shown in FIG. 8 .
  • the preparation process of the isolation column shown in FIG. 8 may include:
  • first isolation layer on the substrate of the transition region, the first isolation layer comprising a first film layer, a second film layer and a third film layer stacked in sequence in a direction away from the substrate, and edges of the first film layer, the second film layer and the third film layer are flush on a side of the first isolation layer facing the display region and a side facing the hole region;
  • a first covering layer is formed on a surface of the third film layer away from the substrate, and the first covering layer covers a side of the first isolation layer facing the display area or the hole area, and on a side of the first isolation layer not covered by the first covering layer, edges of the first film layer, the second film layer and the third film layer protrude beyond an edge of the first covering layer (i.e., a portion of a side of the surface of the third film layer away from the substrate and close to the first isolation layer not covered by the first covering layer is not covered by the first covering layer);
  • Etching the first isolation layer by using an etching process so that on the side of the first isolation layer not covered by the first covering layer, the edges of the second film layer and the third film layer are flush with the edge of the first covering layer, and the edge of the first film layer protrudes from the edges of the second film layer and the third film layer;
  • the third film layer is etched by an etching process, so that the edge of the third film layer is retracted compared to the edge of the first coating layer on the side of the first isolation layer not covered by the first coating layer, and then the part of the first coating layer not supported by the third film layer sags, and the surface of the third film layer located on the side of the first isolation layer not covered by the first coating layer is coated;
  • the second film layer is etched by an etching process, so that on the side of the first isolation layer not covered by the first covering layer, the edge of the second film layer is retracted compared to the edge of the third film layer and the edge of the first film layer, so that the first film layer, the second film layer and the third film layer of the first isolation layer become the first conductive layer, the second conductive layer and the third conductive layer of the first isolation part respectively.
  • the present disclosure also provides a display device, including the display substrate described in any of the above embodiments.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • parallel refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore includes a state where the angle is greater than 85° and less than 95°.
  • connection means a fixed connection, or a detachable connection, or an integral connection
  • installation means a direct connection, or an indirect connection through an intermediate medium, or the internal communication of two elements.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括孔区、围绕孔区的过渡区，以及围绕过渡区的显示区；过渡区设置有围绕孔区的隔离柱，隔离柱包括第一隔离部和第一包覆层；显示基板包括基底，第一隔离部包括第二导电层，第一隔离部的第一侧和第二侧分别朝向显示区和孔区；第一包覆层设于第一隔离部的远离基底一侧，并将第一隔离部的第一侧和第二侧中的其中一侧包覆，在第一隔离部的第一侧和第二侧中的另一侧，第二导电层相较于第一包覆层内缩设置；第一包覆层为绝缘材料。

Description

显示基板及其制备方法、显示装置
本申请要求于2023年3月31日提交中国专利局、申请号为202310341484.5、发明名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
随着显示技术的发展，人们对显示产品的性能要求越来越高，经得起长时间高温高湿测试、压力测试等一系列测试的显示器才能满足需求，才是合格的好产品。
有机发光二极管(OLED)显示产品由于具有自发光、广视角、高对比度、低耗电、极高反应速度等优点，逐渐成为显示领域的主流产品，但是信赖性一直是对OLED显示产品的考验。高温高湿运行测试是在上电的情况下将显示屏放在高温高湿环境中，经过672小时后观察显示屏看是否有信赖性不良。对于设计有开孔的OLED显示产品，由于孔区的边框很窄，孔区附近是信赖性薄弱的地方，为了防止外界水汽和氧气从孔区经发光功能层和阴极层(OLED发光元件包括依次叠设的阳极、发光功能层和阴极层)侵入显示区，一些技术中在孔区的边框内设置了隔离柱以隔断发光功能层和阴极层，以阻挡水氧入侵的通道，但是，显示屏在上电的情况下，在电场作用下显示屏的导电胶或者偏光片里面的导电离子会游离至显示区而造成产品信赖性失效。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板，包括孔区、围绕所述孔区的过渡区，以及围绕所述过渡区的显示区；所述过渡区设置有围绕所述孔区的隔离柱，所述隔离柱包括第一隔离部和第一包覆层；所述显示基板包括基底，所述第一隔离部包括第二导电层，所述第一隔离部的第一侧朝向所述显示区，所述第一隔离部的第二侧朝向所述孔区；所述第一包覆层设于所述第一隔离部的远离所述基底一侧，并将所述第一隔离部的第一侧和第二侧中的其中一侧包覆，在所述第一隔离部的第一侧和第二侧中的另一侧，所述第二导电层相较于所述第一包覆层内缩设置；所述第一包覆层的材料为绝缘材料。
本公开实施例还提供一种显示装置，包括所述的显示基板。
本公开实施例还提供一种制备所述显示基板的方法，包括：
在所述过渡区的基底上形成第一隔离层，所述第一隔离层包括沿远离所述基底方向依次叠设的第一膜层、第二膜层和第三膜层，在所述第一隔离层的朝向所述显示区一侧和朝向所述孔区一侧，所述第一膜层、所述第二膜层和所述第三膜层的边缘平齐；
采用刻蚀工艺将所述第三膜层完全去除；
在所述第二膜层的远离所述基底的表面上形成第一包覆层，且所述第一包覆层将所述第一隔离层的朝向所述显示区或所述孔区的一侧包覆，在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层和所述第一膜层的边缘凸出于所述第一包覆层的边缘；
采用刻蚀工艺对所述第一隔离层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层的边缘与所述第一包覆层的边缘平齐，所述第一膜层的边缘凸出于或平齐于所述第二膜层的边缘；
采用刻蚀工艺对所述第二膜层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层的边缘相较于所述第一包覆层的边缘和所述第一膜层的边缘内缩，从而使得所述第一隔离层的所述第一膜层和所述第二膜层分别成为所述第一隔离部的所述第一导电层和所述第二导电层。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一些示例性实施例的显示基板的平面结构示意图；
图2为在一些示例性实施例中图1中的A-A剖面结构示意图；
图3为一些技术中隔离柱隔断发光功能层的结构示意图；
图4为又一些技术中隔离柱隔断发光功能层的结构示意图；
图5为图4中的隔离柱的第三金属导电层上翘并与发光功能层搭接的结构示意图；
图6为图4中的发光功能层下弯并与隔离柱的第三金属导电层搭接的结构示意图；
图7a为一些示例性实施例的显示基板的隔离柱的剖面结构示意图；
图7b为另一些示例性实施例的显示基板的隔离柱的剖面结构示意图；
图7c为另一些示例性实施例的显示基板的隔离柱的剖面结构示意图；
图8为另一些示例性实施例的显示基板的隔离柱的剖面结构示意图；
图9为又一些示例性实施例的显示基板的隔离柱的剖面结构示意图；
图10为又一些示例性实施例的显示基板的隔离柱的剖面结构示意图；
图11为又一些示例性实施例的显示基板的隔离柱的剖面结构示意图；
图12a为一些示例性实施例的显示基板在形成第四绝缘层后的结构示意图；
图12b为一些示例性实施例的显示基板在形成第一源漏金属层后的结构示意图；
图12c为一些示例性实施例的显示基板在将第一隔离层的第三金属层去除后的结构示意图；
图12d为一些示例性实施例的显示基板在形成钝化层后的结构示意图；
图12e为一些示例性实施例的显示基板在形成第二源漏金属层后的结构示意图；
图12f为一些示例性实施例的显示基板在形成像素界定层后的结构示意图；
图12g为一些示例性实施例的显示基板在对第一隔离层的第二金属层进行刻蚀后的结构示意图；
图13a为另一些示例性实施例的显示基板在形成第二源漏金属层后的结构示意图；
图13b为另一些示例性实施例的显示基板在将第一隔离层的第六金属层去除后的结构示意图；
图13c为另一些示例性实施例的显示基板在形成第二平坦层后的结构示意图；
图13d为另一些示例性实施例的显示基板在形成第一电极后的结构示意图；
图13e为另一些示例性实施例的显示基板在形成像素界定层后的结构示意图；
图13f为另一些示例性实施例的显示基板在对第一隔离层的第五金属层进行刻蚀后的结构示意图；
图14a为又一些示例性实施例的显示基板在形成第四绝缘层后的结构示意图；
图14b为又一些示例性实施例的显示基板在形成第一源漏金属层后的结构示意图；
图14c为又一些示例性实施例的显示基板在对第一隔离层的第三金属层刻蚀一部分后的结构示意图；
图14d为又一些示例性实施例的显示基板在形成钝化层后的结构示意图；
图14e为又一些示例性实施例的显示基板在形成第二源漏金属层后的结构示意图；
图14f为又一些示例性实施例的显示基板在形成像素界定层后的结构示意图；
图14g为又一些示例性实施例的显示基板在对第一隔离层的第二金属层进行刻蚀后的结构示意图；
图15a为又一些示例性实施例的显示基板在形成第四绝缘层后的结构示意图；
图15b为又一些示例性实施例的显示基板在形成第一源漏金属层后的结构示意图；
图15c为又一些示例性实施例的显示基板在形成钝化层后的结构示意图；
图15d为又一些示例性实施例的显示基板在形成第二源漏金属层后的结构示意图；
图15e为又一些示例性实施例的显示基板在对第一隔离层的第三金属层刻蚀一部分后的结构示意图；
图15f为又一些示例性实施例的显示基板在对第一隔离层的第二金属层进行刻蚀后的结构示意图。
具体实施方式
本领域的普通技术人员应当理解，可以对本公开实施例的技术方案进行修改或者等同替换，而不脱离本公开实施例技术方案的精神和范围，均应涵盖在本公开的权利要求范围当中。
如图1和图2所示，图1为一些示例性实施例的显示基板的平面结构示意图，图2为在一些示例性实施例中图1中的A-A剖面结构示意图，显示基板包括孔区200、围绕孔区200的过渡区300，以及围绕过渡区300的显示区100。
示例性地，所述显示区100包括依次叠设于基底10上的驱动结构层20、发光结构层30和封装结构层40。
所述驱动结构层20包括多个像素驱动电路，像素驱动电路包括多个晶体管(T)201和存储电容(C)202。像素驱动电路可以采用3T1C、4T1C、5T1C、5T2C、6T1C或7T1C等结构，本公开对此不作限制。
所述发光结构层30包括多个发光元件，发光元件可以为OLED(有机发光二极管) 或QLED(量子点发光二极管)器件。在垂直于基底10的方向上，发光结构层30包括依次设置的第一电极层、像素界定层32、发光功能层和第二电极层34；第一电极层包括多个第一电极31，像素界定层32设于多个第一电极31的远离基底10一侧并设有多个像素开口，像素开口暴露出第一电极31，发光功能层和第二电极层34依次叠设于第一电极31的远离基底10一侧。发光元件包括第一电极31、发光功能层33和第二电极层34。发光功能层33包括有机发光层，还可以包括位于第一电极31和有机发光层之间的空穴注入层、空穴传输层和电子阻挡层中的任一个或多个膜层，以及位于第二电极层34和有机发光层之间的电子注入层、电子传输层和空穴阻挡层中的任一个或多个膜层。发光元件的第一电极31与像素驱动电路连接，发光元件在像素驱动电路的驱动下发光。
所述封装结构层40可以包括沿远离基底10方向依次叠设的第一封装层41、第二封装层42和第三封装层43。第一封装层41和第三封装层43的主要材料(膜层中成分最大的材料)为无机材料，可以包括氧化硅、氮化硅、氮氧化硅中的至少一种，第二封装层42的主要材料可以是有机材料，比如环氧树脂，这样有助于实现封装，避免水汽的侵蚀。第一封装层41和第三封装层43可以采用化学气相沉积(CVD)工艺形成，第二封装层42可以采用喷墨打印(IJP)工艺形成。
示例性地，所述过渡区300设置有隔离坝60和隔离柱50，隔离坝60和隔离柱50均围绕孔区200设置。隔离坝60的远离基底10的表面高于隔离柱50的远离基底10的表面。隔离坝60和隔离柱50的数目可以不限。在采用喷墨打印工艺形成封装结构层40的第二封装层42过程中，喷墨打印材料会发生溢流，隔离坝60可以起到防止喷墨打印材料溢流的作用。隔离柱50可以起到隔断发光功能层33以及第二电极层34的作用，以避免水氧从孔区200沿发光功能层33和第二电极层34向显示区100侵蚀，保护显示区100的发光功能层33和第二电极层34不受水氧侵蚀。
一些技术中，如图3所示，图3为一些技术中隔离柱隔断发光功能层的结构示意图，隔离柱包括沿远离基底方向依次叠设的第一金属导电层1’、第二金属导电层2’和第三金属导电层3’，在隔离柱的垂直于基底的截面上，第一金属导电层1’、第二金属导电层2’和第三金属导电层3’大致呈“工”字型，发光功能层33被隔离柱隔断后，位于隔离柱两侧(一侧朝向显示区100，另一侧朝向孔区200)的发光功能层33均搭接在第一金属导电层1’上，并通过第一金属导电层1’连接成导电通路，这样，由于在形成孔区后，显示屏的导电胶或者偏光片会在孔区边缘与发光功能层33黏连，这样，显示屏在上电的情况下，在电场作用下，所述导电胶或者偏光片里面的导电离子会通过所述的导电通路游离至显示区而造成产品信赖性失效。针对此问题，对隔离柱的结构做了优化，如图4所示，将隔离柱的一侧用绝缘层4’包覆，以阻断所述的导电通路，绝缘层4’将隔离柱的一侧(第一侧)包覆后，还会部分地位于第三金属导电层3’的远离基底的表面上，第三金属导电层3’的靠近隔离柱另一侧(第二侧)的部分没有被绝缘层4’包覆，发光功能层33在隔离柱的没有被绝缘层4’包覆的一侧的位置断开后，位于隔离柱的第一侧的发光功能层33部分地位于第三金属导电层3’的远离基底的表面上的绝缘层4’上，位于隔离柱的第二侧的发光功能层33部分地位于第一金属导电层1’上。在实际应用中发现，如图5所示，第三金属导电层3’的靠近隔离柱第二侧没有被绝缘层4’包覆的部分会上翘，并可以与位于第三金属导电层3’的远离基底的表面上的绝缘层4’上的发光功能层33搭接，或者，如图6所示，位于第三金属导电层3’的远离基底的表面上的绝缘层4’上的发光功能层33会下弯，并可以与第三金属导电层3’的靠近隔离柱第二侧没有被绝缘层4’包覆的部分搭接，从而位于隔离柱的第一侧的发光功能层33通过第三金属导电层3’、第二金属导电层2’和第一金属导电层1’与位于隔离柱的第二侧的发光功能层33仍然会连接成导电通路，这样，显示屏在上电的情况下，在电场作用下，所述导电胶或者偏光片里面的导电离子仍然会通过所述 的导电通路游离至显示区而造成产品信赖性失效。
如图1、图2、图7a和图8所示，图7a为一些示例性实施例的显示基板的隔离柱的剖面结构示意图，图8为另一些示例性实施例的显示基板的隔离柱的剖面结构示意图，本公开实施例提供一种显示基板，显示基板包括孔区200、围绕所述孔区200的过渡区300，以及围绕所述过渡区300的显示区100；所述过渡区300设置有围绕所述孔区200的隔离柱50，所述隔离柱50包括第一隔离部51和第一包覆层52；所述显示基板包括基底10，所述第一隔离部51包括第二导电层512，所述第一隔离部51的第一侧朝向所述显示区100，所述第一隔离部51的第二侧朝向所述孔区200；所述第一包覆层52设于所述第一隔离部51的远离所述基底10一侧，并将所述第一隔离部51的第一侧和第二侧中的其中一侧包覆，在所述第一隔离部51的第一侧和第二侧中的另一侧，所述第二导电层512相较于所述第一包覆层52内缩设置；所述第一包覆层52的材料为绝缘材料。
本公开实施例的显示基板，通过设置绝缘材料的第一包覆层52，并将所述第一隔离部51的第一侧和第二侧中的其中一侧包覆，在所述第一隔离部51的第一侧和第二侧中的另一侧，所述第二导电层512相较于所述第一包覆层52内缩设置(即所述第一包覆层52相较于所述第二导电层512凸出设置)，这样，显示基板的发光功能层33可以在第一隔离部51的第一侧和第二侧中未被第一包覆层52包覆的一侧断开，当发光功能层33在隔离柱50处断开后，位于第一包覆层52上的发光功能层33不会与第二导电层512搭接，则，位于隔离柱50朝向显示区100一侧的发光功能层33与位于隔离柱50朝向孔区200一侧的发光功能层33不会通过具有导电功能的第一隔离部51连接成导电通路，从而可以避免一些技术中显示屏在上电的情况下，在电场作用下显示屏的导电胶或者偏光片里面的导电离子通过所述的导电通路游离至显示区100而造成产品信赖性失效的问题。
在一些示例性实施例中，如图7a所示，所述第一隔离部51还包括设于所述第二导电层512的靠近所述基底10一侧的第一导电层511，所述第一包覆层52设于所述第二导电层512的远离所述基底10的表面上，并将所述第一隔离部51的第一侧和第二侧中的其中一侧包覆，在所述第一隔离部51的第一侧和第二侧中的另一侧，所述第二导电层512还相较于所述第一导电层511内缩设置。本实施例中，所述第一隔离部51可以仅包括第一导电层511和第二导电层512。
本实施例的一些示例中，所述第二导电层512相较于所述第一包覆层52可以内缩大约0.35微米至0.4微米，这样有助于隔离柱50将发光功能层33隔断，且当发光功能层33在隔离柱50处断开后，位于第一包覆层52上的发光功能层33不会在所述第一隔离部51的第一侧和第二侧中的另一侧与第二导电层512搭接。
本实施例的一些示例中，如图7b所示，图7b为另一些示例性实施例的显示基板的隔离柱的剖面结构示意图，在所述第一隔离部51的第一侧和第二侧中的另一侧(未被第一包覆层52包覆的一侧)，所述第一包覆层52的靠近边缘的部分相较于第一包覆层52的其余部分厚度变小，且所述第一包覆层52的靠近边缘的部分可以具有大约20度至45度的坡度角θ。
在一些示例性实施例中，如图8所示，所述第一隔离部51还可以包括设于所述第二导电层512的远离所述基底10一侧的第三导电层513，所述第一包覆层52设于所述第三导电层513的远离所述基底10的表面上，并将所述第一隔离部51的第一侧和第二侧中的其中一侧包覆；在所述第一隔离部51的第一侧和第二侧中的另一侧，所述第二导电层512还相较于所述第三导电层513内缩设置。
本实施例的一些示例中，如图8所示，所述第一包覆层52还将所述第三导电层513 的位于所述第一隔离部51的第一侧和第二侧中的另一侧(未被第一包覆层52包覆的一侧)的表面包覆，所述第三导电层513在所述基底10上的正投影落入所述第一包覆层52在所述基底10上的正投影内。
本实施例中，由于所述第一包覆层52还将所述第三导电层513的位于所述第一隔离部51的第一侧和第二侧中的另一侧的表面包覆，这样，当发光功能层33在隔离柱50处断开后，位于第一包覆层52上的发光功能层33不会在所述第一隔离部51的第一侧和第二侧中的另一侧与第三导电层513搭接，则，位于隔离柱50朝向显示区100一侧的发光功能层33与位于隔离柱50朝向孔区200一侧的发光功能层33不会通过具有导电功能的第一隔离部51连接成导电通路，从而可以避免一些技术中显示屏在上电的情况下，在电场作用下显示屏的导电胶或者偏光片里面的导电离子通过所述的导电通路游离至显示区100而造成产品信赖性失效的问题。
本实施例的一些示例中，所述第二导电层512相较于所述第一包覆层52可以内缩大约0.35微米至0.4微米。
本实施例的一些示例中，在所述第一隔离部51的第一侧和第二侧中的另一侧，所述第一包覆层52的靠近边缘的部分可以具有大约50度至75度的坡度，可以参考图7b中的坡度角θ。
在一些示例性实施例中，如图9所示，图9为又一些示例性实施例的显示基板的隔离柱的剖面结构示意图，所述隔离柱还可以包括第二隔离部53，所述第二隔离部53设于所述第一隔离部51的朝向所述基底10一侧，所述第二隔离部53包括沿远离所述基底10方向依次叠设的第四导电层531、第五导电层532和第六导电层533；所述第二隔离部53的第一侧朝向所述显示区100，所述第二隔离部53的第二侧朝向所述孔区200；所述第一包覆层52还将所述第二隔离部53的第一侧和第二侧中的其中一侧包覆，在所述第二隔离部53的第一侧和第二侧中的另一侧，所述第五导电层532相较于所述第四导电层531和所述第六导电层533内缩设置。在其他实施方式中，所述第二隔离部53可以仅包括沿远离所述基底10方向依次叠设的第四导电层531和第五导电层532，可以不设置第六导电层533。
本实施例中，通过设置所述第二隔离部53，可以使发光功能层33在第二隔离部53的第一侧和第二侧中未被第一包覆层52包覆的一侧断开，可以提高隔离柱对发光功能层33的隔断效果。
本实施例的一些示例中，如图9所示，所述第一隔离部51的第一侧和第二侧中的被所述第一包覆层52包覆的一侧，与所述第二隔离部53的第一侧和第二侧中的被所述第一包覆层52包覆的一侧位于所述隔离柱的同一侧，比如可以均位于所述隔离柱的朝向所述显示区100的一侧，或者可以均位于所述隔离柱的朝向所述孔区200的一侧。
本实施例的一些示例中，如图9所示，所述第一导电层511可以设于所述第六导电层533的远离所述基底10的表面上。所述第一导电层511和所述第六导电层533的材料可以相同或不同。
在一些示例性实施例中，如图9和图10所示，图10为又一些示例性实施例的显示基板的隔离柱的剖面结构示意图，所述隔离柱包括第一隔离部51、第一包覆层52和第二隔离部53。图9的示例中，第一隔离部51的结构可以与图7a的第一隔离部51的结构相同，第一隔离部51包括沿远离所述基底10方向依次叠设的第一导电层511和第二导电层512，所述第一包覆层52设于所述第二导电层512的远离所述基底10的表面上，并将所述第一隔离部51和第二隔离部53的朝向显示区100或孔区200的一侧包覆，在所述第一隔离部 51的未被第一包覆层52包覆一侧，所述第二导电层512相较于所述第一导电层511和所述第一包覆层52内缩设置。图10的示例中，第一隔离部51的结构可以与图8的第一隔离部51的结构相同，所述第一隔离部51包括沿远离所述基底10方向依次叠设的第一导电层511、第二导电层512和第三导电层513，所述第一包覆层52设于第三导电层513的远离基底10的表面上，并将所述第一隔离部51和第二隔离部53的朝向显示区100或孔区200的一侧包覆，以及将第三导电层513的位于所述第一隔离部51的未被第一包覆层52包覆一侧的表面包覆；在所述第一隔离部51的未被第一包覆层52包覆一侧，所述第二导电层512相较于第一导电层511和所述第三导电层513内缩设置。
在一些示例性实施例中，如图11所示，图11为又一些示例性实施例的显示基板的隔离柱的剖面结构示意图，所述隔离柱50包括第一隔离部51和第一包覆层52；所述第一隔离部51包括沿远离所述基底10方向依次叠设的第一导电层511和第二导电层512，所述第一隔离部51的第一侧朝向所述显示区100，所述第一隔离部51的第二侧朝向所述孔区200；所述第一包覆层52设于所述第一隔离部51的远离所述基底10一侧，并将所述第一隔离部51的第一侧和第二侧中的其中一侧包覆，在所述第一隔离部51的第一侧和第二侧中的另一侧，所述第二导电层512相较于所述第一导电层511和所述第一包覆层52内缩设置；所述第一包覆层52的材料为绝缘材料；
所述隔离柱50还可以包括第二隔离部53和第二包覆层54；所述第二隔离部53设于所述第一隔离部51的朝向所述基底10一侧，所述第二隔离部53的第一侧朝向所述显示区100，所述第二隔离部53的第二侧朝向所述孔区200；所述第二包覆层54设于所述第二隔离部53和所述第一隔离部51之间，并将所述第二隔离部53的第一侧和第二侧中的其中一侧包覆；所述第二隔离部53的材料为导电材料，所述第二包覆层54的材料为绝缘材料。
本实施例的一些示例中，如图11所示，所述第二隔离部53可以包括沿远离所述基底10方向依次叠设的第四导电层531、第五导电层532和第六导电层533；在所述第二隔离部53的第一侧和第二侧中的另一侧(未被所述第二包覆层54包覆的一侧)，所述第五导电层532相较于所述第四导电层531和所述第六导电层533内缩设置。
本实施例的一些示例中，如图11所示，所述第一隔离部51的第一侧和第二侧中的被所述第一包覆层52包覆的一侧，与所述第二隔离部53的第一侧和第二侧中的被所述第二包覆层54包覆的一侧可以位于所述隔离柱50的不同侧。比如，所述第一隔离部51的第一侧和第二侧中的被所述第一包覆层52包覆的一侧位于所述隔离柱50的朝向所述显示区100的一侧，所述第二隔离部53的第一侧和第二侧中的被所述第二包覆层54包覆的一侧位于所述隔离柱50的朝向所述孔区200的一侧；或者，所述第一隔离部51的第一侧和第二侧中的被所述第一包覆层52包覆的一侧位于所述隔离柱50的朝向所述孔区200的一侧，所述第二隔离部53的第一侧和第二侧中的被所述第二包覆层54包覆的一侧位于所述隔离柱50的朝向所述显示区100的一侧。在其他实施方式中，所述第一隔离部51的第一侧和第二侧中的被所述第一包覆层52包覆的一侧，与所述第二隔离部53的第一侧和第二侧中的被所述第二包覆层54包覆的一侧可以位于所述隔离柱50的同一侧。比如可以均位于所述隔离柱50的朝向所述显示区100的一侧，或者可以均位于所述隔离柱50的朝向所述孔区200的一侧。
在一些示例性实施例中，所述隔离柱的隔离部的数量可以为一个或多个，比如图7a和图8的示例中隔离部可以仅为一个(即第一隔离部)，图9、图10和图11的示例中隔离部可以为两个(即第一隔离部和第二隔离部)，在其他实施方式中，隔离部的数量可以为三个或四个等。本公开实施例对隔离柱的隔离部的数量不做限制。
在一些示例性实施例中，如图7a和图8所示，所述隔离柱50还可以包括设于所述第一隔离部51的朝向所述基底10一侧的柱基55，所述柱基55可以包括一个或多个膜层。
本实施例的一些示例中，所述柱基55可以包括一个无机绝缘层或叠设的多个无机绝缘层。或者，所述柱基55可以包括至少一个无机绝缘层和至少一个金属层，所述金属层可以被所述无机绝缘层包覆。
示例性地，如图7c所示，图7c为另一些示例性实施例的显示基板的隔离柱的剖面结构示意图，所述柱基55可以包括沿远离所述基底方向依次叠设的第七金属层555、第一无机绝缘层553、第八金属层556和第二无机绝缘层554，第一无机绝缘层553将第七金属层555包覆，第二无机绝缘层554将第八金属层556包覆。所述第一隔离部51可以设置在第二无机绝缘层554的远离所述基底的表面上。
本实施例的一些示例中，如图7a和图8所示，所述隔离柱50不包括所述第二隔离部53的情况下，所述第一隔离部51的所述第一导电层511可以设置在所述柱基55的远离所述基底10的表面上。
本实施例的一些示例中，如图9和图10所示，所述隔离柱50包括所述第二隔离部53的情况下，所述柱基55设于所述第二隔离部53的朝向所述基底10一侧，所述第二隔离部53的所述第四导电层531可以设置在所述柱基55的远离所述基底10的表面上。
在一些示例性实施例中，如图2所示，所述显示区100包括依次叠设于所述基底10上的驱动结构层20和发光结构层30，所述驱动结构层20包括像素驱动电路，所述像素驱动电路包括多个晶体管201和存储电容202，所述发光结构层30包括多个发光元件，所述发光元件包括沿远离所述基底10方向依次叠设的第一电极31、发光功能层33和第二电极层34。
在垂直于所述基底10的方向上，所述驱动结构层20可以包括沿远离所述基底10方向依次设置的第一源漏金属层、第五绝缘层25、第二源漏金属层和第二平坦层26；所述第一源漏金属层包括至少一个所述晶体管201的源电极2013和漏电极2014，所述第二源漏金属层包括与所述晶体管201的源电极2013或漏电极2014连接的连接电极203，所述连接电极203还与所述第一电极31连接。
本实施例的一些示例中，所述第一源漏金属层可以包括叠设的多个金属层，所述第一隔离部51与所述晶体管201的源电极2013和漏电极2014同层设置。所述第一隔离部51的膜层与所述晶体管201的源电极2013和漏电极2014的膜层可以相同，或者，所述第一隔离部51的膜层数量可以少于所述晶体管201的源电极2013和漏电极2014的膜层数量。
本文中，“A和B同层设置”是指，A的膜层和B的膜层来自于同一个薄膜，该薄膜可以是单层结构或多层复合结构，A的膜层和B的膜层可以相同或不同。“A和B同层设置”可以理解为，同一个薄膜经过同一次图案化工艺同时形成A和B，或者，同一个薄膜经过同一次图案化工艺同时形成A’和B’，对A’进行进一步地加工处理(比如刻蚀等)后得到A，对B’进行进一步地加工处理(比如刻蚀等)后得到B。
示例性地，所述第一源漏金属层可以包括沿远离基底10方向依次叠设的第一金属层301、第二金属层302和第三金属层303，比如，第一金属层301和第三金属层303可以为钛层，第二金属层302可以为铝层。所述晶体管201的源电极2013和漏电极2014的膜层与所述第一源漏金属层的膜层相同，即均包括叠设的第一金属层301、第二金属层302和第三金属层303。在一些示例中，如图7a所示，所述第一隔离部51包括两个膜层，即所述第一导电层511和所述第二导电层512，其中，第一导电层511与所述第一金属层301材质相同，第二导电层512与所述第二金属层302材质相同。在另一些示例中，如图8 所示，所述第一隔离部51包括三个膜层，即所述第一导电层511、所述第二导电层512和所述第三导电层513，其中，第一导电层511与所述第一金属层301材质相同，第二导电层512与所述第二金属层302材质相同，第三导电层513与所述第三金属层303材质相同。
所述第一包覆层52可以与所述第五绝缘层25同层设置，所述第五绝缘层25可以为单层结构或者多层结构。所述第五绝缘层25为单层结构的情况下，所述第一包覆层52的材质与所述第五绝缘层25的材质相同；所述第五绝缘层25为多层结构的情况下，所述第一包覆层52的材质与所述第五绝缘层25中的任意一个膜层的材质相同，或者，所述第一包覆层52可以包括多个膜层，所述第一包覆层52的多个膜层的材质与所述第五绝缘层25中的多个膜层的材质相同。比如，所述第五绝缘层25可以包括沿远离基底10方向依次叠设的钝化层251和第一平坦层252，所述第一包覆层52的材质可以与钝化层251或第一平坦层252的材质相同，或者，所述第一包覆层52可以包括两个膜层，该两个膜层的材质分别与所述钝化层251和第一平坦层252的材质相同。又比如，所述第五绝缘层25可以仅包括第一平坦层252，则所述第一包覆层52的材质与第一平坦层252的材质相同。
本实施例的一些示例中，所述第二源漏金属层可以包括叠设的多个金属层，所述第一隔离部51与所述连接电极203同层设置。所述第一隔离部51的膜层与所述连接电极203的膜层可以相同，或者，所述第一隔离部51的膜层数量可以少于所述连接电极203的膜层数量。
示例性地，所述第二源漏金属层可以包括沿远离基底10方向依次叠设的第四金属层401、第五金属层402和第六金属层403，比如，第四金属层401和第六金属层403可以为钛层，第五金属层402可以为铝层。所述连接电极203的膜层与所述第二源漏金属层的膜层相同，即均包括叠设的第四金属层401、第五金属层402和第六金属层403。在一些示例中，如图7a所示，所述第一隔离部51包括两个膜层，即所述第一导电层511和所述第二导电层512，其中，第一导电层511与所述第四金属层401材质相同，第二导电层512与所述第五金属层402材质相同。在另一些示例中，如图8所示，所述第一隔离部51包括三个膜层，即所述第一导电层511、所述第二导电层512和所述第三导电层513，其中，第一导电层511与所述第四金属层401材质相同，第二导电层512与所述第五金属层402材质相同，第三导电层513与所述第六金属层403材质相同。
所述第一包覆层52可以与所述第二平坦层26同层设置且材质相同。
本实施例的一些示例中，如图9和图10所示，所述隔离柱50包括第一隔离部51、第一包覆层52和第二隔离部53。所述第一隔离部51可以与所述连接电极203同层设置，所述第一包覆层52可以与所述第二平坦层26同层设置且材质相同，所述第二隔离部53可以与所述晶体管201的源电极2013和漏电极2014同层设置。
示例性地，所述第一源漏金属层可以包括沿远离基底10方向依次叠设的第一金属层301、第二金属层302和第三金属层303，比如，第一金属层301和第三金属层303可以为钛层，第二金属层302可以为铝层。所述晶体管201的源电极2013和漏电极2014的膜层与所述第一源漏金属层的膜层相同，即均包括叠设的第一金属层301、第二金属层302和第三金属层303。所述第二隔离部53包括沿远离所述基底10方向依次叠设的第四导电层531、第五导电层532和第六导电层533，所述第四导电层531的材质与所述第一金属层301的材质相同，所述第五导电层532的材质与所述第二金属层302的材质相同，所述第六导电层533的材质与所述第三金属层303的材质相同。
所述第二源漏金属层可以包括沿远离基底10方向依次叠设的第四金属层401、第五金属层402和第六金属层403，比如，第四金属层401和第六金属层403可以为钛层，第五金属层402可以为铝层。所述连接电极203的膜层与所述第二源漏金属层的膜层相同，即均包括叠设的第四金属层401、第五金属层402和第六金属层403。在一些示例中，如图9所示，所述第一隔离部51包括两个膜层，即所述第一导电层511和所述第二导电层512，其中，第一导电层511与所述第四金属层401材质相同，第二导电层512与所述第五金属层402材质相同。在另一些示例中，如图10所示，所述第一隔离部51包括三个膜层，即所述第一导电层511、所述第二导电层512和所述第三导电层513，其中，第一导电层511与所述第四金属层401材质相同，第二导电层512与所述第五金属层402材质相同，第三导电层513与所述第六金属层403材质相同。
本实施例的一些示例中，如图11所示，所述隔离柱50包括第一隔离部51和第一包覆层52，以及第二隔离部53和第二包覆层54。所述第一隔离部51可以与所述连接电极203同层设置，所述第一包覆层52可以与所述第二平坦层26同层设置且材质相同，所述第二隔离部53可以与所述晶体管201的源电极2013和漏电极2014同层设置，所述第二包覆层54可以与所述第五绝缘层25同层设置。本示例中，第一隔离部51和第二隔离部53的膜层结构可以参考图10的示例，所述第二包覆层54的膜层结构可以参考前文示例中在第一包覆层52与所述第五绝缘层25同层设置的情况下第一包覆层52的膜层结构。
本实施例的一些示例中，如图2所示，所述驱动结构层20还可以包括设于所述第一源漏金属层的朝向所述基底10一侧的半导体层、第一栅金属层和第二栅金属层，所述半导体层包括所述晶体管201的有源层2011，所述第一栅金属层可以包括所述晶体管201的栅电极2012和所述存储电容202的一个极板，所述第二栅金属层可以包括所述存储电容202的另一个极板。
所述柱基55可以包括一个无机绝缘层或叠设的多个无机绝缘层。或者，所述柱基55可以包括至少一个无机绝缘层和至少一个金属层，所述金属层可以被所述无机绝缘层包覆。示例性地，所述柱基55的其中一个无机绝缘层可以与位于所述第一源漏金属层和所述第二栅金属层之间的绝缘层同层设置且材料相同。所述柱基55中的金属层可以与所述第一栅金属层或/和所述第二栅金属层同层设置且材料相同。示例性地，如图7c所示，所述柱基55可以包括沿远离所述基底方向依次叠设的第七金属层555、第一无机绝缘层553、第八金属层556和第二无机绝缘层554，第一无机绝缘层553将第七金属层555包覆，第二无机绝缘层554将第八金属层556包覆。所述第七金属层555可以与所述第一栅金属层同层设置且材料相同，所述第八金属层556可以与所述第二栅金属层同层设置且材料相同。
在一些示例性实施例中，如图2所示，所述驱动结构层20包括依次叠设于基底10上的第一绝缘层21、半导体层、第二绝缘层22、第一栅金属层、第三绝缘层23、第二栅金属层、第四绝缘层24、第一源漏金属层、第五绝缘层25、第二源漏金属层和第六绝缘层；其中，第五绝缘层25可以包括沿远离基底10方向依次叠设的钝化层251和第一平坦层252，或者，第五绝缘层25可以仅包括第一平坦层252；第六绝缘层为第二平坦层26。所述第一电极31可以设置在第二平坦层26的远离基底10的表面上。
示例性地，所述基底10可以是柔性基底10，比如可以包括聚酰亚胺(PI)材料。或者，基底10可以为刚性基底10，比如玻璃等。
示例性地，所述第一绝缘层21、第二绝缘层22、第三绝缘层23、第四绝缘层24和钝化层251可以为无机绝缘层，比如可以采用氧化硅(SiOX)、氮化硅(SiNX)和氮氧化硅(SiOXNY)中的任意一种或更多种，可以是单层或多层结构。第一绝缘层21可称为 缓冲(Buffer)层，用于提高基底10的抗水氧能力，第二绝缘层22和第三绝缘层23可称为栅绝缘(GI)层，第四绝缘层24可称为层间绝缘(ILD)层。第一平坦层252和第二平坦层26为有机绝缘层，可以采用有机绝缘材料，比如树脂等。第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构或者多层结构，如Ti/Al/Ti叠设等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等材料，即本公开适用于基于氧化物技术、硅技术以及有机物技术制造的晶体管201。
在一些示例性实施例中，如图2所示，图2中示意了隔离柱50a、隔离柱50b、隔离柱50c和隔离柱50d四个隔离柱。所述隔离柱50的数目可以不限，比如可以设置为一个或多个，所述隔离柱50可以设置在所述隔离坝60的朝向显示区100的一侧或/和朝向孔区200的一侧。所述隔离柱50的数目为多个的情况下，多个所述隔离柱50的结构可以相同或不同，多个所述隔离柱50可以为图7a、图8、图9、图10、图11示例的隔离柱50中的任一种或多种。多个所述隔离柱50中第一隔离部的被第一包覆层包覆的一侧可以均朝向显示区或孔区，或者，至少一个所述隔离柱50中第一隔离部的被第一包覆层包覆的一侧朝向孔区，至少一个所述隔离柱50中第一隔离部的被第一包覆层包覆的一侧朝向显示区。
在一些示例性实施例中，如图2所示，所述隔离坝60可以包括沿远离所述基底10方向依次叠设的第一坝层、第二坝层和第三坝层，所述第一坝层可以与所述第一平坦层252同层设置且材料相同，所述第二坝层可以与所述第二平坦层26同层设置且材料相同，所述第三坝层可以与所述像素界定层32同层设置且材料相同。所述隔离坝60还可以包括设于所述第一坝层的朝向所述基底10一侧的坝基，所述坝基可以包括至少一个无机绝缘层。
下面通过显示基板的制备过程进行示例性说明显示基板的结构。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例性实施例中，以图2示例的显示基板和图7a示例的隔离柱为例，且所述第一隔离部51与所述晶体管201的源电极2013和漏电极2014同层设置，第一包覆层52与第五绝缘层25中的钝化层251同层设置。示例性地，显示基板的制备过程可以包括如下操作：
(1)形成驱动结构层20，以及隔离柱50的膜层。
在基底10上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进 行图案化，形成覆盖基底10的第一绝缘层21，以及设置在第一绝缘层21上的半导体层图案，半导体层图案包括位于显示区100的多个有源层2011。本次图案化工艺后，过渡区300包括设于基底10上的第一绝缘层21。如图12a所示。
随后，依次沉积第二绝缘薄膜和第一栅金属薄膜，通过图案化工艺对第一栅金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层22，以及设置在第二绝缘层22上的第一栅金属层图案，第一栅金属层图案包括位于显示区100的多个栅电极2012和多个第一极板2021。本次图案化工艺后，过渡区300包括依次叠设于基底10上的第一绝缘层21和第二绝缘层22。如图12a所示。
随后，依次沉积第三绝缘薄膜和第二栅金属薄膜，通过图案化工艺对第二栅金属薄膜进行图案化，形成覆盖第一栅金属层的第三绝缘层23，以及设置在第三绝缘层23上的第二栅金属层图案，第二栅金属层图案包括位于显示区100的多个第二极板2022。其中，多个第二极板2022与多个第一极板2021相对设置并形成多个存储电容202。本次图案化工艺后，过渡区300包括依次叠设于基底10上的第一绝缘层21、第二绝缘层22和第三绝缘层23。如图12a所示。
随后，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二栅金属层图案的第四绝缘层24图案，第四绝缘层24图案包括位于过渡区300的第一柱基层551，显示区100的第四绝缘层24设有多个第一过孔V1和多个第二过孔V2，多个第一过孔V1暴露出多个有源层2011的一端，多个第二过孔V2暴露出多个有源层2011的另一端。本次图案化工艺后，过渡区300包括依次叠设于基底10上的第一绝缘层21、第二绝缘层22、第三绝缘层23，以及设于第三绝缘层23上的第一柱基层551。如图12a所示。
随后，沉积第一源漏金属薄膜，通过图案化工艺对第一源漏金属薄膜进行图案化，在第四绝缘层24上形成第一源漏金属层图案，第一源漏金属层图案包括位于显示区100的多个源电极2013和多个漏电极2014，以及位于过渡区300的第一柱基层551上的第一隔离层。源电极2013通过第一过孔V1与有源层2011的一端连接，漏电极2014通过第二过孔V2与有源层2011的另一端连接，显示区100的多个有源层2011、多个栅电极2012、多个源电极2013和多个漏电极2014形成多个晶体管201。如图12b所示。
其中，所述第一源漏金属层可以包括沿远离基底10方向依次叠设的第一金属层301、第二金属层302和第三金属层303，比如，第一金属层301和第三金属层303可以为钛层，第二金属层302可以为铝层。则，源电极2013、漏电极2014和第一隔离层均包括沿远离基底10方向依次叠设的第一金属层301(Ti)、第二金属层302(Al)和第三金属层303(Ti)。第一隔离层的朝向显示区100的一侧以及朝向孔区200的一侧，第一隔离层的第一金属层301、第二金属层302和第三金属层303的边缘可以大致平齐。如图12b所示。
本文中，“A和B的边缘平齐”是指，A和B的边缘在工艺误差范围内的平齐，并非是绝对的平齐。
随后，利用掩模版，采用刻蚀工艺将位于过渡区300的第一隔离层的第三金属层303完全刻蚀掉。如图12c所示。
随后，沉积钝化薄膜，通过图案化工艺对钝化薄膜进行图案化，形成覆盖第一源漏金属层图案的钝化层251图案，钝化层251图案包括位于过渡区300的第一包覆层52，第一包覆层52设置在第一隔离层的第二金属层302的远离基底10的表面上并将第一隔离层的一侧(比如朝向显示区100的一侧)包覆，第一隔离层的第二金属层302的远离基底 10的表面的靠近第一隔离层另一侧(比如朝向孔区200的一侧)的部分可以不被第一包覆层52覆盖。如图12d所示。
随后，涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成设置在钝化层251上的第一平坦层252图案，第一平坦层252形成有位于显示区100的多个第三过孔V3，第三过孔V3内的第一平坦层252和钝化层251被去除并暴露出漏电极2014的表面。如图12e所示。其中，本示例中，钝化层251和第一平坦层252整体可以称为第五绝缘层25，钝化层251可以为无机绝缘材料，第一平坦层252可以为有机绝缘材料。在其他示例中，可以不设置钝化层251，第五绝缘层25可以仅包括第一平坦层252，此种情况下，可以在图案化形成第一平坦层252图案过程中，同时形成第一包覆层52。
随后，沉积第二源漏金属薄膜，采用图案化工艺对第二源漏金属薄膜进行图案化，在第一平坦层252上形成第二源漏金属层图案，第二源漏金属层图案包括位于显示区100的多个阳极连接电极203，阳极连接电极203通过第三过孔V3与漏电极2014连接。如图12e所示。
其中，第二源漏金属层的膜层结构及材料可以与第一源漏金属层的膜层结构及材料相同，比如，所述第二源漏金属层可以包括沿远离基底10方向依次叠设的第四金属层401、第五金属层402和第六金属层403，比如，第四金属层401和第六金属层403可以为钛层，第五金属层402可以为铝层。由此，在对第二源漏金属薄膜进行图案化过程中，过渡区300的第一隔离层的未被第一包覆层52覆盖的部分也会被刻蚀到，本次图案化工艺结束后，过渡区300的第一隔离层的第二金属层302的未被第一包覆层52覆盖的部分被刻蚀掉，在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第二金属层302的边缘与第一包覆层52的边缘大致平齐，第一隔离层的第一金属层301的边缘凸出于第二金属层302的边缘。由于第一隔离层的钛材质的第一金属层301相较于铝材质的第二金属层302难刻蚀，因此，本次图案化工艺结束后，在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第一金属层301的边缘凸出于第二金属层302的边缘。如图12e所示。
随后，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第二源漏金属层图案的第二平坦层26图案，第二平坦层26形成有位于显示区100的多个第四过孔V4，第四过孔V4内的第二平坦层26被去除并暴露出阳极连接电极203的表面。如图12f所示。
至此，制备完成驱动结构层20，以及隔离柱50的膜层。
(2)形成发光结构层30。在示例性实施方式中，形成发光结构层30可以包括：
在形成前述图案的基底10上沉积第一电极薄膜，通过图案化工艺对第一电极薄膜进行图案化，形成第一电极层图案，第一电极层图案包括位于显示区100的多个第一电极31(阳极)，第一电极31通过第二平坦层26上的第四过孔V4与阳极连接电极203连接，从而第一电极31通过阳极连接电极203与漏电极2014连接。如图12f所示。
随后，在形成前述图案的基底10上涂覆像素界定薄膜，通过图案化工艺对像素界定薄膜进行图案化，形成像素界定层32图案，像素界定层32设置有多个像素开口，像素开口暴露出显示区100的第一电极31的表面。如图12f所示。
随后，可以利用掩模版，采用湿法刻蚀工艺，对过渡区300的第一隔离层的第二金属层302进行横向刻蚀，使第一隔离层的第二金属层302在第一隔离层的未被第一包覆层52包覆一侧相较于第一包覆层52内缩一部分。至此，形成最终的隔离柱50结构，第一隔离层的第一金属层301和第二金属层302即成为了隔离柱50的第一隔离部51的第一导 电层511和第二导电层512，第一柱基层551形成了柱基55。如图12g所示。
随后，在形成前述图案的基底10上，涂覆隔垫柱薄膜，通过图案化工艺对隔垫柱薄膜进行图案化，形成隔垫柱层图案，隔垫柱层图案包括位于显示区100的像素界定层32上的多个隔垫柱(图中未示出)。
随后，在形成前述图案的基底10上，可以通过蒸镀工艺依次形成发光功能层33的多个膜层，发光功能层33可以包括沿远离基底方向依次设置的空穴注入层、空穴传输层、电子阻挡层、有机发光层、空穴阻挡层、电子传输层和电子注入层。除有机发光层外，发光功能层33的其余膜层均可以为一体的整面结构，即，发光功能层33的其余膜层可以为不同颜色子像素的共通层，这些共通层在蒸镀的时候可以形成在显示区100和过渡区300。由于在过渡区300设置了隔离柱50，这些共通层会在隔离柱50处断开，阻断了水氧由孔区200经发光功能层33向显示区100传输的路径，可避免水氧侵蚀显示区100的发光功能层33。如图2所示。
随后，在形成前述图案的基底10上，通过蒸镀工艺形成第二电极(阴极)层，不同颜色子像素的第二电极层34是连接为一体结构的共通层，第二电极层34可以形成在显示区100和过渡区300。第二电极层34可以在隔离柱50处断开，阻断了水氧由孔区200经第二电极层34向显示区100传输的路径，可避免水氧侵蚀显示区100的第二电极层34。如图2所示。
至此，制备完成发光结构层30。
(3)形成封装结构层40。在示例性实施方式中，形成封装结构层40可以包括：
在形成前述图案的基底10上，先利用开放式掩模版采用沉积方式沉积第一封装薄膜，形成位于显示区100和过渡区300的第一封装层41。随后，利用开放式掩模版采用喷墨打印工艺打印第二封装材料，形成位于显示区100和过渡区300的第二封装层42，其中，过渡区300的隔离坝60可以阻挡喷墨打印过程中墨水溢流。随后，利用开放式掩模版采用沉积方式沉积第三封装薄膜，形成位于显示区100和过渡区300的第三封装层43。第一封装层41和第三封装层43的材料可以采用无机材料，第二封装层42的材料可以采用有机材料。如图2所示。
随后，可以在封装结构层40的远离基底10一侧依次形成触控结构层和彩膜层等膜层。
在另一些示例性实施例中，以图2示例的显示基板和图7a示例的隔离柱为例，且所述第一隔离部51与所述连接电极203同层设置，第一包覆层52与第二平坦层26同层设置。示例性地，显示基板的制备过程可以包括如下操作：
(1)形成驱动结构层20，以及隔离柱50的膜层。
在基底10上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底10的第一绝缘层21，以及设置在第一绝缘层21上的半导体层图案，半导体层图案包括位于显示区100的多个有源层2011。本次图案化工艺后，过渡区300包括设于基底10上的第一绝缘层21。如图13a所示。
随后，依次沉积第二绝缘薄膜和第一栅金属薄膜，通过图案化工艺对第一栅金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层22，以及设置在第二绝缘层22上的第一栅金属层图案，第一栅金属层图案包括位于显示区100的多个栅电极2012和多个第一极板2021。本次图案化工艺后，过渡区300包括依次叠设于基底10上的第一绝缘层21和第二绝缘层22。如图13a所示。
随后，依次沉积第三绝缘薄膜和第二栅金属薄膜，通过图案化工艺对第二栅金属薄膜进行图案化，形成覆盖第一栅金属层的第三绝缘层23，以及设置在第三绝缘层23上的第二栅金属层图案，第二栅金属层图案包括位于显示区100的多个第二极板2022。其中，多个第二极板2022与多个第一极板2021相对设置并形成多个存储电容202。本次图案化工艺后，过渡区300包括依次叠设于基底10上的第一绝缘层21、第二绝缘层22和第三绝缘层23。如图13a所示。
随后，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二栅金属层图案的第四绝缘层24图案，第四绝缘层24图案包括位于过渡区300的第一柱基层551，显示区100的第四绝缘层24设有多个第一过孔和多个第二过孔，多个第一过孔暴露出多个有源层2011的一端，多个第二过孔暴露出多个有源层2011的另一端。本次图案化工艺后，过渡区300包括依次叠设于基底10上的第一绝缘层21、第二绝缘层22、第三绝缘层23，以及设于第三绝缘层23上的第一柱基层551。如图13a所示。
随后，沉积第一源漏金属薄膜，通过图案化工艺对第一源漏金属薄膜进行图案化，在第四绝缘层24上形成第一源漏金属层图案，第一源漏金属层图案包括位于显示区100的多个源电极2013和多个漏电极2014，源电极2013通过第一过孔与有源层2011的一端连接，漏电极2014通过第二过孔与有源层2011的另一端连接。显示区100的多个有源层2011、多个栅电极2012、多个源电极2013和多个漏电极2014形成多个晶体管201。如图13a所示。
随后，沉积钝化薄膜，通过图案化工艺对钝化薄膜进行图案化，形成覆盖第一源漏金属层图案的钝化层251图案，钝化层251图案包括位于过渡区300的第一柱基层551上的第二柱基层552。如图13a所示。
随后，涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成设置在钝化层251上的第一平坦层252图案，第一平坦层252形成有位于显示区100的多个第三过孔，第三过孔内的第一平坦层252和钝化层251被去除并暴露出漏电极2014的表面。如图13a所示。
随后，沉积第二源漏金属薄膜，采用图案化工艺对第二源漏金属薄膜进行图案化，在第一平坦层252上形成第二源漏金属层图案，第二源漏金属层图案包括位于显示区100的多个阳极连接电极203，以及位于过渡区300的第二柱基层552上的第一隔离层。阳极连接电极203通过第三过孔与漏电极2014连接。如图13a所示。
其中，所述第二源漏金属层可以包括沿远离基底10方向依次叠设的第四金属层401、第五金属层402和第六金属层403，比如，第四金属层401和第六金属层403可以为钛层，第五金属层402可以为铝层。则，所述阳极连接电极203的膜层，以及第一隔离层的膜层均与所述第二源漏金属层的膜层相同，即均包括叠设的第四金属层401、第五金属层402和第六金属层403。第一隔离层的朝向显示区100的一侧以及朝向孔区200的一侧，第一隔离层的第四金属层401、第五金属层402和第六金属层403的边缘可以大致平齐。如图13a所示。
随后，利用掩模版，采用刻蚀工艺将位于过渡区300的第一隔离层的第六金属层403完全刻蚀掉。如图13b所示。
随后，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第二源漏金属层图案的第二平坦层26图案。第二平坦层26形成有位于显示区100的多个第四过孔V4，第四过孔V4内的第二平坦层26被去除并暴露出阳极连接电极203的表面； 第二平坦层26图案包括位于过渡区300的第一包覆层52，第一包覆层52设置在第一隔离层的第五金属层402的远离基底10的表面上并将第一隔离层的一侧(比如朝向显示区100的一侧)包覆，第一隔离层的第五金属层402的远离基底10的表面的靠近第一隔离层另一侧(比如朝向孔区200的一侧)的部分可以不被第一包覆层52覆盖。如图13c所示。
至此，制备完成驱动结构层20，以及隔离柱50的膜层。
(2)形成发光结构层30。在示例性实施方式中，形成发光结构层30可以包括：
在形成前述图案的基底10上沉积第一电极薄膜，通过图案化工艺对第一电极薄膜进行图案化，形成第一电极层图案，第一电极层图案包括位于显示区100的多个第一电极31(阳极)，第一电极31通过第二平坦层26上的第四过孔与阳极连接电极203连接，从而第一电极31通过阳极连接电极203与漏电极2014连接。如图13d所示。
在对第一电极薄膜进行图案化过程中，过渡区300的第一隔离层的未被第一包覆层52覆盖的部分也会被刻蚀到，本次图案化工艺结束后，过渡区300的第一隔离层的第五金属层402的未被第一包覆层52覆盖的部分可以被刻蚀掉，在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第五金属层402的边缘与第一包覆层52的边缘可以大致平齐，第一隔离层的第四金属层401的边缘凸出于第五金属层402的边缘。由于第一隔离层的钛材质的第四金属层401相较于铝材质的第五金属层402难刻蚀，因此，本次图案化工艺结束后，在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第四金属层401的边缘可以凸出于第五金属层402的边缘。如图13d所示。
随后，在形成前述图案的基底10上涂覆像素界定薄膜，通过图案化工艺对像素界定薄膜进行图案化，形成像素界定层32图案，像素界定层32设置有多个像素开口，像素开口暴露出显示区100的第一电极31的表面。如图13e所示。
随后，可以利用掩模版，采用湿法刻蚀工艺，对过渡区300的第一隔离层的第五金属层402进行横向刻蚀，使第一隔离层的第五金属层402在第一隔离层的未被第一包覆层52包覆一侧相较于第一包覆层52内缩一部分。至此，形成最终的隔离柱50结构，第一隔离层的第四金属层401和第五金属层402即成为了隔离柱50的第一隔离部51的第一导电层511和第二导电层512，第一柱基层551和第二柱基层552形成了柱基55。如图13f所示。
随后，在形成前述图案的基底10上，涂覆隔垫柱薄膜，通过图案化工艺对隔垫柱薄膜进行图案化，形成隔垫柱层图案，隔垫柱层图案包括位于显示区100的像素界定层32上的多个隔垫柱(图中未示出)。
随后，在形成前述图案的基底10上，可以通过蒸镀工艺依次形成发光功能层33的多个膜层，发光功能层33可以包括沿远离基底方向依次设置的空穴注入层、空穴传输层、电子阻挡层、有机发光层、空穴阻挡层、电子传输层和电子注入层。除有机发光层外，发光功能层33的其余膜层均可以为一体的整面结构，即，发光功能层33的其余膜层可以为不同颜色子像素的共通层，这些共通层在蒸镀的时候可以形成在显示区100和过渡区300。由于在过渡区300设置了隔离柱50，这些共通层会在隔离柱50处断开，阻断了水氧由孔区200经发光功能层33向显示区100传输的路径，可避免水氧侵蚀显示区100的发光功能层33。如图2所示。
随后，在形成前述图案的基底10上，通过蒸镀工艺形成第二电极(阴极)层，不同颜色子像素的第二电极层34是连接为一体结构的共通层，第二电极层34可以形成在显示 区100和过渡区300。第二电极层34可以在隔离柱50处断开，阻断了水氧由孔区200经第二电极层34向显示区100传输的路径，可避免水氧侵蚀显示区100的第二电极层34。如图2所示。
至此，制备完成发光结构层30。
随后，可以在发光结构层30的远离基底10一侧依次形成封装结构层40、触控结构层和彩膜层等膜层。
基于图12a至图12g的工艺过程或图13a至图13f的工艺过程，本公开实施例提供一种显示基板的制备方法，包括制备图7a示例的隔离柱，图7a示例的隔离柱的制备过程可以包括：
在所述过渡区的基底上形成第一隔离层，所述第一隔离层包括沿远离所述基底方向依次叠设的第一膜层、第二膜层和第三膜层，在所述第一隔离层的朝向所述显示区一侧和朝向所述孔区一侧，所述第一膜层、所述第二膜层和所述第三膜层的边缘平齐；
采用刻蚀工艺将所述第三膜层完全去除；
在所述第二膜层的远离所述基底的表面上形成第一包覆层，且所述第一包覆层将所述第一隔离层的朝向所述显示区或所述孔区的一侧包覆，在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层和所述第一膜层的边缘凸出于所述第一包覆层的边缘；
采用刻蚀工艺对所述第一隔离层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层的边缘与所述第一包覆层的边缘平齐，所述第一膜层的边缘凸出于或平齐于所述第二膜层的边缘；
采用刻蚀工艺对所述第二膜层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层的边缘相较于所述第一包覆层的边缘和所述第一膜层的边缘内缩，从而使得所述第一隔离层的所述第一膜层和所述第二膜层分别成为所述第一隔离部的所述第一导电层和所述第二导电层。
在又一些示例性实施例中，以图2示例的显示基板和图8示例的隔离柱为例，且所述第一隔离部51与所述晶体管201的源电极2013和漏电极2014同层设置，第一包覆层52与第五绝缘层25中的钝化层251同层设置。示例性地，显示基板的制备过程可以包括如下操作：
(1)形成驱动结构层20，以及隔离柱50的膜层。
在基底10上依次形成第一绝缘层21、半导体层、第二绝缘层22、第一栅金属层、第三绝缘层23、第二栅金属层和第四绝缘层24；
其中，在形成显示区100的第四绝缘层24的同时，在过渡区300的第三绝缘层23上形成第一柱基层551，即第一柱基层551与第四绝缘层24同层设置且材质相同。显示区100的第四绝缘层24设有多个第一过孔V1和多个第二过孔V2，多个第一过孔V1暴露出多个有源层2011的一端，多个第二过孔V2暴露出多个有源层2011的另一端。如图14a所示。
随后，沉积第一源漏金属薄膜，通过图案化工艺对第一源漏金属薄膜进行图案化，在第四绝缘层24上形成第一源漏金属层图案，第一源漏金属层图案包括位于显示区100的多个源电极2013和多个漏电极2014，以及位于过渡区300的第一柱基层551上的第一隔离层。源电极2013通过第一过孔与有源层2011的一端连接，漏电极2014通过第二过孔与有源层2011的另一端连接，显示区100的多个有源层2011、多个栅电极2012、多个源 电极2013和多个漏电极2014形成多个晶体管201。如图14b所示。
其中，所述第一源漏金属层可以包括沿远离基底10方向依次叠设的第一金属层301、第二金属层302和第三金属层303，比如，第一金属层301和第三金属层303可以为钛层，第二金属层302可以为铝层。则，源电极2013、漏电极2014和第一隔离层均包括沿远离基底10方向依次叠设的第一金属层301(Ti)、第二金属层302(Al)和第三金属层303(Ti)。第一隔离层的朝向显示区100的一侧以及朝向孔区200的一侧，第一隔离层的第一金属层301、第二金属层302和第三金属层303的边缘可以大致平齐。如图14b所示。
随后，利用掩模版，采用刻蚀工艺将位于过渡区300的第一隔离层的第三金属层303的靠近显示区100或孔区200的一部分(图14c的示例中为靠近孔区200的一部分)刻蚀掉。如图14c所示。
随后，沉积钝化薄膜，通过图案化工艺对钝化薄膜进行图案化，形成覆盖第一源漏金属层图案的钝化层251图案，钝化层251图案包括位于过渡区300的第一包覆层52，第一包覆层52设置在第一隔离层的第三金属层303的远离基底10的表面上，并将第一隔离层的朝向显示区100的一侧包覆，以及将第三金属层303的远离基底10的表面和第三金属层303的位于第一隔离层的朝向孔区200一侧的表面(即第三金属层303的朝向孔区200的表面)包覆。第一隔离层的第二金属层302的远离基底10的表面的靠近孔区200的一部分可以不被第一包覆层52覆盖，即在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第二金属层302的边缘可以凸出于第一包覆层52的边缘。如图14d所示。
随后，涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成设置在钝化层251上的第一平坦层252图案，第一平坦层252形成有位于显示区100的多个第三过孔V3，第三过孔V3内的第一平坦层252和钝化层251被去除并暴露出漏电极2014的表面。如图14e所示。其中，本示例中，钝化层251和第一平坦层252整体可以称为第五绝缘层25，钝化层251可以为无机绝缘材料，第一平坦层252可以为有机绝缘材料。在其他示例中，可以不设置钝化层251，第五绝缘层25可以仅包括第一平坦层252，此种情况下，可以在图案化形成第一平坦层252图案过程中，同时形成第一包覆层52。
随后，沉积第二源漏金属薄膜，采用图案化工艺对第二源漏金属薄膜进行图案化，在第一平坦层252上形成第二源漏金属层图案，第二源漏金属层图案包括位于显示区100的多个阳极连接电极203，阳极连接电极203通过第三过孔V3与漏电极2014连接。如图14e所示。
其中，第二源漏金属层的膜层结构及材料可以与第一源漏金属层的膜层结构及材料相同，比如，所述第二源漏金属层可以包括沿远离基底10方向依次叠设的第四金属层401、第五金属层402和第六金属层403，比如，第四金属层401和第六金属层403可以为钛层，第五金属层402可以为铝层。由此，在对第二源漏金属薄膜进行图案化过程中，过渡区300的第一隔离层的未被第一包覆层52覆盖的部分也会被刻蚀到，本次图案化工艺结束后，过渡区300的第一隔离层的第二金属层302的未被第一包覆层52覆盖的部分被刻蚀掉，在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第二金属层302的边缘与第一包覆层52的边缘大致平齐，第一隔离层的第一金属层301的边缘凸出于第二金属层302的边缘。由于第一隔离层的钛材质的第一金属层301相较于铝材质的第二金属层302难刻蚀，因此，本次图案化工艺结束后，在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第一金属层301的边缘凸出于第二金属层302的边缘。如图14e所示。
随后，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第二源漏金属层图案的第二平坦层26图案，第二平坦层26形成有位于显示区100的多个第 四过孔V4，第四过孔V4内的第二平坦层26被去除并暴露出阳极连接电极203的表面。如图14f所示。
至此，制备完成驱动结构层20，以及隔离柱50的膜层。
(2)形成发光结构层30。在示例性实施方式中，形成发光结构层30可以包括：
在形成前述图案的基底10上沉积第一电极薄膜，通过图案化工艺对第一电极薄膜进行图案化，形成第一电极层图案，第一电极层图案包括位于显示区100的多个第一电极31(阳极)，第一电极31通过第二平坦层26上的第四过孔V4与阳极连接电极203连接，从而第一电极31通过阳极连接电极203与漏电极2014连接。如图14f所示。
随后，在形成前述图案的基底10上涂覆像素界定薄膜，通过图案化工艺对像素界定薄膜进行图案化，形成像素界定层32图案，像素界定层32设置有多个像素开口，像素开口暴露出显示区100的第一电极31的表面。如图14f所示。
随后，可以利用掩模版，采用湿法刻蚀工艺，对过渡区300的第一隔离层的第二金属层302进行横向刻蚀，使第一隔离层的第二金属层302在第一隔离层的未被第一包覆层52包覆一侧相较于第三金属层303内缩一部分。至此，形成最终的隔离柱50结构，第一隔离层的第一金属层301、第二金属层302和第三金属层303即成为了隔离柱50的第一隔离部51的第一导电层511、第二导电层512和第三导电层513，第一柱基层551形成了柱基55。如图14g所示。
随后，形成显示基板的其余膜层。
前文图14a至图14g的工艺过程形成了图8示例的隔离柱50，且所述第一隔离部51与所述晶体管201的源电极2013和漏电极2014同层设置，第一包覆层52与第五绝缘层25中的钝化层251同层设置。在其他实施方式中，图8示例的隔离柱50中，所述第一隔离部51与所述连接电极203同层设置，第一包覆层52与第二平坦层26同层设置，隔离柱50的形成方式可以与14a至图14g中隔离柱50的形成方式相同，此种情况下，可以在图案化形成第二源漏金属层图案的同时，在显示区100形成连接电极203，在过渡区300形成第一隔离层，其中，第二源漏金属层可以包括沿远离基底10方向依次叠设的第四金属层401、第五金属层402和第六金属层403，比如，第四金属层401和第六金属层403可以为钛层，第五金属层402可以为铝层，则第一隔离层包括沿远离基底10方向依次叠设的第四金属层401、第五金属层402和第六金属层403；随后，利用掩模版，采用刻蚀工艺将位于过渡区300的第一隔离层的第六金属层403的靠近显示区100或孔区200的一部分刻蚀掉；随后，在图案化形成第二平坦层26图案的同时，在过渡区300的第一隔离层的第六金属层403上形成第一包覆层52；随后，在图案化形成第一电极31的同时，将第一隔离层的第五金属层402的未被第一包覆层52覆盖的部分刻蚀去除，在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第五金属层402的边缘可以与第一包覆层52的边缘大致平齐，第四金属层401的边缘凸出于第五金属层402的边缘；随后，可以利用掩模版，采用湿法刻蚀工艺，对过渡区300的第一隔离层的第五金属层402进行横向刻蚀，使第一隔离层的第五金属层402在第一隔离层的未被第一包覆层52包覆一侧相较于第六金属层403内缩一部分。至此，形成最终的隔离柱50结构，第一隔离层的第四金属层401、第五金属层402和第六金属层403即成为了隔离柱50的第一隔离部51的第一导电层511、第二导电层512和第三导电层513。
基于图14a至图14g的工艺过程，本公开实施例提供一种显示基板的制备方法，包括制备图8示例的隔离柱，图8示例的隔离柱的制备过程可以包括：
在所述过渡区的基底上形成第一隔离层，所述第一隔离层包括沿远离所述基底方向依次叠设的第一膜层、第二膜层和第三膜层，在所述第一隔离层的朝向所述显示区一侧和朝向所述孔区一侧，所述第一膜层、所述第二膜层和所述第三膜层的边缘平齐；
采用刻蚀工艺将所述第三膜层的靠近所述显示区或所述孔区的一部分刻蚀去除，使得在所述第一隔离层的第一侧，所述第一膜层和所述第二膜层的边缘凸出于所述第三膜层的边缘；
在所述第三膜层的远离所述基底的表面上形成第一包覆层，且所述第一包覆层将所述第一隔离层的第二侧包覆，以及将所述第三膜层的远离所述基底的表面和所述第三膜层的位于所述第一隔离层的第一侧的表面包覆；
采用刻蚀工艺对所述第一隔离层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧(即所述第一隔离层的第一侧)，所述第二膜层的边缘与所述第一包覆层的边缘平齐，所述第一膜层的边缘凸出于或平齐于所述第二膜层的边缘；
采用刻蚀工艺对所述第二膜层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层的边缘相较于所述第三膜层的边缘和所述第一膜层的边缘内缩，从而使得所述第一隔离层的所述第一膜层、所述第二膜层和所述第三膜层分别成为所述第一隔离部的所述第一导电层、所述第二导电层和所述第三导电层。
在又一些示例性实施例中，以图2示例的显示基板和图8示例的隔离柱为例，且所述第一隔离部51与所述晶体管201的源电极2013和漏电极2014同层设置，第一包覆层52与第五绝缘层25中的钝化层251同层设置。示例性地，显示基板的制备过程可以包括如下操作：
在基底10上依次形成第一绝缘层21、半导体层、第二绝缘层22、第一栅金属层、第三绝缘层23、第二栅金属层和第四绝缘层24；
其中，在形成显示区100的第四绝缘层24的同时，在过渡区300的第三绝缘层23上形成第一柱基层551，即第一柱基层551与第四绝缘层24同层设置且材质相同。显示区100的第四绝缘层24设有多个第一过孔V1和多个第二过孔V2，多个第一过孔V1暴露出多个有源层2011的一端，多个第二过孔V2暴露出多个有源层2011的另一端。如图15a所示。
随后，沉积第一源漏金属薄膜，通过图案化工艺对第一源漏金属薄膜进行图案化，在第四绝缘层24上形成第一源漏金属层图案，第一源漏金属层图案包括位于显示区100的多个源电极2013和多个漏电极2014，以及位于过渡区300的第一柱基层551上的第一隔离层。源电极2013通过第一过孔与有源层2011的一端连接，漏电极2014通过第二过孔与有源层2011的另一端连接，显示区100的多个有源层2011、多个栅电极2012、多个源电极2013和多个漏电极2014形成多个晶体管201。如图15b所示。
其中，所述第一源漏金属层可以包括沿远离基底10方向依次叠设的第一金属层301、第二金属层302和第三金属层303，比如，第一金属层301和第三金属层303可以为钛层，第二金属层302可以为铝层。则，源电极2013、漏电极2014和第一隔离层均包括沿远离基底10方向依次叠设的第一金属层301(Ti)、第二金属层302(Al)和第三金属层303(Ti)。第一隔离层的朝向显示区100的一侧以及朝向孔区200的一侧，第一隔离层的第一金属层301、第二金属层302和第三金属层303的边缘可以大致平齐。如图15b所示。
随后，沉积钝化薄膜，通过图案化工艺对钝化薄膜进行图案化，形成覆盖第一源漏金属层图案的钝化层251图案，钝化层251图案包括位于过渡区300的第一包覆层52，第 一包覆层52设置在第一隔离层的第三金属层303的远离基底10的表面上，并将第一隔离层的朝向显示区100或孔区200的一侧(图15c的示例中为朝向显示区100的一侧)包覆，第一隔离层的第三金属层303的靠近第一隔离层的未被第一包覆层52包覆一侧的一部分未被第一包覆层52覆盖(即在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第三金属层303的边缘凸出于第一包覆层52的边缘)。如图15c所示。
随后，涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成设置在钝化层251上的第一平坦层252图案，第一平坦层252形成有位于显示区100的多个第三过孔V3，第三过孔V3内的第一平坦层252和钝化层251被去除并暴露出漏电极2014的表面。如图15d所示。其中，本示例中，钝化层251和第一平坦层252整体可以称为第五绝缘层25，钝化层251可以为无机绝缘材料，第一平坦层252可以为有机绝缘材料。在其他示例中，可以不设置钝化层251，第五绝缘层25可以仅包括第一平坦层252，此种情况下，可以在图案化形成第一平坦层252图案过程中，同时形成第一包覆层52。
随后，沉积第二源漏金属薄膜，采用图案化工艺对第二源漏金属薄膜进行图案化，在第一平坦层252上形成第二源漏金属层图案，第二源漏金属层图案包括位于显示区100的多个阳极连接电极203，阳极连接电极203通过第三过孔V3与漏电极2014连接。如图15d所示。
其中，第二源漏金属层的膜层结构及材料可以与第一源漏金属层的膜层结构及材料相同，比如，所述第二源漏金属层可以包括沿远离基底10方向依次叠设的第四金属层401、第五金属层402和第六金属层403，比如，第四金属层401和第六金属层403可以为钛层，第五金属层402可以为铝层。由此，在对第二源漏金属薄膜进行图案化过程中，过渡区300的第一隔离层的未被第一包覆层52覆盖的部分也会被刻蚀到，本次图案化工艺结束后，过渡区300的第一隔离层的第三金属层303和第二金属层302的未被第一包覆层52覆盖的部分被刻蚀掉，在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第三金属层303和第二金属层302的边缘与第一包覆层52的边缘大致平齐，第一隔离层的第一金属层301的边缘凸出于第三金属层303和第二金属层302的边缘。由于第一隔离层的钛材质的第一金属层301相较于铝材质的第二金属层302难刻蚀，因此，本次图案化工艺结束后，在第一隔离层的未被第一包覆层52包覆一侧，第一隔离层的第一金属层301的边缘凸出于第二金属层302的边缘。如图15d所示。
随后，采用刻蚀工艺将位于过渡区300的第一隔离层的第三金属层303的靠近第一隔离层的未被第一包覆层52包覆一侧的一部分刻蚀去除，之后，第一包覆层52的靠近第一隔离层的未被第一包覆层52包覆一侧的一部分在没有第三金属层303支撑下会下垂，并将第三金属层303的位于第一隔离层的未被第一包覆层52包覆一侧的表面包覆。如图15e所示。
随后，可以利用掩模版，采用湿法刻蚀工艺，对过渡区300的第一隔离层的第二金属层302进行横向刻蚀，使第一隔离层的第二金属层302在第一隔离层的未被第一包覆层52包覆一侧相较于第三金属层303和第一金属层301内缩。至此，形成最终的隔离柱50结构，第一隔离层的第一金属层301、第二金属层302和第三金属层303即成为了隔离柱50的第一隔离部51的第一导电层511、第二导电层512和第三导电层513，第一柱基层551形成了柱基55。如图15f所示。
随后，形成显示基板的其余膜层。
基于图15a至图15f的工艺过程，本公开实施例提供一种显示基板的制备方法，包括制备图8示例的隔离柱，图8示例的隔离柱的制备过程可以包括：
在所述过渡区的基底上形成第一隔离层，所述第一隔离层包括沿远离所述基底方向依次叠设的第一膜层、第二膜层和第三膜层，在所述第一隔离层的朝向所述显示区一侧和朝向所述孔区一侧，所述第一膜层、所述第二膜层和所述第三膜层的边缘平齐；
在所述第三膜层的远离所述基底的表面上形成第一包覆层，且所述第一包覆层将所述第一隔离层的朝向所述显示区或所述孔区的一侧包覆，在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第一膜层、所述第二膜层和所述第三膜层的边缘凸出于所述第一包覆层的边缘(即，所述第三膜层的远离所述基底的表面的靠近所述第一隔离层的未被所述第一包覆层包覆一侧的一部分未被所述第一包覆层覆盖)；
采用刻蚀工艺对所述第一隔离层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层和所述第三膜层的边缘与所述第一包覆层的边缘平齐，且所述第一膜层的边缘凸出于所述第二膜层和所述第三膜层的边缘；
采用刻蚀工艺对所述第三膜层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第三膜层的边缘相较于所述第一包覆层的边缘内缩，之后，所述第一包覆层的未被所述第三膜层支撑的部分下垂，并将所述第三膜层的位于所述第一隔离层的未被所述第一包覆层包覆一侧的表面包覆；
采用刻蚀工艺对所述第二膜层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层的边缘相较于所述第三膜层的边缘和所述第一膜层的边缘内缩，从而使得所述第一隔离层的所述第一膜层、所述第二膜层和所述第三膜层分别成为所述第一隔离部的所述第一导电层、所述第二导电层和所述第三导电层。
本公开实施例还提供一种显示装置，包括前文任一实施例所述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在附图中，有时为了明确起见，夸大表示了构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中每个部件的形状和大小不反映真实比例。此外，附图示意性地示出了一些例子，本公开的实施方式不局限于附图所示的形状或数值。
在本文描述中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，包括85°以上且95°以下的角度的状态。
在本文描述中，术语“上”、“下”、“左”、“右”、“顶”、“内”、“外”、“轴向”、“四角”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开实施例的简化描述，而不是指示或暗示所指的结构具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本文描述中，除非另有明确的规定和限定，术语“连接”、“固定连接”、“安装”、“装配”应做广义理解，例如，可以是固定连接，或是可拆卸连接，或一体地连接；术语“安装”、“连接”、“固定连接”可以是直接相连，或通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开实施例中的含义。

Claims (22)

  1. 一种显示基板，包括孔区、围绕所述孔区的过渡区，以及围绕所述过渡区的显示区；所述过渡区设置有围绕所述孔区的隔离柱，所述隔离柱包括第一隔离部和第一包覆层；
    所述显示基板包括基底，所述第一隔离部包括第二导电层，所述第一隔离部的第一侧朝向所述显示区，所述第一隔离部的第二侧朝向所述孔区；
    所述第一包覆层设于所述第一隔离部的远离所述基底一侧，并将所述第一隔离部的第一侧和第二侧中的其中一侧包覆，在所述第一隔离部的第一侧和第二侧中的另一侧，所述第二导电层相较于所述第一包覆层内缩设置；所述第一包覆层的材料为绝缘材料。
  2. 如权利要求1所述的显示基板，其中，所述第一隔离部还包括设于所述第二导电层的靠近所述基底一侧的第一导电层，所述第一包覆层设于所述第二导电层的远离所述基底的表面上，并将所述第一隔离部的第一侧和第二侧中的其中一侧包覆，在所述第一隔离部的第一侧和第二侧中的另一侧，所述第二导电层还相较于所述第一导电层内缩设置。
  3. 如权利要求1所述的显示基板，其中，所述第一隔离部还包括设于所述第二导电层的远离所述基底一侧的第三导电层，所述第一包覆层设于所述第三导电层的远离所述基底的表面上，并将所述第一隔离部的第一侧和第二侧中的其中一侧包覆；在所述第一隔离部的第一侧和第二侧中的另一侧，所述第二导电层还相较于所述第三导电层内缩设置。
  4. 如权利要求3所述的显示基板，其中，所述第一包覆层还将所述第三导电层的位于所述第一隔离部的第一侧和第二侧中的另一侧的表面包覆，所述第三导电层在所述基底上的正投影落入所述第一包覆层在所述基底上的正投影内。
  5. 如权利要求1至4任一项所述的显示基板，其中，所述第二导电层相较于所述第一包覆层内缩0.35微米至0.4微米。
  6. 如权利要求5所述的显示基板，其中，在所述第一隔离部的第一侧和第二侧中的另一侧，所述第一包覆层的靠近边缘的部分具有20度至45度的坡度角。
  7. 如权利要求1所述的显示基板，其中，所述隔离柱还包括第二隔离部，所述第二隔离部设于所述第一隔离部的朝向所述基底一侧，所述第二隔离部包括沿远离所述基底方向依次叠设的第四导电层和第五导电层；所述第二隔离部的第一侧朝向所述显示区，所述第二隔离部的第二侧朝向所述孔区；所述第一包覆层还将所述第二隔离部的第一侧和第二侧中的其中一侧包覆，在所述第二隔离部的第一侧和第二侧中的另一侧，所述第五导电层相较于所述第四导电层内缩设置。
  8. 如权利要求7所述的显示基板，其中，所述第二隔离部还包括设于所述第五导电层的远离所述基底一侧的第六导电层，在所述第二隔离部的第一侧和第二侧中的另一侧，所述第五导电层还相较于所述第六导电层内缩设置。
  9. 如权利要求1所述的显示基板，其中，所述隔离柱还包括第二隔离部和第二包覆层；所述第二隔离部设于所述第一隔离部的朝向所述基底一侧，所述第二隔离部的第一侧朝向所述显示区，所述第二隔离部的第二侧朝向所述孔区；所述第二包覆层设于所述第二隔离部和所述第一隔离部之间，并将所述第二隔离部的第一侧和第二侧中的其中一侧包覆；所述第二隔离部的材料为导电材料，所述第二包覆层的材料为绝缘材料。
  10. 如权利要求9所述的显示基板，其中，所述第二隔离部包括沿远离所述基底方向依次叠设的第四导电层、第五导电层和第六导电层；在所述第二隔离部的第一侧和第二侧中的另一侧，所述第五导电层相较于所述第四导电层和所述第六导电层内缩设置。
  11. 如权利要求9所述的显示基板，其中，所述第一隔离部的第一侧和第二侧中的被所述第一包覆层包覆的一侧，与所述第二隔离部的第一侧和第二侧中的被所述第二包覆层包覆的一侧位于所述隔离柱的不同侧。
  12. 如权利要求1至4任一项所述的显示基板，其中，所述隔离柱还包括设于所述第一隔离部的朝向所述基底一侧的柱基，所述柱基包括一个或多个膜层。
  13. 如权利要求12所述的显示基板，其中，所述柱基包括一个无机绝缘层或叠设的多个无机绝缘层；或者，所述柱基包括至少一个无机绝缘层和至少一个金属层，所述金属层被所述无机绝缘层包覆。
  14. 如权利要求1所述的显示基板，其中，所述显示区包括依次叠设于所述基底上的驱动结构层和发光结构层，所述驱动结构层包括像素驱动电路，所述像素驱动电路包括多个晶体管和存储电容，所述发光结构层包括多个发光元件，所述发光元件包括沿远离所述基底方向依次叠设的第一电极、发光功能层和第二电极层；
    在垂直于所述基底的方向上，所述驱动结构层包括沿远离所述基底方向依次设置的第一源漏金属层、第五绝缘层、第二源漏金属层和第二平坦层；所述第一源漏金属层包括至少一个所述晶体管的源电极和漏电极，所述第二源漏金属层包括与所述晶体管的源电极或漏电极连接的连接电极，所述连接电极还与所述第一电极连接。
  15. 如权利要求14所述的显示基板，其中，所述第一源漏金属层包括叠设的多个金属层，所述第一隔离部与所述晶体管的源电极和漏电极同层设置，所述第一包覆层与所述第五绝缘层同层设置。
  16. 如权利要求14所述的显示基板，其中，所述第二源漏金属层包括叠设的多个金属层，所述第一隔离部与所述连接电极同层设置，所述第一包覆层与所述第二平坦层同层设置。
  17. 如权利要求14所述的显示基板，其中，所述隔离柱还包括第二隔离部，所述第二隔离部设于所述第一隔离部的朝向所述基底一侧，所述第二隔离部包括沿远离所述基底方向依次叠设的第四导电层和第五导电层；所述第二隔离部的第一侧朝向所述显示区，所述第二隔离部的第二侧朝向所述孔区；所述第一包覆层还将所述第二隔离部的第一侧和第二侧中的其中一侧包覆，在所述第二隔离部的第一侧和第二侧中的另一侧，所述第五导电层相较于所述第四导电层内缩设置；
    所述第一源漏金属层和所述第二源漏金属层均包括叠设的多个金属层，所述第一隔离部与所述连接电极同层设置，所述第一包覆层与所述第二平坦层同层设置，所述第二隔离部与所述晶体管的源电极和漏电极同层设置。
  18. 如权利要求14所述的显示基板，其中，所述隔离柱还包括第二隔离部和第二包覆层；所述第二隔离部设于所述第一隔离部的朝向所述基底一侧，所述第二隔离部的第一侧朝向所述显示区，所述第二隔离部的第二侧朝向所述孔区；所述第二包覆层设于所述第二隔离部和所述第一隔离部之间，并将所述第二隔离部的第一侧和第二侧中的其中一侧包覆；所述第二隔离部的材料为导电材料，所述第二包覆层的材料为绝缘材料；
    所述第一源漏金属层和所述第二源漏金属层均包括叠设的多个金属层，所述第一隔离部与所述连接电极同层设置，所述第一包覆层与所述第二平坦层同层设置，所述第二隔离部与所述晶体管的源电极和漏电极同层设置，所述第二包覆层与所述第五绝缘层同层设置。
  19. 如权利要求14所述的显示基板，其中，所述驱动结构层还包括设于所述第一源漏金属层的朝向所述基底一侧的半导体层、第一栅金属层和第二栅金属层，所述半导体层包括所述晶体管的有源层，所述第一栅金属层包括所述晶体管的栅电极和所述存储电容的一个极板，所述第二栅金属层包括所述存储电容的另一个极板；
    所述隔离柱还包括设于所述第一隔离部的朝向所述基底一侧的柱基，所述柱基包括至少一个无机绝缘层和至少一个金属层，所述金属层被所述无机绝缘层包覆，所述金属层与所述第一栅金属层或者所述第二栅金属层同层设置。
  20. 如权利要求14所述的显示基板，其中，所述第五绝缘层包括沿远离所述基底方 向依次叠设的钝化层和第一平坦层，所述钝化层为无机绝缘层，所述第一平坦层为有机绝缘层；或者，所述第五绝缘层仅包括第一平坦层，所述第一平坦层为有机绝缘层。
  21. 一种显示装置，包括权利要求1至20任一项所述的显示基板。
  22. 一种制备权利要求2所述的显示基板的方法，包括：
    在所述过渡区的基底上形成第一隔离层，所述第一隔离层包括沿远离所述基底方向依次叠设的第一膜层、第二膜层和第三膜层，在所述第一隔离层的朝向所述显示区一侧和朝向所述孔区一侧，所述第一膜层、所述第二膜层和所述第三膜层的边缘平齐；
    采用刻蚀工艺将所述第三膜层完全去除；
    在所述第二膜层的远离所述基底的表面上形成第一包覆层，且所述第一包覆层将所述第一隔离层的朝向所述显示区或所述孔区的一侧包覆，在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层和所述第一膜层的边缘凸出于所述第一包覆层的边缘；
    采用刻蚀工艺对所述第一隔离层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层的边缘与所述第一包覆层的边缘平齐，所述第一膜层的边缘凸出于或平齐于所述第二膜层的边缘；
    采用刻蚀工艺对所述第二膜层进行刻蚀，使得在所述第一隔离层的未被所述第一包覆层包覆一侧，所述第二膜层的边缘相较于所述第一包覆层的边缘和所述第一膜层的边缘内缩，从而使得所述第一隔离层的所述第一膜层和所述第二膜层分别成为所述第一隔离部的所述第一导电层和所述第二导电层。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113066834A (zh) * 2021-03-19 2021-07-02 合肥鑫晟光电科技有限公司 显示装置、显示面板及其制造方法
CN217035640U (zh) * 2021-10-27 2022-07-22 京东方科技集团股份有限公司 一种显示面板及显示装置
CN115802796A (zh) * 2021-09-09 2023-03-14 华为技术有限公司 一种显示面板及其制作方法和电子设备
CN219919629U (zh) * 2023-03-31 2023-10-27 京东方科技集团股份有限公司 一种显示基板及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113066834A (zh) * 2021-03-19 2021-07-02 合肥鑫晟光电科技有限公司 显示装置、显示面板及其制造方法
CN115802796A (zh) * 2021-09-09 2023-03-14 华为技术有限公司 一种显示面板及其制作方法和电子设备
CN217035640U (zh) * 2021-10-27 2022-07-22 京东方科技集团股份有限公司 一种显示面板及显示装置
CN219919629U (zh) * 2023-03-31 2023-10-27 京东方科技集团股份有限公司 一种显示基板及显示装置

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