WO2024155074A1

WO2024155074A1 - Electronic device, and method for managing memory of electronic device

Info

Publication number: WO2024155074A1
Application number: PCT/KR2024/000786
Authority: WO
Inventors: 이기성; 우호빈; 이우중; 신윤호; 전혜은
Original assignee: 삼성전자 주식회사
Priority date: 2023-01-19
Filing date: 2024-01-16
Publication date: 2024-07-25

Abstract

This electronic device may comprise: a plurality of memories including a first memory and a second memory having performance lower than that of the first memory; and a processor. The processor can: measure latency of a plurality of memories; determine, on the basis of the measured latency, a tier to be allocated to at least one memory from among the plurality of memories; and, in response to a migration request of a page, control that a page is not migrated between the memories, to which the same tier is allocated, from among the plurality of memories.

Description

Electronic devices and memory management methods in electronic devices

This document relates to an electronic device that sets a memory balancing policy on a memory tiering system and a memory management method for the electronic device.

Portable electronic devices (hereinafter referred to as electronic devices) such as smart phones can provide user experiences using various applications. As the functions provided by electronic devices increase, improvements in data processing speed are required, and accordingly, improvements in hardware performance such as processors and memory are also required. Accordingly, the capacity of memory (e.g., RAM (random access memory)) is increasing, but in order to run many applications at the same time, it may be necessary to properly manage the memory capacity.

Due to limited memory capacity, electronic devices may perform various memory reclaim operations and process termination operations to monitor the state of the memory and maintain system performance at an acceptable level.

PMEM (persistent memory) has relatively slower access performance than DRAM, but is inexpensive and can replace DRAM. Electronics can be used with DRAM to compensate for PMEM's slow access performance. Electronic devices can perform an auto-balancing operation that allocates memory pages between PMEM and DRAM to compensate for PMEM's slow access performance.

When there is insufficient free space in DRAM, electronic devices can move memory pages that have been accessed less frequently to PMEM, a relatively slow memory, to secure free space. This process is called demotion. Additionally, in order to minimize access to PMEM, which has a relatively slow processing speed, the electronic device can classify recently accessed memory pages on PMEM as hot pages and migrate them onto DRAM. This process is called promotion. Auto-balancing operations may include demotion and promotion.

The promotion process is a way to overcome the shortcomings of the memory hierarchy system, but the migration technique is complicated, so CPU operation may increase. Due to an increase in CPU operation, auto-balancing operation may actually delay the system. Additionally, page migration operations may be necessary in situations where free memory space is insufficient, and as memory is used to perform migration, it may further delay the system.

The electronic device according to this document establishes a memory balancing policy between memory tiers with different performance on a memory tiering system that uses DRAM, a relatively fast memory, and PMEM, a relatively slow memory, and performs balancing operations efficiently. Methods for adjustment can be provided.

The electronic device may include a plurality of memories including a first memory and a second memory having lower performance than the first memory, and a processor. The processor measures the latency of a plurality of memories, determines a tier to be allocated to at least one memory among the plurality of memories based on the measured latency, and responds to the page migration request. Correspondingly, page migration may be controlled not to be performed between memories allocated to the same tier among a plurality of memories.

A memory management method for an electronic device includes measuring the latency of a plurality of memories and determining a tier to be assigned to at least one memory among the plurality of memories based on the measured latency. In response to the operation and page migration request, the method may include controlling not to perform page migration between memories allocated to the same tier among a plurality of memories.

According to one embodiment, the electronic device sets a tier in consideration of the latency of the memory and sets whether to perform an auto-balancing operation between tiers to efficiently use memory resources. You can utilize it.

According to one embodiment, the electronic device sets memories whose latencies do not differ beyond a specified level into one tier and does not perform an auto-balancing operation between memories within the same tier, thereby preventing unnecessary balancing. It can reduce operation and prevent the system from slowing down due to auto-balancing operation.

1 is a block diagram of an electronic device in a network environment, according to various embodiments.

FIG. 2 is a block diagram illustrating a memory management method of an electronic device according to an embodiment.

Figure 3 is a block diagram showing the configuration of an electronic device according to an embodiment.

Figures 4a, 4b, and 4c show the process of classifying tiers based on memory latency.

Figures 5a and 5b illustrate the process of determining the memory allocation order in a situation where migration between tiers occurs.

Figure 6 is a flowchart showing a memory management method of an electronic device according to an embodiment.

1 is a block diagram of an electronic device 101 in a network environment 100, according to various embodiments. Referring to FIG. 1, in the network environment 100, the electronic device 101 communicates with the electronic device 102 through a first network 198 (e.g., a short-range wireless communication network) or a second network 199. It is possible to communicate with at least one of the electronic device 104 or the server 108 through (e.g., a long-distance wireless communication network). According to one embodiment, the electronic device 101 may communicate with the electronic device 104 through the server 108. According to one embodiment, the electronic device 101 includes a processor 120, a memory 130, an input module 150, an audio output module 155, a display module 160, an audio module 170, and a sensor module ( 176), interface 177, connection terminal 178, haptic module 179, camera module 180, power management module 188, battery 189, communication module 190, subscriber identification module 196 , or may include an antenna module 197. In some embodiments, at least one of these components (eg, the connection terminal 178) may be omitted or one or more other components may be added to the electronic device 101. In some embodiments, some of these components (e.g., sensor module 176, camera module 180, or antenna module 197) are integrated into one component (e.g., display module 160). It can be.

The processor 120, for example, executes software (e.g., program 140) to operate at least one other component (e.g., hardware or software component) of the electronic device 101 connected to the processor 120. It can be controlled and various data processing or calculations can be performed. According to one embodiment, as at least part of data processing or computation, the processor 120 stores commands or data received from another component (e.g., sensor module 176 or communication module 190) in volatile memory 132. The commands or data stored in the volatile memory 132 can be processed, and the resulting data can be stored in the non-volatile memory 134. According to one embodiment, the processor 120 includes the main processor 121 (e.g., a central processing unit or an application processor) or an auxiliary processor 123 that can operate independently or together (e.g., a graphics processing unit, a neural network processing unit ( It may include a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor). For example, if the electronic device 101 includes a main processor 121 and a secondary processor 123, the secondary processor 123 may be set to use lower power than the main processor 121 or be specialized for a designated function. You can. The auxiliary processor 123 may be implemented separately from the main processor 121 or as part of it.

The auxiliary processor 123 may, for example, act on behalf of the main processor 121 while the main processor 121 is in an inactive (e.g., sleep) state, or while the main processor 121 is in an active (e.g., application execution) state. ), together with the main processor 121, at least one of the components of the electronic device 101 (e.g., the display module 160, the sensor module 176, or the communication module 190) At least some of the functions or states related to can be controlled. According to one embodiment, co-processor 123 (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module 180 or communication module 190). there is. According to one embodiment, the auxiliary processor 123 (eg, neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. Artificial intelligence models can be created through machine learning. For example, such learning may be performed in the electronic device 101 itself on which the artificial intelligence model is performed, or may be performed through a separate server (e.g., server 108). Learning algorithms may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but It is not limited. An artificial intelligence model may include multiple artificial neural network layers. Artificial neural networks include deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), restricted boltzmann machine (RBM), belief deep network (DBN), bidirectional recurrent deep neural network (BRDNN), It may be one of deep Q-networks or a combination of two or more of the above, but is not limited to the examples described above. In addition to hardware structures, artificial intelligence models may additionally or alternatively include software structures.

The memory 130 may store various data used by at least one component (eg, the processor 120 or the sensor module 176) of the electronic device 101. Data may include, for example, input data or output data for software (e.g., program 140) and instructions related thereto. Memory 130 may include volatile memory 132 or non-volatile memory 134.

The program 140 may be stored as software in the memory 130 and may include, for example, an operating system 142, middleware 144, or application 146.

The input module 150 may receive commands or data to be used in a component of the electronic device 101 (e.g., the processor 120) from outside the electronic device 101 (e.g., a user). The input module 150 may include, for example, a microphone, mouse, keyboard, keys (eg, buttons), or digital pen (eg, stylus pen).

The sound output module 155 may output sound signals to the outside of the electronic device 101. The sound output module 155 may include, for example, a speaker or a receiver. Speakers can be used for general purposes such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part of it.

The display module 160 can visually provide information to the outside of the electronic device 101 (eg, a user). The display module 160 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling the device. According to one embodiment, the display module 160 may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of force generated by the touch.

The audio module 170 can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module 170 acquires sound through the input module 150, the sound output module 155, or an external electronic device (e.g., directly or wirelessly connected to the electronic device 101). Sound may be output through the electronic device 102 (e.g., speaker or headphone).

The sensor module 176 detects the operating state (e.g., power or temperature) of the electronic device 101 or the external environmental state (e.g., user state) and generates an electrical signal or data value corresponding to the detected state. can do. According to one embodiment, the sensor module 176 includes, for example, a gesture sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, It may include a temperature sensor, humidity sensor, or light sensor.

The interface 177 may support one or more designated protocols that can be used to connect the electronic device 101 directly or wirelessly with an external electronic device (eg, the electronic device 102). According to one embodiment, the interface 177 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

The connection terminal 178 may include a connector through which the electronic device 101 can be physically connected to an external electronic device (eg, the electronic device 102). According to one embodiment, the connection terminal 178 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

The haptic module 179 can convert electrical signals into mechanical stimulation (e.g., vibration or movement) or electrical stimulation that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module 179 may include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

The camera module 180 can capture still images and moving images. According to one embodiment, the camera module 180 may include one or more lenses, image sensors, image signal processors, or flashes.

The power management module 188 can manage power supplied to the electronic device 101. According to one embodiment, the power management module 188 may be implemented as at least a part of, for example, a power management integrated circuit (PMIC).

Battery 189 may supply power to at least one component of electronic device 101. According to one embodiment, the battery 189 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

Communication module 190 is configured to provide a direct (e.g., wired) communication channel or wireless communication channel between electronic device 101 and an external electronic device (e.g., electronic device 102, electronic device 104, or server 108). It can support establishment and communication through established communication channels. Communication module 190 operates independently of processor 120 (e.g., an application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module 190 is a wireless communication module 192 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 194 (e.g., : LAN (local area network) communication module, or power line communication module) may be included. Among these communication modules, the corresponding communication module is a first network 198 (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network 199 (e.g., legacy It may communicate with an external electronic device 104 through a telecommunication network such as a cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., LAN or WAN). These various types of communication modules may be integrated into one component (e.g., a single chip) or may be implemented as a plurality of separate components (e.g., multiple chips). The wireless communication module 192 uses subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module 196 within a communication network such as the first network 198 or the second network 199. The electronic device 101 can be confirmed or authenticated.

The wireless communication module 192 may support 5G networks after 4G networks and next-generation communication technologies, for example, NR access technology (new radio access technology). NR access technology provides high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and access to multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low latency). -latency communications)) can be supported. The wireless communication module 192 may support a high frequency band (eg, mmWave band), for example, to achieve a high data rate. The wireless communication module 192 uses various technologies to secure performance in high frequency bands, for example, beamforming, massive array multiple-input and multiple-output (MIMO), and full-dimensional multiplexing. It can support technologies such as input/output (FD-MIMO: full dimensional MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module 192 may support various requirements specified in the electronic device 101, an external electronic device (e.g., electronic device 104), or a network system (e.g., second network 199). According to one embodiment, the wireless communication module 192 supports Peak data rate (e.g., 20 Gbps or more) for realizing eMBB, loss coverage (e.g., 164 dB or less) for realizing mmTC, or U-plane latency (e.g., 164 dB or less) for realizing URLLC. Example: Downlink (DL) and uplink (UL) each of 0.5 ms or less, or round trip 1 ms or less) can be supported.

The antenna module 197 may transmit or receive signals or power to or from the outside (eg, an external electronic device). According to one embodiment, the antenna module 197 may include an antenna including a radiator made of a conductor or a conductive pattern formed on a substrate (eg, PCB). According to one embodiment, the antenna module 197 may include a plurality of antennas (eg, an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network such as the first network 198 or the second network 199 is connected to the plurality of antennas by, for example, the communication module 190. can be selected. Signals or power may be transmitted or received between the communication module 190 and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (eg, radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module 197.

According to various embodiments, the antenna module 197 may form a mmWave antenna module. According to one embodiment, a mmWave antenna module includes a printed circuit board, an RFIC disposed on or adjacent to a first side (e.g., bottom side) of the printed circuit board and capable of supporting a designated high frequency band (e.g., mmWave band), And a plurality of antennas (e.g., array antennas) disposed on or adjacent to the second side (e.g., top or side) of the printed circuit board and capable of transmitting or receiving signals in the designated high frequency band. can do.

At least some of the components are connected to each other through a communication method between peripheral devices (e.g., bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)) and signal ( (e.g. commands or data) can be exchanged with each other.

According to one embodiment, commands or data may be transmitted or received between the electronic device 101 and the external electronic device 104 through the server 108 connected to the second network 199. Each of the external

electronic devices

102 or 104 may be of the same or different type as the electronic device 101. According to one embodiment, all or part of the operations performed in the electronic device 101 may be executed in one or more of the external

electronic devices

102, 104, or 108. For example, when the electronic device 101 needs to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device 101 may perform the function or service instead of executing the function or service on its own. Alternatively, or additionally, one or more external electronic devices may be requested to perform at least part of the function or service. One or more external electronic devices that have received the request may execute at least part of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device 101. The electronic device 101 may process the result as is or additionally and provide it as at least part of a response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology can be used. The electronic device 101 may provide an ultra-low latency service using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device 104 may include an Internet of Things (IoT) device. Server 108 may be an intelligent server using machine learning and/or neural networks. According to one embodiment, the external electronic device 104 or server 108 may be included in the second network 199. The electronic device 101 may be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

Electronic devices according to various embodiments disclosed in this document may be of various types. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to embodiments of this document are not limited to the above-described devices.

The various embodiments of this document and the terms used herein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various changes, equivalents, or replacements of the embodiments. In connection with the description of the drawings, similar reference numbers may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the relevant context clearly indicates otherwise. As used herein, “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B or C”, “at least one of A, B and C”, and “A Each of phrases such as “at least one of , B, or C” may include any one of the items listed together in the corresponding phrase, or any possible combination thereof. Terms such as "first", "second", or "first" or "second" may be used simply to distinguish one component from another, and to refer to those components in other respects (e.g., importance or order) is not limited. One (e.g., first) component is said to be “coupled” or “connected” to another (e.g., second) component, with or without the terms “functionally” or “communicatively.” Where mentioned, it means that any of the components can be connected to the other components directly (e.g. wired), wirelessly, or through a third component.

The term “module” used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and is interchangeable with terms such as logic, logic block, component, or circuit, for example. It can be used as A module may be an integrated part or a minimum unit of the parts or a part thereof that performs one or more functions. For example, according to one embodiment, the module may be implemented in the form of an application-specific integrated circuit (ASIC).

Various embodiments of the present document are one or more instructions stored in a storage medium (e.g., built-in memory 136 or external memory 138) that can be read by a machine (e.g., electronic device 101). It may be implemented as software (e.g., program 140) including these. For example, a processor (e.g., processor 120) of a device (e.g., electronic device 101) may call at least one command among one or more commands stored from a storage medium and execute it. This allows the device to be operated to perform at least one function according to the at least one instruction called. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. A storage medium that can be read by a device may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' only means that the storage medium is a tangible device and does not contain signals (e.g. electromagnetic waves). This term refers to cases where data is stored semi-permanently in the storage medium. There is no distinction between temporary storage cases.

According to one embodiment, methods according to various embodiments disclosed in this document may be included and provided in a computer program product. Computer program products are commodities and can be traded between sellers and buyers. The computer program product may be distributed in the form of a machine-readable storage medium (e.g. compact disc read only memory (CD-ROM)) or through an application store (e.g. Play StoreTM) or on two user devices (e.g. It can be distributed (e.g. downloaded or uploaded) directly between smart phones) or online. In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored or temporarily created in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

According to various embodiments, each component (e.g., module or program) of the above-described components may include a single or plural entity, and some of the plurality of entities may be separately placed in other components. there is. According to various embodiments, one or more of the components or operations described above may be omitted, or one or more other components or operations may be added. Alternatively or additionally, multiple components (eg, modules or programs) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each component of the plurality of components identically or similarly to those performed by the corresponding component of the plurality of components prior to the integration. . According to various embodiments, operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, or omitted. Alternatively, one or more other operations may be added.

Figure 2 is a block diagram showing a memory management method of the electronic device 101 according to an embodiment of the present disclosure.

In one embodiment, the electronic device 101 may include a user space and a kernel space. The program 140 included in the electronic device 101 can freely access the user space, but may not directly access the kernel space.

In one embodiment, user space may refer to all code that program 140 executes outside of kernel space. User space may be a memory area where all user mode applications operate. Kernel space may be a spare space for executing kernel and kernel extension functions. User space and kernel space may be the same as user space and kernel space. User space may contain various programs and/or libraries that it uses to interact with kernel space.

In one embodiment, user space may include a virtual address space (virtual address space) 211. Kernel space may include a file system (file system, 23).

In one embodiment, the electronic device 101 may enhance security by separating user space and kernel space. The electronic device 101 may perform processes involving hardware operations such as reading and/or writing files in kernel space. The electronic device 101 can manipulate data included in the kernel space using a system call.

In one embodiment, when manipulating data by calling it from kernel space using system calls (e.g., system calls such as read() and/or write()), kernel context switching and user buffers Performance degradation may occur due to memory copying.

In one embodiment, the electronic device 101 can read or write a file mapped to memory. The electronic device 101 can map and use files in a virtual address space using the mmap system call. The electronic device 101 may read and write data and/or files using load and/or store processor instructions instead of read and/or write system calls.

In one embodiment, the electronic device 101 may include a plurality of

nodes

201 and 202. Each of the plurality of

nodes

201 and 202 may have different access speeds. For example, the access speed may be the time it takes for the processor 120 to access a specific address of the memory 130 and obtain data. However, it is not limited to this, and each of the plurality of

nodes

201 and 202 may have the same access speed.

In one embodiment, the electronic device 101 may include a first node 201 and a second node 202. The first node 201 and the second node 202 may have different access speeds. However, it is not limited to this, and the first node 201 and the second node 202 may have the same access speed.

In one embodiment, differences in access speed between memory nodes may be caused by logical factors such as physical distance and/or access latency between the processor 120 (e.g., CPU, application processor) and the memory 130. You can.

In one embodiment, a node may be a bundle of processors and local memory with the same access speed. For example, in two-socket non-uniform memory access (NUMA), the processor and memory mounted on each socket may constitute a node. However, it is not limited to this, and a node consisting of only memory may also exist.

In one embodiment, the electronic device 101 may include zones in which the physical memory of the node is divided according to purpose. The electronic device 101 may set a target zone when allocating memory. When allocating memory, the electronic device 101 sets a preferred zone based on a request flag, and if memory allocation fails in the zone, allocation is made while traversing the zone list. You can try .

In one embodiment, the first node 201 may include a first memory 1311 and the second node 202 may include a second memory 1312. The first memory 1311 and the second memory 1312 may be different types of memory. For example, the first memory 1311 may be a dynamic random access memory (DRAM), and the second memory 1312 may be a persistent memory (PMEM). PMEM can be a memory that can be accessed in byte units like DRAM and includes non-volatility (persistence) of data. The first memory 1311 and the second memory 1312 may have different access latencies depending on their physical characteristics.

In one embodiment, the first node 201 may be a node with a faster access speed than the second node 202.

In one embodiment, an anonymous page 210 represents unread memory from a file and may be a page allocated for general purposes required for execution of a program, such as the heap and/or stack of a process. there is.

In one embodiment, file

pages

220 and 230 may be data structures representing memory containing file data.

File pages

220 and 230 may be managed and/or accessed by a page cache.

File pages

220 and 230 may require relatively slow access speeds compared to the anonymous page 210.

In one embodiment, the anonymous page 210 is mapped directly to the virtual address space 211 and can be accessed according to load and/or store processor instructions. Accordingly, the anonymous page 210 may request an access waiting time faster than the specified access waiting time. The anonymous page 210 may have a faster access latency than the file pages 220 and 230.

In one embodiment, the electronic device 101, under the control of the processor 120, when there is a memory allocation request for the anonymous page 210, the electronic device 101 includes the first node 201, which is a node faster than the specified access speed. 1 An anonymous page 210 can be allocated to memory 1311.

In one embodiment, the electronic device 101, under the control of the processor 120, may determine whether there is a file mapped to the memory when a memory allocation request is made for the file pages 220 and 230. For example, the first file page 220 includes a file mapped to memory, and the file can be mapped and used in the virtual address space 211.

In one embodiment, if the file has pages mapped to memory, the electronic device 101, under control of the processor 120, transfers the file page (e.g., the first file page 220) to a node faster than the specified access speed. A file page (eg, first file page 220) may be allocated to the first memory 1311 included in the first node 201.

In one embodiment, if there are no pages mapped to memory in the file, the electronic device 101, under control of the processor 120, transfers the file page (e.g., the second file page 230) to a node slower than the specified access speed. A file page (eg, the second file page 230) may be allocated to the second memory 1312 included in the second node 202.

In one embodiment, under the control of the processor 120, when a memory allocation request is made, the electronic device 101 selects a node faster than the specified access speed or a node slower than the specified access speed based on the properties and/or type of the page. You can choose.

In one embodiment, under the control of the processor 120, when a memory allocation request is made, the electronic device 101 may select a node faster than a specified access speed or a node slower than the specified access speed based on a user hint.

In one embodiment, under the control of the processor 120, when a memory allocation request is made, the electronic device 101 may select a node faster than a specified access speed or a node slower than the specified access speed based on the file page cache hit rate. .

In one embodiment, the electronic device 101 may allocate pages to the selected node under the control of the processor 120.

In one embodiment, under the control of the processor 120, when a page migration request is made, the electronic device 101 may determine whether to allow page migration based on the properties and/or type of the page.

In one embodiment, under the control of the processor 120, when a page migration request is made, the electronic device 101 may determine whether to allow page migration based on a user hint.

In one embodiment, under the control of the processor 120, when a page migration request is made, the electronic device 101 may determine whether to allow page migration based on whether the file has pages mapped to memory.

In one embodiment, under the control of the processor 120, when a page migration request is made, the electronic device 101 may determine whether to allow page migration based on the file page cache hit rate.

In one embodiment, page migration may be an operation to move an address in memory to another location in logic such as memory compaction.

In one embodiment, the electronic device 101 may manage pages based on mobility attributes to prevent memory fragmentation and improve efficiency. Movable properties may be movable, non-movable, and/or reclaimable. Pages with non-movable properties may not be migrated.

According to FIG. 3, memory management 320 may include a memory checker 322, a migrator 324, and a migration manager 326. The memory management 320, memory checker 322, migrator 324, and migration manager 326 may be software modules that include at least one instruction executed on a processor (e.g., processor 120 in FIG. 1). . In this case, the operations of the memory management 320, the memory checker 322, the migrator 324, and the migration manager 326 can be understood as the operations of the processor 120.

The memory checker 322 can measure latency at the nodes between each memory. Latency may refer to the time required to send a request to a memory (e.g., memory 130 in FIG. 1) and obtain the requested data.

The migrator 324 can perform page migration between layers of a plurality of memories. A page may refer to a data structure for storing data. A page may refer to a space in which a memory area is divided into a certain size. A page may contain file data. Alternatively, a page may refer to an anonymous page containing data requested by a process through a specific function (e.g. malloc). . Page migration may refer to the operation of moving a page containing file data to another layer. The migrator (324) uses fast memory (e.g., DRAM) (310) with relatively low latency and fast access, and slow memory (e.g., persistent memory) (312) with relatively high latency and slow access. , 314), page migration can be performed. The migrator 324 may not perform migration if the first slow memory 312 and the second slow memory 314 are of the same tier. When the memory capacity of the first slow memory (312) is full, the migrator (324) does not migrate pages to the second slow memory (314) of the same tier, but swaps them onto the storage (316). (swap) can be performed. For example, the migrator 324 may swap an anonymous page onto the storage 316 without migrating it. The migrator (324) can reflect the dirty page in the file if its contents have been changed while containing file data. If it is not a dirty page, the migrator (324) can determine that no changes have been made and delete the page. Swap may refer to an operation that utilizes some space in the storage 316 to assist work when there is insufficient memory on the system.

An electronic device (e.g., the electronic device 101 of FIG. 1) can prevent data loss or system errors from occurring due to full memory capacity through swapping on the storage 316. Swapped pages are located on the storage 316, so access speed may be relatively slower than random access memory (RAM). The electronic device 101 uses the storage 316 by performing swap when there is insufficient space in the random access memory (RAM), and when the space in the random access memory (RAM) becomes free again, the memory (e.g. The electronic device 101 can move files or pages onto the DRAM (310) or persistent memory (312, 314) and swap them onto the storage (316) when RAM (random access memory) space is insufficient. Swap out and a flush operation may be performed to rewrite the content of the page to the storage space (e.g., storage 316). The device 101 can read data written through swap on the storage 316 (swap in).

The migration manager (326) can manage the logical tier (328) and migration policy (330). The logical tier 328 may refer to information about a tier classified by a processor (e.g., processor 120 of FIG. 1) based on the latency of the memory. The processor 120 measures the latency on each memory node, and if the difference in latency between one node and another node is less than a specified level (e.g., about 40%), the two nodes are placed in the same tier. Can be classified. The specified level is only an example, is not fixed, and may vary depending on settings. The migration policy 330 may include a policy for path settings when performing page migration.

According to one embodiment, the electronic device 101 sets a tier in consideration of the latency of the memory and sets whether to perform an auto-balancing operation between tiers to efficiently Memory resources can be utilized. Auto-balancing may include page migration operations. A page may refer to a data structure for storing data. A page may refer to a space in which a memory area is divided into a certain size. A page may contain file data. Alternatively, a page may refer to an anonymous page containing data requested by a process through a specific function (e.g. malloc). Page migration may refer to the operation of moving a page containing file data to another layer. Auto-balancing is a demotion operation that moves pages from fast memory (e.g. DRAM), which is relatively fast to access, to slow memory (e.g. persistent memory), which is relatively slow to access, in situations where free memory space is insufficient. may include. In addition, auto-balancing transfers hot pages that are accessed in excess of a specified level from relatively slow access slow memory (e.g. persistent memory) to relatively fast access fast memory (e.g. DRAM) in situations where memory is available. ) can include a promotion action that moves it to the top.

An embodiment in which the processor 120 distinguishes tiers based on the latency on each memory node and sets a migration path based on the tiers will be described with reference to FIGS. 4A to 5B. will be.

According to one embodiment, a processor (e.g., processor 120 of FIG. 1) measures the latency of a plurality of memories and determines a tier between memories based on the measured latency. can be distinguished.

According to FIG. 4A, the processor 120 processes the first tier 410a and the second tier 420a based on the latency difference between the DRAM 412a and the persistent memory (PMEM) 422a exceeding a specified level. It can be divided into: For example, the specified level may mean a level at which the latency of the PMEM 422a differs by less than about 40% based on the latency of the DRAM 412a. This is only an example, and the specified level is not limited to 40% and may vary depending on settings.

The processor 120 may determine that there will be a performance gain when performing migration because there is a clear difference in latency between the DRAM 412a and the PMEM 422a, resulting in a difference in read performance. Migration may refer to the operation of moving a page containing file data to another layer. Migration operations are complex and require CPU performance during the page allocation process, which can cause system delays. Additionally, the processor 120 may perform a migration operation when there is insufficient free space in the memory, but overhead may occur to perform the migration operation. The processor 120 may actually cause further system delay due to overhead for performing a migration operation. The OS logic to perform a migration operation may occupy the CPU. In this situation, the CPU of the processor 120 may be occupied and the response to the user request may be delayed. Overhead may refer to a situation where the reply to a user request is delayed due to a migration operation.

To prevent such system delays, the electronic device according to this document (e.g., the electronic device 101 in FIG. 1) uses a memory that uses DRAM, a memory with a relatively fast read speed, and PMEM, a memory with a relatively slow read speed. It is possible to establish a memory balancing policy between memory tiers with different performance in a memory tiering system and provide a method for efficiently controlling balancing operations.

According to one embodiment, when a memory shortage situation occurs in memory with relatively short latency between memories between different tiers, the processor 420 moves pages to memory with relatively long latency. can be controlled to migrate.

According to FIG. 4B, the processor 120 divides the two memories into one tier (e.g., a first tier) based on the latency difference between the DRAM 412b and the persistent memory (PMEM) 414b not exceeding a specified level. It can be classified into tiers (410b)). According to one embodiment, the processor 420 may control pages not to be migrated between memories within the same tier. If the latency difference between a plurality of memories does not exceed a specified level, the processor 120 has a greater possibility of system delay that may occur during migration than the performance gain obtained by performing migration. You can decide it's big. For this reason, if the latency difference does not exceed a specified level, the processor 120 classifies the plurality of memories into one tier (e.g., the first tier 410b), and between memories within the same tier, page You can control (page) from migrating.

According to FIG. 4C, the processor 120 divides the two memories into one tier (e.g., It can be classified into the first tier (410c). On the other hand, the processor 120 is classified into the second tier 420c based on the latency difference for the first PMEM 422c and the second PMEM 424c compared to the DRAM 412c exceeding a specified level. can do.

The processor 120 may control pages not to be migrated between the DRAM 412c classified as the first tier 410c and the third PMEM 414c. Additionally, the processor 120 may control pages not to be migrated between the first PMEM 422c and the second PMEM 424c classified as the second tier 420c. If the free space of the DRAM 412c is less than a specified level, the processor 120 may migrate pages onto the first PMEM 422c and/or the second PMEM 424c. If the free space of the third PMEM 414c is less than a specified level, the processor 120 may migrate pages onto the first PMEM 422c and/or the second PMEM 424c.

According to FIG. 5A, a processor (eg, processor 120 of FIG. 1) may migrate a page from memory in the first tier 510a to memories in the second tier 520a.

According to one embodiment, an electronic device (e.g., the electronic device 101 in FIG. 1) sets a tier in consideration of the latency of the memory and performs auto-balancing between tiers. You can utilize memory resources efficiently by setting whether to perform an operation. Auto-balancing may include page migration operations. A page may refer to a data structure for storing data. A page may refer to a space in which a memory area is divided into a certain size. A page may contain file data. Alternatively, a page may refer to an anonymous page containing data requested by a process through a specific function (e.g. malloc). Page migration may refer to the operation of moving a page containing file data to another layer. Auto-balancing is a demotion operation that moves pages from fast memory (e.g. DRAM), which is relatively fast to access, to slow memory (e.g. persistent memory), which is relatively slow to access, in situations where free memory space is insufficient. may include. In addition, auto-balancing transfers hot pages that are accessed in excess of a specified level from relatively slow access slow memory (e.g. persistent memory) to relatively fast access fast memory (e.g. DRAM) in situations where memory is available. ) can include a promotion action that moves it to the top.

The processor 120 may migrate a page on the DRAM 512a in the first tier 510a to either the first PMEM 522a or the second PMEM 524a in the second tier 520a. The processor 120 may determine which memory page to migrate first among the first PMEM 522a and the second PMEM 524a based on the fallback list. The fallback list may include information about the migration order determined based on latency for a plurality of memories. For example, if the latency of the first PMEM 522a is relatively lower than that of the second PMEM 524a, the rank of the first PMEM 522a is higher than that of the second PMEM 524a on the fallback list. It can be recorded as being ahead of . The processor 120 checks the free space of the first PMEM 522a based on the fallback list, and if the free space of the first PMEM 522a exceeds a specified level, the processor 120 moves the page of the DRAM 512a to the first PMEM ( 522a) It can be moved to phase 522a). If the free space of the first PMEM 522a is less than a specified level, the processor 120 may check the free space of the second PMEM 524a as a later priority. If the free space of the second PMEM 524a exceeds a specified level, the processor 120 may move the page of the DRAM 512a onto the second PMEM 524a.

Figure 5b illustrates a similar situation without the latencies of the first PMEM 522b and the second PMEM 524b exceeding the specified level. In this case, the fallback list may record the first PMEM 522b and the second PMEM 524b in the same ranking. In a situation where the free space of the DRAM 512b is less than a specified level, the processor 120 may check the free space of both the first PMEM 522b and the second PMEM 524b. The processor 120 may move the page of the DRAM 512b to a memory of the first PMEM 522b and the second PMEM 524b whose free space exceeds a specified level.

According to one embodiment, the processor 120 determines the capacity ( The page of the DRAM 512b can be preferentially moved to a memory with a relatively larger size. In a situation where the free space of the DRAM 512b on the first tier 510b is less than a specified level, the processor 120 blocks other memories on the second tier 520b (e.g., the first PMEM 522b and the second PMEM 524b). )), the page of the DRAM 512b can be migrated. The processor 120 moves pages on the memories on the second tier 520b to another tier when there is insufficient free space in the memories on the second tier 520b or when other pages need to be moved further on the DRAM 512b. It can be moved to memories. However, if no other tier exists, the processor 120 may swap pages onto storage (eg, storage 316 in FIG. 3). Swap may refer to an operation that utilizes some space in the storage 316 to assist work when there is insufficient memory on the system. When moving or swapping pages to another tier, CPU resources may be consumed. In order to reduce CPU resource consumption, the processor 120 may need to control pages to prevent possible migration or swap. Memory with a relatively larger capacity (size) has enough free space, so the probability of migrating or swapping a specific page to another tier may be relatively low. On the other hand, memory with a relatively smaller capacity may have insufficient free space, so the probability of migrating or swapping a specific page to another tier may be relatively high depending on the situation. For this reason, the processor 120 may preferentially move the page of the DRAM 512a to a memory with a relatively larger capacity among the first PMEM 522b and the second PMEM 524b. The processor 120 preferentially moves pages of the DRAM 512a onto memory with a relatively larger capacity among the first PMEM 522b and the second PMEM 524b to migrate specific pages to another tier. This can lower the probability of swapping and reduce CPU resource consumption.

The operations described with reference to FIG. 6 may be implemented based on instructions that can be stored in a computer recording medium or memory (eg, memory 130 in FIG. 1). The illustrated method 600 can be executed by the electronic device previously described with reference to FIGS. 1 to 5B (e.g., the electronic device 101 and the processor 120 of FIG. 1), and the technical features described above are described below. Decided to omit it. The order of each operation in FIG. 6 may be changed, some operations may be omitted, and some operations may be performed simultaneously.

In operation 610, a processor (eg, processor 120 of FIG. 1) may measure the latency of a plurality of memories. The plurality of memories may be, for example, dynamic random access memory (DRAM) and/or persistent memory (PMEM). PMEM can be a memory that can be accessed in byte units like DRAM and includes non-volatility (persistence) of data. This is only an example, and the types of plural memories are not limited to this. Latency may refer to the time it takes to send a request to memory and obtain the requested data.

In operation 615, the processor 120 may measure the latency of a plurality of memories and distinguish tiers between memories based on the measured latency. The processor 120 measures the latency on each memory node, and if the difference in latency between one node and another node is less than a specified level (e.g., about 40%), the two nodes are placed in the same tier. Can be classified. The specified level is only an example, is not fixed, and may vary depending on settings.

At operation 620, the processor 120 may determine whether the plurality of memories are of the same tier.

If the plurality of memories are of the same tier (operation 620 - Yes), in operation 625, the processor 120 may control not to migrate pages between the plurality of memories. Migration may refer to the operation of moving a page containing file data to another layer. Migration operations are complex and require CPU performance during the page allocation process, which can cause system delays. Additionally, the processor 120 may perform a migration operation when there is insufficient free space in the memory, but overhead may occur to perform the migration operation. Overhead may refer to the time and/or memory required to perform a migration operation. The processor 120 may actually cause further system delay due to overhead for performing a migration operation. To prevent such system delays, the electronic device according to this document (e.g., the electronic device 101 of FIG. 1) uses memory tiering that uses DRAM, a memory with a relatively fast read speed, and PMEM, a memory with a relatively slow read speed. It is possible to establish a memory balancing policy between memory tiers with different performance in a memory tiering system and provide a method for efficiently controlling balancing operations.

If the latency difference between a plurality of memories does not exceed a specified level, the processor 120 has a greater possibility of system delay that may occur during migration than the performance gain obtained by performing migration. You can decide it's big. For this reason, if the latency difference does not exceed a specified level, the processor 120 classifies the plurality of memories into one tier (e.g., the first tier 410b), and between memories within the same tier, page You can control (page) from migrating.

If a plurality of memories are of different tiers (operation 620-No), in operation 630, when a memory shortage occurs in memory with relatively low latency, a page is transferred to memory with relatively long latency. ) can be controlled to migrate.

According to one embodiment, the processor 120 may classify the memory into one tier when the difference in latency between the plurality of memories is less than a specified level. The processor 120 may classify the memory into different tiers when the difference in latency between the plurality of memories exceeds a specified level.

According to one embodiment, the processor 120 classifies memories whose latency corresponds to a first level (e.g., 10ns) into the first tier, and selects memories whose latency is relatively longer than the first level. Memories corresponding to the second level (e.g., 20ns) can be classified into the second tier.

According to one embodiment, the processor 120 may classify memory whose latency is within a certain level (e.g., 40%) compared to the first level (e.g., 10 ns) as the first tier. The processor 120 may classify memory whose latency is within a certain level (e.g., 40%) compared to the second level (e.g., 20 ns) as the second tier. The processor 120 determines that the latency of the memory at the third level (e.g., 30 ns) is not within a certain range compared to the first level (e.g., 10 ns) and the second level (e.g., 20 ns), and , can be classified into the third tier.

According to one embodiment, the processor 120 determines whether memory can be allocated to a node belonging to the second tier based on the lack of memory in the node belonging to the first tier, and ensures that migration does not occur between the tiers of the first tier. You can control it so that it does not, and memory can be allocated to nodes belonging to the second tier.

According to one embodiment, the processor 120 configures both the first PMEM (e.g., first PMEM 522b in FIG. 5B) and the second PMEM (e.g., second PMEM 524b in FIG. 5B) with free space at a specified level. If it exceeds , the page of the DRAM 512a may be preferentially moved to a memory with a relatively larger capacity among the first PMEM 522b and the second PMEM 524b.

The processor 120 may differently determine which memory to prioritize migration in response to changes in pressure stall information (PSI) depending on runtime conditions. Pressure stall information (PSI) may refer to an indicator of whether a delay occurs in a task due to a lot of resources being allocated. PSI (pressure stall information) can indicate 'some' time when a delay occurs due to one or more processes lacking resources in memory or CPU. PSI (pressure stall information) can indicate the time when all tasks are delayed due to lack of resources in memory as 'full'. If the full value is high, it means that there is a loss in overall throughput due to a lack of resources.

According to one embodiment, the processor 120 distinguishes tiers between memories based on information about the latency of a plurality of memories, and provides empty space in the order of memories with shorter latency. You can check if it exists. The processor 120 controls to allocate pages on memory where free space is confirmed, and when free space is not confirmed, pages can be allocated on memory of another tier.

According to one embodiment, the latency of a plurality of memories may be measured at least one of a process stage, an initial booting time of the electronic device, or a hot plugging time of the memory, but there is no limitation. For example, the delay time of a plurality of memories may be measured when a specific application is executed, may be measured according to a designated cycle, or may be measured based on the occurrence of an event for measuring the delay time.

According to one embodiment, the processor 120 may obtain information about the latency of the memory from product information of the memory.

The embodiments of this document disclosed in the specification and drawings are merely presented as specific examples to easily explain the technical content according to the embodiments of this document and to aid understanding of the embodiments of this document, and limit the scope of the embodiments of this document. That's not what I want to do. Therefore, the scope of an embodiment of this document should be interpreted as including all changes or modified forms derived based on the technical idea of an embodiment of this document in addition to the embodiments disclosed herein.

Claims

In electronic devices,

a plurality of memories including a first memory and a second memory having lower performance than the first memory; and

Contains a processor,

The processor is

Measure the latency of a plurality of memories,

Determine a tier to be allocated to at least one memory among the plurality of memories based on the measured latency,

In response to a page's migration request,

An electronic device that controls not to perform page migration between memories allocated to the same tier among the plurality of memories.
According to claim 1,

The processor is

If the difference in latency between the first memory and the second memory is less than a specified level, assigning the same tier to the first memory and the second memory,

When the difference in latency between the first memory and the second memory exceeds a specified level, the tier allocated to the first memory and the tier allocated to the second memory are determined differently,

Controlling page migration between memories allocated to different tiers among the plurality of memories,

The above page is

An electronic device that migrates from a memory with a tier corresponding to a relatively low latency to a memory with a tier corresponding to a relatively high latency.
According to claim 1,

The processor is

Allocating a first tier to memories whose latency corresponds to a first level among the plurality of memories,

Allocating a second tier to memories corresponding to a second level among the plurality of memories whose latency is greater than the first level,

Classifying the first memory into the first tier based on the latency of the first memory being measured at the first level,

An electronic device that classifies the second memory into the second tier based on the latency of the second memory being measured at the second level.
According to clause 3,

The processor is

Based on the latency of the third memory being measured at the third level

If the third level is within a certain range from the first level, classify the third memory into the first tier,

If the third level is within a certain range from the second level, classify the third memory into the second tier,

An electronic device that, if the third level is not within a certain range of the first level and the second level, creates a new third tier corresponding to the third level, and classifies the third memory into the third tier.
According to clause 3,

The processor is

Based on the remaining capacity of the memory allocated to the first tier, check whether it is possible to migrate the page stored in the memory allocated to the first tier to the memory allocated to the second tier,

Controlling so that migration does not occur between layers of the first tier,

An electronic device that migrates the page to memory allocated to the second tier.
According to clause 5,

The processor is

An electronic device that selects a memory to perform migration among the memories allocated to the second tier based on at least one of latency or memory size.
According to clause 6,

The processor is

An electronic device that determines which memory to perform migration among the memories allocated to the second tier in response to changes in pressure stall information (PSI) according to runtime situations.
According to clause 1,

The processor is

Check the remaining capacity of each of the plurality of memories in an order determined based on latency,

An electronic device that controls the allocation of pages on memory with a remaining capacity greater than or equal to a specified size.
According to claim 1,

The latency of multiple memories is

An electronic device measured at least one of a process step, an initial booting time of the electronic device, or a hot plugging time of a memory.
According to claim 1,

The processor is

Obtain information about the latency of the memory from the product information of the memory,

An electronic device that checks whether there is free space in a memory sequence with low latency and controls the allocation of resources to the memory for which free space is confirmed.
In a memory management method of an electronic device,

An operation of measuring latency of a plurality of memories;

An operation of determining a tier to be allocated to at least one memory among the plurality of memories based on measured latency; And

In response to a page's migration request,

A method comprising controlling not to perform page migration between memories allocated to the same tier among the plurality of memories.
According to claim 11,

The memory management method of the electronic device is

Further comprising controlling to perform page migration between memories allocated to different tiers among the plurality of memories,

The operation of determining a tier to be allocated to at least one memory among the plurality of memories based on the measured latency

If the difference in latency between the first memory and the second memory is less than a specified level, assigning the same tier to the first memory and the second memory,

When the difference in latency between the first memory and the second memory exceeds a specified level, an operation of determining a tier allocated to the first memory and a tier allocated to the second memory to be different from each other is further performed. Contains,

The above page is

A method of migrating from memory with a tier corresponding to relatively low latency to memory with a tier corresponding to relatively high latency.
According to claim 11,

The operation of determining a tier to be allocated to at least one memory among the plurality of memories based on the measured latency

Allocating a first tier to memories whose latency corresponds to a first level among the plurality of memories,

Allocating a second tier to memories corresponding to a second level among the plurality of memories whose latency is greater than the first level,

Classifying the first memory into the first tier based on the latency of the first memory being measured at the first level,

The method further includes classifying the second memory into the second tier based on the latency of the second memory being measured at the second level.
According to clause 13,

The operation of determining a tier to be allocated to at least one memory among the plurality of memories based on the measured latency

Based on the latency of the third memory being measured at the third level

If the third level is within a certain range from the first level, the third memory is classified into the first tier, or

If the third level is within a certain range from the second level, the third memory is classified into the second tier, or

If the third level is not within a certain range of the first level and the second level, a new third tier corresponding to the third level is created and the third tier is classified into the third tier. How to include it.
According to clause 13,

The memory management method of the electronic device is

An operation of checking whether pages stored in the memory allocated to the first tier can be migrated to the memory allocated to the second tier based on insufficient remaining capacity of the memory allocated to the first tier; and

The method further includes controlling migration to not occur between layers of the first tier and migrating the page to memory allocated to the second tier.