WO2024007974A1 - Clock synchronization method and electronic device - Google Patents

Abstract

Provided in the embodiments of the present application are a clock synchronization method and an electronic device. The method comprises: a first chip in a first slave device triggers a first interruption so as to send a first signal to a second chip in the first slave device; according to the first signal, the second chip triggers a second interruption; the second chip acquires a first moment of triggering the first interruption; and, according to the first moment and a second moment of triggering the second interruption, the second chip performs clock synchronization processing. When clock synchronization is performed between first chips in a plurality of first slave devices and a master device clock, clock synchronization processing is performed by means of second chips of the plurality of first slave devices, so that data of the plurality of first slave devices can be synchronously output.

Description

A clock synchronization method and electronic device

This application claims priority to the Chinese patent application filed with the China Patent Office on July 6, 2022, with the application number 202210798871.7 and the application title "A clock synchronization method and electronic device", the entire content of which is incorporated herein by reference. Applying.

Technical field

The present application relates to the field of terminals, and more specifically, to a clock synchronization method and electronic equipment.

Background technique

In data sharing scenarios, there are situations where multiple devices display the same data at the same time. For example, in a whole-house or multi-room music playback scenario, when multiple devices play the same song at the same time, if the sound of each device cannot be synchronized, There will be polyphonies.

At present, the digital signal processing of most devices has been integrated into the central processing chip, while the sound processing in the analog stage (converting digital sound effect data into output analog signals) is mostly performed by codecs (coder/decoder, codec). ) chip is responsible. If you want to synchronize the output signals of multiple devices, you need to achieve clock synchronization between the codec chips of multiple devices.

Contents of the invention

The present application provides a clock synchronization method and electronic device, which can achieve clock synchronization between the first chip and the second chip of a slave device, thereby achieving synchronization of output signals of multiple slave devices.

In a first aspect, a system is provided. The system includes a master device and a plurality of slave devices. Each slave device in the plurality of slave devices includes a first chip and a second chip. The first chip interacts with the device in a first manner. The master device communicates, and the first method includes a short-range wired connection or a short-range wireless connection, wherein the first chip in the first slave device is used to perform a first clock synchronization process with the master device based on the first method, The first slave device is any one of the plurality of slave devices; the first chip is used to trigger a first interrupt to send a first signal to the second chip in the first slave device; the second The chip is used to trigger the second interrupt according to the first signal; the second chip is also used to obtain the first time when the first interrupt is triggered; the second chip is also used to trigger the first time according to the first time and the second interrupt. At the second moment of the second interrupt, the second clock synchronization process is performed.

In the embodiment of the present application, the first chip in the first slave device is synchronized with the clock of the master device through the first clock synchronization process. The first slave device is any slave device among the plurality of slave devices; the first slave device The second chip in the device performs a second clock synchronization process based on the time when it receives the interrupt signal of the first chip and the time when the first chip triggers the interrupt, to achieve clock synchronization with the first chip. By performing the second clock synchronization process on the second chip of the plurality of first slave devices, the data of the plurality of slave devices can be output synchronously.

In connection with the first aspect, in some implementations of the first aspect, the second chip is also used to obtain the first time when the first interrupt is triggered, including: receiving the third time from the first chip at a third time. A piece of information, the first information is used to indicate the first time, and the third time is earlier than the second time.

In conjunction with the first aspect, in some implementations of the first aspect, the first interrupt is the Nth interrupt triggered by the first chip, and the first information is the fourth interrupt triggered by the first chip. The moment and the first duration are determined. The first duration is the duration between two adjacent interrupts triggered by the first chip, N≥2, N is an integer, or the first information is based on the first slave device. The fifth moment when the first chip triggers the N _1th interrupt and the first duration are determined, N ₁ =N-1, N≥3, and N is an integer.

In conjunction with the first aspect, in some implementations of the first aspect, the first interrupt is the Nth interrupt triggered by the first chip, and the first chip is also used to: trigger the _N1th interrupt to provide the signal to the The second chip sends a second signal, N ₁ =N-1, N≥2, N is an integer; the second chip is also used to trigger a third interrupt according to the second signal; the second chip is also used to Receive second information from the first chip, the second information is used to indicate the sixth time when the _N1th interrupt is triggered; the second chip is also used to indicate the seventh time when the third interrupt is triggered and the third time. The two moments determine the first duration, which is the duration between two adjacent interrupts triggered by the first chip; the second chip is also used to obtain the first moment that triggers the first interrupt, including: the third The second chip determines the first time based on the sixth time and the first duration.

In conjunction with the first aspect, in some implementations of the first aspect, the second chip is further configured to perform a second clock synchronization process based on the first moment and the second moment when the second interrupt is triggered, including: according to The first time and the second time determine a first time offset value; the local clock is adjusted according to the first time offset value.

In connection with the first aspect, in some implementations of the first aspect, the first interrupt is one of M interrupts triggered by the first chip, and the second chip is also used to: obtain the trigger triggered by the first chip. M moments corresponding to M interrupts; M time deviation values are determined based on the M moments and the M moments corresponding to the second chip triggering M interrupts, and the i-th time deviation value among the M time deviation values is It is determined based on the time when the first chip triggers the i-th interrupt and the time when the second chip triggers the i-th interrupt; wherein, the i-th interrupt triggered by the second chip is based on the i-th interrupt triggered by the first chip. Interrupt triggered, M≥2, M is an integer, i=1, 2,...,M.

In conjunction with the first aspect, in some implementations of the first aspect, the second chip is further configured to perform a second clock synchronization process based on the first moment and the second moment when the second interrupt is triggered, including: according to The average of the M time deviation values adjusts the local clock with a first duration as a period; or, adjusts the local clock with a second duration as a period based on the average value of the M time deviation values, and the second duration is longer than the first duration; The first duration is the duration between two adjacent interrupts triggered by the first chip.

In a second aspect, a clock synchronization method is provided. The method is applied to a first system. The first system includes a master device and a plurality of slave devices. Each slave device in the plurality of slave devices includes a first chip and a third slave device. Two chips, the first chip communicates with the master device through a first method, the first method includes a short-range wired connection or a short-range wireless connection, the method includes: the first chip in the first slave device, based on the first The method performs a first clock synchronization process with the master device, and the first slave device is any slave device among the plurality of slave devices; the first chip triggers a first interrupt to send a message to the second slave device among the first slave devices. The chip sends a first signal; the second chip triggers a second interrupt based on the first signal; the second chip obtains the first time that triggers the first interrupt; the second chip triggers the second interrupt based on the first time and At the second moment of the interruption, the second clock synchronization process is performed.

In the embodiment of the present application, the first chip in the first slave device is synchronized with the clock of the master device through the first clock synchronization process. The first slave device is any slave device among the plurality of slave devices; the first slave device The second chip in the device performs a second clock synchronization process based on the time when it receives the interrupt signal of the first chip and the time when the first chip triggers the interrupt, to achieve clock synchronization with the first chip. By performing the second clock synchronization process on the second chip of the plurality of first slave devices, the data of the plurality of slave devices can be output synchronously.

In conjunction with the second aspect, in some implementations of the second aspect, the second chip receives first information from the first chip, and the first information is used to indicate the first moment.

Combined with the second aspect, in some implementations of the second aspect, the second chip receives the first information from the first chip at a third time, and the third time is earlier than the second time.

Combined with the second aspect, in some implementations of the second aspect, the first interrupt is the Nth interrupt triggered by the first chip, and the first information is the fourth interrupt triggered by the first chip. moment and the first duration, the first duration is the duration between two adjacent interrupts triggered by the first chip, N≥2, N is an integer, or the first information is based on the first chip triggering the first interrupt. The fifth moment of N ₁ interruptions and the first duration are determined, N ₁ =N-1, N≥3, and N is an integer.

Combined with the second aspect, in some implementations of the second aspect, the first interrupt is the Nth interrupt triggered by the first chip, and the first chip triggers the _N1th interrupt to send a message to the second chip. The second signal, N ₁ =N-1, N≥2, N is an integer; the second chip triggers a third interrupt according to the second signal; the second chip receives the second information from the first chip, and the second chip The second information is used to indicate the sixth time when the _N1th interrupt is triggered; the second chip determines the first duration based on the seventh time when the third interrupt is triggered and the second time, and the first duration is the first time. The first chip of the slave device triggers the duration between two adjacent interrupts; the second chip determines the first moment based on the sixth moment and the first duration.

Combined with the second aspect, in some implementations of the second aspect, the second chip determines a first time offset value based on the first time and the second time; the second chip adjusts the local time offset value based on the first time offset value. clock.

Combined with the second aspect, in some implementations of the second aspect, the first interrupt is one of M ₁ interrupts triggered by the first chip, and the second chip obtains the M interrupts triggered by the first chip. Corresponding M times; the second chip determines M time deviation values based on the M times and the M times corresponding to the second chip triggering M interrupts, and the i-th time deviation value among the M time deviation values It is determined based on the time when the first chip triggers the i-th interrupt and the time when the second chip triggers the i-th interrupt; wherein, the i-th interrupt triggered by the second chip is based on the i-th interrupt triggered by the first chip. Triggered by interrupts, M≥2, M is an integer, i=1, 2,...,M.

Combined with the second aspect, in some implementations of the second aspect, the second chip uses an average value of the M time deviation values according to the A period of time is used to adjust the local clock; or, the second chip adjusts the local clock to a period of a second period of time based on the average of the M time deviation values, and the second period of time is greater than the first period of time; wherein, the first period of time is The first chip triggers the duration between two adjacent interrupts.

In a third aspect, a clock synchronization method is provided, characterized in that the method is applied to an electronic device. The electronic device includes a first chip and a second chip. The first chip triggers a first interrupt to send a signal to the second chip. Send a first signal; the second chip triggers a second interrupt based on the first signal; the second chip obtains the first time that triggers the first interrupt; the second chip triggers the second interrupt based on the first time and At the second moment, clock synchronization is performed.

Combined with the third aspect, in some implementations of the third aspect, the second chip receives the first information from the first chip at a third time, the first information is used to indicate the first time, the third time The third moment is earlier than the second moment.

Combined with the third aspect, in some implementations of the third aspect, the first interrupt is the Nth interrupt triggered by the first chip, and the first information is the fourth interrupt triggered by the first chip. moment and the first duration, the first duration is the duration between two adjacent interrupts triggered by the first chip, N≥2, N is an integer, or the first information is based on the first chip triggering the first interrupt. The fifth moment of N ₁ interruptions and the first duration are determined, N ₁ =N-1, N≥3, and N is an integer.

Combined with the third aspect, in some implementations of the third aspect, the first interrupt is the Nth interrupt triggered by the first chip, and the first chip triggers the _N1th interrupt to send a message to the second chip. The second signal, N ₁ =N-1, N≥2, N is an integer; the second chip triggers a third interrupt according to the second signal; the second chip receives the second information from the first chip, and the second chip The second information is used to indicate the sixth time when the _N1th interrupt is triggered; the second chip determines the first duration based on the seventh time when the third interrupt is triggered and the second time, and the first duration is the first time. The chip triggers the duration between two adjacent interrupts; the second chip obtains the first moment when the first interrupt is triggered, and the second chip determines the first moment based on the sixth moment and the first duration.

Combined with the third aspect, in some implementations of the third aspect, the second chip determines a first time offset value based on the first time and the second time; the second chip adjusts the local time offset value based on the first time offset value. clock.

Combined with the third aspect, in some implementations of the third aspect, the first interrupt is one of the M ₁ interrupts triggered by the first chip, and the second chip obtains the M interrupts triggered by the first chip. Corresponding M times; the second chip determines M time deviation values based on the M times and the M times corresponding to the second chip triggering M interrupts, and the i-th time deviation value among the M time deviation values It is determined based on the time when the first chip triggers the i-th interrupt and the time when the second chip triggers the i-th interrupt; wherein, the i-th interrupt triggered by the second chip is based on the i-th interrupt triggered by the first chip. Triggered by interrupts, M≥2, M is an integer, i=1, 2,...,M.

Combined with the third aspect, in some implementations of the third aspect, the second chip adjusts the local clock according to the average of the M time deviation values with a first duration as a period; or, the second chip adjusts the local clock according to the M time deviation values. The average value of the time deviation value adjusts the local clock with a second duration as a period, and the second duration is greater than the first duration; wherein the first duration is the duration between two adjacent interrupts triggered by the first chip.

A fourth aspect provides an electronic device, which includes a first chip and a second chip, wherein the first chip is used to trigger a first interrupt to send a first signal to the second chip; the second chip The chip is used to trigger the second interrupt according to the first signal; the second chip is also used to obtain the first time when the first interrupt is triggered; the second chip is also used to trigger the first time according to the first time and the second interrupt. At the second moment of the second interrupt, clock synchronization processing is performed.

Combined with the fourth aspect, in some implementations of the fourth aspect, the second chip is also used to obtain the first time when the first interrupt is triggered, including: receiving a signal from the first chip at a third time. The first information is used to indicate the first time, and the third time is earlier than the second time.

In connection with the fourth aspect, in some implementations of the fourth aspect, the first interrupt is the Nth interrupt triggered by the first chip, and the first information is the fourth interrupt triggered by the first chip. moment and the first duration, the first duration is the duration between two adjacent interrupts triggered by the first chip, N≥2, N is an integer, or the first information is based on the first chip triggering the first interrupt. The fifth moment of N ₁ interruptions and the first duration are determined, N ₁ =N-1, N≥3, and N is an integer.

Combined with the fourth aspect, in some implementations of the fourth aspect, the first chip is also used to trigger the N _1th interrupt to send a second signal to the second chip, N ₁ =N-1, N≥ 2, N is an integer; the second chip is also used to trigger a third interrupt according to the second signal; the second chip is also used to receive second information from the first chip, and the second information is used to Indicates the sixth moment when the _N1th interrupt is triggered; the second chip is also used to determine a first duration based on the seventh moment when the third interrupt is triggered and the second moment, and the first duration is for the first chip The duration between triggering two adjacent interrupts; the second chip is also used to obtain the first moment when the first interrupt is triggered, Including: determining the first moment based on the sixth moment and the first duration.

In connection with the fourth aspect, in some implementations of the fourth aspect, the second chip is further configured to perform clock synchronization processing according to the first moment and the second moment when the second interrupt is triggered, including: according to the first moment A first time offset value is determined from a time point and the second time point; the local clock is adjusted according to the first time offset value.

Combined with the fourth aspect, in some implementations of the fourth aspect, the first interrupt is one of M ₁ interrupts triggered by the first chip, and the second chip is also used to: obtain the trigger of the first chip M moments corresponding to the M interrupts; determine M time deviation values based on the M moments and the M moments corresponding to the second chip triggering M interrupts, and the i-th time deviation value among the M time deviation values It is determined based on the time when the first chip triggers the i-th interrupt and the time when the second chip triggers the i-th interrupt; wherein, the i-th interrupt triggered by the second chip is based on the i-th interrupt triggered by the first chip. Triggered by interrupts, M≥2, M is an integer, i=1, 2,...,M.

In connection with the fourth aspect, in some implementations of the fourth aspect, the second chip is also configured to perform clock synchronization processing according to the first moment and the second moment when the second interrupt is triggered, including: according to the M The average value of the M time deviation values is used to adjust the local clock with a first duration as a period; or, the local clock is adjusted with a second duration as a period based on the average value of the M time deviation values, and the second duration is greater than the first duration; wherein, The first duration is the duration between two adjacent interrupts triggered by the first chip.

In a fifth aspect, a clock synchronization method is provided. The method is applied to a second chip. The second chip is wired to the first chip. The method includes: the second chip triggers a second interrupt according to the first signal, and the second chip is connected to the first chip through a wired connection. A signal is a signal generated by the first chip triggering the first interrupt; the second chip obtains the first time that triggers the first interrupt; the second chip obtains the first time that triggers the first interrupt; the second chip based on the first time and the second time that triggers the second interrupt, Perform clock synchronization.

In conjunction with the fifth aspect, in some implementations of the fifth aspect, the second chip receives first information from the first chip at a third time, the first information is used to indicate the first time, and the third time earlier than this second time.

In conjunction with the fifth aspect, in some implementations of the fifth aspect, the first interrupt is the Nth interrupt triggered by the first chip, and the first information is the fourth interrupt triggered by the first chip. moment and the first duration, the first duration is the duration between two adjacent interrupts triggered by the first chip, N≥2, N is an integer, or the first information is based on the first chip triggering the first interrupt. The fifth moment of N ₁ interruptions and the first duration are determined, N ₁ =N-1, N≥3, and N is an integer.

Combined with the fifth aspect, in some implementations of the fifth aspect, the first interrupt is triggered by the first chip for the Nth time, the second chip receives a second signal, and the second signal is triggered by the first chip. Trigger the signal generated by the N _1th interrupt, N ₁ =N-1, N≥2, N is an integer; the second chip triggers the third interrupt according to the second signal; the second chip receives the signal from the first chip The second information is used to indicate the sixth time when the _N1th interrupt is triggered; the second chip determines the first duration based on the seventh time when the third interrupt is triggered and the second time. A duration is the duration between two adjacent interrupts triggered by the first chip; the second chip determines the first moment based on the sixth moment and the first duration.

In connection with the fifth aspect, in some implementations of the fifth aspect, the second chip determines a first time offset value based on the first time and the second time; the second chip adjusts the local time offset value based on the first time offset value. clock.

Combined with the fifth aspect, in some implementations of the fifth aspect, the first interrupt is one of M ₁ interrupts triggered by the first chip, and the second chip obtains the M interrupts triggered by the first chip. Corresponding M times; the second chip determines M time deviation values based on the M times and the M times corresponding to the second chip triggering M interrupts, and the i-th time deviation value among the M time deviation values It is determined based on the time when the first chip triggers the i-th interrupt and the time when the second chip triggers the i-th interrupt; wherein, the i-th interrupt triggered by the second chip is based on the i-th interrupt triggered by the first chip. Triggered by interrupts, M≥2, M is an integer, i=1, 2,...,M.

Combined with the fifth aspect, in some implementations of the fifth aspect, the second chip adjusts the local clock according to the average of the M time deviation values with a first duration as a period; or, the second chip adjusts the local clock according to the M time deviation values. The average value of the time deviation value adjusts the local clock with a second duration as a period, and the second duration is greater than the first duration; wherein the first duration is the duration between two adjacent interrupts triggered by the first chip.

In a sixth aspect, a chip is provided, including: one or more processors; memory; and one or more computer programs. Wherein, one or more computer programs are stored in the memory, and the one or more computer programs include instructions. When the instruction is executed by the chip, the chip is caused to execute the method in any of the possible implementations of the fifth aspect.

A seventh aspect provides a computer program product containing instructions, which when the computer program product is run on a chip, causes the chip to execute the method described in the fifth aspect.

In an eighth aspect, a chip is provided for executing instructions. When the chip is running, the chip executes the method described in the fifth aspect.

Description of the drawings

Figure 1 is a schematic diagram of an application scenario provided by an embodiment of the present application.

Figure 2 is a schematic diagram of a clock synchronization system.

FIG. 3 is a schematic flow chart of a clock synchronization method provided by an embodiment of the present application.

Figure 4 is a schematic diagram of triggering an interrupt and sending time information that triggers the interrupt provided by an embodiment of the present application.

Figure 5 is a schematic flow chart of a clock synchronization method provided by an embodiment of the present application.

Figure 6 is a schematic diagram of a clock synchronization method provided by an embodiment of the present application.

FIG. 7 is a schematic structural diagram of a clock synchronization device provided by an embodiment of the present application.

FIG. 8 is a schematic structural diagram of a clock synchronization device provided by an embodiment of the present application.

FIG. 9 is a schematic structural diagram of a chip provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

In the description of the embodiments of the present application, unless otherwise stated, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. quantity. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

Figure 1 is a schematic diagram of a scenario applicable to the clock synchronization method provided by the embodiment of the present application.

Figure 1 shows an application scenario of whole-house music playback. In this scenario, at least one slave device is placed in each room, for example, slave device 121 to slave device 126. The slave device can be a music playback device, such as a smart speaker. . Secondly, at least one main device is placed in the whole house, for example, the main device 110. The main device 110 is used to control music playback. When the master device 110 controls music to start playing, the slave devices 121 to 126 need to output sounds synchronously, so as to realize synchronous playback of music in the whole house (for example, including room 1 to room 4).

Exemplarily, the main device 110 may include at least one first chip, which may be a processor. The first chip may include one or more processing units. For example, the processor 110 may include an application processor. , AP), modem processor, controller, memory, video codec, digital signal processor (DSP), etc. Among them, different processing units can be independent devices or integrated in one or more processors.

Among them, the controller may be the nerve center and command center of the main device 110 . The controller can generate operation control signals based on the instruction operation code and timing signals to complete the control of fetching and executing instructions.

A memory may also be provided in the first chip for storing instructions and data. In some embodiments, the memory in the first chip is a cache memory. The memory can store the instructions or data just used or recycled by the first chip. If the first chip needs to use the instruction or data again, it can be directly called from the memory. Repeated access is avoided and the waiting time of the processor 110 is reduced, thus improving the efficiency of the system.

In some embodiments, the first chip may include one or more interfaces. Interfaces may include integrated circuit (inter-integrated circuit, I2C) interface, inter-integrated circuit audio (inter-integrated circuit sound, I2S) interface, pulse code modulation (PCM) interface, universal asynchronous receiver and transmitter (universal asynchronous receiver/transmitter, UART) interface, general-purpose input/output (GPIO) interface, etc.

Among them, the I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the first chip may include multiple sets of I2C buses.

The I2S interface can be used for audio communication. In some embodiments, the first chip may also include multiple sets of I2S buses. The first chip can be coupled with the audio module through the I2S bus to realize communication between the first chip and the audio module.

The PCM interface can also be used for audio communications to sample, quantize and encode analog signals. In some embodiments, the audio module and the wireless communication module may be coupled through a PCM bus interface. Both the I2S interface and the PCM interface can be used for audio communication.

The UART interface is a universal serial data bus used for asynchronous communication. The bus can be a bidirectional communication bus. it will be transmitted The data is converted between serial communication and parallel communication. In some embodiments, the UART interface is generally used to connect the first chip and the wireless communication module. For example: the first chip communicates with the Bluetooth module in the wireless communication module through the UART interface to implement the Bluetooth function. In some embodiments, the audio module can transmit audio signals to the wireless communication module through the UART interface to implement the function of playing music through the Bluetooth headset.

The GPIO interface can be configured through software. The GPIO interface can be configured as a control signal or as a data signal. In some embodiments, the GPIO interface can be used to connect the first chip to the display screen, wireless communication module, audio module, etc. The GPIO interface can also be configured as an I2C interface, I2S interface, UART interface, etc.

The wireless communication function of the main device 110 can be implemented through antenna 1, antenna 2, mobile communication module, wireless communication module, modem processor, baseband processor, etc.

Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in master device 110 may be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example: Antenna 1 can be reused as a diversity antenna for a wireless LAN. In other embodiments, antennas may be used in conjunction with tuning switches.

The mobile communication module can provide wireless communication solutions including 2G/3G/4G/5G applied to the main device 110. The mobile communication module may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module can receive electromagnetic waves through the antenna 1, perform filtering, amplification and other processing on the received electromagnetic waves, and transmit them to the modem processor for demodulation. The mobile communication module can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves through the antenna 1 for radiation. In some embodiments, at least part of the functional modules of the mobile communication module may be disposed in the first chip. In some embodiments, at least part of the functional modules of the mobile communication module may be provided in the same device as at least part of the modules of the first chip.

The main device 110 may also include a wireless communication module. The wireless communication module may provide a wireless local area network (WLAN) (such as a wireless fidelity (Wi-Fi) network) applied to the main device 110. , Bluetooth (bluetooth, BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication technology (near field communication, NFC), infrared technology (infrared, IR), etc. Wireless communication solutions. The wireless communication module may be one or more devices integrating at least one communication processing module. The wireless communication module receives electromagnetic waves through the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the first chip. The wireless communication module can also receive the signal to be sent from the first chip, frequency modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 for radiation.

The slave device (eg, any one of slave device 121 to slave device 126) may include the first chip and the second chip. The second chip may be an audio module. Specifically, the audio module is used to convert digital audio information into an analog audio signal output, and is also used to convert analog audio input into a digital audio signal. The audio module can also be used to encode and decode audio signals. The audio module can include a hardware codec (encode and decode, codec) chip for audio collection and playback. When audio is to be played, the first chip sends the audio digital signal to the codec chip through the I2S bus, and then the second chip converts the digital signal into an analog signal (ie, D/A conversion) and then plays it out. The codec can also perform corresponding processing on audio signals, such as volume control, equalize (EQ) control, etc.

The second chip can also be connected to various peripherals, such as a microphone (MIC), an earpiece (earpiece), a speaker (speaker), etc. There is a power amplifier (PA) between the codec and the peripherals, which is used to amplify the power of the audio signal and amplify the volume of the sound unit.

The slave device can implement audio functions through audio modules, speakers, receivers, microphones, headphone interfaces, and application processors. Such as music playback, recording, etc.

The first chip of the slave device can interact with the first chip of the master device 110 through a wired or wireless communication network. The format or standard of the communication network is not limited. It can be a wide area network, a local area network, a point-to-point connection, etc., or any combination thereof. .

In one implementation, as shown in FIG. 2 , the master device 110 and the slave devices 121 to 126 interact through a power line communication (PLC) network. Among them, the main device 110 is used to modulate user Ethernet data and then transmit it on the power line. The slave device filters out the modulated signal through a filter, and then demodulates it to obtain the original communication signal. The first chips of the main device can communicate with each other through a gigabit ethernet (GE) interface. Each first chip of the main device 110 can be connected to a PLC loop, for example, the loop shown in Figure 2 1. Loop 2 and Loop 3. The loop 1 to loop 3 can be connected to slave devices respectively. For example, loop 1 is connected to the slave device 124 of room 3; loop 2 can be connected to the slave device 125 and slave device 126 of room 4; loop 3 can be connected to room 1 and slave devices in room 2 (e.g., slave devices 121 to 123), thus The interaction between master and slave devices can be realized through the PLC loop.

The master device 110 and the first chip of the plurality of slave devices have respective clock systems. The clock system performs timing according to predefined rules; the time rule can be a time system defined according to international standards, or a time standard defined according to a local LAN. The first chip of the slave device can calibrate its own clock system through the PLC network, that is, clock synchronization can be achieved between the first chips of multiple devices and the first chip of the master device 110 . If synchronization of the final output signal is to be achieved, clock synchronization between the second chips of multiple slave devices is required. Therefore, how to calibrate the clock system of the second chip using the clock system of the first chip as a reference has become an urgent problem to be solved.

Assume that the time information of the first chip is represented by T ₁ and the time information of the second chip is represented by T ₂ , and assume that T ₂ =T ₁ +T _offset , that is, the clock systems of the first chip and the second chip are at the same time T _offset time deviation of the displayed time information. The purpose of clock synchronization in the embodiment of this application is to estimate and eliminate the time offset T _offset .

FIG. 3 is a schematic flow chart of a clock synchronization method 300 provided by an embodiment of the present application. The method 300 shown in FIG. 3 may be applied to the system 200 shown in FIG. 2 , for example. The method may be executed by a first slave device, for example, the first slave device is any one of the slave devices 121 to 126 . The first slave device includes a first chip and a second chip.

S301. The first chip performs first clock synchronization processing with the master device based on the first method.

The first method may be a connection method for the first chip to communicate with the host device. For example, the first method includes a short-range wireless connection or a short-range wired connection. The first clock synchronization process may be a clock synchronization process based on a clock synchronization protocol (eg, Precision Time Protocol, or G.hn standard).

Optionally, S302, the first chip receives the first data from the master device, and the first data carries the first time timestamp T ₀ .

The first data may be audio data, picture data or video data, for example. The first timestamp T ₀ may be determined by the master device, for example, the local time of the master device when the master device sends the first data.

S303. The first chip triggers an interrupt to send an interrupt signal to the second chip. Correspondingly, the second chip triggers an interrupt according to the interrupt signal.

Specifically, as shown in Figure 4, the first chip can trigger an interrupt at a first time interval, and the duration of the first time interval is T. That is, the first chip triggers a scheduled interrupt, and the timing duration is the duration of the first time interval. T. The first chip triggering an interrupt can be understood as the first chip receiving or generating an interrupt signal (for example, high level, low level, rising edge, falling edge or pulse signal) to trigger the interrupt. For example, the first chip The chip triggers a GPIO interrupt. The value of the first time interval T can be set according to the actual situation. For example, the value of T can be 100ms, that is, every 100ms, the first chip generates an interrupt and sends an interrupt signal to the second chip.

Taking an interrupt triggered by the first chip as an example, the first chip can trigger a first interrupt to send a first signal to the second chip; the second chip triggers a second interrupt based on the first signal.

S304: The second chip obtains the time information of the interrupt triggered by the first chip.

The time information at which the first chip triggers an interrupt includes information at each time the first chip triggers an interrupt. For example, the time information of the first chip is a time value corresponding to each time the first chip triggers an interrupt. The time value is, for example, a network time reference (NTR) value. The time when the first chip triggers the Nth interrupt can be expressed as T ₁ , T ₁ ={t _{1_1} , t _{1_2} ...t _{1_n} }, where t _{1_n} represents the time when the first chip triggers the Nth interrupt, and N is greater than or equal to 2 is a positive integer.

In one example, the first chip sends time information when the first chip triggers the interrupt to the second chip.

Taking an interrupt triggered by the first chip as an example, the first chip triggers the first interrupt at the first moment; the second chip triggers the second interrupt at the fourth moment, and the second interrupt is triggered based on the first interrupt. The first chip sends first information to the second chip, the first information indicates the first time, and the first information may include the NTR value of the first time. Wherein, the first interrupt may be the Nth interrupt triggered by the first chip, N≥2, and N is an integer.

In a possible implementation, the first chip sends the first information before the first time to ensure the accuracy of clock calibration.

For example, the first chip sends the first information to the second chip at a third time, which is a time between the first time and the second time, or in other words, the first time and the second time. The duration between the three moments is less than the duration T of the first time interval. The second time is the time when the first chip triggers the N-1th interrupt.

The NTR value of the first moment sent by the first chip at the third moment may be determined by the second moment and the duration T of the first time interval, or by the moment when the first chip triggers the first interrupt and the third time. The duration T of a time interval is determined. That is to say, the first chip can determine the information of the first time based on the information of the known time before the first time.

For example, the first chip can record the NTR value at the moment when the interrupt is triggered for the first time (recorded as the first NTR value). then the first time The NTR value at the moment is the sum of the first NTR value and the duration T of (N-1) first time intervals; when N is greater than or equal to 3, the NTR value at the first moment can also be the second NTR value and the The sum of the duration T of the first time interval, the second NTR value is the NTR value at the time when the first chip triggers the N-1th interrupt. For example, the first chip can record the time at which the N-1th interrupt is triggered. NTR value.

It should be understood that the first chip sending the first information at the third time can cause the second chip to receive the information at the first time before the fourth time.

In another example, the second chip determines the time information at which the first chip triggers the interrupt.

Specifically, taking the N-1th interrupt (first interrupt) and the Nth interrupt (second interrupt) triggered by the first chip as an example, the first chip triggers the first interrupt at the first moment, and triggers the first interrupt at the second moment. The second interrupt is triggered; in response to the first interrupt and the second interrupt, the second chip triggers a third interrupt and a fourth interrupt at a third time and a fourth time respectively. The second chip receives the second information sent by the first chip at the fifth time, the second information indicates the time, and the fifth time is a time between the third time and the fourth time; the third time The second chip determines the duration T of the first time interval based on the three moments and the fourth moment, and the second chip determines the time information of the second moment based on the second information and the duration T of the first time interval, N≥2, N is an integer.

S305: The second chip performs a second clock synchronization process based on the time information of the first chip triggering the interrupt and the time information of the second chip triggering the interrupt.

Specifically, the second chip determines the time offset T _offset based on the time information of the first chip triggering the interrupt and the time information of the second chip triggering the interrupt, and eliminates T _offset .

Wherein, the time information of the second chip triggering the interrupt includes information of the time when the second chip triggers the interrupt each time. It can be understood that the second chip triggers an interrupt according to the interrupt triggered by the first chip. The first chip triggers N interrupts. Correspondingly, the second chip triggers N interrupts. The time when the second chip triggers the interrupt can be expressed as T ₂ , T ₁ ={t _{2_1} , t _{2_2} ...t _{2_n} }, where , t _{2_n} represents the time when the second chip triggers the Nth interrupt, N≥2, N is an integer. T ₂ and T ₁ correspond one to one.

The time offset T _offset between the first chip and the second chip can be determined by the time offset t offset_n between the time t _{2_n} when the second chip triggers the interrupt for the Nth time and the time t _{1_n} when the first chip triggers the interrupt for the _Nth time. composition. T _offset = {t _{offset_1} , t _{offset_2,} ..., t _{offset_n} }, t _{offset_n} = t _{2_n} – t _{1_n} .

The second chip can calibrate the local time according to the value of T _offset every time T of the first time interval.

Optionally, the second chip can determine the deviation law of the time deviation according to the values of multiple time deviations T _offset .

For example, the second chip can determine an average of multiple time deviation values, and the average of the time deviations can represent the time length T of the second chip's local time every first time interval compared to that of the first chip. The first time offset value of the local time offset.

For example, the second chip can calibrate the local time according to the deviation rule within the first time period without the first chip needing to send the time information for the first chip to trigger the interrupt. The length of the first time period may be the length of M first time intervals, where M is a positive integer greater than or equal to 2. For example, the value of M may be 1,000.

For another example, the second chip can determine the second time offset value of the local time of the second chip compared to the local time offset of the first chip at every second time interval based on the plurality of time offset values, wherein, The duration of the second time interval may be greater than the duration of the first time interval. Subsequently, the second chip can also calibrate the local time every second time interval according to the deviation rule. For example, the second chip can directly calibrate the local time according to the second time deviation value, or the second chip can calibrate the local time directly according to the second time deviation value. The second chip may receive the time information of the first chip triggering the interrupt sent by the first chip every second time interval, and calibrate the local time based on the time information of the first chip triggering the interrupt.

That is to say, the second chip can perform time calibration according to the timing interrupt #1 triggered by the first chip during the first time period (the timing duration is the duration of the first time interval). After the first duration, the second chip Self-calibration can be performed according to the time deviation rule; or, after the first time period, the second chip receives the interrupt signal sent by the first chip and the time information of the first chip triggering the interrupt at the second time interval according to the time deviation rule. , and local time calibration is performed based on the time information of the first chip triggering the interrupt. The length of the second time interval is longer than the length of the first time interval, thereby saving data transmission resources.

For example, the first chip can trigger n timing interrupts starting from time t ₀ , and the timing duration is t; the second chip determines n time deviation values based on the n interrupts; the second chip determines n time deviation values based on the n time deviations. The value determines the time deviation rule; after time t ₀ +nt, the second chip can calibrate the local time every time t according to the time deviation rule without processing the time information sent by the first chip that triggers the interrupt, or , the first chip does not need to trigger an interrupt after time _{t 0} +nt; or, the second chip calibrates the local time every time t ₁ according to the time deviation law after time t 0 +nt without processing the first The time information of the first chip triggering the interrupt sent by one chip, t ₁ can be greater than t; optionally, starting from the time t ₀ +mt, the second chip can also continue to receive the A chip triggers the first time information of the interrupt, and re-determines multiple time deviation values based on the first time information, and re-determines the time deviation law, m>n, m, n is a positive integer. Optionally, starting from time t ₀ +mt, the period in which the second chip receives the first time information may be greater than the timing duration t. For example, the second chip may determine a time deviation every integer multiple of the timing duration.

Optionally, S306, the first chip sends the first data to the second chip.

Correspondingly, the second chip receives the first data.

Optionally, S307, the second chip determines a second timestamp of the first data, and the second timestamp is determined based on T ₀ and the time offset value T _offset .

The clock synchronization method provided by the embodiment of the present application will be described in detail below with reference to FIG. 5 . The method is applied to the first slave device.

S501, the first chip triggers N interrupts, the N interrupts are scheduled interrupts, and the scheduled duration is t.

The time when the first chip triggers the Nth interrupt is represented as T ₁ , T ₁ ={t _{1_1} , t _{1_2} ...t _{1_n} }, and t _{1_n} represents the time when the first chip triggers the Nth interrupt.

Correspondingly, the second chip triggers N interrupts, and the N interrupts triggered by the second chip can be understood as interrupt responses to the N interrupts triggered by the first chip. In other words, in response to N interrupts triggered by the first chip, the second chip triggers N interrupts. The time when the second chip triggers the Nth interrupt is expressed as T ₂ ={t _{2_1} , t _{2_2} ...t _{2_n} }, t _{2_n} represents the time when the Nth interrupt is triggered, N≥2, and N is an integer.

S502, the second chip obtains the information of T ₁ .

Take the first chip triggering the second interrupt at time t _{1_2} and the second chip triggering the second interrupt at time t _{2_2} as an example.

In one example, the first chip may send the NTR value of t _{1_2} , and accordingly, the second chip receives the NTR value of t _{1_2} .

Referring to (a) of Figure 6, the first chip can send the NTR value of t _{1_2} at time t _1. Time t ₁ is a time between t _{1_1} and t _{1_2} , that is, the time between t ₁ and t _{1_1} is less than the time The interval t, for example, the time between t ₁ and t _{1_1} can be 50ms. Among them, t _{1_2} =t _{1_1} +t. The first chip can send the NTR value of t _{1_2} at time t ₁ , which can reduce the calculation error caused by the second chip not receiving the NTR value of t _{1_2} in time.

Correspondingly, the second chip receives the NTR value of t _{1_2} at time t ₂ .

In another example, the second chip determines the NTR value of t _{1_2} .

Referring to (b) of FIG. 6 , the second chip receives the NTR value of t _{1_1} sent by the first chip at time t ₃ at time t ₃ , and time t ₄ is a time between t _{1_1} and t _{1_2} . The second chip determines the timing duration t based on t _{2_1} and t _{2_2} ; the second chip determines the NTR value of t _{1_2} based on the determined timing duration t and the NTR value of t _{1_1} . t _{1_2} =t _{1_1} +t.

Among them, the time interval between t ₃ and t _{2_1} is less than t.

S503: The second chip determines the time offset T _offset based on the information of T ₁ and the information of T ₂ .

Among them, T ₂ includes N times when the second chip triggers N interrupts. The second chip can read the local clock and obtain the information of _T2 every time the interrupt is triggered. For example, the second chip can read the NTR value at time t _{2_2} that triggers the second interrupt.

The second chip determines a primary clock offset t _{offset_1} based on the received NTR value of t _{1_2} and the NTR value of t _{2_2} . Among them, t _{1_2} =t _{1_1} +t.

The values of t _{1_1} , t _{2_2} and t _{offset_1} satisfy the following relationship:
t _{offset_1} =t _{2_2} -(t _{1_1} +t)+t _delay (1)

Among them, t _delay is the time delay between the second chip responding to the interrupt signal triggered by the first chip and the first chip triggering the interrupt. t _delay is usually at the nanometer level. Therefore, t _delay is negligible relative to t _{offset_1} . Right now:
t _{offset_1} =t _{2_2} -(t _{1_1} +t) (2)

In the above relationship (2), t _{offset_1} can be understood as the local time t _{2_2} when the second chip triggers the second second interrupt and the local time t _{1_2} of the first chip when the first chip triggers the second first interrupt. The deviation between them, or in other words, the time deviation of the second chip relative to t _{1_2} of the first chip, using the clock system of the first chip as a reference.

It should be understood that the value of t _{offset_1} can be positive, negative, or 0, that is, taking the clock system of the first chip as a reference, the time of the second chip is ahead, behind, or equal to that of the first chip.

It can be understood that the second chip determines a value of time offset T _offset every time interval t, T _offset ={t _{offset_1} , t _{offset_2} ,..., t _{offset_n} }, n is a positive integer.

Optionally, S504, the second chip determines the time deviation rule according to the T _offset .

The time deviation rule can be referred to the description in S304 and will not be described again.

Therefore, the second chip can calibrate the clock system of the second chip according to the time deviation law and the clock system of the first chip as a reference. local time to achieve clock synchronization between the second chip and the first chip.

Optionally, in S505, the second chip may receive the first data from the master device through the first chip, and the first data carries the first timestamp.

Optionally, S506, the second chip can determine the second timestamp of the first data according to the time deviation value or time deviation law.

For example, the first time stamp of the first data is T ₀ , the time offset value determined by the second chip is T _offset , the second time stamp is T ₁ , T ₁ =T ₀ +T _offset .

The above is a clock synchronization method between the first chip and the second chip in the first slave device. It can be understood that the first chip and the second chip can be implemented between the first chip and the second chip of multiple slave devices based on the above method. Chip time synchronization. Therefore, when multiple slave devices receive the first data from the master device, the multiple slave devices can realize synchronous output of the first data based on the above method.

Figure 7 shows a schematic block diagram of a device 700 provided by an embodiment of the present application. The device 700 may be provided in the above-mentioned first slave device, and the device 700 may be the first chip in the first slave device. The device 700 includes: a processing unit 710 for performing a first clock synchronization process, triggering an interrupt, and Extract the local clock; the transceiver unit 720 is used to send an interrupt signal and information, for example, the extracted local clock information.

Figure 8 shows a schematic block diagram of a device 800 provided by an embodiment of the present application. The device 800 may be provided in the above-mentioned first slave device. The device 800 may be a second chip in the first slave device. The device 800 includes: a processing unit 810 that performs second clock synchronization processing, triggers interrupts and extracts local Clock; transceiver unit 820, used to receive interrupt signals and information.

For the case where the device is implemented in the form of a chip, please refer to the schematic structural diagram of the chip shown in Figure 9 . The chip shown in Figure 9 includes a processor 901 and an interface 902. The number of processors 901 may be one or more, and the number of interfaces 902 may be multiple. Interface 902 is used for signal reception and transmission. Optionally, the chip may include memory 903. The memory 903 is used to store necessary program instructions and data for the chip. The chip provided by the embodiment of the present application can be used to support the electronic device to implement the functions involved in the first chip and/or the second chip in the above method embodiment, for example, determining or processing the data and information involved in the above method. At least one.

The embodiment of the present application provides a system, including a master device and multiple slave devices, and the system is used to implement the technical solutions in the above embodiments. The implementation principles and technical effects are similar to the above-mentioned method-related embodiments, and will not be described again here.

Embodiments of the present application provide a readable storage medium that contains instructions that, when the instructions are run on the first chip of the first slave device, cause the first chip of the first slave device to execute Technical solution of the above embodiment. The implementation principles and technical effects are similar and will not be described again here.

Embodiments of the present application provide a readable storage medium that contains instructions that, when the instructions are run on a second chip of a first slave device, cause the second chip of the first slave device to execute Technical solution of the above embodiment. The implementation principles and technical effects are similar and will not be described again here.

Embodiments of the present application provide a chip. The chip is used to execute instructions. When the chip is running, the technical solutions in the above embodiments are executed. The implementation principles and technical effects are similar and will not be described again here.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments of the present application.

Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be described again here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application are essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code. .

The above are only specific implementation modes of the present application, but the protection scope of the embodiments of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes within the technical scope disclosed in the embodiments of the present application. or replacement, all should be covered by the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims (14)

1. A clock synchronization method, characterized in that the method is applied to electronic equipment, the electronic equipment includes a first chip and a second chip, and the method includes:

   The first chip triggers a first interrupt to send a first signal to the second chip;

   The second chip triggers a second interrupt according to the first signal;

   The second chip obtains the first moment when the first interrupt is triggered;

   The second chip performs clock synchronization processing based on the first time and the second time when the second interrupt is triggered.
2. The method of claim 1, wherein the second chip obtains the first moment when the first interrupt is triggered, including:

   The second chip receives the first information from the first chip at a third time, the first information is used to indicate the first time, and the third time is earlier than the second time.
3. The method of claim 2, wherein the first interrupt is the Nth interrupt triggered by the first chip, and the first information is the Nth interrupt triggered by the first chip. Determined by four moments and a first duration, the first duration is the duration between two adjacent interrupts triggered by the first chip, N≥2, N is an integer, or the first information is based on the The fifth moment when the first chip triggers the N _1th interrupt and the first duration are determined, N ₁ =N-1, N≥3, and N is an integer.
4. The method of claim 1, wherein the first interrupt is the Nth interrupt triggered by the first chip, and the method further includes:

   The first chip triggers the N _1th interrupt to send a second signal to the second chip, N ₁ =N-1, N≥2, N is an integer;

   The second chip triggers a third interrupt according to the second signal;

   The second chip receives second information from the first chip, and the second information is used to indicate the sixth moment when the _N1th interrupt is triggered;

   The second chip determines a first duration based on the seventh moment when the third interrupt is triggered and the second moment, where the first duration is the duration between two adjacent interrupts triggered by the first chip;

   The second chip obtains the first moment when the first interrupt is triggered, including:

   The second chip determines the first time based on the sixth time and the first duration.
5. The method according to any one of claims 1 to 4, characterized in that the second chip performs clock synchronization processing according to the first time and the second time when the second interrupt is triggered, including:

   The second chip determines a first time deviation value based on the first time and the second time;

   The second chip adjusts the local clock according to the first time offset value.
6. The method according to any one of claims 1 to 4, wherein the first interrupt is one of M interrupts triggered by the first chip, and the method further includes:

   The second chip obtains M times corresponding to the first chip triggering the M interrupts;

   The second chip determines M time deviation values based on the M times and the M times corresponding to the second chip triggering M interrupts, and the i-th time deviation value among the M time deviation values is based on The moment when the first chip triggers the i-th interrupt and the moment when the second chip triggers the i-th interrupt are determined;

   Wherein, the i-th interrupt triggered by the second chip is triggered according to the i-th interrupt triggered by the first chip, M≥2, M is an integer, i=1, 2,...,M.
7. The method of claim 6, wherein the second chip performs clock synchronization processing based on the first time and the second time when the second interrupt is triggered, including:

   The second chip adjusts the local clock according to the average value of the M time deviation values with a first duration as a period; or,

   The second chip adjusts the local clock according to the average value of the M time deviation values with a second duration as a period, and the second duration is greater than the first duration;

   Wherein, the first duration is the duration between two adjacent interrupts triggered by the first chip.
8. An electronic device, characterized in that the electronic device includes a first chip and a second chip, and the first chip and the second chip are wired, wherein,

   The first chip is used to trigger a first interrupt to send a first signal to the second chip;

   The second chip is used to trigger a second interrupt according to the first signal;

   The second chip is also used to obtain the first moment when the first interrupt is triggered;

   The second chip is also configured to perform clock synchronization processing based on the first time and the second time when the second interrupt is triggered.
9. The electronic device according to claim 8, characterized in that the second chip is also used to obtain the first moment when the first interrupt is triggered, including:

   First information from the first chip is received at a third time, the first information is used to indicate the first time, and the third time is earlier than the second time.
10. The electronic device according to claim 9, wherein the first interrupt is the Nth interrupt triggered by the first chip, and the first information is based on the first interrupt triggered by the first chip. The fourth moment and the first duration are determined, the first duration is the duration between two adjacent interrupts triggered by the first chip, N≥2, N is an integer, or the first information is based on the The fifth moment when the first chip triggers the N _1th interrupt and the first duration are determined, N ₁ =N-1, N≥3, and N is an integer.
11. The electronic device according to claim 8, characterized in that the first chip is also used to trigger the N _1th interrupt to send a second signal to the second chip, N ₁ =N-1, N≥ 2, N is an integer;

    The second chip is also used to trigger a third interrupt according to the second signal;

    The second chip is also configured to receive second information from the first chip, where the second information is used to indicate the sixth moment when the _N1th interrupt is triggered;

    The second chip is also configured to determine a first duration based on the seventh moment when the third interrupt is triggered and the second moment, where the first duration is between two adjacent interrupts triggered by the first chip. duration;

    The second chip is also used to obtain the first moment when the first interrupt is triggered, including:

    The first time is determined based on the sixth time and the first duration.
12. The electronic device according to any one of claims 8 to 11, characterized in that the second chip is further configured to perform clock synchronization based on the first time and the second time when the second interrupt is triggered. Processing, including:

    Determine a first time deviation value based on the first time and the second time;

    Adjust the local clock according to the first time offset value.
13. The electronic device according to any one of claims 8 to 11, wherein the first interrupt is one of M interrupts triggered by the first chip, and the second chip is also used for:

    Obtain M times corresponding to the first chip triggering the M interrupts;

    M time deviation values are determined based on the M times and the M times corresponding to the second chip triggering M interrupts. The i-th time deviation value among the M time deviation values is based on the first chip. The moment when the i-th interrupt is triggered and the moment when the second chip triggers the i-th interrupt are determined;

    Wherein, the i-th interrupt triggered by the second chip is triggered according to the i-th interrupt triggered by the first chip, M≥2, M is an integer, i=1, 2,...,M.
14. The electronic device according to claim 13, wherein the second chip is further configured to perform clock synchronization processing based on the first time and the second time when the second interrupt is triggered, including:

    Adjust the local clock according to the average value of the M time deviation values with a first duration as a period; or,

    Adjust the local clock according to the average value of the M time deviation values with a second duration as a period, and the second duration is longer than the first duration;

    Wherein, the first duration is the duration between two adjacent interrupts triggered by the first chip.