WO2024092961A1

WO2024092961A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2024092961A1
Application number: PCT/CN2022/137471
Authority: WO
Inventors: 魏丹清; 罗清威
Original assignee: 武汉新芯集成电路制造有限公司
Priority date: 2022-10-31
Filing date: 2022-12-08
Publication date: 2024-05-10
Also published as: CN115621352A

Abstract

Provided in the present invention are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a substrate, which has a first surface and a second surface facing away from each other; and a first ion-doped region and a second ion-doped region, which have opposite doping types, wherein the first ion-doped region extends from the first surface into the substrate, the second ion-doped region extends towards the second surface from the side of the first ion-doped region that is away from the first surface, the second ion-doped region includes at least two layers of ion implantation regions, the ion doping concentrations of the layers of ion implantation regions increase layer by layer in a direction from the first surface to the second surface, and the widths of the layers of ion implantation regions increase layer by layer in a direction parallel to the first surface, such that the first ion-doped region and the second ion-doped region form a graded junction. The technical solution of the present invention can improve the detection efficiency of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof.

Background technique

Avalanche photodiode is a P-N junction type light detection diode, which uses the avalanche multiplication effect of carriers to amplify the photoelectric signal to improve the sensitivity of detection. The avalanche photodiode structures currently used are guard ring type and pull-through (also known as pass) type. The former is a ring-shaped isolation structure deposited on the basis of the latter to prevent avalanche breakdown at the edge of the P-N junction under high reverse voltage. The currently commonly used pull-through avalanche photodiode (read-through APD, also known as RAPD) often uses a Read diode structure (i.e., N+PIP+ type structure) that is easy to produce an avalanche multiplication effect. In which the P+ side receives light; I is a low-doped area close to the intrinsic, where most of the incident photons are absorbed and generate photogenerated carriers; the multiplied high electric field area is concentrated in a narrow area near the P-N+ junction; N+ and P+ are highly doped and low-resistance, which are used to reduce the contact resistance to facilitate connection with the electrode.

Referring to a semiconductor device shown in FIG. 1a and FIG. 1b, it is a P-N junction structure, and its P-type material is composed of three parts. After photons are injected from the P+ layer 11 and enter the intrinsically doped I (p) layer 12, the material absorbs the light energy and generates primary electron-hole pairs. At this time, the photoelectrons are accelerated by the weaker electric field of the depletion layer in the I layer 12, and move to the P-N junction composed of the P layer 13 and the N+ layer 14. The avalanche collision effect occurs under the acceleration of the strong electric field. Finally, the photoelectrons that have obtained avalanche multiplication reach the N+ layer 14, and the holes are absorbed by the P+ layer 11. Its depletion region is pulled from the P-N junction region to the range where the I layer 12 and the P+ layer 11 are connected, and its multiplication region 15 is located between the P-N junction composed of the P layer 13 and the N+ layer 14. The electric field in the depletion region increases slightly over the entire range. When the field strength in the depletion region reaches a sufficiently large value (~3*10^5V/cm), the photogenerated carriers will be accelerated to a very high speed. When they collide with atoms in the lattice during movement, they will be ionized, generating additional electron-hole pairs. These newly born electrons and holes are also accelerated, and new collisions and ionizations occur, generating more electron-hole pairs. This physical process is called the avalanche effect, which multiplies the primary photocurrent and amplifies it.

However, the above semiconductor device has the following problems: 1) When a reverse bias voltage is applied to the avalanche photodiode, the potential difference between the P+ layer 11 and the N+ layer 14 is only in the vertical direction, and the carriers outside the width of the multiplication region 15 in the horizontal direction cannot reach the multiplication region 15, which leads to low detection efficiency; 2) In order to improve the detection efficiency, it is usually chosen to increase the width of the multiplication region 15 in the horizontal direction by increasing the width of the N+ layer 14, but this will cause the defects and damage caused by the shallow trench and/or deep trench etching on the periphery of the avalanche photodiode to directly contact the multiplication region 15, which will cause the dark count rate to increase and reduce the device performance; 3) In order to improve the semiconductor device, the potential difference between the P+ layer 11 and the N+ layer 14 is only in the vertical direction, and the carriers outside the width of the multiplication region 15 in the horizontal direction cannot reach the multiplication region 15, which leads to low detection efficiency; 4) In order to improve the detection efficiency, the N+ layer 14 is usually increased in the horizontal direction to increase the width of the multiplication region 15, which will cause the defects and damage caused by the shallow trench and/or deep trench etching on the periphery of the avalanche photodiode to directly contact the multiplication region 15, which will cause the dark count rate to increase and reduce the device performance; 5) In order to improve the semiconductor device, the N+ layer 14 is increased in the horizontal direction to increase the width of the multiplication region 15, which will cause the dark count rate to increase and reduce the device performance; 6) In order to improve the detection efficiency, the N+ layer 14 is increased in the horizontal direction to increase the width of the multiplication region 15, which will cause the dark count rate to increase and reduce the device performance; 7) In order to improve the detection efficiency, the N+ layer 14 is increased in the horizontal direction to increase the width of the multiplication region 15, which will cause the dark The absorption efficiency of the conductor device for near-infrared light (905nm~940nm) requires that the thickness of the semiconductor device be very large (usually above 7.5μm), while the thickness of the multiplication region 15 in the vertical direction is relatively small, resulting in the need for carriers to diffuse through a long distance of the intrinsic doped layer 12 in the depletion region between the P+ layer 11 and the multiplication region 15 before avalanche can occur. In addition, there is energy consumption in the diffusion process, resulting in only a small number of carriers being able to produce avalanches, thereby reducing the detection efficiency. The long diffusion time also affects the sensitivity of the semiconductor device.

Therefore, how to improve detection efficiency is an urgent problem that needs to be solved.

Summary of the invention

The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the detection efficiency of the semiconductor device.

To achieve the above object, the present invention provides a semiconductor device, comprising:

a substrate having a first surface and a second surface opposite to each other;

A first ion doping region and a second ion doping region of opposite doping types, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from a side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.

Optionally, the substrate includes a base and an intrinsic doping layer formed on the base, and the first ion doping region and the second ion doping region are formed in the intrinsic doping layer.

Optionally, the doping type of the substrate is P type, the doping type of the first ion doping region is N type, and the doping type of the second ion doping region is P type.

Optionally, the ion implantation regions of each layer are stacked layer by layer.

Optionally, in the adjacent ion implantation regions, the ion implantation region far away from the first ion doping region wraps the ion implantation region close to the first ion doping region.

Optionally, a width of a contact area between the second ion-doped region and the first ion-doped region in a direction parallel to the first surface is smaller than a width of the first ion-doped region in a direction parallel to the first surface.

Optionally, the semiconductor device further includes:

A guard ring is formed at the periphery of the first ion-doped region.

The present invention also provides a method for manufacturing a semiconductor device, comprising:

Providing a substrate having a first surface and a second surface opposite to each other;

A first ion doping region and a second ion doping region of opposite doping types are formed, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from a side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, wherein the ion doping concentration of each layer of the ion implantation regions increases layer by layer in a direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.

Optionally, the method for manufacturing the semiconductor device further includes:

A guard ring is formed at the periphery of the first ion doped region.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

1. The semiconductor device of the present invention comprises a first ion doping region and a second ion doping region of opposite doping types, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from a side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in the direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction, thereby improving the detection efficiency of the semiconductor device.

2. The manufacturing method of the semiconductor device of the present invention forms a first ion doping region and a second ion doping region of opposite doping types, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from the side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in the direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction, thereby improving the detection efficiency of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a is a schematic diagram of a semiconductor device;

FIG. 1b is a schematic diagram of carrier diffusion of the semiconductor device shown in FIG. 1a ;

FIG. 2a is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

FIG2b is a schematic diagram of carrier diffusion of the semiconductor device shown in FIG2a;

FIG. 3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

The reference numerals of Figures 1a to 3 are described as follows:

11-P-type substrate; 12-intrinsic doping layer; 13-P-type well region; 14-N-type well region; 15-multiplication region; 21-substrate; 211-intrinsic doping layer; 22-first ion doping region; 221-heavy ion doping region; 23-second ion doping region; 231-first ion implantation region; 232-second ion implantation region; 233-third ion implantation region; 234-fourth ion implantation region; 24-guard ring; 25-first electrode; 26-second electrode; 27-multiplication region.

Detailed ways

In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

An embodiment of the present invention provides a semiconductor device, comprising: a substrate, the substrate having a first surface and a second surface opposite to each other; a first ion doping region and a second ion doping region of opposite doping types, the first ion doping region extending from the first surface into the substrate, the second ion doping region extending from a side of the first ion doping region away from the first surface toward the second surface, the second ion doping region comprising at least two layers of ion implantation regions, the ion doping concentration of each layer of the ion implantation regions increasing layer by layer in a direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increasing layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.

The semiconductor device provided in this embodiment is described in detail below with reference to FIG. 2a and FIG. 2b.

The substrate includes a base 21 and an intrinsic doping layer 211 formed on the base 21, wherein the intrinsic doping layer 211 is an epitaxial layer formed on the base 21 by an epitaxial process, and the substrate has a first surface and a second surface opposite to each other, wherein the side of the intrinsic doping layer 211 away from the base 21 is the first surface, and the side of the base 21 away from the intrinsic doping layer 211 is the second surface.

The intrinsic doping layer 211 has a very low doping level (e.g., less than 5×10 ¹⁴ atoms/cm ³ ). As an example, the intrinsic doping layer 211 may be an unintentionally doped semiconductor substrate, i.e., a substrate having P- or N-type doping caused only by accidental contamination by impurities during its manufacture. As a variant, the intrinsic doping layer 211 may also be a semiconductor substrate with a higher doping level.

The doping types of the substrate 21 and the intrinsic doping layer 211 may be the same or different. For example, the doping type of the substrate 21 is P-type, and the doping type of the intrinsic doping layer 211 may be N-type or P-type; the doping type of the substrate 21 is N-type, and the doping type of the intrinsic doping layer 211 may be N-type or P-type. Preferably, the substrate 21 is P+ type, the intrinsic doping layer 211 is P- type, and the doping concentration of the substrate 21 is greater than the doping concentration of the intrinsic doping layer 211.

The material of the substrate can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs) or indium phosphide (InP), etc.

The first ion doping region 22 and the second ion doping region 23 are formed in the substrate, that is, the first ion doping region 22 extends from the first surface of the substrate into the substrate, and the second ion doping region 23 extends from the side of the first ion doping region 22 away from the first surface toward the second surface.

Among them, the first ion doping region 22 and the second ion doping region 23 can be formed in the intrinsic doping layer 211. Since the ion doping concentration of the intrinsic doping layer 211 is very low, which is much smaller than the ion doping concentration of the first ion doping region 22 and the second ion doping region 23, the intrinsic doping layer 211 can be used as a neutral region.

The first ion-doped region 22 and the second ion-doped region 23 have opposite doping types, and the second ion-doped region 23, the substrate 21 and the intrinsic doping layer 211 have the same doping type. Preferably, the first ion-doped region 22 has an N-type doping type, and the second ion-doped region 23, the substrate 21 and the intrinsic doping layer 211 have a P-type doping type, so that a P-N junction is formed between the first ion-doped region 22 and the second ion-doped region 23.

The second ion doping region 23 includes at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation region increases layer by layer in the direction from the first surface to the second surface, and the width of each layer of the ion implantation region in the direction parallel to the first surface increases layer by layer, so that the first ion doping region 22 and the second ion doping region 23 form a graded junction. In the cross section parallel to the first surface, the cross-sectional shape of each layer of the ion implantation region can be a circle, a square, a diamond or other suitable shapes. The ion doping concentration of each layer of the ion implantation region can be greater than, equal to or less than the ion doping concentration of the substrate 21. A multiplication region 27 is formed between the ion implantation region closest to the first ion doping region 22 and the first ion doping region 22.

Among them, since the ion doping concentration of each layer of the ion implantation area increases layer by layer in the direction from the first surface to the second surface, a vertical built-in electric field perpendicular to the first surface is formed between adjacent ion implantation areas, and the direction of the vertical built-in electric field is the same as the direction of the electric field generated by applying a reverse bias voltage to the photodiode in the working state, thereby increasing the diffusion speed of carriers to the multiplication zone 27, thereby reducing the carrier loss in the diffusion process, increasing the probability of avalanche occurrence, and thus improving the detection efficiency of the semiconductor device.

In particular, when the thickness of the substrate is designed to be very large (usually above 7.5 μm) in order to improve the absorption efficiency of semiconductor devices for near-infrared light (905 nm to 940 nm), the thickness of the intrinsic doping layer 211 is very large, while the thickness of the multiplication zone 27 is relatively small, resulting in the need for carriers to pass through a long distance of the depletion zone (from the P-N junction to the range where the intrinsic doping layer 211 and the substrate 21 are connected) to produce an avalanche. In this embodiment, a vertical built-in electric field is formed to increase the diffusion speed of the carriers, thereby reducing the energy consumption of the carriers in the depletion zone, and more carriers can diffuse into the multiplication zone 27, thereby increasing the probability of avalanche occurrence.

Among them, the width of each layer of the ion implantation region in the direction parallel to the first surface increases layer by layer from the first surface toward the second surface, so that the built-in electric field formed between adjacent ion implantation regions includes not only a vertical built-in electric field perpendicular to the first surface but also a curved built-in electric field that is non-parallel to the vertical built-in electric field. The curved built-in electric field can diffuse the carriers in the edge area outside the width range of the ion implantation region in the intrinsic doping layer 211 into the multiplication region 27 under the action of the curved built-in electric field (as shown by the curved arrow in FIG. 2b ), thereby improving the utilization rate of the carriers and further improving the detection efficiency of the semiconductor device.

The orthographic projection of the vertical built-in electric field on the first surface overlaps with the orthographic projection of the ion implantation region closest to the first ion doping region 22 on the first surface; the curved built-in electric field is located outside the vertical built-in electric field and its orthographic projection on the first surface overlaps or intersects with the orthographic projection of the ion implantation region farthest from the first ion doping region 22 on the first surface.

Each layer of the ion implantation region may include but is not limited to being wrapped layer by layer or stacked layer by layer, and is arranged as required. When each layer of the ion implantation region is wrapped layer by layer, the doping depth of each layer of the ion implantation region in the direction perpendicular to the first surface extends from the interface between the first ion doping region 22 and the second ion doping region 23 toward the second surface, that is, in the adjacent ion implantation regions, the ion implantation region far away from the first ion doping region 22 is not only located at the bottom surface of the ion implantation region close to the first ion doping region 22, but also located at the side surface of the ion implantation region close to the first ion doping region 22, that is, the ion implantation region far away from the first ion doping region 22 wraps the ion implantation region close to the first ion doping region 22 in a groove shape. When the ion implantation regions of each layer are stacked layer by layer, the doping depth of each layer of the ion implantation regions in the direction perpendicular to the first surface extends from the interface of the adjacent ion implantation regions toward the second surface, and is distributed in a step-like manner similar to a hemisphere, that is, in the adjacent ion implantation regions, the ion implantation regions far away from the first ion doping region 22 are only located on the bottom surface of the ion implantation regions close to the first ion doping region 22, and not on the side surface of the ion implantation regions close to the first ion doping region 22. The ion implantation regions of each layer may share the same axis; in the adjacent ion implantation regions, the doping depth of each layer of the ion implantation regions in the direction perpendicular to the first surface may be the same or different.

The width of the first ion doping region 22 in the direction parallel to the first surface may be between the maximum width and the minimum width of the ion implantation regions of each layer in the direction parallel to the first surface; or, the width of the first ion doping region 22 in the direction parallel to the first surface may be greater than the maximum width of the ion implantation regions of each layer in the direction parallel to the first surface; or, the width of the first ion doping region 22 in the direction parallel to the first surface may be less than the minimum width of the ion implantation regions of each layer in the direction parallel to the first surface. In one embodiment, the width of the contact area between the second ion doping area 23 and the first ion doping area 22 in a direction parallel to the first surface is smaller than the width of the first ion doping area 22 in a direction parallel to the first surface, so as to avoid lateral edge breakdown of the photodiode; wherein, when the ion implantation areas of each layer are stacked layer by layer, the width of the contact area between the second ion doping area 23 and the first ion doping area 22 in a direction parallel to the first surface is the width of the ion implantation area closest to the first ion doping area 22 in a direction parallel to the first surface, then, the width of the ion implantation area closest to the first ion doping area 22 in a direction parallel to the first surface is smaller than the width of the first ion doping area 22 in a direction parallel to the first surface; when the ion implantation areas of each layer are wrapped layer by layer, the width of the contact area between the second ion doping area 23 and the first ion doping area 22 in a direction parallel to the first surface is the width of the ion implantation area farthest from the first ion doping area 22 in a direction parallel to the first surface, then, the width of the ion implantation area farthest from the first ion doping area 22 in a direction parallel to the first surface is smaller than the width of the first ion doping area 22 in a direction parallel to the first surface.

Moreover, the larger the width of the ion implantation region closest to the first ion doping region 22 in the direction parallel to the first surface, the larger the width of the multiplication region 27 in the direction parallel to the first surface; the larger the width of the ion implantation region farthest from the first ion doping region 22 in the direction parallel to the first surface, the greater the number of carriers in the edge area of the ion implantation region in the intrinsic doping layer 211 that diffuse into the multiplication region 27, thereby achieving that the carriers in the edge area of the multiplication region 27 can also diffuse into the multiplication region 27 under the action of the curved built-in electric field, thereby improving the utilization rate of the carriers and improving the detection efficiency of the semiconductor device.

In the embodiment shown in FIG. 2a to FIG. 2b, the second ion doping region 23 comprises four layers of ion implantation regions stacked in a direction from the first surface toward the second surface, namely, a first ion implantation region 231, a second ion implantation region 232, a third ion implantation region 233 and a fourth ion implantation region 234 stacked in layers, the ion doping concentration of the first ion implantation region 231 to the fourth ion implantation region 234 gradually increases, and the width of the first ion implantation region 231 to the fourth ion implantation region 234 in a direction parallel to the first surface gradually increases. The number of ion implantation region layers in the second ion doping region 23 is not specifically limited and can be set as needed.

The semiconductor device further includes: an ion heavily doped region 221 formed on the surface of the first ion doped region 22 , and the ion heavily doped region 221 has the same doping type as the first ion doped region 22 .

The semiconductor device further includes a guard ring 24 formed at the periphery of the first ion doping region 22. The guard ring 24 surrounds the first ion doping region 22, and the substrate is spaced between the guard ring 24 and the first ion doping region 22.

Preferably, the depth of the guard ring 24 is not less than the depth of the first ion-doped region 22 .

The guard ring 24 may be a shallow trench isolation structure or an ion-doped ring. If the guard ring 24 is an ion-doped ring, the doping type of the ion-doped ring may be N-type or P-type.

The semiconductor device further includes: an annular deep trench isolation structure (not shown) formed in the substrate outside the guard ring 24, the deep trench isolation structure and the guard ring 24 being separated by the substrate, and the deep trench isolation structure is used to achieve isolation between adjacent photodiodes to avoid crosstalk.

The depth of the deep trench isolation structure is not less than the depth of the first ion doping region 22 .

The deep trench isolation structure is formed in an annular trench (not shown) in the substrate, and includes an insulating material layer (not shown) covering the inner surface of the annular trench and a conductive layer (not shown) filling the annular trench.

Among them, since in an embodiment of the present invention, there is no need to increase the width of the multiplication region 27 by increasing the width of the first ion doping region 22 in a direction parallel to the first surface, it is avoided that the width of the multiplication region 27 is too large, which causes the defects and damages generated by etching the grooves when forming the shallow trench isolation structure and the deep trench isolation structure to directly contact the multiplication region 27, thereby avoiding causing the dark count rate to increase and reduce the device performance.

The semiconductor device also includes: a first electrode 25 and a second electrode 26, the first electrode 25 is formed on the ion heavily doped region 221, and the second electrode 26 is formed on the first surface or the second surface of the substrate. In the embodiments shown in Figures 2a to 2b, the second electrode 26 is formed on the second surface of the substrate; the ion heavily doped region 221 is used to connect the first ion doped region 22, so that when a voltage is applied to the first ion doped region 22 through the first electrode 25, the contact resistance is reduced; and a reverse bias voltage is applied to the photodiode through the first electrode 25 and the second electrode 26.

In summary, the semiconductor device provided by the present invention comprises: a substrate having a first surface and a second surface facing each other; a first ion doping region and a second ion doping region of opposite doping types, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from the side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation region increases layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation region in the direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction. The semiconductor device of the present invention can improve the detection efficiency of the semiconductor device.

An embodiment of the present invention provides a method for manufacturing a semiconductor device. Referring to FIG. 3 , FIG. 3 is a flow chart of the method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device includes:

Step S1, providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other;

Step S2, forming a first ion-doped region and a second ion-doped region of opposite doping types, wherein the first ion-doped region extends from the first surface into the substrate, and the second ion-doped region extends from a side of the first ion-doped region away from the first surface toward the second surface, and the second ion-doped region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in a direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increases layer by layer, so that the first ion-doped region and the second ion-doped region form a graded junction.

The method for manufacturing the semiconductor device provided in this embodiment is described in more detail below with reference to FIGS. 2a and 2b.

According to step S1 , a substrate is provided, wherein the substrate has a first surface and a second surface opposite to each other.

The substrate includes a base 21 and an intrinsic doping layer 211 formed on the base 21, the intrinsic doping layer 211 is an epitaxial layer formed on the base 21 by an epitaxial process, the side of the intrinsic doping layer 211 away from the base 21 is the first surface, and the side of the base 21 away from the intrinsic doping layer 211 is the second surface.

According to step S2, a first ion doping region 22 and a second ion doping region 23 of opposite doping types are formed, and the first ion doping region 22 and the second ion doping region 23 are formed in the substrate, that is, the first ion doping region 22 extends from the first surface of the substrate into the substrate, and the second ion doping region 23 extends from the side of the first ion doping region 22 away from the first surface toward the second surface.

The doping types of the first ion doping region 22 and the second ion doping region 23 are opposite, and the doping types of the second ion doping region 23, the substrate 21 and the intrinsic doping layer 211 are the same. Preferably, the doping type of the first ion doping region 22 is N-type, and the doping type of the second ion doping region 23, the substrate 21 and the intrinsic doping layer 211 are P-type, so that a P-N junction is formed between the first ion doping region 22 and the second ion doping region 23.

The second ion doping region 23 includes at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in the direction from the first surface to the second surface, and the width of each layer of the ion implantation regions in the direction parallel to the first surface increases layer by layer, so that the first ion doping region 22 and the second ion doping region 23 form a graded junction. A multiplication region 27 is formed between the ion implantation region closest to the first ion doping region 22 and the first ion doping region 22.

Among them, the width of each layer of the ion implantation region in the direction parallel to the first surface increases layer by layer in the direction from the first surface to the second surface, so that the built-in electric field formed between adjacent ion implantation regions includes not only a vertical built-in electric field perpendicular to the first surface but also a curved built-in electric field that is non-parallel to the vertical built-in electric field. The curved built-in electric field can diffuse the carriers in the edge area outside the width range of the ion implantation region in the intrinsic doping layer 211 into the multiplication region 27 under the action of the curved built-in electric field (as shown by the curved arrow in FIG. 2b ), thereby improving the utilization rate of the carriers and further improving the detection efficiency of the semiconductor device.

Each layer of the ion implantation region may include but is not limited to being wrapped layer by layer or stacked layer by layer, and is arranged as required. When each layer of the ion implantation region is wrapped layer by layer, the doping depth of each layer of the ion implantation region in the direction perpendicular to the first surface extends from the interface between the first ion doping region 22 and the second ion doping region 23 toward the second surface, that is, in the adjacent ion implantation regions, the ion implantation region far away from the first ion doping region 22 is not only located at the bottom surface of the ion implantation region close to the first ion doping region 22, but also located at the side surface of the ion implantation region close to the first ion doping region 22, that is, the ion implantation region far away from the first ion doping region 22 wraps the ion implantation region close to the first ion doping region 22 in a groove shape. When the ion implantation regions of each layer are stacked, the doping depth of each layer of the ion implantation regions in the direction perpendicular to the first surface extends from the interface of the adjacent ion implantation regions toward the second surface, and is distributed in a step-like manner similar to a hemisphere, that is, in the adjacent ion implantation regions, the ion implantation regions far away from the first ion doping region 22 are only located at the bottom surface of the ion implantation regions close to the first ion doping region 22, and not at the side surface of the ion implantation regions close to the first ion doping region 22. The ion implantation regions of each layer may share the same axis; in the adjacent ion implantation regions, the doping depth of each layer of the ion implantation regions in the direction perpendicular to the first surface may be the same or different.

In the embodiment shown in FIG. 2a to FIG. 2b, the second ion doping region 23 comprises four ion implantation regions stacked in layers from the first surface toward the second surface, namely, the first ion implantation region 231, the second ion implantation region 232, the third ion implantation region 233 and the fourth ion implantation region 234 stacked in layers, the ion doping concentration of the first ion implantation region 231 to the fourth ion implantation region 234 gradually increases, and the width of the first ion implantation region 231 to the fourth ion implantation region 234 in the direction parallel to the first surface gradually increases. The number of ion implantation region layers in the second ion doping region 23 is not specifically limited and can be set as needed.

An ion implantation process may be used to first form the first ion doping region 22 and then form the second ion doping region 23 , or to first form the second ion doping region 23 and then form the first ion doping region 22 .

Taking the stacking of each layer of the ion implantation region as an example, the step of forming the second ion doping region 23 may include: first, forming a patterned mask layer (not shown) on the first surface of the substrate, the patterned mask layer having an opening for ion implantation into the substrate; then, when the layers of the ion implantation region are formed in sequence along the direction from the first surface to the second surface, the width of the opening can be adjusted to become larger by replacing the mask for multiple times, and after each adjustment of the width of the opening, the patterned mask layer with the opening of the adjusted width is used as a mask to perform ion implantation into the substrate, and the energy and dose of the ion implantation gradually increase with each increase in the width of the opening, so that a layer of ion implantation region with a predetermined depth and width is formed after each ion implantation; when the layers of the ion implantation region are formed in sequence along the direction from the second surface to the first surface, the width of the opening can be adjusted to become smaller by replacing the mask for multiple times, and after each adjustment of the width of the opening, the patterned mask layer with the opening of the adjusted width is used as a mask. The mask is used to perform ion implantation into the substrate, wherein the energy and dosage of the ion implantation are gradually reduced as the width of the opening is adjusted each time, so that a layer of ion implantation region with a predetermined depth and width is formed after each ion implantation.

Furthermore, after each ion implantation, the substrate needs to be annealed to remove the breakage or damage of the semiconductor lattice caused by ion collision.

The method for manufacturing the semiconductor device further includes: forming an ion heavily doped region 221 on the surface of the first ion doped region 22 by an ion implantation process, wherein the ion heavily doped region 221 has the same doping type as the first ion doped region 22 .

The method for manufacturing the semiconductor device further includes: forming a guard ring 24 on the periphery of the first ion-doped region 22 , wherein the guard ring 24 surrounds the first ion-doped region 22 , and the substrate is spaced between the guard ring 24 and the first ion-doped region 22 .

The manufacturing method of the semiconductor device also includes: forming an annular deep trench isolation structure (not shown) in the substrate outside the guard ring 24, the deep trench isolation structure and the guard ring 24 are separated by the substrate, and the deep trench isolation structure is used to achieve isolation between adjacent photodiodes to avoid crosstalk.

Among them, since in an embodiment of the present invention, there is no need to increase the width of the multiplication region 27 by increasing the width of the first ion doping region 22 in a direction parallel to the first surface, it is avoided that the width of the multiplication region 27 is too large, which causes the defects and damage caused by etching the groove when forming the shallow trench isolation structure and the deep trench isolation structure to directly contact the multiplication region 27, thereby avoiding causing the dark count rate to increase and reduce the device performance.

The manufacturing method of the semiconductor device also includes: forming a first electrode 25 on the heavily ion-doped region 221, and forming a second electrode 26 on the first surface or the second surface of the substrate. In the embodiments shown in Figures 2a to 2b, the second electrode 26 is formed on the second surface of the substrate; the heavily ion-doped region 221 is used to connect the first ion-doped region 22, so that when a voltage is applied to the first ion-doped region 22 through the first electrode 25, the contact resistance is reduced; and a reverse bias voltage is applied to the photodiode through the first electrode 25 and the second electrode 26.

In summary, the manufacturing method of the semiconductor device provided by the present invention includes: providing a substrate, the substrate having a first surface and a second surface opposite to each other; forming a first ion doping region and a second ion doping region of opposite doping types, the first ion doping region extending from the first surface into the substrate, the second ion doping region extending from the side of the first ion doping region away from the first surface toward the second surface, the second ion doping region comprising at least two layers of ion implantation regions, the ion doping concentration of each layer of the ion implantation region increasing layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation region in the direction parallel to the first surface increasing layer by layer, so that the first ion doping region and the second ion doping region form a graded junction. The manufacturing method of the semiconductor device of the present invention can improve the detection efficiency of the semiconductor device.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

A semiconductor device, comprising:

a substrate having a first surface and a second surface opposite to each other;

A first ion doping region and a second ion doping region of opposite doping types, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from a side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, and the ion doping concentration of each layer of the ion implantation regions increases layer by layer in the direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.
The semiconductor device according to claim 1, characterized in that the substrate comprises a base and an intrinsic doping layer formed on the base, and the first ion doping region and the second ion doping region are formed in the intrinsic doping layer.
The semiconductor device according to claim 2 is characterized in that the doping type of the substrate is P type, the doping type of the first ion doping region is N type, and the doping type of the second ion doping region is P type.
The semiconductor device as claimed in claim 1 is characterized in that the ion implantation regions of each layer are stacked layer by layer.
The semiconductor device according to claim 1, characterized in that, in the adjacent ion implantation regions, the ion implantation region far away from the first ion doping region wraps the ion implantation region close to the first ion doping region.
The semiconductor device according to claim 1 is characterized in that the width of the contact area between the second ion-doped region and the first ion-doped region in a direction parallel to the first surface is smaller than the width of the first ion-doped region in a direction parallel to the first surface.
The semiconductor device according to claim 1, characterized in that the semiconductor device further comprises:

A guard ring is formed at the periphery of the first ion-doped region.
A method for manufacturing a semiconductor device, comprising:

Providing a substrate having a first surface and a second surface opposite to each other;

A first ion doping region and a second ion doping region of opposite doping types are formed, wherein the first ion doping region extends from the first surface into the substrate, and the second ion doping region extends from a side of the first ion doping region away from the first surface toward the second surface, and the second ion doping region comprises at least two layers of ion implantation regions, wherein the ion doping concentration of each layer of the ion implantation regions increases layer by layer in a direction from the first surface toward the second surface, and the width of each layer of the ion implantation regions in a direction parallel to the first surface increases layer by layer, so that the first ion doping region and the second ion doping region form a graded junction.
The method for manufacturing a semiconductor device as described in claim 8 is characterized in that the ion implantation regions of each layer are stacked layer by layer.
The method for manufacturing a semiconductor device according to claim 8, characterized in that, in the adjacent ion implantation regions, the ion implantation region far away from the first ion doping region wraps the ion implantation region close to the first ion doping region.
The method for manufacturing a semiconductor device according to claim 8, further comprising:

A guard ring is formed at the periphery of the first ion doped region.