WO2024088494A1

WO2024088494A1 - Semiconductor package

Info

Publication number: WO2024088494A1
Application number: PCT/EP2022/079494
Authority: WO
Inventors: Lasse Petteri PALM; Mirko Bernardoni; Mo Huai Chang; Andreas Munding; Frank Winter
Original assignee: Huawei Digital Power Technologies Co., Ltd.
Priority date: 2022-10-23
Filing date: 2022-10-23
Publication date: 2024-05-02
Also published as: WO2024088555A1

Abstract

The disclosure relates to a semiconductor package (100) comprising an electronic chip (140);an encapsulant (150) encapsulating at least part of the at least one electronic chip (140); a first metal layer (110) placed upon at least one of a first main surface (150a) or a second main surface (150b) of the encapsulant (150); and a second metal layer (120) placed upon at least one side wall (150c) of the encapsulant (150). The first metal layer (110) is electrically connecting a first connection terminal (141) of the electronic chip (140) by at least one electrical conductor (111) extending from the first connection terminal (141) to the first metal layer (110). The second metal layer (120) is contacting the first metal layer (110) to form an electrically and thermally conductive connection between the second metal layer (120) and the first metal layer (110). The second metal layer (120) extends along the at least one side wall (150c) of the encapsulant (150) to a third metal layer (130) of the semiconductor package (100) to form an electrically and thermally conductive connection of the first connection terminal (141) via the at least one side wall (150c) to the third metal layer (130) of the semiconductor package (100).

Description

Semiconductor Package

TECHNICAL FIELD

The disclosure relates to the field of chip embedding and packaging technology for power packaging. In particular, the disclosure relates to a semiconductor package, a method for manufacturing an embedded component layer and a method for manufacturing a PCB (Printed Circuit Board) layer with embedded electronic chip.

BACKGROUND

Chip embedding technology is a new packaging technology that is nowadays used also for power packaging. The main benefit of the embedding technology is that it allows to reduce the parasitic inductances and to maximize the electrical performance of the modules and at the same time to reduce the package size.

In currently available solutions balancing the gate and source connection of the chip in multidie packages and modules and at the same time minimizing the signal lengths can be challenging. A non-balanced gate and source connection may lead to uneven current distribution over the singular devices causing non-simultaneous switching (different gate line length, different inherent gate resistances) and uneven temperature distribution of the chips with respect to each other. This can lead to uneven aging of the parts in long term considerations, and short circuit weakness in short term. Strong oscillations in the gate path may occur, leading to a self-switching of the device, higher gate resistances and increasing the losses during switching.

SUMMARY

This disclosure provides a solution for overcoming the above-described problems with chip embedding technology.

The foregoing and other objectives are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

Embodiments described in this disclosure are based on Chip Embedding Technology, 3D stacking and plated side wall connections with improved routing and package design as described hereinafter. A stacked parallel die package and a stacked half-bridge package are disclosed. This disclosure presents a new semiconductor package and a new method to manufacture small sized and stacked multi-die 3D packages for power semiconductor devices. The power dies can be embedded inside PCB layers which can be laminated by using PCB processes. Plated through-holes or larger sized routed slots (e.g., oval vias) can provide the electrical connections from top side to bottom side of the package. The electrical connections can be diced at the center line of the package and exposed at the side walls of the package. Embodiments presented hereinafter offer several advantages, especially for parallel die configurations, but also for multi-die packages such as for example half-bridge, power stage, etc.

To increase the power density 3D stacking can be advantageously applied as described hereinafter. By stacking the dies instead of mounting them next to each other the overall package size is significantly reduced leading to a reduced final product size and thus lower substrate costs.

Some embodiments include paralleling MOSFETs. There, the RDS O., (Drain-Source on resistance) is reduced by providing more chips in parallel which also reduces conduction losses. Paralleling also allows to reach higher currents, especially with SiC as it is still limited in chip size and therefore Amperes per chip. The generated heat can be pulled over a larger area for more heat transfer efficiency. This is not in contradiction to the stacked configuration presented in this disclosure, as it is compatible with dual sided cooling and provides methods to improve heat extraction from between the dies to the package sidewalls, and via solder filler to the main board.

Embodiments described in this disclosure allow manufacturing of power packages (see e.g. Figures 2 to 7) where power dies are connected in parallel or in half-bridge configuration. However, also other configurations are possible, for example a single-die configuration as shown in Figure 1.

In case of parallel die package configuration the current path length can be minimized and full balance of the source and gate connections can be achieved by applying symmetricity to the current path that connects both source and gate pads or to both drain pads. In half-bridge configuration the High Side (HS) and Low Side (LS) switch are stacked above each other. This allows to minimize the distance between drain and source connection, and thus, depending on the configuration the input voltage or High Side supply voltage connection path (VIN), switched node or output voltage connection path (VSWH, VOUT), power ground or low side supply voltage connection path (PGND) can be improved, and the length can be minimized, e.g., by source up or source down configuration. In case of a half-bridge package configuration also partial shielding can be implemented.

The embedding can be done by using available chip embedding processes or prepackage embedding processes. After embedding the components inside the PCB core layer(s), a PCB manufacturing process can be applied. The main benefits are the following:

Minimized parasitic, such as loop resistance, loop inductance;

Large cross section current path from the die to the footprint;

Balanced gate and source (preferred option) or drain connections to minimize the differences in the loop inductances between the dies and footprint (Parallel die package)',

Short and/or direct connection between HS and LS (Half-bridge package)’,

Minimized package size (3D stacking, minimized die to package edge distance due to no vias or vertical connection elements or clips in the package area);

Easily adjustable clearance/creepage distance;

Package side wall connection for improved reliability, soldering and LTI (lead tip inspection). Package side wall means the exterior package faces perpendicular to the upper and lower main faces of the package and not an internal plated via sidewall;

Better thermal heat dissipation also through the package side walls.

Embodiments presented in this disclosure are:

1. Single die package (see Figure 1),

2. Parallel die package - common source and common drain (see Figures 2 to 4),

3. Half-bridge package - source up and source down (see Figures 5 to 7).

In this disclosure the following terms, abbreviations and notations will be used:

PCB Printed Circuit Board

CE Chip Embedding

ECP Embedded Component Package or Packaging

LTI Lead Tip Inspection

PTH Plated Through Hole

Ros_on Drain-Source on resistance

CE/ECP: Chip embedding or embedded component packaging. Packaging technology where bare dies typically with Cu metallization are embedded inside PCB material and connected to the Cu routing on the package with plated pvias. LTI: Lead Tip Inspection is a method used especially in automotive and it allows optical inspection to check the soldering quality of all connection. The pads on the package are exposed on the side of the package allowing the solder wetting and fillet on the side wall. This can be inspected optically and used to judge if the soldering has been successfully.

PTH: Mechanically drilled hole with typically 20-30pm plated Cu on the side walls.

RDs_o_n: Drain-Source on resistance or the total resistance between the drain and source in a Metal Oxide Field Effect Transistor, or MOSFET when the MOSFET is “on.” RDS OII (or RDS(on)) is the basis for a maximum current rating of the MOSFET and is also associated with current loss. The lower the R_Ds(on), the better.

VI N input voltage or high side supply voltage connection path

VSWH switched node connection path

VOUT output voltage connection path

PGND power ground or low side supply voltage connection path

In this disclosure, chip embedding technologies are described. There are several different types of embedding processes available: In a typical chip embedding process, the electronic components (chips, capacitors, resistors, etc.) are either placed inside an opening in a PCB core layer or soldered on a two or multilayer PCB board. The actual embedding inside the final PCB board can be performed by laminating FR4 prepregs or other polymer sheets above and below the core layer that holds the components to be embedded. The electrical connection between the embedded components and the PCB metal layers can be formed by soldering the component terminals to the inner laminate layers and subsequently laminating the PCB layers together. In more advanced embedding technologies, the components can be electrically connected by galvanically filled micro vias which is more robust, since there is no remelting of solder inside the package or board, which has to be considered when mounting the other components to the outer layers of the PCB by additional reflow processes. The micro vias are usually formed after lamination by laser drilling from the top surface through the thin laminate layer to the active chip pads or to the terminals of an embedded component package.

When using Plated Through Holes, the inner walls of the holes are covered with a thin layer of copper, which makes the entire inner hole area conductive. This conductivity establishes an electrical connection between components and Copper tracks. It also enhances mechanical stability and reduces the overall resistance to support smooth current flow. The average Cu plating thickness is minimum 20 pm. As electronic components become more integrated and complex, double-sided and multi-layered PCBs were developed along with plated through holes, so that components may connect to the desired layers, whenever required.

In this disclosure side wall connections are described which can be plated and arranged on an outer surface of the package. To manufacture these side wall connections PCB processes can be used. On panel level, large plated through holes can be mechanically drilled or oval slots can be mechanically milled along the package outline before plating/separation. After drilling/milling electroless and electrochemical plating processes can be applied to plate a metal layer, e.g., a metal layer of 20-30pm Cu, on the through holes or the oval slots. Later, during separation of the panel into individual packages, the plated through holes or slots can be cut in half such that a section of the through hole or slot is left to one side of the cut and another section is left to the opposite size of the cut, where the cutting line defines the package outline.

According to a first aspect, the disclosure relates to a semiconductor package comprising: at least one electronic chip comprising at least one first connection terminal for an electrical connection of the at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip, the encapsulant comprising a first main surface and a second main surface opposing the first main surface, and one or more side walls between the first main surface and the second main surface; a first metal layer placed upon at least one of the first main surface or the second main surface of the encapsulant, the first metal layer electrically connecting the at least one first connection terminal of the at least one electronic chip by at least one electrical conductor extending from the at least one first connection terminal to the first metal layer; a second metal layer placed upon at least one side wall of the one or more side walls of the encapsulant, the second metal layer contacting the first metal layer to form an electrically and thermally conductive connection between the second metal layer and the first metal layer, wherein the second metal layer extends along the at least one side wall of the encapsulant to a third metal layer of the semiconductor package to form an electrically and thermally conductive connection of the at least one first connection terminal via the at least one side wall to the third metal layer of the semiconductor package.

Such a semiconductor package enables balancing the gate and source connection of the chip and at the same time minimizing the signal lengths. Due to the balanced gate and source connection the current distribution over the singular devices is more even which avoids nonsimultaneous switching and uneven temperature distribution of the chips with respect to each other. The semiconductor package thus has improved aging characteristics. Strong oscillations in the gate path can be avoided resulting in avoidance of self-switching, lower gate resistances and reduced losses during switching.

The electronic chip may be formed as a power semiconductor device with vertical current flow through the device from top to bottom or vice versa (also simply referred to as a vertical device). The electronic chip may also be formed as a power semiconductor device with lateral current flow parallel to one main surface of the die (also simply referred to as a lateral device). No current is flowing vertically through the device. In case of a power semiconductor device with lateral current flow, further routing may be applied, for example, to build a half-bridge or parallel die combination.

The electronic chip(s) can be for example, logic chips, analog chips, driver chips, or even passives, and any combination thereof.

In exemplary implementation(s) of the semiconductor package, the at least one electronic chip comprises at least one or a combination of the following device types: a Si MOSFET, a GaN FET, an IGBT, a SiC FET, a GaAs FET or another wide band gap semiconductor device or another device type. Thus, the semiconductor device can be realized based on wide band gap semiconductors and offers the flexibility of implementing also other types of power components.

In an exemplary implementation of the semiconductor package, the second metal layer extends upon a predominant portion of the at least one side wall of the encapsulant. Thus, the heat extraction path of the device can be routed via package side walls which results in improved thermal dissipation of the semiconductor package.

The encapsulant is a three-dimensional body that may be geometrically defined by the first main surface, e.g., located on top of the encapsulant, the second main surface, e.g. located at the bottom of the encapsulant and one or more side walls between the first and second main surfaces. The side walls may also be referred to as “side faces”, “side surfaces” or simply as “sides” of the encapsulant.

The predominant portion of a side wall specifies an area of at least 50 percent of the respective side wall. That means, the second metal layer occupies an area that corresponds to at least the half of the respective side wall or even more. This results in improved thermal and electrical performance due to electrical and thermal conduction via the side walls. In an exemplary implementation of the semiconductor package, the semiconductor package comprises: a substrate for carrying the encapsulant with the at least one electronic chip, the substrate comprising at least one solder pad for electrically and thermally connecting the at least one electronic chip; and a solder fillet or solder meniscus arranged at side faces of the second metal layer and below the first metal layer, wherein the solder fillet or solder meniscus is formed to extract at least a portion of heat generated by the at least one electronic chip via the second metal layer placed on the side walls of the encapsulant to the at least one solder pad of the substrate.

In the solder fillet (or solder meniscus) application, the main portion of solder comes from SMD (surface-mounted device) assembly, which also defines the shape of the fillet or meniscus. In contrast to such a solder fillet or meniscus, a thin plated layer would not support the thermal extraction function.

This provides the advantage that the solder pads of the package can be extended also to two, three or four sides of the package which improves heat dissipation characteristics. Besides, the clearance and creepage distance can be maximized, e.g., in an implementation of solder pads on sidewalls or periphery only.

The solder fillet or solder meniscus may not be arranged only at a small fraction near the lower edges of the metal-plated encapsulant, it can rather extend over the complete metal-plated vertical fraction of the side walls of the encapsulant in order to provide an electrical and thermal connection being able of providing a high current carrying capacity. The solder fillet or solder meniscus may not be plated but spread to the side wall due to wetting. For example, the solder fillet or solder meniscus may be L-shaped or quasi L-shaped, see Figures 4 and 7 for a three- dimensional view of the solder fillet or solder meniscus.

The heat extraction via the solder fillet or solder meniscus does not exclude heat extraction via the first metal layer. That means, heat is extracted by both, the first metal layer and the solder fillet or solder meniscus. A small part of heat can also be extracted via the third metal layer.

The at least one solder pad may extend via the solder fillet or solder meniscus from the substrate of the semiconductor package to the side walls of the semiconductor package.

The at least one electrical conductor may comprise at least one contact via extending through the encapsulant to form an electrically and thermally conductive path between the at least one first connection terminal of the at least one electronic chip and the first metal layer. This contact via does not extend through the package, but only from the outer surface to the connection terminal of the chip. The contact via can be a laser drilled microvia or a mechanically drilled via, for example.

In an exemplary implementation of the semiconductor package, the at least one electronic chip comprises at least one second connection terminal; wherein the first metal layer comprises a first portion electrically connecting the at least one first connection terminal of the at least one electronic chip and a second portion electrically connecting the at least one second connection terminal of the at least one electronic chip; wherein the second metal layer comprises a first portion contacting the first portion of the first metal layer and a second portion contacting the second portion of the first metal layer; wherein the first portion of the second metal layer extends along a first side wall of the at least one side wall to a first portion of the third metal layer to form an electrically and thermally conductive connection of the at least one first connection terminal via the first side wall to the first portion of the third metal layer of the semiconductor package; and wherein the second portion of the second metal layer extends along a second side wall of the at least one side wall to a second portion of the third metal layer to form an electrically and thermally conductive connection of the at least one second connection terminal via the second side wall to the second portion of the third metal layer of the semiconductor package.

Thus, a stacked multi-die architecture can be realized in which the dies can be embedded inside a laminate and 3D stacked above each other, whereas the sidewall metallization (second metallization) can be used for heat extraction, electrical connection and EMI shielding.

In an exemplary implementation of the semiconductor package, the third metal layer is placed upon a main surface of the encapsulant opposing the main surface of the encapsulant upon which the first metal layer is placed. The third metal layer and the first metal layer are placed upon the two main surfaces of the encapsulant in order to efficiently extract heat produced by the chip to the outside of the encapsulant.

In an exemplary implementation of the semiconductor package, the at least one electronic chip comprises at least one third connection terminal; wherein the third metal layer is electrically connecting the at least one third connection terminal of the at least one electronic chip by at least one third electrical conductor extending from the at least one third connection terminal to the third metal layer. A stacked MOSFET or IGBT configuration can be efficiently implemented. The MOSFETs or IGBTs can be embedded inside a laminate, for example, and 3D stacked above each other. The control loop of the stacked configuration can be implemented in a highly symmetrical and thus in an extremely balanced way.

The third electrical conductor may be designed similar to the at least one electrical conductor. E.g. the third electrical conductor may comprise at least one contact via extending through the encapsulant to form an electrically and thermally conductive path between the at least one third connection terminal of the at least one electronic chip and the third metal layer.

In an exemplary implementation of the semiconductor package, the semiconductor package comprises: at least one second electronic chip comprising at least one first connection terminal; a second encapsulant encapsulating at least part of the at least one second electronic chip, the second encapsulant comprising a first main surface and a second main surface opposing the first main surface, and one or more side walls between the first main surface and the second main surface, wherein the second encapsulant with the encapsulated at least one second electronic chip is stacked upon the encapsulant with the encapsulated at least one electronic chip. Thus, a stacked configuration of two or more chips or dies can be realized which results in improved thermal and electric behavior due to shorter connection lines between the dies and a reduced footprint relative to non-stacked configurations with the same active die area.

In an exemplary implementation of the semiconductor package, the semiconductor package comprises: a fourth metal layer placed upon at least one of the first main surface or the second main surface of the second encapsulant; and a fifth metal layer placed upon one of the main surfaces of the second encapsulant opposite to the fourth metal layer. Therefore, these fourth and fifth metal layers can be used, additionally to the first and third metal layers, for heat transfer in order to improve heat dissipation of the multi-die semiconductor package.

In an exemplary implementation of the semiconductor package, the second metal layer is further placed upon at least one side wall of the one or more side walls of the second encapsulant to form an electrically and thermally conductive connection between the at least one side wall of the second encapsulant and the at least one side wall of the encapsulant. Heat extraction can be efficiently performed by the metal layers placed on the side walls of both encapsulants which results in improved thermal performance of the multi-die semiconductor package. In an exemplary implementation of the semiconductor package, the at least one side wall of the second encapsulant and the at least one side wall of the encapsulant are located at a same side of the semiconductor package. Thus, the above-described same side of the semiconductor package has a larger area which improves heat transfer.

In an exemplary implementation of the semiconductor package, the at least one electronic chip and the at least one second electronic chip are electrically connected in parallel or in a halfbridge configuration. Thus two chips can interact in order to realize different switching configurations, e.g., high side (HS) switches or low side (LS) switches, etc.

In an exemplary implementation of the semiconductor package, for the parallel configuration, the electrical connection is based on a common source configuration or a common drain configuration; and for the half-bridge configuration, the electrical connection is based on a source down configuration ora drain down configuration. Thus, typical switching configurations can be efficiently implemented by the semiconductor package.

In an exemplary implementation of the semiconductor package, for the parallel configuration the at least one first terminal of the at least one electronic chip and the at least one first terminal of the at least one second electronic chip are facing in opposite directions; wherein the electrical connection of the at least one electronic chip and the at least one second electronic chip is formed by an interconnection of the third metal layer with the fifth metal layer and by the second metal layer that is placed upon the side walls of the encapsulant and upon the side walls of the second encapsulant. A symmetrical routing can be applied, e.g., to source and gate pads of parallel dies package. Symmetrical routing is beneficial to the switching behavior as it results in a low loop inductance which avoids oscillations and overshoots of current/voltage.

In an exemplary implementation of the semiconductor package, for the half-bridge configuration the at least one first terminal of the at least one electronic chip and the at least one first terminal of the at least one second electronic chip are facing in the same direction; wherein the electrical connection of the at least one electronic chip and the at least one second electronic chip is formed by an interconnection of the third metal layer with the fifth metal layer and by the second metal layer that is placed upon the side walls of the encapsulant and upon the side walls of the second encapsulant. Improved shielding performance for the half-bridge configuration is therefore provided. In an exemplary implementation of the semiconductor package, for the half-bridge configuration a source terminal of the at least one electronic chip is connected to a drain terminal of the at least one second electronic chip by the interconnection of the third metal layer with the fifth metal layer and by the second metal layer that is placed upon the side walls of the encapsulant and upon the side walls of the second encapsulant. Improved shielding of the third metal layer and fifth metal layer via the second metal layer placed on the side walls of the two encapsulants is therefore provided.

According to a second aspect, the disclosure relates to a method for manufacturing an embedded component layer, the method comprising: providing a printed circuit board, PCB, core layer with openings in the PCB core layer; mounting at least one electronic chip inside the openings of the PCB core layer; embedding the at least one electronic chip inside the PCB core layer by lamination to form an embedded component layer; cutting microvias into the embedded component layer; electrically connecting the at least one electronic chip by metal plating; and structuring the embedded component layer.

By such method an easy manufacturing of an embedded component layer and thus of a semiconductor package as described above with respect to the first aspect can be implemented.

By electrically connecting the at least one electronic chip with metal plating; and subsequent structuring of the embedded component layer, a semiconductor package as described above with respect to the first aspect can be manufactured, e.g. a semiconductor package in which the second metal layer extends along the at least one side wall of the encapsulant to the third metal layer, forming an electrically and thermally conductive side wall connection with improved thermal and electrical properties.

According to a third aspect, the disclosure relates to a method for manufacturing a printed circuit board, PCB, layer with at least one electronic chip embedded inside the PCB layer, the method comprising: laying-up at least one embedded component layer and laminating the layered-up at least one embedded component layer to form a lay-up package, the lay-up package comprising a top side and a bottom side opposing the top side and side walls between the top side and the bottom side; cutting through holes or slot openings into the lay-up package extending from the top side to the bottom side of the lay-up package, wherein the through holes or slot openings are cutting through a metal plating of the at least one embedded component layer, the metal plating providing an electrically and thermally conducting connection of at least one first connection terminal of the at least one electronic chip; metal plating the through holes or slot openings of the lay-up package to electrically and thermally connect the at least one first connection terminal of the at least one electronic chip; and dicing the lay-up package by cutting from a middle of a through hole or slot opening of the lay-up package and exposing one side of the plated through hole or slot opening to form one or more PCB layers with at least one electronic chip embedded inside the PCB layer.

By such method an easy manufacturing of a PCB layer with at least one electronic chip embedded inside the PCB layer and thus of a single-die or multi-die semiconductor package as described above with respect to the first aspect can be implemented.

In particular, by metal plating the through holes or slot openings of the lay-up package; and subsequent dicing the lay-up package, a PCB layer with embedded electronic chip(s) can be manufactured, in which the second metal layer extends along the at least one side wall of the encapsulants to the third metal layer, forming an electrically and thermally conductive side wall connection with improved thermal and electrical properties.

In an exemplary implementation of the method, laying-up the at least one embedded component layer comprises placing the at least one embedded component layer between prepreg material and metal foils to form the lay-up package comprising at least one of a top metal foil at the top side of the lay-up package and a bottom metal foil at the bottom side of the lay-up package. Such a process step can be easily implemented, e.g., by applying available PCB processing.

In an exemplary implementation of the method, the method comprises: stacking at least two embedded component layers above each other; and electrically connecting the at least one electronic chips of the at least two embedded component layers to form a parallel or a halfbridge configuration. Different stacked dies of different configurations can be produced. These stacked dies have improved thermal dissipation properties due to short line paths in the package.

Exemplary implementation(s) of the method comprises may comprise:

- Dies are embedded inside a laminate and 3D stacked above each other.

- Solder pads of the package are extended also to 2, 3 or 4 sides of the package.

- Heat extraction path via package sidewall and solder fillet.

- Symmetrical routing to source and gate pads (parallel die package with common source).

- Shielding (half-bridge). - The clearance and creepage distance can be maximized (e.g., solder pads on sidewalls/periphery only).

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the disclosure will be described with respect to the following figures, in which:

Figure 1 shows a schematic cross section of a single die semiconductor package 100 according to the disclosure;

Figure 2 shows a schematic cross section of a multi-die semiconductor package 200a in a common drain configuration;

Figure 3 shows a schematic cross section of a multi-die semiconductor package 200b in a common source and gate configuration;

Figure 4 shows a schematic 3-dimensional representation of the multi-die semiconductor package 200b of Figure 3 and two exemplary circuit diagrams 200d, 200c of the multi-die semiconductor packages 200a, 200b;

Figure 5 shows a schematic cross section of a multi-die semiconductor package 300a in a halfbridge configuration with drain down;

Figure 6 shows a schematic cross section of a multi-die semiconductor package 300b in a halfbridge configuration with source down;

Figure 7 shows a schematic 3-dimensional representation of the multi-die semiconductor package 300a of Figure 5 and an exemplary circuit diagram 300c of the multi-die semiconductor package 300a;

Figure 8 shows a schematic diagram of an exemplary process flow 800 to embed power dies according to the disclosure;

Figure 9 shows cross views of an exemplary process flow 900 for lamination and connecting of two embedded layers;

Figure 10 shows top views of the process steps routing or drilling 903, plating 904 and structuring and separation 905 shown in Figure 9; and

Figure 11 shows schematic 3-dimensional representations of exemplary source connection 1110, drain connection 1120 and gate connection 1130 of a multi-die semiconductor package according to an embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

Figure 1 shows a schematic cross section of a single die semiconductor package 100 according to the disclosure. Although Figure 1 depicts only a single die, the semiconductor package may also comprise more than one dies, e.g., as exemplarily shown in Figures 2 to 7. Besides, one layer of the semiconductor package 100 can also include several dies.

The semiconductor package 100 shown in Figure 1 comprises at least one electronic chip 140 comprising at least one first connection terminal 141 for an electrical connection of the at least one electronic chip 140.

The semiconductor package 100 comprises an encapsulant 150 encapsulating at least part of the at least one electronic chip 140. The encapsulant 150 comprises a first main surface 150a and a second main surface 150b opposing the first main surface 150a, and one or more side walls 150c between the first main surface 150a and the second main surface 150b.

The semiconductor package 100 further comprises a first metal layer 110 and a second metal layer 120.

The first metal layer 110 is placed upon at least one of the first main surface 150a or the second main surface 150b of the encapsulant 150. The first metal layer 110 electrically connects the at least one first connection terminal 141 of the at least one electronic chip 140 by at least one electrical conductor 111 extending from the at least one first connection terminal 141 to the first metal layer 110.

The second metal layer 120 is placed upon at least one side wall of the one or more side walls 150c of the encapsulant 150. The second metal layer 120 contacts the first metal layer 110 to form an electrically and thermally conductive connection between the second metal layer 120 and the first metal layer 110. The second metal layer 120 extends along the at least one side wall 150c of the encapsulant 150 to a third metal layer 130 of the semiconductor package 100 to form an electrically and thermally conductive connection of the at least one first connection terminal 141 via the at least one side wall 150c to the third metal layer 130 of the semiconductor package 100.

The electronic chip may be formed as a vertical device or as a lateral device. In case of a planar device, further routing may be applied, for example, to build a half-bridge or parallel die combination.

The electronic chip(s) can be, for example, logic chips, analog dies, driver dies, or even passives, and any combination thereof.

The at least one electronic chip 140 may comprise at least one or a combination of the following device types: a MOSFET, a GaN, an IGBT, a SiC, a GaAs or another wide band gap semiconductor or another device type.

The second metal layer 120 may extend upon a predominant portion of the at least one side wall of the encapsulant. In Figure 1 , the second metal layer covers the left and right side walls 150c of the encapsulant 150. It understands that not the full area of the side walls 150c have to be covered. In some embodiments only portions of the side walls 150c may be covered by the second metal layer 120.

The encapsulant 150 is a three-dimensional body that may be geometrically defined by the first main surface, e.g., located on top of the encapsulant, the second main surface, e.g., located at the bottom of the encapsulant and one or more side walls between the first and second main surfaces. The side walls may also be referred to as “side faces”, “side surfaces” or simply as “sides” of the encapsulant.

The predominant portion of a side wall specifies an area of at least 50 percent of the respective side wall. That means, the second metal layer occupies an area that corresponds to at least the half of the respective side wall or even more. This results in improved thermal and electrical performance due to electrical and thermal conduction via the side walls.

The semiconductor package may further comprise a substrate for carrying the encapsulant 150 with the at least one electronic chip 140. The substrate 101 comprises at least one solder pad 102 for electrically and thermally connecting the at least one electronic chip 140. The semiconductor package may further comprise a solder fillet or solder meniscus 103 arranged at the side faces of the second metal layer 120 and below the first metal layer 110. The solder fillet or solder meniscus 103 may be formed to extract at least a portion of heat generated by the at least one electronic chip 140 via the second metal layer 120 placed on the side walls 150c of the encapsulant 150 to the at least one solder pad 102 of the substrate 101.

The solder fillet or solder meniscus 103 may not be arranged only at a small fraction near the lower edges of the metal-plated encapsulant, it can rather extend over the complete metal- plated vertical fraction of the side walls 150c of the encapsulant in order to provide an electrical and thermal connection being able of providing a high current carrying capacity. The solder fillet or solder meniscus 103 may not be plated but spread to the side wall 150c due to wetting. For example, the solder fillet or solder meniscus may be L-shaped or quasi L-shaped, see Figures 4 and 7 for a three-dimensional view of the solder fillet or solder meniscus 103.

The heat extraction via the solder fillet or solder meniscus 103 does not exclude heat extraction via the first metal layer 110. That means, heat is extracted by both, the first metal layer 110 and the solder fillet or solder meniscus 103. A small part of heat can also be extracted via the third metal layer 130.

The at least one solder pad may extend via the fillet or solder meniscus 103 from the substrate 101 of the semiconductor package 100 to the side walls 150c of the semiconductor package 100.

The at least one electrical conductor 111 may comprise at least one contact via extending through the encapsulant 150 to form an electrically and thermally conductive path between the at least one first connection terminal 141 of the at least one electronic chip 140 and the first metal layer 110.

The at least one electronic chip may comprise at least one second connection terminal 142.

The first metal layer 110 may comprise a first portion electrically connecting the at least one first connection terminal 141 of the at least one electronic chip 140 and a second portion electrically connecting the at least one second connection terminal 142 of the at least one electronic chip 140.

The second metal layer 120 may comprise a first portion contacting the first portion of the first metal layer 110 and a second portion contacting the second portion of the first metal layer. The first portion of the second metal layer 120 may extend along a first side wall of the at least one side wall 150c to a first portion of the third metal layer 130 to form an electrically and thermally conductive connection of the at least one first connection terminal 141 via the first side wall 150c to the first portion of the third metal layer 130 of the semiconductor package 100.

The second portion of the second metal layer 120 may extend along a second side wall of the at least one side wall 150c to a second portion of the third metal layer 130 to form an electrically and thermally conductive connection of the at least one second connection terminal 142 via the second side wall to the second portion of the third metal layer 130 of the semiconductor package 100.

The third metal layer 130 may be placed upon a main surface of the encapsulant 150 opposing the main surface of the encapsulant 150 upon which the first metal layer 110 is placed.

The at least one electronic chip 140 may comprise at least one third connection terminal 143.

The third metal layer 130 may be electrically connecting the at least one third connection terminal 143 of the at least one electronic chip 140 by at least one third electrical conductor 113 extending from the at least one third connection terminal 143 to the third metal layer 130.

The third electrical conductor 113 may be designed similar to the at least one electrical conductor 111. E.g. the third electrical conductor 113 may comprise at least one contact via extending through the encapsulant 150 to form an electrically and thermally conductive path between the at least one third connection terminal 143 of the at least one electronic chip 140 and the third metal layer 130.

Figure 2 shows a schematic cross section of a multi-die semiconductor package 200a in a common drain configuration; Figure 3 shows a schematic cross section of a multi-die semiconductor package 200b in a common source and gate configuration; and Figure 4 shows a schematic 3-dimensional representation of the multi-die semiconductor package 200b of Figure 3.

The multi-die semiconductor packages 200a, 200b are specific implementations of the semiconductor package 100 shown in Figure 1 , where multiple electronic chips 140, 160 are embedded in the package. In addition to the features described above for the semiconductor package 100, the multi-die semiconductor packages 200a, 200b comprise: at least one second electronic chip 160 comprising at least one first connection terminal 161; and a second encapsulant (170) encapsulating at least part of the at least one second electronic chip (160).

The second encapsulant 170 comprises a first main surface 170a and a second main surface 170b opposing the first main surface 170a, and one or more side walls 170c between the first main surface 170a and the second main surface 170b. The second encapsulant 170 with the encapsulated at least one second electronic chip 160 is stacked upon the encapsulant 150 with the encapsulated at least one electronic chip 140.

The multi-die semiconductor packages 200a, 200b comprise: a fourth metal layer 190 placed upon at least one of the first main surface 170a or the second main surface 170b of the second encapsulant 170; and a fifth metal layer 180 placed upon one of the main surfaces 170a, 170b of the second encapsulant 170 opposite to the fourth metal layer 190.

The second metal layer 120 is further placed upon at least one side wall of the one or more side walls 170c of the second encapsulant 170 to form an electrically and thermally conductive connection between the at least one side wall 170c of the second encapsulant 170 and the at least one side wall 150c of the encapsulant 150.

The at least one side wall 170c of the second encapsulant 170 and the at least one side wall 150c of the encapsulant 150 may be located at a same side of the semiconductor package 200a, 200b.

The at least one electronic chip 140 and the at least one second electronic chip 160 may be electrically connected in parallel configuration (see Figures 2 to 4) or in a half-bridge configuration (see Figures 5 to 7).

For the parallel configuration shown in Figures 2 to 4, the electrical connection may be based on a common source configuration (Figure 3) or on a common drain configuration (Figure 2). High level circuit diagrams of the parallel configuration in common source configuration 200d and in common drain configuration 200c are shown in Figure 4. In the parallel configuration in common source configuration 200d the source terminals S of both chips 140, 160 are connected and serve as a common terminal. In the parallel configuration in common drain configuration 200c the drain terminals D of both chips 140, 160 are connected and server as a common terminal.

For the parallel configuration shown in Figures 2 to 4, the at least one first terminal 141 of the at least one electronic chip 140 and the at least one first terminal 141 of the at least one second electronic chip 160 are facing in opposite directions.

The electrical connection of the at least one electronic chip 140 and the at least one second electronic chip 160 may be formed by an interconnection of the third metal layer 130 with the fifth metal layer 180 and by the second metal layer 120 that is placed upon the side walls 150c of the encapsulant 150 and upon the side walls 170c of the second encapsulant 170.

In the following, the parallel configuration shown in Figures 2 to 4 is described in more detail.

In the parallel configuration, two (or more) MOSFETs 140, 160 or other power components are embedded inside two different layers 150, 170 that may be laminated together with normal PCB lamination process. The connection between the dies 140, 160 and package footprint can be done with plated through holes or slots that are located on the dicing street. After dicing/package separation on side of the plated via/slot side wall is exposed. This process can be an existing PCB process with some variation in the process how the exposed plated side walls are produced. The side walls of the package can be plated to improve the soldering and heat transfer and to connect the dies together. The large area/cross section side wall connections instead of limited number of plated vias also helps to minimize the current density in the copper routing from top side of the package to the footprint side.

The package can be designed either with common source and gate configuration as shown in Figure 3 or with common drain configuration as shown in Figure 2.

A preferred package option (or embodiment) with balanced source and gate connection is presented in Figure 3. For this option (or embodiment) the source and gate sides of both dies 140, 160 are facing towards each other, connected to the inner layers 130, 180 (layer 2 and 3) and routed to the edge area of the package, e.g. to the second metal layer 120. The drain of both dies 140, 160 are facing outside and connected to the outer layers 110, 190 (layer 1 and 4) and routed to the opposite side edge area of the package, e.g. also to the second metal layer 120 shown in Figure 3. After slot routing the L2 and L3 inner layer metal lines 130, 180 and metal line in the outer layer L1 and L4, 110, 190 are exposed and connected together by plating, e.g. by the second metal layer 120 as illustrated in Figure 3. Both lines are routed to the package bottom side to form a footprint.

Figure 5 shows a schematic cross section of a multi-die semiconductor package 300a in a halfbridge configuration with drain down; Figure 6 shows a schematic cross section of a multi-die semiconductor package 300b in a half-bridge configuration with source down; and Figure 7 shows a schematic 3-dimensional representation of the multi-die semiconductor package 300a of Figure 5.

The multi-die semiconductor packages 300a, 300b are specific implementations of the semiconductor package 100 shown in Figure 1, where multiple electronic chips 140, 160 are embedded in the package.

In addition to the features described above for the semiconductor package 100, the multi-die semiconductor packages 300a, 300b comprise the features described above with respect to Figures 2 to 4 which are not specifically related to the parallel dies configuration. Besides the specific implementation of the parallel dies described above with respect to Figures 2 to 4, the multi-die semiconductor packages 300a, 300b comprise the following features:

The at least one electronic chip 140 and the at least one second electronic chip 160 are electrically connected in a half-bridge configuration.

For the half-bridge configuration shown in Figures 5 to 7, the electrical connection can be based on a source down configuration (see Figure 6) or a drain down configuration (see Figures 5 and 7).

A high-level circuit diagram of the half-bridge configuration in either drain down or source down configuration 300c is shown in Figure 7. In the half-bridge configuration 300c the source terminal S of the second chip 160 is connected to the drain terminal D of the first chip 140.

For the half-bridge configuration shown in Figures 5 to 7, the at least one first terminal 141 of the at least one electronic chip 140 and the at least one first terminal 141 of the at least one second electronic chip 160 can face in the same direction.

For the half-bridge configuration shown in Figures 5 to 7, a source terminal of the at least one electronic chip 140 may be connected to a drain terminal of the at least one second electronic chip 160 by the interconnection of the third metal layer 130 with the fifth metal layer 180 and by the second metal layer 120 that is placed upon the side walls 150c of the encapsulant 150 and upon the side walls 170c of the second encapsulant 170.

In the following, the half-bridge configuration shown in Figures 5 to 7 is described in more detail.

In the multi die package with half-bridge configuration, HS and LS MOSFETs 140, 160 are embedded inside different layers 150, 170 that are laminated together so that the drain of one power die is facing toward source of the other power die and connected to the inner layers 130, 180 (layer 2 and 3) and routed to the edge area, e.g. the second metal layer 120 shown in Figure 5 of the package. By achieving the aim of reducing HS switching losses from package, the LS is minimized by internal routing. The drain of one die and source of the other die are facing outside and connected to the outer layers 110, 190 (layer 1 and 4).

After slot routing the L2 and L3 inner layer metal lines 130, 180 and metal line 110, 190 in the outer layer L1 are exposed. All connections are routed to the package bottom side to form a footprint. The package can be designed either in source down (see Figure 6) or drain down configuration (see Figure 5). Asymmetrical HS and LS dies can be implemented as well so the dies doesn’t have to be of same sizes. The HS source is facing LS drain and by achieving the aim of reducing HS switching losses from package, the LS is minimized by internal routing.

To improve the performance the connection between the HS and LS dies can be implemented by applying additional hybrid bonding method, e.g., as described below. The hatched area 510 between the stacked dies 140, 160 in Figures 5 and 6 as well as in Figures 2 and 3 shows the hybrid bonding area. Hybrid bonding can be applied as an option to both embodiments (see Figures 2, 3 and 5, 6) to improve heat extraction from between the dies 140, 160 towards the package sidewalls.

The plated side walls, e.g. the second metal layer 120, of the package improve the soldering, allow LTI and heat transfer. Large area/cross section side wall connections instead of limited number of plated vias also helps to minimize the current density in copper routing from top side of the package to the footprint side.

Hybrid bonding as referred to in this disclosure is a process that allows simultaneously bonding of metallic contacts and dielectric areas in one bonding process. Hybrid bonding can be used for 3D-integration on wafer level and on package level. A method or process to form these connections has the following characteristics: Using a standard PCB lamination process (bond temperature, pressure, format); using hybrid bonding to bond metal to metal and dielectric to dielectric in one step; Several premanufactured layers can be connected to each other in one lamination step or in several sequential lamination steps; the bonding materials can be attached or applied to the surface of the laminate layers or placed between the laminate layers prior to bonding.

A semiconductor power entity, e.g., a semiconductor device according to the first aspect as described above, that may be produced by using a hybrid bonding process and a method for producing such semiconductor power entity by using hybrid bonding is described below (after the description with respect to Figure 11).

Figure 8 shows a schematic diagram of an exemplary process flow 800 to embed power dies according to the disclosure.

Figure 8 illustrates embedding of at least two power dies 140 inside separate PCB core layers that are laminated with respect to each other, and the components are connected together and to the footprint with plated side wall connections. The plated side wall connections can be manufactured with normal PTH and/or routing process. An example of such manufacturing flow how core layers with embedded components can be manufactured is presented in Figure 8.

In an embedding process as exemplarily shown in Figure 8, bare dies with Cu metallization are embedded inside an opening of the core layer. The opening of the core layer (with or without Cu) can be implemented for example by laser cutting (also routing, punching, etc. can be used). A tape is laminated on the bottom side of the core layer and the die is placed inside the opening and attached to the tape with a pick and placement machine.

After the die placement a prepreg sheet and a Cu foil are prelaminated on the top side of the core layer with a vacuum laminator. Then the bonding tape is removed and another prepreg and Cu foil are laminated on the bottom side (during second lamination the pre laminated prepreg is also fully cured). After lamination vias to the die from both sides are drilled with laser drilling. The dies are connected and the vias filled with electroless and electrochemical plating. Finally, the Cu is structured with lithography and etching processes.

This is only an example of a typical embedding process. Other kinds of embedding processes can be used as well. Instead of bare dies also prepackaged dies can be embedded.

The process flow 800 comprises multiple process steps or process blocks and can be described as follows.

A first step 801 may comprise: providing a printed circuit board, PCB, core layer 820, e.g., FR4 laminate, having a top side and a bottom side opposing the top side.

A second step 802, 803 may comprise: cutting at least one opening 821 in the PCB core layer 820, the at least one opening 821 extending from the top side to the bottom side of the PCB core layer 820. This can be implemented by Plated Through-Hole (PTH) drilling, laser cutting, punching, routing, etc., for example.

A third step 804 may comprise: attaching a bonding tape 822 to the PCB core layer 820, e.g., by tape lamination, the bonding tape 822 covering the at least one opening 821 of the PCB core layer 820 from the bottom side.

A fourth step 805 may comprise: placing at least one electronic chip, e.g., an electronic chip 140 as shown above with respect to Figures 1 to 7, inside the at least one opening 821 of the PCB core layer 820 and attaching the at least one electronic chip 140 to the bonding tape 822.

A fifth step 806 may comprise: applying a first lamination layer 823 on the top side of the PCB core layer 820 to form an embedded component package embedding the at least one electronic chip 140, the embedded component package 850 comprising a top side above the top side of the PCB core layer 820 and a bottom side below the bottom side of the PCB core layer 820, and attaching a first metal foil 824, e.g., a Cu foil attached by lamination, on the top side of the embedded component package 850.

A sixth step 807 may comprise: removing the bonding tape 822 from the bottom side of the embedded component package 850, applying a second lamination layer 825 on the bottom side of the embedded component package 850 and attaching a second metal foil 826, e.g., a Cu foil attached by lamination, on the bottom side of the embedded component package 850. A seventh step 808 may comprise: cutting at least one microvia 827, e.g., by pvia drilling, into the embedded component package 850 to expose at least one first connection terminal, e.g., at least one first connection terminal 141 as shown in Figures 1 to 7, of the at least one electronic chip 140.

An eighth step 809 may comprise: disposing a photoresist layer 827 on the top side and/or on the bottom side of the embedded component package 850, e.g., by lithography, and forming one or more openings in the photoresist layer to form a photoresist pattern 828 on the top side and/or on the bottom side of the embedded component package 850.

A ninth step 810 may comprise: metal plating, e.g., by pattern plating, the top side or the bottom side of the embedded component package 850 to provide electrically and thermally connections of the at least one first connection terminal 141 of the at least one electronic chip 140 according to the photoresist pattern 828 on the top side or the bottom side of the embedded component package. Note that structuring at this phase can be done only on one side, either top side or bottom side. Structuring of the second side can be done after laminating two layers together.

A tenth step 811 may comprise: removing the photoresist layer 827 and parts of the first metal foil 824 covered by the photoresist layer 827 from the top side of the embedded component package and removing, e.g., by etching, the photoresist layer and parts of the second metal foil covered by the photoresist layer from the bottom side of the embedded component package 850.

The process 800 shown in Figure 8 can also be described in terms of a method, e.g., in a simplified version as presented in the following.

The process 800 represents a method for manufacturing aN embedded component layer, e.g., an embedded component layer of a semiconductor package 100 as shown in Figure 1 or an embedded component layer of a multi-die semiconductor package 200a, 200b, 300a, 300b as shown in Figures 2 to 7.

This method comprises: providing 801 , 802, 803, 804 a printed circuit board, PCB, core layer with openings in the PCB core layer; mounting 805 at least one electronic chip 140 inside the openings of the PCB core layer; embedding 806 the at least one electronic chip 140 inside the PCB core layer by lamination to form an embedded component layer; cutting microvias 808 into the embedded component layer; electrically connecting 809, 810 the at least one electronic chip 140 by metal plating; and structuring 811 the embedded component layer.

By electrically connecting the at least one electronic chip 140 with metal plating; and subsequent structuring of the embedded component layer, a semiconductor package 100 as described above with respect to Figures 1 to 7 can be manufactured, e.g. a semiconductor package in which the second metal layer 120 extends along the at least one side wall 150c of the encapsulant 150 to the third metal layer 130, forming an electrically and thermally conductive side wall connection with improved thermal and electrical properties.

Figure 9 shows cross views of an exemplary process flow 900 for lamination and connecting of two embedded layers 910, 920. In particular, Figure 9 explains how 2 core layers 910, 920 with embedded dies 140, 160 can be laminated together and connected with plated side walls.

Alternatively, the 2 core layers 910, 920 can be electrically and mechanically bonded together by means of the hybrid bonding method as specified below. As referenced below, and according to the teaching of this disclosure this method can be used to simultaneously connect metal areas with metal areas and dielectric areas with metallic or dielectric areas in one bonding step.

The first step 901 , 902 in the process is the layup and lamination step 901 , 902 where two core layers 910, 920 with embedded dies 140, 160 are laminated together, e.g., by using PCB vacuum lamination. The layup may consist of Cu foil 931 , prepreg 932, first core layer 910 with embedded dies 140, prepreg 933, second core layer 920 with embedded dies 160, prepreg 934 and Cu foil 935.

The Cu foil 931 , 935 and prepreg 932, 934 on both sides can be removed if the Cu layers underneath of these are not structured during the process described above with respect to Figure 8.

After lamination 902 mechanical drilled though holes or routed slot openings 940 are manufactured 903 on the edge areas of the modules. After drilling step 903 Cu is plated 904 on the side walls 941 of the PTHs or slots 940 with electroless and electrochemical plating processes. Then, the copper layer 931 , 935 is structured 905 with photolithography and etching processes and the package 950 is separated 905, e.g., by mechanical dicing or other package separation process. However, the outermost layers 931 , 935 in the final stack 950 (see also Figure 2) can also be structured after lamination 902. The dicing can be done along the center line of the plated PTH /slot so that one side of the plated side wall is exposed as can be seen in Figure 10. To improve the thermal performance and top side cooling an additional heat sink can be mounted on the top side.

The process 900 shown in Figure 9 can also be described in terms of a method as presented in the following.

Such method for manufacturing a printed circuit board, PCB, layer with at least one electronic chip 140 embedded inside the PCB layer, e.g., as shown in Figures 1 to 7 comprises the following:

Laying-up 901 at least one embedded component layer and laminating 902 the layed-up at least one embedded component layer to form a lay-up package, the lay-up package comprising a top side and a bottom side opposing the top side and side walls between the top side and the bottom side.

Cutting through holes or slot openings 903 into the lay-up package extending from the top side to the bottom side of the lay-up package, wherein the through holes or slot openings are cutting through a metal plating of the at least one embedded component layer, the metal plating providing an electrically and thermally connection of at least one first connection terminal of the at least one electronic chip 140.

Metal plating 904 the through holes or slot openings of the lay-up package to electrically and thermally connect the at least one first connection terminal 141 of the at least one electronic chip 140.

Dicing 905 the lay-up package by cutting through the middle of a through hole or slot opening of the lay-up package and exposing one side of the plated through hole or slot opening to form one or more PCB layers with at least one electronic chip 140 embedded inside the PCB layer 100.

By metal plating the through holes or slot openings of the lay-up package; and subsequent dicing the lay-up package, a PCB layer with embedded electronic chip(s) can be manufactured, in which the second metal layer 120 extends along the at least one side wall 150c, 170c of the encapsulants 150, 170 to the third metal layer 130, forming an electrically and thermally conductive side wall connection with improved thermal and electrical properties, e.g. as described above with respect to Figures 2 to 7. Laying-up the at least one embedded component layer may comprise placing the at least one embedded component layer between prepreg material and metal foils to form the lay-up package comprising at least one of a top metal foil at the top side of the lay-up package and a bottom metal foil at the bottom side of the lay-up package.

The method 900 may further comprise: stacking at least two embedded component layers above each other; and electrically connecting the at least one electronic chips 140, 160 of the at least two embedded component layers to form a parallel or a half-bridge configuration, e.g., as described above with respect to Figures 2 to 7.

Figure 10 shows top views of the process steps routing or drilling 903, plating 904 and structuring and separation 905 shown in Figure 9.

In the routing/drilling step 903 illustrated in Figure 10, through holes or slot openings 940 are cut into the lay-up package 950 extending from the top side to the bottom side of the lay-up package 950. The white areas illustrate these through holes or slot openings 940. This routing and drilling is illustrated in the left-hand picture of Figure 10.

I n the metal plating and etching step 904 shown in Figure 10, the through holes or slot openings 940 of the lay-up package 950 are metal plated 941 to electrically and thermally connect the at least one first connection terminal 141 of the at least one electronic chip 140. These metal platings 941 are illustrated in the middle picture of Figure 10.

In the dicing 905 step, the lay-up package 950 is cut 960 from a middle of a through hole or slot opening 940 of the lay-up package 950 to expose one side of the plated through hole or slot opening 940 to form one or more PCB layers with at least one electronic chip 140 embedded inside the PCB layer 100. This dicing and separation is illustrated in the righthand picture of Figure 10.

The process to manufacture the stacked package 950 may be based on normal PCB and chip embedding processes. The process can be used for manufacturing of several different kinds of packages, e.g., parallel common source or drain package, half-bridge package with source down or drain down, e.g., as described above.

Although on the pictures the die size is the same in half-bridge package the HS and LS die can also be of different sizes. The process described in this disclosure can also be used for manufacturing of single die and other types of multi-die packages. The layers with embedded components that are laminated together can be manufactured with various kind of chip embedding or package embedding processes. Due to the plated side wall connections the soldering is easier, lead tip inspection (LTI) possible and the reliability is improved. Due to the large area plated sidewalls the Cu cross section is increased and allows higher current carrying capability and lower the current density in Cu lines. The metallized side walls can also be used for effective heat extraction. 3D stacking allows to minimize the package size and increase the power density.

The ideas and embodiments presented in this disclosure are supported by some simulations to extract the parasitic components from the packaging solutions. As an example, the balanced common source and gate package is considered, as shown in Figure 11 .

The following pictures show the electrical ports which have been defined in order to extract the matrix of parasitic inductances. Due to the position of the gate contact for the exemplary die which was considered (which may be placed in a corner, for example, to better suit the routing to the package contacts), two source pads 1111, 1112 (A and B) have been defined, as shown in the left-hand picture of Figure 11.

Assuming that the package may be contacted only on the bottom surface, the fact that the source and the gate connection are running symmetrically between the two stacked dies is confirmed by the values of the gate and source inductances.

In the simulations, it has been shown that already very small values of parasitic inductances (in the order of hundreds of pH) can be obtained due to the small dimensions of the package itself. Since the drain potential is applied on the backside, the parasitic inductance to the drain of the bottom die is smaller than that of the top die, for obvious geometric reasons. However, the source and gate inductances can be much closer to each other which can be relevant when a tight synchronization between different devices is requested.

The simulations have shown that a gate inductance of about 190 pH versus about 210 pH can be obtained, at bottom and top, respectively. The simulations have also shown that a source inductance of about 70 pH versus about 80 pH can be obtained, at bottom and top, respectively.

In both cases, the unbalance between the two paths is small, about 10% at the source and about 13% at the gate in this example.

The small unbalance can be explained by basic geometry. Nevertheless, the presence of the vertical walls is really important because they bring the equipotential surface (input port at the bottom of the package) closer to the dies themselves, hence improving the electrical symmetry of the parasitic interconnections.

Assuming that the potential can be brought even directly to the vertical walls themselves (e.g., via soldering on the sidewall), the unbalance in the interconnections can be further reduced (due to the fact that the external equipotential surface is applied even closer to the geometric symmetry plane of the package). A further reduction of the unbalancing at gate and source terminals can be obtained thanks to the vertical walls when they are actively contacted and used as equipotential surface.

The simulations, which are only examples that are based on the design that was used in simulation, have shown that a gate inductance of about 160 pH versus about 165 pH can be obtained, at bottom and top, respectively. The simulations have also shown that a source inductance of about 60 pH versus about 65 pH can be obtained, at bottom and top, respectively.

In both cases, the unbalance between the two paths is further reduced and almost negligible, e.g., about 3% at the source and about 5% at the gate.

Hybrid Bonding

In the following a semiconductor power entity that may be produced by applying hybrid bonding and a method for producing a semiconductor power entity by using hybrid bonding is described. The semiconductor power entity may correspond to the semiconductor package as described above with respect to Figures 1 to 7. Note that the metal layers described in the following with respect to the hybrid bonding may be different from the metal layers described above with respect to the Figures.

Such a semiconductor power entity comprises: a first laminate layer having a first laminate upper main face and a first laminate lower main face opposing the first laminate upper main face; a second laminate layer having a second laminate upper main face and a second laminate lower main face opposing the second laminate upper main face; an isolation layer arranged between the first laminate layer and the second laminate layer; a first metal layer arranged at the first laminate upper main face of the first laminate layer and a second metal layer arranged at the first laminate lower main face of the first laminate layer; a third metal layer arranged at the second laminate upper main face of the second laminate layer and a fourth metal layer arranged at the second laminate lower main face of the second laminate layer; and a connection metal layer embedded in the isolation layer between the first laminate layer and the second laminate layer, the connection metal layer forming an electrical connection with the second metal layer and the third metal layer.

Such semiconductor power entity provides the advantage of having direct vertical connections between two or more laminate core layers. These vertical connections can be made within the projected physical outline of embedded components if the laminate layer have such embedded components; they are not confined to a certain shape or size, e.g. they can be flexible designed in shape and size; they do not need an outer layer plating process to form the electrical connection; they are suitable for power electronics, since they have low inductance and high current capability; they are reliable and do not remelt at bond temperature. These vertical connections can be formed, for example by solid-liquid interdiffusion (SLID), transient liquid phase (TLP) bonding or sintering.

Thus, the semiconductor power entity provides increased power density and efficiency, short, current-capable low-parasitic interconnection paths, a very good thermal management and improved electrical isolation. Conductor traces with a current capability of several ten Amperes up to hundreds of Amperes and even higher, and power modules with an internal stray inductance below about 10 nH and even lower can be achieved.

The first, second, third and fourth metal layers can be redistribution or routing metal layers for redistributing or routing current paths. It understands that the semiconductor power entity is not restricted to these four metal layers and two laminate layers. The semiconductor power entity can also have more layers. The layers that are laminated may also be the layers of a multi-layer board, e.g., four layers or six layers, instead of an exemplary two-layer board.

The semiconductor power entity can also be referred to as semiconductor power product. Such product can also be a module or a larger size product (PCB), for example, where the power components may be embedded inside the PCB and the rest of the components may be placed on top. Some or all of the passives may also be embedded in the PCB, depending on the passive components, e.g., depending on a type of the passive components.

In an exemplary implementation of the semiconductor power entity, the connection metal layer forms a non-remelting electrical and mechanical connection.

Such a “non-remelting” connection is different from a normal solder connection such as formed during a conventional TC/NCP process (thermo-compression bonding with solder and preapplied non-conductive polymer). A non-remelting connection provides the advantage that it is a connection which will not remelt or decompose at temperatures much higher than the process temperature it was formed.

In an exemplary implementation of the semiconductor power entity, the connection metal layer forms one of a diffusion soldering connection or a sintering connection.

Diffusion soldering or diffusion bonding is a metal joining technique which can be advantageously applied to electronic packaging. It operates on the principle of interdiffusion of two dissimilar metals, wherein a liquid phase is completely transformed into solid state by means of metallic phase reactions and intermetallic compound formation. Similar terms for such technique are transient liquid phase bonding, solid-liquid interdiffusion, isothermal solidification. The technique provides the advantage that the resulting solid phase has a higher melting point than the temperature of the formation process.

Sintering is the process of compacting and forming a solid mass of material by heat or pressure without melting it to the point of liquefaction. Sintering happens as part of a manufacturing process used with metals, ceramics, plastics, and other materials. The atoms in the materials diffuse across the boundaries of the particles, fusing the particles together and creating one solid piece. The advantage of sintering is the following: Because the sintering temperature does not have to reach the melting point of the material, sintering is often chosen as the shaping process for materials with extremely high melting points.

The connection metal can form a composed metal layer, for example. Such composed metal layer may include a compound from more than two metals, e.g., such as inter-metallic layer, or a connection of metal layers consisting of one single metal, or a connection of a metal and a polymer or polymer mixture. For such inter-metallic layer, the melting point of the inter metallic layer is higher than the lamination/process temperature where it was formed.

The connection metal layer may consist of more than 80% metal and less than 20% pores or polymers, for example.

The connection metal layer is designed for high current loads.

In one embodiment, the inter-metallic layer may have a minimum lateral size of typically >1mm in each dimension, but not smaller than 0.1 mm.

The intermetallic layer may have a large cross-section, short length and good conductor and due to that is suitable for high current loads.

In one embodiment, the connection metal layer may have a typical thickness of 5 to 50 um, but not thicker than 0.2 mm (in case of a single layer structure).

In an exemplary implementation of the semiconductor power entity, the first laminate layer is embedding a first power semiconductor; and/or the second laminate layer is embedding a second power semiconductor.

Such a semiconductor power entity provides the advantage of increased power density and efficiency, short, current-capable low-parasitic interconnection paths, a very good thermal management and improved electrical isolation. Conductor traces with a high current capability of e.g., several ten Amperes up to hundreds of Amperes, and power modules with an internal stray inductance, e.g. below about 10 nH can be implemented.

When defining a first power semiconductor and a second power semiconductor this does not exclude that more than one first power semiconductor can be embedded in the first laminate layer and more than one second power semiconductor can be embedded in the second laminate layer.

In an exemplary implementation of the semiconductor power entity, the connection metal layer vertically connects the second metal layer with the third metal layer providing a vertical electrical connection for the first power semiconductor and the second power semiconductor. This provides the advantage that a shortest-path electrically connection can be realized which reduces stray inductance of the power entity and impedance between the two metal layers.

In an exemplary implementation of the semiconductor power entity, the connection metal layer forms a direct electrical connection path between the first power semiconductor and the second power semiconductor without a detour via through-hole vias arranged laterally to the two power semiconductors.

As described above, such a direct electrical connection path provides the advantage of shortest-path large area electrical connection between the two metal layers, reducing impedance and stray inductance.

In an exemplary implementation of the semiconductor power entity, the second metal layer and/or the third metal layer comprise at least one of copper, gold, silver, palladium or nickel or a combination thereof; wherein in case of a diffusion soldering connection, the connection metal layer comprises any suitable low temperature melting metal like for example tin and indium in combination with any of the metals of the second metal layer or the third metal layer or an alloy thereof; wherein in case of a sintering connection, the connection metal layer comprises a porous layer of silver or copper or other suitable sintering metal with optional polymer filling.

This provides the advantage that a lot of metals and metal alloys or combinations thereof with different characteristics can be applied.

Note that such connection metal layer includes also the following combination: (tin OR indium OR (tin AND indium)) in combination with any of the metals of the second metal layer or the third metal layer or an alloy thereof.

In an exemplary implementation of the semiconductor power entity, the first power semiconductor and the second power semiconductor are configured to form a half-bridge configuration. It understands that a lot of other configurations of the two power semiconductors can be implemented as well.

This provides the advantage that the semiconductor power entity can be efficiently used in automotive power conversion systems and in other applications of the semiconductor power entity. The half-bridge configuration is a reoccurring key topology element in power electronics conversion circuits. In an exemplary implementation of the semiconductor power entity, the first power semiconductor is a vertical device comprising at least one first terminal opposing the first laminate upper main face and a second terminal opposing the first laminate lower main face; and the second power semiconductor is a vertical device comprising at least one first terminal opposing the second laminate upper main face and a second terminal opposing the second laminate lower main face.

This provides the advantage that the semiconductor power entity can provide high current density, high power dissipation and high reverse breakdown voltage.

In an alternative exemplary implementation of the semiconductor power entity, the first power semiconductor can be a lateral device and the second power semiconductor can be a lateral device.

In an exemplary implementation of the semiconductor power entity, the semiconductor power entity comprises: at least one first via and at least one second via extending through the first laminate layer, the at least one first via forming an electrical connection between the at least one first terminal of the first power semiconductor and the first metal layer and the at least one second via forming an electrical connection between the second terminal of the first power semiconductor and the second metal layer; and at least one third via and at least one fourth via extending through the second laminate layer, the at least one third via forming an electrical connection between the at least one first terminal of the second power semiconductor and the third metal layer and the at least one fourth via forming an electrical connection between the second terminal of the second power semiconductor and the fourth metal layer.

Such a design provides the advantage that the shortest path between the two facing inner terminals of the power semiconductors can be used for electrical connection. This results in low parasitic impedance, high current capability of this buried connection due to large area. It can be even made larger than the die itself. Without the disclosed technique, such connections are only possible by arrangement of through-holes at the periphery outside the projected die area.

By such design both power semiconductors can be fully embedded in the respective laminate layers which results in excellent electrical performance. In an alternative embodiment, these vias can be replaced by large area connections such that either the die front or the die back side can be in direct connection to the metal layers without any distance. Note that the large area connections are typically made on one face of the chip per layer. With development and process modification large area connections can be on both sides, but in such a case there most likely would be one large area connection/via instead of multiple small vias.

These large area connections have the advantage that configurations are possible that allow further improvement of a) parasitic impedance by shortening the electrical path, or b) thermal path by enabling direct heat extraction without microvias at the outer surface of the entity.

In an exemplary implementation of the semiconductor power entity, the first power semiconductor has a first semiconductor upper main face and a first semiconductor lower main face opposing the first semiconductor upper main face; wherein the first semiconductor upper main face is coplanar arranged with the first laminate upper main face to form an electrical connection between the at least one first terminal of the first power semiconductor and the first metal layer at the first laminate upper main face; and wherein the second terminal of the first power semiconductor forms an electrical connection with the second metal layer at the first laminate lower main face by one or more microvias extending through the first laminate layer. Alternatively, the first semiconductor lower main face is coplanar arranged with the first laminate lower main face to form an electrical connection between the second terminal of the first power semiconductor and the second metal layer at the first laminate lower main face; and wherein the at least one first terminal of the first power semiconductor forms an electrical connection with the first metal layer at the first laminate upper main face by one or more microvias extending through the first laminate layer.

Such a design provides the advantage of large area chip connection on one side of the chip with the respective metal layer which provides improved thermal dissipation and improved electrical performance.

In an exemplary implementation of the semiconductor power entity, the second power semiconductor has a second semiconductor upper main face and a second semiconductor lower main face opposing the second semiconductor upper main face; wherein the second semiconductor upper main face is coplanar arranged with the second laminate upper main face to form an electrical connection between the at least one first terminal of the second power semiconductor and the third metal layer at the second laminate upper main face; and wherein the second terminal of the second power semiconductor forms an electrical connection with the fourth metal layer at the second laminate lower main face by one or more microvias extending through the second laminate layer. Alternatively, the second semiconductor lower main face is coplanar arranged with the second laminate lower main face to form an electrical connection between the second terminal of the second power semiconductor and the fourth metal layer at the second laminate lower main face; and wherein the at least one first terminal of the second power semiconductor forms an electrical connection with the third metal layer at the second laminate upper main face by one or more microvias extending through the second laminate layer.

Such a design provides the same advantage of large area chip connection on one side of the chip with the respective metal layer as described above. This large area chip connection results in improved thermal dissipation and improved electrical performance.

In the following, a method for producing a semiconductor power entity based on hybrid bonding is described. Note that the metal layers described in the following with respect to the hybrid bonding may be different from the metal layers described above with respect to the Figures.

Such a method for producing a semiconductor power entity comprises: providing a first laminate layer embedding a first power semiconductor, the first laminate layer having a first laminate upper main face and a first laminate lower main face opposing the first laminate upper main face; wherein a first metal layer is arranged at the first laminate upper main face of the first laminate layer and a second metal layer is arranged at the first laminate lower main face of the first laminate layer; providing a second laminate layer embedding a second power semiconductor, the second laminate layer having a second laminate upper main face and a second laminate lower main face opposing the second laminate upper main face; wherein a third metal layer is arranged at the second laminate upper main face of the second laminate layer and a fourth metal layer is arranged at the second laminate lower main face of the second laminate layer; applying a bonding metal at the second metal layer of the first laminate layer and/or the third metal layer of the second laminate layer, the bonding metal being placed between the first power semiconductor and the second power semiconductor and/or between respective electrical contact pairs in the first laminate layer and the second laminate layer, arranging an isolation layer between the second metal layer of the first laminate layer and the third metal layer of the second laminate layer; and laying-up and laminating the first laminate layer, the second laminate layer and the isolation layer to a semiconductor power entity, wherein the laminating transforms the bonding metal to a connection metal layer forming an electrical connection with the second metal layer and the third metal layer. Such method or process provides the advantage to form the above-described vertical connections. The method or process provides the following advantageous characteristics: Use of a standard PCB lamination process with respect to bond temperature, pressure, format; use of hybrid bonding to bond metal to metal and dielectric to metal or dielectric in one step. The latter one, e.g. dielectric to metal, is the case when there is a misalignment between contacts, or there is a metal routing without a mirrored counterpart at the opposing surface. Then, there is a contact metal to dielectric bond, without bonding metal, hence a dielectric to metal bond. Several premanufactured layers can be connected to each other in one lamination step or in several sequential lamination steps; the bonding materials can be attached or applied to the surface of the laminate layers or placed between the laminate layers prior to bonding.

In an exemplary implementation of the method, the connection metal layer is formed simultaneously with the lamination of the first laminate layer, the second laminate layer and the isolation layer.

This provides the advantage that the fabrication method can be simplified due to performing two production steps simultaneously.

In an exemplary implementation of the method, the method comprises: applying the bonding metal at the second metal layer of the first laminate layer; before the laying-up and laminating; and applying the isolation layer at the third metal layer of the second laminate layer before the laying-up and laminating, wherein the isolation layer is structured to form an opening for embedding the bonding metal.

This provides the advantage of flexibility in the sequence of the different production steps. It does not matter, for example, to which laminate layer the bonding metal or the isolation layer is applied to. They only need to be complementary.

In an exemplary implementation of the method, applying the bonding metal comprises plating of metals, printing or dispending of pastes, placing of preforms; and wherein applying the isolation layer comprises printing, coating, laminating or dispensing of dielectric material.

This provides the advantage of providing alternatives for application of the bonding metal and application of the isolation layer.

In an exemplary implementation of the method, the method comprises: applying the isolation layer at the third metal layer of the second laminate layer before the laying-up and laminating, wherein the isolation layer is structured to form an opening for embedding the bonding metal; and placing the bonding metal into the opening of the isolation layer on the third metal layer.

This provides the advantage of flexibility in the sequence of the different production steps.

In an exemplary implementation of the method, the method comprises: placing the isolation layer between the second metal layer of the first laminate layer and the third metal layer of the second laminate layer during the laying-up and laminating, wherein the isolation layer is nonstructured.

In an exemplary implementation of the method, the method comprises: placing the isolation layer between the second metal layer of the first laminate layer and the third metal layer of the second laminate layer during the laying-up and laminating, wherein the isolation layer is structured to form an opening for embedding the bonding metal.

This provides the advantage of providing alternatives for placement of the isolation layer.

In an exemplary implementation of the method, the method comprises: placing a hybrid bonding sheet between the second metal layer of the first laminate layer and the third metal layer of the second laminate layer during the laying-up and laminating. The hybrid bonding sheet comprising an isolating carrier with any-shape metal through-connections, a dielectric bonding layer at the top and at the bottom of this carrier, and a metallic bonding layer embedded in the dielectric bonding layer, the metallic bonding layer arranged to connect with the metallic through-connections of the isolating carrier layer.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.

Claims

1. A semiconductor package (100) comprising: at least one electronic chip (140) comprising at least one first connection terminal (141) for an electrical connection of the at least one electronic chip (140); an encapsulant (150) encapsulating at least part of the at least one electronic chip (140), the encapsulant (150) comprising a first main surface (150a) and a second main surface (150b) opposing the first main surface (150a), and one or more side walls (150c) between the first main surface (150a) and the second main surface (150b); a first metal layer (110) placed upon at least one of the first main surface (150a) or the second main surface (150b) of the encapsulant (150), the first metal layer (110) electrically connecting the at least one first connection terminal (141) of the at least one electronic chip (140) by at least one electrical conductor (111) extending from the at least one first connection terminal (141) to the first metal layer (110); a second metal layer (120) placed upon at least one side wall of the one or more side walls (150c) of the encapsulant (150), the second metal layer (120) contacting the first metal layer (110) to form an electrically and thermally conductive connection between the second metal layer (120) and the first metal layer (110), wherein the second metal layer (120) extends along the at least one side wall (150c) of the encapsulant (150) to a third metal layer (130) of the semiconductor package (100) to form an electrically and thermally conductive connection of the at least one first connection terminal (141) via the at least one side wall (150c) to the third metal layer (130) of the semiconductor package (100).

2. The semiconductor package (100) of claim 1 , wherein the at least one electronic chip (140) comprises at least one or a combination of the following device types: a MOSFET, a GaN, an IGBT, a SiC, a GaAs or another wide band gap semiconductor or another device type.

3. The semiconductor package (100) of claim 1 or 2, wherein the second metal layer (120) extends upon a predominant portion of the at least one side wall (150c) of the encapsulant (150).

4. The semiconductor package (100) of any of the preceding claims, comprising: a substrate (101) for carrying the encapsulant (150) with the at least one electronic chip (140), the substrate (101) comprising at least one solder pad (102) for electrically and thermally connecting the at least one electronic chip (140); and a solder fillet (103) arranged at side faces of the second metal layer (120) and below the first metal layer (110), wherein the solder fillet (103) is formed to extract at least a portion of heat generated by the at least one electronic chip (140) via the second metal layer (120) placed on the side walls (150c) of the encapsulant (150) to the at least one solder pad (102) of the substrate (101).

5. The semiconductor package (100) of any of the preceding claims, wherein the at least one electronic chip (140) comprises at least one second connection terminal (142); wherein the first metal layer (110) comprises a first portion electrically connecting the at least one first connection terminal (141) of the at least one electronic chip (140) and a second portion electrically connecting the at least one second connection terminal (142) of the at least one electronic chip (140); wherein the second metal layer (120) comprises a first portion contacting the first portion of the first metal layer (110) and a second portion contacting the second portion of the first metal layer; wherein the first portion of the second metal layer (120) extends along a first side wall of the at least one side wall (150c) to a first portion of the third metal layer (130) to form an electrically and thermally conductive connection of the at least one first connection terminal (141) via the first side wall (150c) to the first portion of the third metal layer (130) of the semiconductor package (100); and wherein the second portion of the second metal layer (120) extends along a second side wall of the at least one side wall (150c) to a second portion of the third metal layer (130) to form an electrically and thermally conductive connection of the at least one second connection terminal (142) via the second side wall to the second portion of the third metal layer (130) of the semiconductor package (100).

6. The semiconductor package (100) of any of the preceding claims, wherein the third metal layer (130) is placed upon a main surface of the encapsulant (150) opposing the main surface of the encapsulant (150) upon which the first metal layer (110) is placed.

7. The semiconductor package (100) of claim 6, wherein the at least one electronic chip (140) comprises at least one third connection terminal (143); wherein the third metal layer (130) is electrically connecting the at least one third connection terminal (143) of the at least one electronic chip (140) by at least one third electrical conductor (113) extending from the at least one third connection terminal (143) to the third metal layer (130).

8. The semiconductor package (100) of any of claims 1 to 5, comprising: at least one second electronic chip (160) comprising at least one first connection terminal (161); a second encapsulant (170) encapsulating at least part of the at least one second electronic chip (160), the second encapsulant (170) comprising a first main surface (170a) and a second main surface (170b) opposing the first main surface (170a), and one or more side walls (170c) between the first main surface (170a) and the second main surface (170b), wherein the second encapsulant (170) with the encapsulated at least one second electronic chip (160) is stacked upon the encapsulant (150) with the encapsulated at least one electronic chip (140).

9. The semiconductor package (100) of claim 8, comprising: a fourth metal layer (190) placed upon at least one of the first main surface (170a) or the second main surface (170b) of the second encapsulant (170); and a fifth metal layer (180) placed upon one of the main surfaces (170a, 170b) of the second encapsulant (170) opposite to the fourth metal layer (190).

10. The semiconductor package (100) of claim 9, wherein the second metal layer (120) is further placed upon at least one side wall of the one or more side walls (170c) of the second encapsulant (170) to form an electrically and thermally conductive connection between the at least one side wall (170c) of the second encapsulant (170) and the at least one side wall (150c) of the encapsulant (150).

11. The semiconductor package (100) of claim 10, wherein the at least one side wall (170c) of the second encapsulant (170) and the at least one side wall (150c) of the encapsulant (150) are located at a same side of the semiconductor package (100).

12. The semiconductor package (100) of any of claims 9 to 11, wherein the at least one electronic chip (140) and the at least one second electronic chip (160) are electrically connected in parallel or in a half-bridge configuration.

13. The semiconductor package (100) of claim 12, wherein for the parallel configuration, the electrical connection is based on a common source configuration or a common drain configuration; wherein for the half-bridge configuration, the electrical connection is based on a source down configuration or a drain down configuration.

14. The semiconductor package (100) of claim 13, wherein for the parallel configuration the at least one first terminal (141) of the at least one electronic chip (140) and the at least one first terminal (141) of the at least one second electronic chip (160) are facing in opposite directions; wherein the electrical connection of the at least one electronic chip (140) and the at least one second electronic chip (160) is formed by an interconnection of the third metal layer (130) with the fifth metal layer (180) and by the second metal layer (120) that is placed upon the side walls (150c) of the encapsulant (150) and upon the side walls (170c) of the second encapsulant (170).

15. The semiconductor package (100) of claim 13, wherein for the half-bridge configuration the at least one first terminal (141) of the at least one electronic chip (140) and the at least one first terminal (141) of the at least one second electronic chip (160) are facing in the same direction; wherein the electrical connection of the at least one electronic chip (140) and the at least one second electronic chip (160) is formed by an interconnection of the third metal layer (130) with the fifth metal layer (180) and by the second metal layer (120) that is placed upon the side walls (150c) of the encapsulant (150) and upon the side walls (170c) of the second encapsulant (170).

16. The semiconductor package (100) of claim 15, wherein for the half-bridge configuration a source terminal of the at least one electronic chip (140) is connected to a drain terminal of the at least one second electronic chip (160) by the interconnection of the third metal layer (130) with the fifth metal layer (180) and by the second metal layer (120) that is placed upon the side walls (150c) of the encapsulant (150) and upon the side walls (170c) of the second encapsulant (170).

17. A method for manufacturing an embedded component layer, the method comprising: providing a printed circuit board, PCB, core layer with openings in the PCB core layer; mounting at least one electronic chip (140) inside the openings of the PCB core layer; embedding the at least one electronic chip (140) inside the PCB core layer by lamination to form an embedded component layer; cutting microvias into the embedded component layer; electrically connecting the at least one electronic chip (140) by metal plating; and structuring the embedded component layer.

18. A method for manufacturing a printed circuit board, PCB, layer with at least one electronic chip (140) embedded inside the PCB layer, the method comprising: laying-up at least one embedded component layer and laminating the layed-up at least one embedded component layer to form a lay-up package, the lay-up package comprising a top side and a bottom side opposing the top side and side walls between the top side and the bottom side; cutting through holes or slot openings into the lay-up package extending from the top side to the bottom side of the lay-up package, wherein the through holes or slot openings are cutting through a metal plating of the at least one embedded component layer, the metal plating providing an electrically and thermally connection of at least one first connection terminal of the at least one electronic chip (140); metal plating the through holes or slot openings of the lay-up package to electrically and thermally connect the at least one first connection terminal (141) of the at least one electronic chip (140); and dicing the lay-up package by cutting from a middle of a through hole or slot opening of the lay-up package and exposing one side of the plated through hole or slot opening to form one or more PCB layers with at least one electronic chip (140) embedded inside the PCB layer (100).

19. The method of claim 18, wherein laying-up the at least one embedded component layer comprises placing the at least one embedded component layer between prepreg material and metal foils to form the lay-up package comprising at least one of a top metal foil at the top side of the lay-up package and a bottom metal foil at the bottom side of the lay-up package.

20. The method of claim 18 or 19, comprising: stacking at least two embedded component layers above each other; and electrically connecting the at least one electronic chips (140, 160) of the at least two embedded component layers to form a parallel or a half-bridge configuration.