WO2024066407A1 - 电路版图的布线方法、装置、设备、存储介质及产品 - Google Patents
电路版图的布线方法、装置、设备、存储介质及产品 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004590 computer program Methods 0.000 claims description 11
- 230000001174 ascending effect Effects 0.000 claims description 5
- 238000004422 calculation algorithm Methods 0.000 abstract description 33
- 238000012545 processing Methods 0.000 abstract description 11
- 230000000875 corresponding effect Effects 0.000 description 33
- 238000010586 diagram Methods 0.000 description 25
- 238000013461 design Methods 0.000 description 19
- 239000000243 solution Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000006870 function Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000012895 dilution Substances 0.000 description 3
- 238000010790 dilution Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 101000827703 Homo sapiens Polyphosphoinositide phosphatase Proteins 0.000 description 2
- 102100023591 Polyphosphoinositide phosphatase Human genes 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000005610 quantum mechanics Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 1
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 1
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 1
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 239000003570 air Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
- G06F30/3953—Routing detailed
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/04—Constraint-based CAD
Definitions
- the embodiments of the present application relate to the field of micro-nano processing technology, and in particular to a wiring method, device, equipment, storage medium and product of a circuit layout.
- automatic wiring refers to the layout of circuits in the process of automatically completing the design of circuit layouts through software.
- the automatic routing algorithm usually divides the routing area into several grids or rectangular areas, and controls the routing path to be arranged along the grid lines, or controls the routing path to cross the rectangular area of the path, so as to connect the components or solder joints in the routing area.
- the wiring path obtained by the solution in the above-mentioned related technology is a horizontal and vertical route, and there is usually a large bend at the turn, which does not meet the requirements of some chip designs that require small curvature wiring, affecting the scope of application of the above-mentioned automatic wiring algorithm.
- the embodiments of the present application provide a wiring method, device, equipment, storage medium and product for a circuit layout, which can generate small curvature turns in the wiring path during the automatic wiring process, thereby expanding the scope of application of the automatic wiring algorithm.
- the technical solution is as follows:
- a wiring method for a circuit layout is provided, the method being executed by a computer device, the method comprising:
- a routing path passing through the at least one routing point is generated; the routing path starts turning at the turning start position with the turning radius.
- a wiring device for a circuit layout comprising:
- a first acquisition module configured to acquire location information of at least one wiring point in the circuit layout from wiring planning information of the circuit layout
- a second acquisition module is used to calculate the turning starting position and the turning radius corresponding to each of the at least one routing point based on the position information
- the path generation module is used to generate a routing path passing through the at least one routing point based on the turning starting position and the turning radius; the routing path starts turning at the turning starting position with the turning radius.
- At least one routing point includes n routing points; n is greater than or equal to 2, and n is an integer;
- the second acquisition module is used to:
- the auxiliary frames of the n wiring points are obtained; the auxiliary frames of the n wiring points do not overlap each other; the auxiliary frames are U-shaped square frames; the opening direction of the auxiliary frames is the same as the wiring extension direction at the wiring points, and the center position of the auxiliary frames is On an extension line starting from the wiring point;
- the turning starting positions and turning radii corresponding to the n routing points are calculated;
- the turning starting position of the routing point is obtained based on the offset between the center of the auxiliary frame of the routing point and the routing point; and the turning radius of the routing point is obtained based on the side length of the auxiliary frame of the routing point.
- the offset of each of the n wiring points increases in sequence according to the arrangement order.
- the side lengths of the auxiliary frames of the n wiring points increase in ascending order.
- the second acquisition module is used to acquire the auxiliary frames of the n routing points based on the arrangement order of the n routing points, the position information of the components in the extension direction of the n routing points, and the position information of the n routing points.
- the second acquisition module is used to sort the positions of the n routing points in a direction opposite to the turning direction to obtain an arrangement order of the n routing points.
- the first acquisition module is used to traverse the position information of each of the wiring points in the wiring planning information to obtain the position information of n wiring points;
- the turning directions of the n routing points are the same, and the position information of any two adjacent routing points among the n routing points meets the specified conditions.
- the specified condition includes:
- the difference between the horizontal coordinates of any two adjacent wiring points is less than a first difference threshold, and the difference between the vertical coordinates of any two adjacent wiring points is less than a second difference threshold.
- the path generation module is used to:
- the turning angle of the first routing point is obtained; the first routing point is any one of the at least one routing point;
- a routing path of the first routing point is generated based on a turning start position of the first routing point, a turning radius of the first routing point, and a turning angle of the first routing point.
- a chip product comprising: at least one wiring point;
- the at least one routing point has a turning start position and a turning radius on the respective routing path, and the routing path starts from the turning position and turns with the turning radius.
- a computer device which includes a processor and a memory, wherein the memory stores at least one computer instruction, and the at least one computer instruction is loaded and executed by the processor to implement the above-mentioned circuit layout wiring method.
- a computer-readable storage medium wherein at least one computer instruction is stored in the storage medium, and the at least one computer instruction is loaded and executed by a processor to implement the above-mentioned circuit layout wiring method.
- a computer program product or a computer program comprising computer instructions, the computer instructions being stored in a computer-readable storage medium.
- a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the wiring method of the circuit layout.
- the initial turning position of the above wiring point and the turning radius corresponding to the turning curvature are obtained, and the wiring path is controlled to turn based on the obtained initial turning position and turning radius, so as to realize the control of the turning curvature of the wiring path in the automatic wiring process, so that the automatic wiring algorithm can be applicable to the automatic wiring of chips that have requirements on the turning curvature, thereby expanding the applicable scenarios of the automatic wiring algorithm.
- FIG1 is a schematic diagram of an application scenario of a superconducting quantum chip provided by an embodiment of the present application
- FIG2 is a schematic diagram of the classic automatic routing involved in the present application.
- FIG3 is a schematic diagram of a CPW circuit involved in the present application.
- FIG4 is a flow chart of a wiring method for a circuit layout provided by an embodiment of the present application.
- FIG5 is a schematic diagram of a dense area involved in this application.
- FIG6 is a schematic diagram of simulated CPW wiring through an airport involved in the present application.
- FIG7 is a flow chart of a wiring method for a circuit layout provided by an embodiment of the present application.
- FIG8 is a schematic diagram of the arrangement of wiring points involved in the embodiment shown in FIG7;
- FIG9 is a schematic diagram of offset settings involved in the embodiment shown in FIG7 ;
- FIG10 is a schematic diagram of the turning radius involved in the embodiment shown in FIG7 ;
- FIG11 is a schematic diagram of a wiring path involved in the embodiment shown in FIG7 ;
- FIG. 12 is a process flow chart of the automatic routing algorithm involved in the embodiment shown in FIG. 7;
- FIG13 is a schematic diagram of a wiring path of a chip product according to an embodiment of the present application.
- FIG14 is a block diagram of a wiring device for a circuit layout according to an embodiment of the present application.
- FIG. 15 is a schematic diagram of the structure of a computer device provided in one embodiment of the present application.
- Superconducting quantum chip The central processing unit of a superconducting quantum computer.
- a quantum computer is a machine that uses the principles of quantum mechanics to perform calculations. Based on the superposition principle and quantum entanglement of quantum mechanics, quantum computers have strong parallel processing capabilities and can solve some problems that are difficult for classical computers to calculate.
- the zero resistance characteristics of superconducting quantum bits and the manufacturing process that is close to that of integrated circuits make the quantum computing system built using superconducting quantum bits one of the most promising systems for realizing practical quantum computing.
- Figure 1 shows a schematic diagram of an application scenario of a superconducting quantum chip provided by an embodiment of the present application.
- the application scenario can be a superconducting quantum computing platform, which includes: a quantum computing device 11, a dilution refrigerator 12, a control device 13 and a computer 14.
- the quantum computing device 11 is a circuit that acts on a physical quantum bit.
- the quantum computing device 11 can be realized as a quantum chip, such as a superconducting quantum chip near absolute zero.
- the dilution refrigerator 12 is used to provide an absolute zero environment for the superconducting quantum chip.
- the control device 13 is used to control the quantum computing device 11, and the computer 14 is used to control the control device 13.
- the written quantum program is compiled into instructions by the software in the computer 14 and sent to the control device 13 (such as an electronic/microwave control system).
- the control device 13 converts the above instructions into electronic/microwave control signals and inputs them into the dilution refrigerator 12 to control the superconducting quantum bits at a temperature less than 10mK.
- the reading process is the opposite, and the reading waveform is transmitted to the quantum computing device 11.
- EDA Electronic Design Automation
- Automatic routing Use software to automatically complete the layout of circuits and chip designs, and connect components according to rules and requirements. It is mostly used in large-scale and ultra-large-scale integrated circuit design and is one of the links. It is usually performed after the layout is completed.
- Layout Also known as circuit layout, it is a design drawing that describes how the components in the circuit are laid out, placed, and connected. It is a planar geometric shape description of the actual circuit physical situation.
- the layout design must comply with constraints such as manufacturing process, timing, area, and power consumption.
- the layout design file contains the shape, area, and position information of each hardware unit on the chip. interest.
- Component A general term for elements and devices, which are electronic parts and components in the circuit, such as resistors, capacitors, inductors, etc.
- Coplanar waveguide It consists of a central conductor on the substrate and coplanar grounding layers on both sides. It is a microwave planar transmission line with superior performance and convenient processing. It is used to transmit microwave signals. A large number of coplanar waveguide technologies are used in superconducting quantum chips.
- Radius of curvature is the reciprocal of the curvature and is represented by R. For a curve, the radius of curvature is equal to the radius of the arc closest to the curve at that point.
- Topology is a discipline that studies topological space. It is developed from geometry and set theory. It mainly studies the properties of geometric figures or spaces that remain unchanged after continuous changes in shape. It studies concepts such as space, dimension, and transformation. Topology only considers the positional relationship between objects rather than the shape and size. Topological wiring is a wiring method based on topological structure and topological network.
- Pads exist on circuit boards and are used to connect electronic components and circuits. Solder is usually used to solder the pins of components to the circuit board. In classical circuits, pads are usually polygonal copper sheets; in superconducting quantum chips, the shape and structure of pads are different.
- Classic automatic routing is a single-line arrangement in a geometric form.
- Figure 2 shows a schematic diagram of the classic automatic routing involved in this application.
- the grid routing in the classic automatic routing uses a chessboard-like grid to cover the entire routing area.
- the components on the layout are placed in the grid like chess pieces, and the routing path is carried out along the horizontal and vertical grid lines, as shown in part (a) of Figure 2.
- the shape routing in the classic automatic routing is improved from the grid routing. Its characteristic is that it uses graphics such as rectangles instead of grids to divide the routing area into several rectangular areas, so that the routing path crosses the rectangles of the path in turn, as shown in part (b) of Figure 2.
- These geometric routing algorithms all require auxiliary positioning functions, and use the geometric coordinates and geometric characteristics of components to determine the routing path.
- the above-mentioned classic wiring methods are sequential and need to be wired one by one, which will increase the difficulty of wiring in the later stage, reduce wiring efficiency and result in very long lines.
- Current circuit designs are becoming more and more complex, making automatic wiring tools based on grid and geometric methods increasingly limited.
- the classic automatic wiring algorithm does not take into account the physical characteristics of the design requirements of some chips that require small curvature turns (such as quantum chips, specifically superconducting quantum chips).
- its wiring algorithm may generate lines with a turning radius that does not meet the design requirements, and it is impossible to customize the radius of curvature of the chip line.
- CPW coplanar waveguides
- Figure 3 shows a schematic diagram of the CPW line involved in this application.
- the structure of the CPW line is shown in part (a) of Figure 3. It consists of a central conductor on the substrate and ground wires on both sides. The central conductor and the ground wire are both formed by metal films. Therefore, when microwaves propagate therein, the electric field is distributed in the air, substrate and metal layer.
- CPW is different from the signal line in the classical chip.
- the potential difference caused by it will generate a parasitic mode in the circuit and couple with the CPW mode, which will have a greater impact on the transmission characteristics of the circuit. Therefore, the wiring algorithms and rules of classical EDA cannot be directly applied to the automatic wiring of superconducting quantum chips.
- FIG. 4 shows a flow chart of a wiring method for a circuit layout provided by an embodiment of the present application.
- the execution subject of each step of the method may be a computer device.
- the method may include the following steps:
- Step 41 obtaining location information of at least one wiring point in the circuit layout from wiring planning information of the circuit layout.
- the routing point is an endpoint of a routing path in the circuit layout, or the routing point is a node passed through in the routing path in the circuit layout.
- the wiring point can be a node of a pin of a component or solder joint in a circuit layout, or a wiring point
- the position may also be a node of an extension line of a pin of a component or a solder joint.
- a wiring path may be set between two wiring points. Step 42, based on the position information, calculate the turning starting position and turning radius corresponding to each of at least one wiring point.
- the turning radius may refer to the radius of the circle where the arc formed by the turning of the wiring path is located.
- an auxiliary frame is set in the routing extension direction of the routing point, the auxiliary frame is a U-shaped square frame, the opening direction of the auxiliary frame is the same as the routing extension direction at the routing point, the center of the auxiliary frame is located on the extension line starting from the routing point, the midpoint of the line between the center of the auxiliary frame and the routing point is used as the starting position of the turn, and the side length of the auxiliary frame is used as the turning radius.
- a pair of wiring points may not be directly connected by a horizontal or vertical line, or there may be other components or solder joints between the pair of wiring points, which results in the wiring path between the pair of wiring points needing to go through one or more turns.
- the position where the wiring point starts to turn on the subsequent wiring path and the turning radius can be determined, so that the turning area of the subsequent wiring path can be controlled.
- Step 43 based on the turning start position and the turning radius, generating a routing path passing through at least one routing point; the routing path starts turning at the turning start position with the turning radius.
- Each of the at least one routing point corresponds to a routing path. For example, when there are n routing points, n routing paths may be generated.
- the subsequent wiring path after the wiring point is extended to the starting turning position and then starts to turn with the turning radius, thereby obtaining a wiring path for at least one wiring point.
- the scheme shown in the embodiment of the present application obtains the initial turning position of the above-mentioned wiring point and the turning radius corresponding to the turning curvature through the position information of at least one wiring point, and controls the wiring path to turn based on the obtained initial turning position and turning radius, thereby realizing the control of the turning curvature of the wiring path during the automatic wiring process, so that the automatic wiring algorithm can be applied to the automatic wiring of chips that have requirements for the turning curvature, thereby expanding the applicable scenarios of the automatic wiring algorithm.
- the automatic wiring software/tool can determine the dense area of wiring points in the circuit layout by traversing the position information of each wiring point in the wiring planning information, and control the turning curvature in the wiring path of the wiring points in the dense area to reduce the calculation amount of automatic wiring.
- the solution provided in the embodiments of the present application can add the position of the U-shaped block (represented by "airport") and the setting of the runway sequence on the basis of the superconducting quantum chip pad and pin docking algorithm to achieve the goal of smoothing the large curvature wiring in dense areas.
- a U-shaped block can be placed at the end point of the CPW to be connected in the dense area to guide the direction of the arc of the CPW turn.
- the radius of the arc can be positively correlated with the side length of the U-shaped block (for example, half the side length of the U-shaped block), so the size of the U-shaped block can be changed according to actual needs. The larger the required curvature radius, the larger the size of the U-shaped block should be.
- FIG. 6 shows a schematic diagram of simulating CPW wiring through an airport involved in this application.
- the "airport” is a U-shaped block in actual wiring
- the "runway” inside the airport is a fixed CPW wiring path
- the "passenger plane” 61 is the head of the wiring.
- the passenger plane takes off and turns according to a predetermined arc path, corresponding to the automatic wiring to make a small curvature turn.
- FIG. 7 shows a flow chart of a wiring method for a circuit layout provided by an embodiment of the present application.
- the execution subject of each step of the method may be a computer device.
- the method may include the following steps:
- Step 701 Acquire location information of at least one wiring point in the circuit layout from wiring planning information of the circuit layout.
- the circuit layout may be a circuit layout of a quantum chip, for example, a circuit layout of a superconducting quantum chip.
- the solution shown in the embodiment of the present application can be processed for a single wiring point, or can also be processed for two or more wiring points.
- the position information of the at least one routing point when processing is performed on two or more routing points, includes position information of n routing points, where n is greater than or equal to 2 and is an integer.
- the step of acquiring the position information of at least one wiring point in the circuit layout from the wiring planning information of the circuit layout may include:
- the turning directions of the n routing points are the same, and the position information of any two adjacent routing points among the n routing points meets the specified conditions.
- the above specified conditions include:
- the difference between the horizontal coordinates of any two adjacent wiring points is less than the first difference threshold, and the difference between the vertical coordinates of any two adjacent wiring points is less than the second difference threshold.
- the automatic routing software/tool can determine the dense area of routing points in the circuit layout by traversing the position information of each routing point in the routing planning information, and control the curvature of the routing path of the routing points in the dense area.
- Whether points t 1 , t 2 satisfy p(t i ) ⁇ p(t k ) can be determined based on whether the difference in the horizontal and vertical coordinates of t 1 , t 2 is less than twice the neighborhhood parameter, that is,
- the 2*neighborhhood1 is the first difference threshold
- the 2*neighborhhood2 is the second difference threshold.
- the neighborhood1 and neighborhood2 may be the same or different.
- the first difference threshold and the second difference threshold may also be set to different parameter values.
- the currently traversed routing point is added to the point set corresponding to the previously traversed routing point.
- one or more point sets can be traversed from the routing planning information, that is, corresponding to one or more dense areas. Afterwards, the routing points in any point set can be obtained as at least one of the above-mentioned routing points, and the position information of at least one routing point can be obtained.
- the computer device can divide the four CPW lines into two independent dense areas (i.e., the upper two CPW lines constitute one dense area, and the lower two CPW lines constitute another dense area), and perform subsequent processing separately.
- the turning direction may be determined by a positional relationship between a routing point and an end point of a routing path of the routing point.
- the turning direction refers to a direction perpendicular to the extension direction of the current wiring point. For example, taking the extension direction of the current wiring point as forward, the turning direction may be left or right.
- Step 702 Calculate the turning start position and turning radius corresponding to at least one routing point based on the position information.
- the step of obtaining the turning starting position and turning radius of each of the at least one routing point based on the position information of the at least one routing point may include:
- the turning directions of the routing paths of the n routing points are the same, and obtaining the arrangement order of the n routing points includes:
- the positions of the n routing points are sorted in the reverse direction of the turning direction to obtain the arrangement order of the n routing points.
- the algorithm provided in the embodiment of the present application can refer to the method for setting the track and the starting position of the athlete in the track and field long-distance running event.
- the inside of the track and field track is the first to turn and has the smallest turning radius. Since the curvature of the inner curve is larger, the athletes on the inner track also need to stand further back when starting.
- Figure 8 shows a schematic diagram of the wiring point sorting involved in the embodiment of the present application.
- the CPW located on the inside should also turn first, and the turning radius is the smallest (but not less than the minimum radius that meets the design requirements), leaving turning space for the remaining CPW lines on the outside.
- the turning order of each pair of CPW is determined by sorting from the inside to the outside.
- the above-mentioned sorting from the inside to the outside is the sorting in the opposite direction of the turning direction.
- the auxiliary frame determination order corresponding to the n wiring points is determined according to the arrangement order; according to the auxiliary frame determination order, auxiliary frames are set in sequence in the wiring extension direction of each of the n wiring points to obtain auxiliary frames for each of the n wiring points.
- the turning starting positions and turning radius of the n routing points are obtained.
- the midpoint of the line between the center of the auxiliary frame corresponding to the i-th routing point and the i-th routing point is used as the turning start position, and the side length of the auxiliary frame is used as the turning radius.
- i is a positive integer.
- the turning start position of the routing point is obtained based on the offset between the center of the auxiliary frame of the routing point and the routing point; and the turning radius of the routing point is obtained based on the side length of the auxiliary frame of the routing point.
- the offsets of the n wiring points are increased in order of arrangement.
- the side lengths of the auxiliary frames of the n wiring points increase in order of arrangement.
- a U-shaped block, "airport”, which is used to control the turning curvature radius can be established based on the turning order at the place where the dense area CPW is about to turn. At this time, it is necessary to consider where the "airport" is placed.
- airports are scattered in different provinces and cities based on factors such as city size, population density, and geographical location. Often a city will only have one or two airports at most, and the distance between airports will not be too close to avoid conflicts in routes and scheduling between airports.
- the algorithm involved in this application needs to avoid the U-shaped blocks on the CPW from crossing or overlapping each other, because this will cause errors in automatic routing.
- the algorithm also needs to avoid mutual obstruction and interference when the CPW turns.
- the scheme shown in the embodiment of this application can specifically control the density of the U-shaped blocks in each dense area. If the distance is too close, the turning space will be limited or the CPWs will be too close. If the distance is too far, it will cause a waste of layout space and even affect the routing of other places.
- an "airport" is set before turning for each pair of CPWs in a dense area.
- an offset parameter may be set before each "airport” to control the horizontal distance and take-off order of the "airport" under the premise that the layout space allows.
- Figure 9 shows a schematic diagram of the offset setting involved in the embodiment of the present application.
- the scheme shown in the embodiment of the present application sets an offset parameter (i.e., the above-mentioned offset), which is the horizontal distance offset between the middle of the "airport" (the center of the U-shaped square) and the end of the CPW straight line in the original layout near the turn, which is used to adjust the density between airports.
- the above-mentioned offset value can be non-fixed, that is, the offset can be increased in sequence according to the above-mentioned arrangement order, and the difference between the offsets of adjacent wiring points can be pre-set by the developer or designer, or it can be determined according to the layout information.
- the scheme shown in the embodiment of the present application can set independent offsets for different dense areas.
- the above-mentioned obtaining the auxiliary frames of the n wiring points based on the arrangement order of the n wiring points and the position information of the n wiring points includes:
- the auxiliary frames of the n wiring points are obtained.
- a computer device determines an offset value based on position information of components in the extension direction of the n routing points and position information of the n routing points, and determines the auxiliary frame corresponding to each of the n routing points in sequence according to the auxiliary frame determination order based on the determined offset value.
- the algorithm shown in the embodiment of the present application can traverse and search for possible offset values based on the layout information around the dense area, including the distance between components and obstacles, etc., and set a suitable solution so that the "airports" do not affect each other or overlap, while minimizing the occupation of the layout space.
- the algorithm involved in the embodiment of the present application is characterized in that the curvature radius of the CPW turn is set by using a U-shaped block and guiding the turn.
- the curvature radius of the CPW turn can be set to half the side length of the U-shaped block. If you want to increase the turning radius, just increase the side length of the block accordingly.
- FIG. 10 shows a schematic diagram of the turning radius involved in an embodiment of the present application. As shown in Figure 10, it shows an arc turn made by a CPW with an order of 1 in a dense area, and its curvature radius is R_1. As the turning path setting continues, the curvature radius set for the later turns in the same dense area can be larger and larger to avoid the CPW arc with a higher order.
- the initial value and increase of the curvature radius are selected by automatically traversing the values (for example, starting from the minimum design requirement and increasing) until the optimal solution is obtained.
- the initial value and increment of the curvature radius may also be preset by a developer or designer.
- the computer device when determining the auxiliary frames of each of the n routing points, the computer device first sets the side length and offset value of each of the n routing points to the initial side length and initial offset value; then, according to the arrangement order of the n routing points, the side length and offset value of the auxiliary frame of each routing point are determined in turn according to the pre-specified side length increase step and offset value increase step, so that the auxiliary frame of the current routing point does not overlap with the auxiliary frame of the previous routing point, and the side length of the auxiliary frame of the current routing point is greater than the side length of the auxiliary frame of the previous routing point; at the same time, the size and offset value of the auxiliary frame are restricted, for example, the auxiliary frame is restricted to not overlap with other components.
- the solution shown in the embodiment of the present application specifies the radius and location of the "airport" through protobuf, where
- the neighborhood field (taking neighborhood1 and neighborhood2 as an example) controls the size of the airport, and the offset controls the location of the airport.
- the algorithm provided in the embodiment of the present application (which may be referred to as the "airport" algorithm) can be implemented, and its code may be as follows:
- Step 703 Acquire a turning angle of the first routing point based on the turning start position of the first routing point, the turning radius of the first routing point, and the position information of the target routing point corresponding to the first routing point.
- the first wiring point is any one of the at least one wiring point.
- the computer device takes the turning starting position of the first wiring point as the starting point, takes the position information of the target wiring point corresponding to the first wiring point as the end point, turns with the turning radius of the first wiring point between the starting point and the end point, and calculates the turning angle corresponding to this turn.
- the turning angle can be determined in combination with the position information of the corresponding target routing point of at least one routing point, that is, it is necessary to determine how much angle to turn from the turning starting position.
- Step 704 Generate a routing path for the first routing point based on the turning start position of the first routing point, the turning radius of the first routing point, and the turning angle of the first routing point.
- the computer device takes the turning start position of the first routing point as the starting point, turns according to the turning radius and the turning angle of the first routing point, and determines the generated route as the routing path of the first routing point.
- the above-mentioned generated wiring path can refer to the point set corresponding to the generated wiring path; for example, taking CPW as an example, the above-mentioned wiring path can be implemented as a CPW point set, and the CPW point set includes the position information of n points in the CPW line laid out on the wiring path.
- the computer device can also generate parameter information of the arc segment of the wiring at the turning point corresponding to the first wiring point; wherein the parameter information of the arc segment includes arc parameters and center parameters, the arc parameters can be used to indicate the arrangement order of each point contained in the arc segment, and the center parameters can be used to indicate the center position corresponding to the arc segment.
- the wiring path starts from a turning position and turns at a turning radius.
- the wiring path corresponding to the first wiring point starts from the starting position of the turn, and after turning the turning angle according to the turning radius, extends forward along the tangent direction of the circle where the arc formed by the turn is located. That is to say, when calculating the turning angle, it is necessary to comprehensively consider the corresponding target wiring point of the wiring point.
- the turning start position and turning radius of the first routing point and the target routing point can be calculated at the same time, and the turning start position and turning radius of the first routing point and the target routing point can be calculated respectively.
- the turning radius of each of the first routing point and the target routing point can be determined, and then combined with the respective turning starting positions and turning angles of the first routing point and the target routing point, the routing path between the first routing point and the target routing point can be drawn.
- Figure 11 shows a schematic diagram of a wiring path involved in an embodiment of the present application.
- the turning radius 1101 of the wiring path generated according to the scheme shown in the embodiment of the present application is significantly larger than the turning radius 1102 of the wiring path generated according to the classic automatic wiring algorithm, and the curvature radius is significantly reduced.
- the algorithm used in the solution shown in the embodiment of the present application is not only applicable to densely populated areas, but can also be extended to any wiring point in the layout that requires flexible adjustment of its turning radius.
- the scheme shown in the embodiment of the present application obtains the initial turning position of the starting turning of the above-mentioned wiring point and the turning radius corresponding to the turning curvature through the position information of at least one wiring point, and controls the wiring path to turn based on the obtained initial turning position and turning radius, thereby realizing the control of the turning curvature of the wiring path during the automatic wiring process, so that the automatic wiring algorithm can be applicable to the automatic wiring of chips that have requirements for the turning curvature, thereby expanding the applicable scenarios of the automatic wiring algorithm.
- the scheme shown in the embodiment of the present application is not limited to horizontal and vertical wiring paths. It can comprehensively consider offset parameters and turning radius in combination with multiple wiring points. It does not need to be wired one by one through a serial wiring method. It can reduce the wiring difficulty and improve the wiring efficiency in large-scale chip wiring.
- the automatic routing algorithm has more tolerance in the selection of routing paths and routing directions. While realizing automatic routing, it can automatically identify and increase the curvature radius of lines in dense areas (such as CPW) at turns, thereby improving chip research and development efficiency.
- the topological routing algorithm can generate routing paths according to the circuit routing rules.
- An important parameter in the rule is the neighborhood parameter, which is usually set to the minimum spacing between routing lines in the layout (dense area) to ensure the distance between lines (avoid line overlap and intersection) for automatic routing.
- the neighbor parameter is usually a fixed value, when the CPW spacing in the dense area of the layout is small, there will be a problem of excessive curvature of the automatically arranged CPW in the dense area.
- the scheme shown in the embodiment of the present application introduces a new automatic routing algorithm for processing, and the processing flow chart of the automatic routing algorithm can be shown in Figure 12.
- the automatic routing tool may traverse each routing point in the routing planning information of the circuit layout in order from small to large abscissas/ordinates to search for and locate a dense area of routing points in the circuit layout.
- the automatic routing tool searches for at least two routing points with the same turning direction, and the difference between the horizontal coordinate and the vertical coordinate between each two adjacent routing points in the at least two routing points is less than the difference threshold, it is determined that the routing point dense area has been entered.
- the automatic routing tool may sort the at least two routing points in the dense area according to the reverse direction of the turning direction of the at least two routing points in the dense area to obtain the arrangement order of the at least two routing points in the dense area.
- the automatic routing tool may set the offset of each of the at least two routing points in the dense area in an incremental manner according to the arrangement order of the at least two routing points in the dense area.
- the automatic wiring tool can set the wiring points in an incremental manner according to the arrangement order of at least two wiring points in the above dense area.
- the turning radius corresponding to at least two wiring points in the dense area is set (that is, the side length of the airport is set), and then based on the offset and turning radius of at least two wiring points in the dense area, a wiring path for at least two wiring points to turn from their respective turning starting positions is generated, and the extension direction of the wiring path after the turn is tangent to the circle where the arc formed by the turning position is located, and can be connected to the target wiring point.
- the solution shown in the above embodiment of the present application is based on topological wiring, and an algorithm is developed that can identify dense wiring areas and customize the curvature radius of the line (such as CPW) at the turning point, so that the automatic wiring can be achieved while taking into account the effect of small curvature turns in dense areas, meeting the automatic wiring requirements of superconducting quantum chips.
- the above solution has the following advantages:
- an embodiment of the present application also provides a chip product, which includes: at least one wiring point; and the at least one wiring point has a turning starting position and a turning radius on its respective wiring path, and the wiring path starts from the turning position and turns with the turning radius.
- the wiring path of the chip product can be obtained according to the method shown in FIG. 4 or FIG. 7 .
- Figure 13 shows a schematic diagram of the wiring path of the chip product involved in the embodiment of the present application.
- the chip product includes at least one wiring point 1301 and a wiring path 1302 corresponding to the wiring point 1301, wherein the wiring path 1302 starts to turn at a turning position 1303, turns at a certain turning radius, and forms an arc-shaped turning section.
- the at least one routing point includes n routing points, and the offsets of the n routing points increase in order of arrangement.
- the offset of each wiring point in the chip product increases in sequence in the reverse direction of the turning direction.
- the turning radius of each of the n routing points increases in order of arrangement.
- the turning radius of each wiring point in the chip product increases in sequence in the reverse direction of the turning direction.
- a difference between the horizontal coordinates of any two adjacent routing points is less than a first difference threshold, and a difference between the vertical coordinates of any two adjacent routing points is less than a second difference threshold.
- the chip product is a quantum chip, for example, a superconducting quantum chip.
- FIG14 is a block diagram of a wiring device for a circuit layout according to an exemplary embodiment.
- the wiring device for the circuit layout can implement all or part of the steps performed by a computer device in the method provided in the embodiment shown in FIG4 or FIG7, and the wiring device for the circuit layout includes:
- a first acquisition module 1401 is used to acquire location information of at least one wiring point in the circuit layout from wiring planning information of the circuit layout;
- the second acquisition module 1402 is used to calculate the turning starting position and turning radius corresponding to at least one routing point based on the position information
- the path generation module 1403 is used to generate a routing path passing through at least one routing point based on the turning starting position and the turning radius; the routing path starts turning at the turning starting position with the turning radius.
- At least one routing point includes n routing points; n is greater than or equal to 2, and n is an integer;
- the second acquisition module 1402 is used to:
- the n wiring points Based on the arrangement order of the n wiring points and the position information of the n wiring points, obtain the n wiring points Auxiliary frames for each wiring point; the auxiliary frames for each of the n wiring points do not overlap each other; the auxiliary frames are U-shaped square frames; the opening direction of the auxiliary frames is the same as the wiring extension direction at the wiring point, and the center of the auxiliary frames is located on the extension line starting from the wiring point;
- the turning starting positions and turning radii corresponding to the n routing points are calculated;
- the turning starting position of the routing point is obtained based on the offset between the center of the auxiliary frame of the routing point and the routing point; and the turning radius of the routing point is obtained based on the side length of the auxiliary frame of the routing point.
- the offsets of the n wiring points are increased in ascending order according to the arrangement order.
- the side lengths of the auxiliary frames of the n wiring points increase in ascending order.
- the second acquisition module 1402 is used to acquire the auxiliary frames of the n routing points based on the arrangement order of the n routing points, the position information of the components in the extension direction of the n routing points, and the position information of the n routing points.
- the second acquisition module 1402 is used to sort the positions of the n routing points in a reverse direction of the turning direction to obtain an arrangement order of the n routing points.
- the first acquisition module 1401 is used to traverse the location information of each routing point in the routing planning information to obtain location information of n routing points;
- the turning directions of the n routing points are the same, and the position information of any two adjacent routing points among the n routing points meets the specified conditions.
- the specified condition includes:
- the difference between the horizontal coordinates of any two adjacent wiring points is less than a first difference threshold, and the difference between the vertical coordinates of any two adjacent wiring points is less than a second difference threshold.
- the path generation module 1403 is used to:
- the turning angle of the first routing point is obtained; the first routing point is any one of the at least one routing point;
- a routing path of the first routing point is generated based on a turning start position of the first routing point, a turning radius of the first routing point, and a turning angle of the first routing point.
- the circuit layout is a circuit layout of a superconducting quantum chip.
- the scheme shown in the embodiment of the present application obtains the initial turning position of the starting turning of the above-mentioned wiring point and the turning radius corresponding to the turning curvature through the position information of at least one wiring point, and controls the wiring path to turn based on the obtained initial turning position and turning radius, thereby realizing the control of the turning curvature of the wiring path during the automatic wiring process, so that the automatic wiring algorithm can be applicable to the automatic wiring of chips that have requirements for the turning curvature, thereby expanding the applicable scenarios of the automatic wiring algorithm.
- the device provided in the above embodiment when implementing its functions, only uses the division of the above functional modules as an example.
- the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.
- the device and method embodiments provided in the above embodiment belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.
- FIG15 is a schematic diagram of a computer device according to an exemplary embodiment.
- the computer device 1500 includes a processor 1501, such as a central processing unit (CPU), a system memory 1504 including a random access memory (RAM) 1502 and a read-only memory (ROM) 1503, and a system bus 1505 connecting the system memory 1504 and the processor 1501.
- the computer device 1500 also includes an input/output system 1506 for facilitating the transfer of information between various components within the computer, and a mass storage device 1507 for storing an operating system 1513 , application programs 1514 , and other program modules 1515 .
- the mass storage device 1507 is connected to the processor 1501 through a mass storage controller (not shown) connected to the system bus 1505.
- the mass storage device 1507 and its associated computer readable medium provide non-volatile storage for the computer device 1500. That is, the mass storage device 1507 may include a computer readable medium (not shown) such as a hard disk or a Compact Disc Read-Only Memory (CD-ROM) drive.
- a computer readable medium such as a hard disk or a Compact Disc Read-Only Memory (CD-ROM) drive.
- the computer-readable medium may include computer storage media and communication media.
- Computer storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data.
- Computer storage media include RAM, ROM, flash memory or other solid-state storage technologies, CD-ROM, or other optical storage, cassettes, magnetic tapes, disk storage or other magnetic storage devices.
- RAM random access memory
- the computer device 1500 can be connected to the Internet or other network devices through a network interface unit 1516 connected to the system bus 1505 .
- the memory also includes one or more computer instructions, which are stored in the memory.
- the processor 1501 implements all or part of the steps of the method shown in either Figure 4 or Figure 7 by executing the one or more computer instructions.
- a non-transitory computer-readable storage medium including instructions is also provided, such as a memory including a computer program (instructions), and the above program (instructions) can be executed by a processor of a computer device to complete the methods shown in various embodiments of the present application.
- the non-transitory computer-readable storage medium can be a ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
- a computer program product or a computer program is also provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium.
- the processor of the computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method shown in each of the above embodiments.
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Abstract
Description
Claims (15)
- 一种电路版图的布线方法,所述方法由计算机设备执行,所述方法包括:从电路版图的布线规划信息中获取所述电路版图中的至少一个布线点位的位置信息;基于所述位置信息,计算所述至少一个布线点位各自对应的转弯起始位置以及转弯半径;基于所述转弯起始位置以及转弯半径,生成经过所述至少一个布线点位的布线路径;所述布线路径在所述转弯起始位置以所述转弯半径开始转弯。
- 根据权利要求1所述的方法,其中,所述至少一个布线点位包含n个布线点位;n大于或者等于2,且n为整数;所述基于所述位置信息,计算所述至少一个布线点位各自对应的转弯起始位置以及转弯半径,包括:获取n个所述布线点位的排列次序;基于n个所述布线点位的排列次序,以及n个所述布线点位的位置信息,获取n个所述布线点位各自的辅助框;n个所述布线点位各自的所述辅助框互不重叠;所述辅助框为U型方框;所述辅助框的开口方向与所述布线点位处的布线延伸方向相同,所述辅助框的中心位于从所述布线点位开始的延长线上;基于n个所述布线点位各自的辅助框,计算n个所述布线点位各自对应的转弯起始位置以及转弯半径;其中,所述布线点位的转弯起始位置基于所述布线点位的所述辅助框的中心与所述布线点位之间的偏移量获得;所述布线点位的转弯半径基于所述布线点位的辅助框的边长获得。
- 根据权利要求2所述的方法,其中,n个所述布线点位各自的所述偏移量按照所述排列次序递增。
- 根据权利要求2所述的方法,其中,n个所述布线点位各自的所述辅助框的的边长按照所述排列次序递增。
- 根据权利要求2所述的方法,其中,所述基于n个所述布线点位的排列次序,以及n个所述布线点位的位置信息,获取n个所述布线点位各自的辅助框,包括:基于n个所述布线点位的排列次序,n个所述布线点位的延伸方向上的元器件的位置信息,以及n个所述布线点位的位置信息,获取n个所述布线点位各自的辅助框。
- 根据权利要求2所述的方法,其中,n个所述布线点位的布线路径的转弯方向相同,所述获取n个所述布线点位的排列次序,包括:将n个所述布线点位的位置按照所述转弯方向的逆方向进行排序,获得n个所述布线点位的排列次序。
- 根据权利要求2所述的方法,其中,所述从电路版图的布线规划信息中获取所述电路版图中的至少一个布线点位的位置信息,包括:遍历所述布线规划信息中的各个所述布线点位的位置信息,获得n个所述布线点位的位置信息;其中,n个所述布线点位的转弯方向相同,且n个所述布线点位中的任意两个相邻布线点位的位置信息满足指定条件。
- 根据权利要求7所述的方法,其中,所述指定条件包括:所述任意两个相邻布线点位的横坐标的差值小于第一差值阈值,且所述任意两个相邻布线点位的纵坐标的差值小于第二差值阈值。
- 根据权利要求1所述的方法,其中,所述基于所述转弯起始位置以及转弯半径,生成经过所述至少一个布线点位的布线路径,包括:基于第一布线点位的转弯起始位置、所述第一布线点位的转弯半径以及与所述第一布线点位对应的目标布线点位的位置信息,获取所述第一布线点位的转弯角度;所述第一布线点位是所述至少一个布线点位中的任意一个;基于第一布线点位的转弯起始位置、所述第一布线点位的转弯半径以及所述第一布线点位的转弯角度,生成所述第一布线点位的布线路径。
- 根据权利要求1至9任一所述的方法,其中,所述电路版图是超导量子芯片的电路版图。
- 一种芯片产品,其中,所述芯片产品包括:至少一个布线点位;所述至少一个布线点位在各自的布线路径上具有转弯起始位置和转弯半径,且所述布线路径从所述转弯位置处开始,以所述转弯半径进行转弯。
- 一种电路版图的布线装置,其中,所述装置包括:第一获取模块,用于从电路版图的布线规划信息中获取所述电路版图中的至少一个布线点位的位置信息;第二获取模块,用于基于所述位置信息,计算所述至少一个布线点位各自对应的转弯起始位置以及转弯半径;路径生成模块,用于基于所述转弯起始位置以及转弯半径,生成经过所述至少一个布线点位的布线路径;所述布线路径在所述转弯起始位置以所述转弯半径开始转弯。
- 一种计算机设备,其中,所述计算机设备包含处理器和存储器,所述存储器中存储有至少一条计算机指令,所述至少一条计算机指令由所述处理器加载并执行以实现如权利要求1至10任一所述的电路版图的布线方法。
- 一种计算机可读存储介质,其中,所述存储介质中存储有至少一条计算机指令,所述至少一条计算机指令由处理器加载并执行以实现如权利要求1至10任一所述的电路版图的布线方法。
- 一种计算机程序产品,其中,所述计算机程序产品包括计算机指令,所述计算机指令存储在计算机可读存储介质中;所述计算机指令由计算机设备的处理器执行,以实现如权利要求1至10任一所述的电路版图的布线方法。
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US18/638,544 US20240265187A1 (en) | 2022-09-30 | 2024-04-17 | Circuit layout routing method and apparatus, device, storage medium, and product |
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JP2005203632A (ja) * | 2004-01-16 | 2005-07-28 | Matsushita Electric Ind Co Ltd | 半導体集積回路の電源配線設計方法及びそのプログラム |
CN111680471A (zh) * | 2020-06-12 | 2020-09-18 | 深圳华大九天科技有限公司 | 一种集成电路版图中的布线倒角方法 |
CN112818626A (zh) * | 2021-02-26 | 2021-05-18 | 北京华大九天科技股份有限公司 | 一种基于多重掩膜版的版图布线方法 |
CN114970439A (zh) * | 2021-02-23 | 2022-08-30 | 联合微电子中心有限责任公司 | 自动布线方法、装置、计算机设备、存储介质 |
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JP2005203632A (ja) * | 2004-01-16 | 2005-07-28 | Matsushita Electric Ind Co Ltd | 半導体集積回路の電源配線設計方法及びそのプログラム |
CN111680471A (zh) * | 2020-06-12 | 2020-09-18 | 深圳华大九天科技有限公司 | 一种集成电路版图中的布线倒角方法 |
CN114970439A (zh) * | 2021-02-23 | 2022-08-30 | 联合微电子中心有限责任公司 | 自动布线方法、装置、计算机设备、存储介质 |
CN112818626A (zh) * | 2021-02-26 | 2021-05-18 | 北京华大九天科技股份有限公司 | 一种基于多重掩膜版的版图布线方法 |
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