WO2023239376A1

WO2023239376A1 - Apparatus and method for low-power synchronization

Info

Publication number: WO2023239376A1
Application number: PCT/US2022/033131
Authority: WO
Inventors: Chengzhi LI
Original assignee: Zeku, Inc.
Priority date: 2022-06-10
Filing date: 2022-06-10
Publication date: 2023-12-14

Abstract

Some embodiments of apparatuses and methods for low-power synchronization are provided. The apparatus may include a radio frequency (RF) chip and a baseband chip. The RF chip may be configured to enter a warm-up period associated with discontinuous reception (DRX) and obtain a physical downlink control channel (PDCCH) symbol. The baseband chip may be configured to estimate at least one timing offset (TO) and at least one frequency offset (FO) based on the PDCCH symbol.

Description

APPARATUS AND METHOD FOR LOW-POWER SYNCHRONIZATION

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatuses and methods for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services, e.g., telephony, video, data, messaging, and broadcasts. In wireless communication systems, such as the 4th-generation (4G) Long Term Evolution (LTE) or the 5th- generation (5G) New Radio (NR), various mechanisms are defined and introduced for cell search and selection. During the processes, a user equipment (UE) acquires synchronization with a cell both in a time domain and in a frequency domain. Under some situations, a UE that wakes up from a discontinuous reception (DRX) mode will still require maintaining the time and frequency synchronization with a cell.

SUMMARY

[0003] Some embodiments of apparatuses and methods for low-power synchronization are disclosed herein.

[0004] According to one aspect of the present disclosure, an apparatus for low-power synchronization is provided. The apparatus may include a radio frequency (RF) chip and a baseband chip. The RF chip may be configured to enter a warm-up period associated with discontinuous reception (DRX) and obtain a physical downlink control channel (PDCCH) symbol. The baseband chip may be configured to estimate at least one timing offset (TO) and at least one frequency offset (FO) based on the PDCCH symbol.

[0005] According to another aspect of the present disclosure, a method of low-power synchronization is provided. A warm-up period associated with discontinuous reception (DRX) may be entered. A physical downlink control channel (PDCCH) symbol may be obtained. At least one timing offset (TO) and at least one frequency offset (FO) may be estimated based on the PDCCH symbol.

[0006] According to still another aspect of the present disclosure, a baseband chip is provided. The baseband chip may include a processor and memory coupled to the processor and storing instructions. When executed by the processor, the instructions may cause the processor to upon a radio frequency (RF) chip entering a warm-up period associated with discontinuous reception (DRX), obtain a physical downlink control channel (PDCCH) symbol. At least one TO may be estimated based on at least one TO hypothesis. A number of the at least one TO hypothesis may be determined by a previous sleep duration. The at least one TO hypothesis may include a timing difference relative to a timing boundary of the PDCCH symbol. At least one FO may be estimated based on a plurality of FO hypotheses. The plurality of FO hypotheses may include a current FO based on the PDCCH symbol, the current FO plus delta FO, and the current FO minus the delta FO. The delta FO may be indicative of a frequency difference relative to the current FO based on the PDCCH symbol.

[0007] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0009] FIG. 1 illustrates an exemplary processing timeline for page monitoring and reception.

[0010] FIG. 2 illustrates an exemplary wireless network, in which certain aspects of the present disclosure may be implemented.

[0011] FIG. 3 illustrates a block diagram of an exemplary node, according to some aspects of the present disclosure.

[0012] FIG. 4 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency chip, and a host chip, according to some aspects of the present disclosure. [0013] FIG. 5 illustrates a block diagram of an exemplary pre-synchronization unit, according to some aspects of the present disclosure.

[0014] FIG. 6 illustrates a flow diagram of an exemplary method of low-power synchronization, according to some aspects of the present disclosure.

[0015] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0017] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” “other embodiments,” “an instance,” “some instances,” “an example,” “some examples,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0018] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures, or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for the existence of additional factors not necessarily expressly described, again, depending at least in part on the context.

[0019] Various aspects of wireless communication systems will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0020] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0021] Power consumption is an important performance index when designing a wireless communication system. In particular, for a system including a wireless device that applies a battery as an onboard power source, the low energy consumption of the wireless device becomes a crucial concern. In order to save the power, certain control mechanism, such as discontinuous reception (DRX), was introduced in the art. The DRX is a technique where the radio receiver of a UE is allowed to be switched off during some time durations when there is no allocated transmission to the UE (the OFF durations). Without the DRX, a UE may always remain awake to monitor physical downlink control channel (PDCCH) signals for the reception of the downlink data. The steady monitoring process may consume a lot of power. On the contrary, when the DRX is implemented, a UE does not need to continuously monitor the channel. Instead, the DRX can allow the radio frequency (RF) chip of the UE to enter a sleep mode for certain periods and discontinuously listen to the downlink. Through the DRX, the UE may power down a majority of the circuitry when no packets are received, and therefore, a significant reduction of the power consumption can be obtained.

[0022] While the RF chip of a UE is switched off, however, the UE may lose the synchronization as established earlier. In addition, when a UE sleeps and wakes up again (the ON durations) for the paging or the PDCCH reception, the crystal of the UE may experience certain errors, in terms of parts per million (ppm) (termed “crystal ppm error”). A UE crystal generates frequency signals that a system uses to drive the heartbeats for chipsets and thus makes command and communication possible. Due to the error of the UE crystal, the frequency and timing may further offset. As a result, at the DRX mode, a UE may still require synchronization (i.e., DRX synchronization). Through the DRX synchronization, the time domain and the frequency domain of the UE can be aligned with a cell, and the UE may be put into the sleep mode again during appropriate timing.

[0023] FIG. 1 illustrates an exemplary processing timeline for page monitoring and reception. In some other approaches in the 5GNR, at least one synchronization signal block (SSB) may be utilized in the synchronization process. Before a UE is at a page occasion, the UE may need to wake up at a predetermined time and turn on its hardware, including the RF chip, in preparation for the data reception, as shown in FIG. 1. It is a “warm-up” process. How much time in advance a UE requires to wake up may highly depend on the RF condition of the UE. Generally speaking, in a poor RF condition, a UE may need to wake up earlier than a UE in a good RF condition. Subsequently, the SSB(s) may be used to estimate timing and frequency offsets at a presynchronization stage. In order to decode a PDCCH symbol at the DRX, the pre-synchronization procedure is required.

[0024] As shown in FIG. 1, under a low signal -to-interference-plus-noise ratio (SINR) scenario, more than one SSB may be utilized so that a combination of multiple SSB measurements may be performed to obtain a required level of synchronization. In the cases where a UE is monitoring multiple SSBs, the UE may be put into a light sleep mode between the SSB monitoring, as shown in FIG. 1. The timing and frequency offsets may be estimated based on the SSBs. When the UE receives a PDCCH symbol, the UE may perform the PDCCH blind decoding to determine whether there is a paging downlink control information (DCI) in the PDCCH symbol. DCI provides the UE with the necessary information, such as physical layer resource allocation, power control commands, and hybrid automatic repeat request (HARQ) information for the downlink.

[0025] In response that the DCI indicates that there is no paging message (i.e., it is a PDCCH-only reception), the UE may go into light sleep again, as shown in FIG. 1. On the other hand, if the DCI is successfully decoded, indicating that there is a paging message carried in a physical downlink shared channel (PDSCH) symbol, accordingly, the UE may decode the PDSCH symbol. Afterward, the UE may go into a deep sleep mode.

[0026] In these approaches, however, the wake-up, warm-up, and pre-synchronization based on the SSB(s) can drain a significant amount of power from the UE. Moreover, as described above, a UE in a poor RF condition may need to wake up much earlier, for the preparation, in advance for the reception of an SSB. These processes based on the SSBs can be unfavorable for a wireless device with an onboard battery because the large power consumption may reduce the lifetime of the battery. Further, it is noted that the lifetime of the wireless device strongly correlates to the lifetime of the battery.

[0027] To overcome the above and other challenges associated with the other approaches, the present disclosure accordingly provides an inventive scheme, in which timing and frequency offsets may be directly estimated based on a received PDCCH symbol. That is, for some scenarios, the UE does not need to wake up before the PDCCH reception. Hence, the power consumption can be reduced, and the lifetime of a UE can be prolonged. In some scenarios, to further reduce the power in a PDCCH-only reception, once the PDCCH symbols are received, the RF chain in the UE may be turned off, and the pre-synchronization may be performed offline. Accordingly, the power consumption can be further decreased, thereby enhancing the user experience.

[0028] Reference will now be made in detail to exemplary embodiments of the present disclosure in the following, which may be illustrated in the accompanying drawings. It is apparent that the described embodiments are some but not all of the embodiments of the present disclosure, and the drawings are used for illustration but not for limitation.

[0029] FIG. 2 illustrates an exemplary wireless network 200, in which certain aspects of the present disclosure may be implemented. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as a user equipment (UE) 202, an access node 204, and a core network element 206. UE 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (loT) node. It is understood that UE 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0030] Access node 204 may be a device that communicates with UE 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to UE 202, a wireless connection to UE 202, or any combination thereof. Access node 204 may be connected to UE 202 by multiple connections, and UE 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0031] Core network element 206 may serve access node 204 and UE 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR system. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0032] Core network element 206 may connect with a large network, such as Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from UE 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node.

[0033] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle the authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack.

[0034] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 300 in FIG. 3. Node 300 may be configured as UE 202, access node 204, or core network element 206 in FIG. 2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is UE 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible.

[0035] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to UE 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0036] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware structure having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0037] As shown in FIG. 3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0038] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more SoCs. In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0039] Any suitable node of wireless network 200, as shown in FIG. 2, which receives signals from another node (e.g., UE 202 that receives signals from access node 204 via the downlink) may implement the methods of low-power synchronization below, with reference to FIGs. 4-7, provided by the present disclosure. Compared with the known solutions in the other approaches, it can provide a wireless communication system having better performance, less power consumption, and a longer lifetime. [0040] FIG. 4 illustrates a block diagram of an apparatus 400 according to some aspects of the present disclosure. Apparatus 400 may be an example of any suitable node of wireless network 200 in FIG. 2, such as UE 202 or access node 204. Apparatus 400 may be configured to receive signals from another node in the network. As shown in FIG. 4, apparatus 400 may include a baseband chip 402, an RF chip 404, a host chip 406, and one or more antennas 408. In some embodiments, baseband chip 402 may be embodied by processor 302 and memory 304, and RF chip 404 may be embodied by processor 302, memory 304, and transceiver 306, as described above with reference to FIG. 3. Memory 304 may be referred to as “on-chip” memory. Besides the on- chip memory (also known as “internal memory” or “local memory,” e.g., registers, buffers, or caches) on each chip 402, 404, or 406, apparatus 400 may further include an external memory 410 (e.g., the system memory or main memory) that can be shared by each chip 402, 404, or 406 through the system/main bus.

[0041] Although baseband chip 402 is illustrated as a standalone SoC in FIG. 4, it is understood that in one example, baseband chip 402 and RF chip 404 may be integrated as one SoC; in another example, baseband chip 402 and host chip 406 may be integrated as one SoC; in still another example, baseband chip 402, RF chip 404, and host chip 406 may be integrated as one SoC, as described above. The present disclosure does not limit thereto.

[0042] In the uplink, host chip 406 may generate raw data and send it to baseband chip 402 for encoding, modulation, and mapping. An interface (not shown) of baseband chip 402 may be configured to receive the data from host chip 406. Baseband chip 402 may also access the raw data generated by host chip 406 and stored in external memory 410, for example, using direct memory access (DMA). Baseband chip 402 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multiphase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 402 may perform any other functions, such as a symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 402 may send the modulated signal to RF chip 404 via the interface (not shown). RF chip 404 may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 408 (e.g., an antenna array) may transmit the RF signals provided by a transmitter TX of RF chip 404.

[0043] In the downlink, antenna 408 may receive RF signals (may be also referred to as an “RF samples”) that may include, among other signals, at least one PDCCH symbol, which may be used by baseband chip 402 for pre-synchronization. The RF signals may be passed to the receiver RX of RF chip 404. RF chip 404 may perform any suitable front-end RF functions, such as filtering, direct current (DC) offset compensation, IQ imbalance compensation, down-conversion, or sample-rate conversion, and convert the RF signals into low-frequency digital signals (baseband signals) that can be processed by baseband chip 402. In the downlink, baseband chip 402 may demodulate and decode the baseband signals to extract raw data that can be processed by host chip 406. Baseband chip 402 may perform additional functions, such as error checking, de-mapping, channel estimation, descrambling, etc. The raw data provided by baseband chip 402 may be sent to host chip 406 directly or stored in external memory 410.

[0044] In the downlink, baseband chip 402 in FIG. 4 may implement the method of low- power synchronization based on PDCCH symbols, according to some embodiments of the present disclosure. Baseband chip 402 may include a pre-synchronization unit 4022 that is configured to perform low-power synchronization according to some aspects of the present disclosure. Consistent with the scope of the present disclosure, baseband chip 402 may further include a demodulation unit 4024. In some embodiments, demodulation unit 4024 may be configured to receive signals outputted from pre-synchronization unit 4022 and perform a demodulation operation based on the output signals. In some instances, baseband chip 402 may further include a local memory 4026 to function as a cache and/or buffer so as to avoid communication overhead between baseband chip 402 and external memory 410 based on a bus.

[0045] In the present disclosure, the term “pre-synchronization” may be used to describe the process of estimating timing and frequency offsets when apparatus 400 (e.g., UE 202) operates at the DRX mode. More specifically, the term “pre-synchronization” may refer to a portion of synchronization that may further include cell detection, demodulation, frequency offset compensation, etc. For the simplicity of description, however, the terms “pre-synchronization,” “DRX synchronization,” and “synchronization” may be used interchangeably in the present disclosure.

[0046] In FIG. 4, pre-synchronization unit 4022 and demodulation unit 4024 are illustrated as two standalone blocks in order to introduce and describe their respective functions/operations. In some embodiments, pre-synchronization unit 4022 and demodulation unit 4024 may be electrically connected via wires or wirelessly coupled in a sequential manner, as shown in FIG. 4, so that demodulation unit 4024 can take output signals from pre-synchronization unit 4022 and use them as inputs. Pre-synchronization unit 4022 and demodulation unit 4024 may include different modules/sub-units to support their respective functions/operations. In some embodiments, presynchronization unit 4022 and demodulation unit 4024 may also be combined and integrated as an integral function block. In some embodiments, at least a portion of pre-synchronization unit 4022 and demodulation unit 4024 may include existing modules from other units, such as an existing Fast Fourier transformation module for regular synchronization based on SSBs. Further, it can be understood that baseband chip 402 may include other blocks, modules, units, components, circuits, and elements configured to perform other functions/operations not directly related to the present disclosure.

[0047] Pre-synchronization unit 4022 and demodulation unit 4024 may be embodied using electronic hardware, firmware, computer software, or any combination thereof. In some embodiments, at least part of pre-synchronization unit 4022 and demodulation unit 4024 may be implemented by hardware circuitry, such as ASICs, FPGAs, or PLDs. In some embodiments, at least part of pre-synchronization unit 4022 and demodulation unit 4024 may be implemented by software modules executed by a baseband processor to configure the baseband processor for performing the low-power synchronization provided by some embodiments of the present disclosure. Whether these units are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0048] Based on some lab experiment data, Tables 1 and 2 below show timing offset (TO) and frequency offset (FO) drifts under different crystal ppm errors and various DRX cycles. The term “DRX cycle” may refer to a combination of one “ON” duration and one “OFF” duration in the time domain. Typically, 0.16ppm error/sec can be considered as the worst case for the crystal ppm error, and the TO/FO drifts under the worst scenario are given in Table 1. For comparison, an even worse scenario (i.e., 0.5ppm/sec) is also given in Table 2. From Tables 1 and 2, it can be observed that the associated FO drifts are generally less than % subcarrier spacing (SCS), while the TO drifts are generally less than 20% for a cyclic prefix (CP) length of 1.28s and under. These discoveries, based on Tables 1 and 2, motivate the present disclosure to apply different TO-FO hypotheses, based on PDCCH symbols, to roughly estimate the TO/FO. Besides, the PDCCH decoding has a less stringent requirement for the signal-to-noise ratio (SNR) so that it can tolerate more TO/FO errors and make the rough estimation of the TO/FO feasible.

Table 1 TO/FO drifts under 0.16ppm error/sec in crystal ppm error and various DRX cycles

Table 2 TO/FO drifts under 0.5ppm error/sec in crystal ppm error and various DRX cycles [0049] FIG. 5 illustrates a block diagram of an exemplary pre-synchronization unit 4022, according to some aspects of the present disclosure. FIG. 6 illustrates a flow diagram of an exemplary method of low-power synchronization, according to some aspects of the present disclosure. The schemes for low-power synchronization using PDCCH symbols, provided by some embodiments of the present disclosure, are described below with reference to FIGs. 5 and 6.

[0050] According to some aspects of the present disclosure, pre-synchronization unit 4022 may include a timing offset (TO) hypothesis module 502, a Fast Fourier transform (FFT) module 504, a PDCCH hypothesis module 506, a frequency offset (FO) hypothesis module 508, a signal- to-noise ratio (SNR) calculation module 510, and a selection module 512. These modules are illustrated in FIG. 5 as separate and individual modules according to their respective functions/operations. It can be understood that, in other embodiments, some of these modules may be combined and integrated and/or may employ an existing module of another functional unit.

[0051] As shown in a method 600 of FIG. 6, apparatus 400 may wake up RF chip 404 at 602 of the DRX mode. Subsequently, RF chip 404 may enter a warm-up period in preparation for the reception of at least one PDCCH symbol at 604. In some embodiments, the system may determine the probability that the PDCCH symbol may indicate a paging message. That is, whether the PDCCH symbol is a PDCCH-only reception may be evaluated. When the probability that the PDCCH symbol indicates a paging message is less than a threshold (possibly PDCCH-only reception), once the PDCCH symbol is received, the RF chain of RF chip 404 may be turned off so that the pre-synchronization can be performed offline at 606 in FIG. 6. In some embodiments, once the PDCCH symbol is received, the RF chain of RF chip 404 may be directly switched off without evaluating the probability. These procedures can further decrease power consumption. It can be understood that the procedure of switching the RF chain of RF chip 404 off can be optional. That is, in some embodiments, RF chip 404 may remain on during the processing of the presynchronization.

[0052] At 608 in FIG. 6, in some embodiments, it may be determined whether a previous sleep duration is greater than a threshold time. Depending on the length of the previous sleep duration, TO hypothesis module 502 may determine whether one or more TO hypotheses are required to be applied for the estimation of the timing offsets. That is, to improve the accuracy of the TO estimation, apparatus 400 (e.g., UE 202) may perform a plurality of parallel TO hypotheses. [0053] In some embodiments, at 610, in response to the previous sleep duration being less than or equal to the threshold time, which implies that apparatus 400 woke up from a relatively short sleep (less than or equal to the threshold time), the TO drift may also be small. That is, the current timing (the current TO) may be satisfactory for the PDCCH reception. The current TO may be estimated based on the existing PDCCH symbol, i.e., the previously-received PDCCH symbol. [0054] On the contrary, when the previous sleep duration is greater than the threshold time, it may imply that apparatus 400 had been sleeping for a longer period of time. At 612, in response to the previous sleep duration being greater than the threshold time, to meet a requirement for estimation error, a plurality of TO hypotheses (e.g., three in FIG. 5) may be applied in TO hypothesis module 502 to estimate the corresponding TOs.

[0055] As shown in FIG. 5, the plurality of TO hypotheses may include a current TO+ delta

TO, the current TO, and the current TO-delta TO, where “+” denotes an addition operator, and ” denotes a subtraction operator. While FIG. 5 illustrates an exemplary block diagram showing three TO hypotheses used by TO hypothesis module 502, it can be understood that depending on the previous sleep duration, the condition of the UE crystal, the RF condition, and so on, fewer or more TO hypotheses may also be provided to TO hypothesis module 502. For example, in some embodiments, the plurality of TO hypotheses may include a current TO+ 2xdelta TO, the current TO+delta TO, the current TO, the current TO-delta TO, and the current TO-2xdelta TO, where “x” denotes a multiplication operator.

[0056] Each of the plurality of TO hypotheses may include a timing difference relative to a timing boundary of the PDCCH symbol. The current TO may be estimated by the PDCCH symbols and may represent a timing offset that is estimated using the existing PDCCH symbols, i.e., the previously-received PDCCH symbols. On the other hand, the delta TO may indicate timedomain compensation for the TO drifts impacted by, e.g., the crystal ppm error. Accordingly, the plurality of TO hypotheses by introducing the delta TO can be employed to estimate the potential TO. The delta TO may depend on at least the previous sleep duration and the crystal ppm error (may further relate to a surrounding temperature) and can be obtained in advance of the estimation. In some instances, the threshold time may be, e.g., 1 second.

[0057] At 614 in FIG. 6, in some embodiments, FFT module 504 may be configured to perform FFT on the at least one TO as estimated in the time domain to obtain their corresponding conversions in a frequency domain. In some embodiments, at 616 in FIG. 6, PDCCH hypothesis module 506 may perform PDCCH decoding based on at least one PDCCH hypothesis and the FFT of the at least one TO hypothesis. In the PDCCH decoding, apparatus 400 does not have sufficient information about the location, the structure, and scrambling codes of a control channel, so it may blindly decode the received PDCCH symbols by monitoring a set of PDCCH candidates to identify the right candidate. Apparatus 400 may perform the PDCCH blind decoding over a PDCCH search space attempting to find all the possible DCI data across each PDCCH candidate. The at least one TO obtained earlier can provide certain information in the PDCCH blind decoding. In the present disclosure, the meaning of the term “PDCCH blind decoding” may be equivalent to that of the term “PDCCH decoding,” and thus these two terms may be used interchangeably.

[0058] At 618 in FIG. 6, in some embodiments, for each of the at least one PDCCH hypothesis, FO hypothesis module 508 may estimate at least one FO, using the FFT of the PDCCH symbols, based on a plurality of FO hypotheses. The plurality of FO hypotheses may include a current FO+ delta FO, the current FO, and the current FO-delta FO, where “+” denotes an addition operator, and denotes a subtraction operator.

[0059] Similarly, the current FO may represent a frequency offset that is estimated based on the existing PDCCH symbol, i.e., the previously-received PDCCH symbol. On the other hand, the delta FO may indicate frequency-domain compensation for frequency drifts impacted by, e.g., the previous sleep duration, temperature, and the crystal ppm error. Accordingly, the plurality of frequency hypotheses by introducing the delta FO may be employed to estimate the frequency offsets. The delta FO may depend on the previous sleep duration and the crystal ppm error (may further relate to a surrounding temperature) and can be obtained in advance of the estimation.

[0060] FIG. 5 illustrates an exemplary block diagram showing three frequency hypotheses used in FO hypothesis module 508. It can be understood again that depending on the condition of the UE crystal, the RF condition, and so on, fewer or more FO hypotheses may also be applied in FO hypothesis module 508. For example, in some embodiments, the plurality of FO hypotheses may include a current FO+ 2xdelta FO, the current FO+delta FO, the current FO, the current FO- delta FO, and the current FO-2xdelta FO, where “x” denotes a multiplication operator.

[0061] In some embodiments, frequency offset correction may be applied to the PDCCH symbols captured in the time domain, and the procedure can be expressed as: y(ri) = r( )ei^£n (1), where r(n) denotes an input sequence of the PDCCH symbols, n is a sampling index and may belong to a non-negative number, e^7cn denotes a phase rotation matrix, e denotes a frequency offset that may be fed back from the previous estimation, and (n) denotes an output sequence based on the phase rotation.

[0062] In some embodiments, the phase offset correction may be implemented in the time domain according to Equation (1). In these embodiments, however, an additional FFT may be required to be implemented after the reception of the PDCCH symbols. For that reason, in some embodiments, an inter-carrier-interference (ICI) filter (not shown) may be readily using FFT module 504 and implemented after FFT module 504 to obtain the FFT of e^;en, C(co ), as:

C(c ) = FFT(ei^cn) (2).

[0063] Based on Equation (2), Equation (1) can be further translated as:

T(co ) = /?(« ) * C(o> ) (3), where A(m ) denotes the frequency-domain transformation of the input sequence of the PDCCH symbols, * is a convolution operator, C(u> ) denotes the FFT of e^;en, and F(ui ) denotes the frequency-domain transformation of the output sequence. Accordingly, F(ui ), with the phase offset correction, may be inputted to PDCCH hypothesis module 506 for the PDCCH blind decoding.

[0064] At 620, SNR calculation module 510 may calculate SNRs each corresponding to one of TO-FO hypothesis pairs. The term “TO-FO” may be used to indicate that each pair of the TO-FO hypotheses for respective PDCCH hypotheses may include one TO estimated by one TO hypothesis and one FO estimated by one FO hypothesis. For each PDCCH hypothesis, each SNR may be calculated using the PDCCH symbol that is compensated by the TO and the FO in the pair of the TO-FO hypotheses. The SNR may be defined as a ratio of signal power to noise power and may be expressed in decibels.

[0065] Further, at 622, for each PDCCH hypothesis, selection module 512 may evaluate the calculated SNRs to determine a TO-FO hypothesis pair from the combinations of the TO hypotheses and FO hypotheses, according to a selection rule. In some embodiments, the highest SNR may be selected, and a TO-FO hypothesis pair associated with the highest SNR may be identified to determine the corresponding TO and FO as a candidate TO and a candidate FO. A higher SNR may indicate more signals than noises and/or the noises are small. Consequently, the estimation error associated with the highest SNR may be relatively smaller.

[0066] At 624, frequency-domain signals and the candidate TO-FO for each PDCCH hypothesis may be transmitted to demodulation unit 4024 for the demodulation procedure.

[0067] In some embodiments of the present disclosure, SSB-based pre-synchronization may still be implemented so as to obtain an accurate estimation for the TO and FO. For example, for a longer DRX cycle, such as 2.56 seconds, regular SSB-based pre-synchronization may be employed. Although the SSB-based pre-synchronization is still applied, through the low-power synchronization provided by the present disclosure, it becomes less frequent to resort to the SSB- based pre-synchronization. That is, the power consumption can be significantly reduced.

[0068] In view of the above, the present disclosure accordingly provides the inventive concepts for low-power synchronization, in which timing and frequency offsets may be directly estimated based on the PDCCH symbols. As a result, the UE does not need to wake up before the PDCCH reception. Accordingly, power consumption can be reduced, and thus the life of the associated electronic device can be prolonged.

[0069] According to one aspect of the present disclosure, an apparatus for low-power synchronization is provided. The apparatus may include a radio frequency (RF) chip and a baseband chip. The RF chip may be configured to enter a warm-up period associated with discontinuous reception (DRX) and obtain a physical downlink control channel (PDCCH) symbol. The baseband chip may be configured to estimate at least one timing offset (TO) and at least one frequency offset (FO) based on the PDCCH symbol.

[0070] In some embodiments, the baseband chip may be configured to estimate the at least one TO based on at least one TO hypothesis. A number of the at least one TO hypothesis may be determined at least by a previous sleep duration. The at least one TO hypothesis may include a timing difference relative to a timing boundary of the PDCCH symbol.

[0071] In some embodiments, the baseband chip may be configured to in response to the previous sleep duration being less than or equal to a threshold time, estimate the at least one TO based on a current TO hypothesis. The current TO hypothesis may include a current TO based on the PDCCH symbol. The baseband chip may further be configured to in response to the previous sleep duration being greater than the threshold time, estimate the at least one TO based on a plurality of TO hypotheses. The plurality of TO hypotheses may include the current TO plus a delta TO, the current TO, and the current TO minus the delta TO. The delta TO may be determined at least by the previous sleep duration and a crystal error.

[0072] In some embodiments, the baseband chip may be configured to estimate the at least one FO based on a plurality of FO hypotheses. The plurality of FO hypotheses may include a current FO based on the PDCCH symbol, the current FO plus delta FO, and the current FO minus the delta FO. The delta FO may be determined at least by a previous sleep duration and a crystal error and may be indicative of a frequency difference relative to the current FO based on the PDCCH symbol.

[0073] In some embodiments, the baseband chip may be configured to transform the PDCCH symbol in a time domain to obtain a PDCCH signal in a frequency domain and estimate the at least one FO, using the PDCCH signal in the frequency domain, based on the plurality of FO hypotheses.

[0074] In some embodiments, the baseband chip may be configured to perform a PDCCH decoding based on the at least one TO and at least one PDCCH hypothesis.

[0075] In some embodiments, the baseband chip may be configured to calculate a signal- to-noise ratio (SNR) for each pair of TO-FO hypotheses. Each pair of TO-FO hypotheses may include one TO of the at least one TO and one FO of the at least one FO.

[0076] In some embodiments, the baseband chip may be further configured to determine a candidate TO and a candidate FO based on a highest SNR of the calculated SNRs and perform demodulation at least based on the candidate FO.

[0077] In some embodiments, upon reception of the PDCCH symbol, an RF chain of the RF chip may be turned off.

[0078] In some embodiments, the baseband chip may further include an inter-carrier- interference (ICI) filter that is configured to perform a phase rotation, in a frequency domain, based on frequency conversion of the PDCCH symbol and a convolution factor. The convolution factor may be determined based on a previous estimation of the at least one FO.

[0079] According to another aspect of the present disclosure, a method of low-power synchronization is provided. A warm-up period associated with discontinuous reception (DRX) may be entered. A physical downlink control channel (PDCCH) symbol may be obtained. At least one timing offset (TO) and at least one frequency offset (FO) may be estimated based on the PDCCH symbol.

[0080] In some embodiments, the at least one TO may be estimated based on at least one TO hypothesis. A number of the at least one TO hypothesis may be determined at least by a previous sleep duration. The at least one TO hypothesis may include a timing difference relative to a timing boundary of the PDCCH symbol.

[0081] In some embodiments, in response to the previous sleep duration being less than or equal to a threshold time, the at least one TO may be estimated based on a current TO hypothesis. The current TO hypothesis may include a current TO based on the PDCCH symbol. In response to the previous sleep duration being greater than the threshold time, the at least one TO may be estimated based on a plurality of TO hypotheses. The plurality of TO hypotheses may include the current TO plus a delta TO, the current TO, and the current TO minus the delta TO. The delta TO may be determined at least by the previous sleep duration and a crystal error.

[0082] In some embodiments, the at least one FO may be estimated based on a plurality of FO hypotheses. The plurality of FO hypotheses may include a current FO based on the PDCCH symbol, the current FO plus delta FO, and the current FO minus the delta FO. The delta FO may be determined at least by a previous sleep duration and a crystal error and may be indicative of a frequency difference relative to the current FO based on the PDCCH symbol.

[0083] In some embodiments, the PDCCH symbol in a time domain may be transformed to obtain a PDCCH signal in a frequency domain. The at least one FO may be estimated, using the PDCCH signal in the frequency domain, based on the plurality of FO hypotheses.

[0084] In some embodiments, a signal -to-noise ratio (SNR) for each pair of TO-FO hypotheses may be calculated. Each pair of TO-FO hypotheses may include one TO of the at least one TO and one FO of the at least one FO.

[0085] In some embodiments, a candidate TO and a candidate FO may be obtained based on a highest SNR of the calculated SNRs. Demodulation may be performed at least based on the candidate FO.

[0086] In some embodiments, upon reception of the PDCCH symbol, an RF chain of the RF chip may be turned off.

[0087] According to still another aspect of the present disclosure, a baseband chip is provided. The baseband chip may include a processor and memory coupled to the processor and storing instructions. When executed by the processor, the instructions may cause the processor to upon a radio frequency (RF) chip entering a warm-up period associated with discontinuous reception (DRX), obtain a physical downlink control channel (PDCCH) symbol. At least one TO may be estimated based on at least one TO hypothesis. A number of the at least one TO hypothesis may be determined by a previous sleep duration. The at least one TO hypothesis may include a timing difference relative to a timing boundary of the PDCCH symbol. At least one FO may be estimated based on a plurality of FO hypotheses. The plurality of FO hypotheses may include a current FO based on the PDCCH symbol, the current FO plus delta FO, and the current FO minus the delta FO. The delta FO may be indicative of a frequency difference relative to the current FO based on the PDCCH symbol.

[0088] In some embodiments, the instructions may further cause the processor to in response to a previous sleep duration being less than or equal to a threshold time, estimate the at least one TO based on a current TO hypothesis, the current TO hypothesis comprising a current TO based on the PDCCH symbol; and in response to the previous sleep duration being greater than the threshold time, estimate the at least one TO based on a plurality of TO hypotheses, the plurality of TO hypotheses comprising the current TO plus a delta TO, the current TO, and the current TO minus the delta TO. The delta TO may be determined at least by the previous sleep duration and a crystal error.

[0089] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0090] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0091] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0092] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in diverse ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0093] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. An apparatus for low-power synchronization, comprising: a radio frequency (RF) chip configured to: enter a warm-up period associated with discontinuous reception (DRX); and obtain a physical downlink control channel (PDCCH) symbol; and a baseband chip configured to: estimate at least one timing offset (TO) and at least one frequency offset (FO) based on the PDCCH symbol.

2. The apparatus of claim 1, wherein the baseband chip is configured to: estimate the at least one TO based on at least one TO hypothesis, a number of the at least one TO hypothesis being determined at least by a previous sleep duration, and the at least one TO hypothesis comprising a timing difference relative to a timing boundary of the PDCCH symbol.

3. The apparatus of claim 2, wherein the baseband chip is configured to: in response to the previous sleep duration being less than or equal to a threshold time, estimate the at least one TO based on a current TO hypothesis, the current TO hypothesis comprising a current TO based on the PDCCH symbol; and in response to the previous sleep duration being greater than the threshold time, estimate the at least one TO based on a plurality of TO hypotheses, the plurality of TO hypotheses comprising the current TO plus a delta TO, the current TO, and the current TO minus the delta TO, and the delta TO being determined at least by the previous sleep duration and a crystal error.

4. The apparatus of claim 1, wherein the baseband chip is configured to: estimate the at least one FO based on a plurality of FO hypotheses, the plurality of FO hypotheses comprising a current FO based on the PDCCH symbol, the current FO plus delta FO, and the current FO minus the delta FO, and the delta FO being determined at least by a previous sleep duration and a crystal error and being indicative of a frequency difference relative to the current FO based on the PDCCH symbol.

5. The apparatus of claim 4, wherein the baseband chip is configured to: transform the PDCCH symbol in a time domain to obtain a PDCCH signal in a frequency domain; and estimate the at least one FO, using the PDCCH signal in the frequency domain, based on the plurality of FO hypotheses.

6. The apparatus of claim 1, wherein the baseband chip is configured to: perform a PDCCH decoding based on the at least one TO and at least one PDCCH hypothesis.

7. The apparatus of claim 1, wherein the baseband chip is configured to: calculate a signal-to-noise ratio (SNR) for each pair of TO-FO hypotheses, each pair of TO- FO hypotheses comprising one TO of the at least one TO and one FO of the at least one FO.

8. The apparatus of claim 7, wherein the baseband chip is further configured to: determine a candidate TO and a candidate FO based on a highest SNR of the calculated

SNRs; and perform demodulation at least based on the candidate FO.

9. The apparatus of claim 1, wherein: upon reception of the PDCCH symbol, an RF chain of the RF chip is turned off.

10. The apparatus of claim 1, wherein the baseband chip further comprises: an inter-carrier-interference (ICI) filter configured to perform a phase rotation, in a frequency domain, based on frequency conversion of the PDCCH symbol and a convolution factor, the convolution factor being determined based on a previous estimation of the at least one FO.

11. A method of low-power synchronization, comprising: entering a warm-up period of a radio frequency (RF) chip associated with discontinuous reception (DRX); obtaining a physical downlink control channel (PDCCH) symbol; and estimating at least one timing offset (TO) and at least one frequency offset (FO) based on the PDCCH symbol.

12. The method of claim 11, wherein estimating the at least one TO comprises: estimating the at least one TO based on at least one TO hypothesis, a number of the at least one TO hypothesis being determined at least by a previous sleep duration, and the at least one TO hypothesis comprising a timing difference relative to a timing boundary of the PDCCH symbol.

13. The method of claim 12, wherein estimating the at least one TO comprises: in response to the previous sleep duration being less than or equal to a threshold time, estimating the at least one TO based on a current TO hypothesis, the current TO hypothesis comprising a current TO based on the PDCCH symbol; and in response to the previous sleep duration being greater than the threshold time, estimating the at least one TO based on a plurality of TO hypotheses, the plurality of TO hypotheses comprising the current TO plus a delta TO, the current TO, and the current TO minus the delta TO, and the delta TO being determined at least by the previous sleep duration and a crystal error.

14. The method of claim 11, wherein estimating the at least one FO comprises: estimating the at least one FO based on a plurality of FO hypotheses, the plurality of FO hypotheses comprising a current FO based on the PDCCH symbol, the current FO plus delta FO, and the current FO minus the delta FO, and the delta FO being determined at least by a previous sleep duration and a crystal error and being indicative of a frequency difference relative to the current FO based on the PDCCH symbol.

15. The method of claim 14, further comprising transforming the PDCCH symbol in a time domain to obtain a PDCCH signal in a frequency domain, wherein: estimating the at least one FO comprises estimating the at least one FO, using the PDCCH signal in the frequency domain, based on the plurality of FO hypotheses.

16. The method of claim 11, further comprising: calculating a signal-to-noise ratio (SNR) for each pair of TO-FO hypotheses, each pair of TO-FO hypotheses comprising one TO of the at least one TO and one FO of the at least one FO.

17. The method of claim 16, further comprising: determining a candidate TO and a candidate FO based on a highest SNR of the calculated SNRs; and performing demodulation at least based on the candidate FO.

18. The method of claim 11, further comprising: upon reception of the PDCCH symbol, turning off an RF chain of the RF chip.

19. A baseband chip, comprising: a processor; and memory coupled to the processor and storing instructions that, when executed by the processor, cause the processor to: upon a radio frequency (RF) chip entering a warm-up period associated with discontinuous reception (DRX), obtain a physical downlink control channel (PDCCH) symbol; estimate at least one TO based on at least one TO hypothesis, a number of the at least one TO hypothesis being determined by a previous sleep duration, and the at least one TO hypothesis comprising a timing difference relative to a timing boundary of the PDCCH symbol; and estimate at least one FO based on a plurality of FO hypotheses, the plurality of FO hypotheses comprising a current FO based on the PDCCH symbol, the current FO plus delta FO, and the current FO minus the delta FO, and the delta FO being indicative of a frequency difference relative to the current FO based on the PDCCH symbol.

20. The baseband chip of claim 19, wherein the instructions further cause the processor to: in response to a previous sleep duration being less than or equal to a threshold time, estimate the at least one TO based on a current TO hypothesis, the current TO hypothesis comprising a current TO based on the PDCCH symbol; and in response to the previous sleep duration being greater than the threshold time, estimate the at least one TO based on a plurality of TO hypotheses, the plurality of TO hypotheses comprising the current TO plus a delta TO, the current TO, and the current TO minus the delta TO, and the delta TO being determined at least by the previous sleep duration and a crystal error.