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WO2023207108A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023207108A1
WO2023207108A1 PCT/CN2022/137201 CN2022137201W WO2023207108A1 WO 2023207108 A1 WO2023207108 A1 WO 2023207108A1 CN 2022137201 W CN2022137201 W CN 2022137201W WO 2023207108 A1 WO2023207108 A1 WO 2023207108A1
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WO
WIPO (PCT)
Prior art keywords
layer
power supply
display panel
voltage signal
supply voltage
Prior art date
Application number
PCT/CN2022/137201
Other languages
English (en)
French (fr)
Inventor
袁鑫
周秀峰
袁海江
Original Assignee
绵阳惠科光电科技有限公司
惠科股份有限公司
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Application filed by 绵阳惠科光电科技有限公司, 惠科股份有限公司 filed Critical 绵阳惠科光电科技有限公司
Publication of WO2023207108A1 publication Critical patent/WO2023207108A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • the wiring design of the power supply voltage signal line (Vdd) is narrowed. Especially when the power supply voltage signal line is a single line extending vertically, IR Drop (current flowing through the power supply voltage signal line) will occur. The voltage drop caused by the phenomenon causes the brightness of the display panel to be uneven, and it is easy to cause visually visible display unevenness (Mura).
  • an additional metal layer is usually added to the backplane circuit to overlap with the metal layer where the power supply voltage signal line is located to form a mesh power supply signal line to reduce IR Drop.
  • adding a metal layer will require an additional photomask process, which increases the difficulty of the process.
  • the purpose of this application is to provide a display panel and a display device that can adopt a mesh power supply voltage signal line design without increasing the process difficulty and reduce the display unevenness caused by IR Drop.
  • embodiments of the present application provide a display panel, including a base substrate and a driving array layer located on the base substrate.
  • the driving array layer includes thin film transistors and a plurality of power supply voltage signal lines.
  • the thin film transistors include oppositely arranged The bottom gate and the top gate, as well as the source and drain located on both sides of the top gate, the power supply voltage signal lines are arranged in the same layer as the source and drain.
  • the driving array layer also includes multiple branches arranged in the same layer as the bottom gate. A plurality of voltage dividing lines and a plurality of power supply voltage signal lines intersect each other in a grid-like distribution, and at least part of the intersections of the voltage dividing lines and the power supply voltage signal lines are electrically connected through vias.
  • embodiments of the present application also provide a display device, including the display panel as mentioned above.
  • multiple voltage dividing lines are arranged on the same layer as the metal layer where the bottom gate of the thin film transistor is located, and are distributed in a grid pattern across multiple power supply voltage signal lines. And at least part of the intersections between the voltage dividing traces and the power supply voltage signal lines are electrically connected through vias, so that the voltage dividing traces can be located at a meshed power supply voltage signal line design without increasing the process difficulty, thereby reducing the risk of IR Drop. The problem of uneven display.
  • Figure 1 shows a schematic top structural view of a display panel provided by the first embodiment of the present application
  • Figure 2 shows an enlarged structural view of area A in Figure 1;
  • Figure 3 shows a cross-sectional view along the B-B direction of Figure 2;
  • Figure 4 shows a cross-sectional view along the C-C direction of Figure 2;
  • Figure 5 shows a schematic top structural view of a display panel provided by the second embodiment of the present application.
  • FIG. 6 shows a schematic top structural view of a display panel provided by the third embodiment of the present application.
  • Second metal layer 221. Connection part; 222. Scan line;
  • the third metal layer 231. Power supply voltage signal line; 232. Data line;
  • First insulating layer 241. Buffer layer; 242. Gate insulating layer; H1, first via hole; H3, third via hole;
  • Second insulation layer H2, second via hole; 26. Passivation layer; 27. Planarization layer;
  • the display panel provided by the embodiment of the present application can adopt a mesh power supply voltage signal line design without increasing the process difficulty, thereby reducing the problem of uneven display caused by IR Drop.
  • the specific structure of the display panel provided by each embodiment will be described in detail below with reference to the accompanying drawings.
  • Figure 1 shows a schematic top structural view of the display panel provided by the first embodiment of the present application.
  • Figure 2 shows an enlarged structural view of area A in Figure 1.
  • Figure 3 shows a cross-sectional view along the B-B direction of Figure 2.
  • Figure 4 Take the cross-sectional view along the C-C direction in Figure 2.
  • the display panel provided by the first embodiment of the present application includes a base substrate 1 and a driving array layer located on the base substrate 1.
  • the driving array layer includes a thin film transistor 2a and a plurality of power supply voltage signals.
  • Line 231 the thin film transistor 2a includes a bottom gate G1 and a top gate G2 arranged opposite each other, and a source S and a drain D located on both sides of the top gate G2.
  • the power supply voltage signal line 231 is arranged in the same layer as the source S and the drain D. .
  • the driving array layer also includes a plurality of voltage dividing traces 211 arranged on the same layer as the bottom gate G1.
  • the multiple voltage dividing traces 211 and the plurality of power supply voltage signal lines 231 intersect with each other in a grid-like distribution, and the voltage dividing traces 211 At least part of the intersection with the power supply voltage signal line 231 is electrically connected through the via hole H.
  • the driving array layer includes a first metal layer 21, a second metal layer 22, and a third metal layer 23 that are stacked in sequence in a direction away from the base substrate 1.
  • the first metal layer 21 includes the bottom gate of the thin film transistor 2a.
  • the second metal layer 22 includes the top gate of the thin film transistor 2 a;
  • the third metal layer 23 includes a plurality of power supply voltage signal lines 231 .
  • the material of the base substrate 1 may be glass, transparent resin, quartz, sapphire, etc.
  • the material of the first metal layer 21 , the second metal layer 22 and the third metal layer 23 includes aluminum or aluminum alloy, which improves the conductivity and bending characteristics of the metal traces and reduces the breakage of dynamic bending. risk.
  • the plurality of power supply voltage signal lines 231 located in the third metal layer 23 and the multiple voltage dividing lines 211 located in the first metal layer 21 intersect with each other and are distributed in a grid shape, and the voltage dividing lines 211 and At least part of the intersections of the power supply voltage signal lines 231 are electrically connected through the vias H to form a double-layer wiring structure.
  • a via H is provided at each intersection of the voltage dividing trace 211 and the power supply voltage signal line 231. The greater the number of vias H, the better the current sharing effect, thereby reducing the power supply voltage signal line 231.
  • the resistance value reduces the voltage loss drop value, improves the resistance uniformity within the entire display panel, and thereby improves the brightness uniformity of the display panel.
  • the power supply voltage signal line 231 adopts a double-layer wiring structure, and the voltage dividing wiring 211 is connected in parallel with the power supply voltage signal line 231.
  • the voltage dividing wiring 211 is connected in parallel with the power supply voltage signal line 231.
  • the voltage dividing line 211 and the bottom gate G1 of the thin film transistor 2a are both located on the first metal layer 21 and can be prepared on the same layer.
  • an additional metal layer is added to arrange the voltage dividing line 211 in the related art. Compared with the technical solution, one photomask process can be eliminated, which will not increase the difficulty of the process and help reduce the production cost.
  • the bottom gate G1 occupies a small area in the entire first metal layer 21. There is enough space to arrange the voltage dividing wiring 211, and the impact on the aperture ratio is relatively small.
  • the voltage dividing traces 211 are arranged on other film layers, such as the second metal layer 22, since the second metal layer 22 needs to arrange various signal lines, the voltage dividing traces 211 will occupy more wiring space and affect the display panel. opening rate.
  • the first metal layer 21 and the third metal layer 23 are separated by multiple film layers such as the second metal layer 22, the distance between the first metal layer 21 and the third metal layer 23 is relatively far. The parasitic capacitance between them is small, which is beneficial to reducing the load of the power supply voltage signal line 231 and improving the display performance of the display panel.
  • An embodiment of the present application provides a display panel by arranging multiple voltage dividing lines 211 on the same layer as the metal layer where the bottom gate of the thin film transistor 2a is located, and intersecting with multiple power supply voltage signal lines 231 in a grid-like distribution. , and at least part of the intersection between the voltage dividing line 211 and the power supply voltage signal line 231 is electrically connected through the via H, so that the voltage dividing line 211 can adopt a mesh power supply voltage signal line design without increasing the process difficulty, reducing Display unevenness caused by IR Drop.
  • the display panel further includes a light-emitting layer 3 located on a side of the driving array layer facing away from the base substrate 1 .
  • the light-emitting layer 3 includes a plurality of sub-pixels 31 distributed in an array.
  • the voltage dividing trace 211 extends along the first direction X
  • the power supply voltage signal line 231 extends along the second direction Y intersecting the first direction At least one sub-pixel 31 is arranged therein.
  • a plurality of sub-pixels 31 are arranged in an array along the first direction X and the second direction Y.
  • One sub-pixel 31 is arranged in each grid defined by the intersection of the voltage dividing line 211 and the power supply voltage signal line 231 . , that is, multiple grids correspond to multiple sub-pixels 31 one-to-one.
  • Each grid is formed by the intersection of two adjacent power supply voltage signal lines 231 and two adjacent voltage dividing lines 211, and a via H is provided at the four intersections of each grid, so that The pressure trace 211 can share the current of the power supply voltage signal line 231 and reduce the IR-Drop degree of the power supply voltage signal line 231.
  • multiple power supply voltage signal lines 231 and multiple voltage dividing lines 211 are intersected to form multiple intersection points distributed in an array.
  • the driving array layer also includes a connection portion 221 arranged in the same layer as the top gate G2.
  • the connection portion 221 is at least partially connected to the orthographic projection of the voltage dividing line 211 and the power supply voltage signal line 231 on the substrate substrate 1. Overlapping, the via hole H and the connecting portion 221 are overlapped.
  • overlap means that the via H is filled with metal in the depth direction between the third metal layer 23 and the first metal layer 21 , and the connection portion 221 located in the second metal layer 22 connects the via H
  • the metal inside is divided into two parts, and the two parts of metal are connected to each other through the connecting part 221 to realize the electrical connection between the voltage dividing line 211 and the power supply voltage signal line 231 .
  • the through holes H located on both sides of the connecting portion 221 in the depth direction can be aligned or disposed.
  • connection portion 221 can be arranged on the second metal layer 22, and the via H and the connection portion 221 can be overlapped and connected.
  • the distance between the connecting portion 221 of the second metal layer 22 and the voltage dividing line 211 of the first metal layer 21 and the distance between the connecting portion 221 and the power supply voltage signal line 231 of the third metal layer 23 are relatively small. Reducing the depth of the via hole H on both sides of the connection portion 221 is beneficial to improving the electrical connection performance between the power supply voltage signal line 231 and the voltage dividing line 211 .
  • the driving array layer also includes a first insulating layer 24 and a second insulating layer 25.
  • the first insulating layer 24 is located between the voltage dividing line 211 and the connecting part 221.
  • the second insulating layer 25 is located between the connecting part 221 and the power supply voltage.
  • the via hole H includes a first via hole H1 and a second via hole H2 respectively overlapping the connecting portion 221.
  • the first via hole H1 penetrates the first insulating layer 24, and the second via hole H2 penetrates the second via hole H1. Insulating layer 25.
  • the first insulation layer 24 includes a buffer layer 241 and a gate insulation layer 242, and the first via hole H1 is provided through the buffer layer 241 and the gate insulation layer 242.
  • the second insulating layer 25 is an interlayer insulating layer, and the second via hole H2 is provided through the interlayer insulating layer. Since the first via hole H1 and the second via hole H2 are respectively overlapped with the connecting portion 221 to achieve electrical connection, the first via hole H1 and the second via hole H2 do not need to be aligned in the depth direction, which simplifies the manufacturing process.
  • the orthographic projection of the first via hole H1 on the base substrate 1 overlaps with the orthographic projection of the second via hole H2 on the base substrate 1 .
  • the occupied space can be reduced, which is beneficial to improving the opening ratio.
  • the first insulating layer 24 is also provided with a third via hole H3, and the top gate G2 is electrically connected to the bottom gate G1 through the third via hole H3.
  • the second metal layer 22 also includes a scan line 222 extending along the first direction X
  • the third metal layer 23 further includes a data line 232 extending along the second direction Y.
  • the data line 232 is connected to the power supply voltage signal line 231 adjacent settings.
  • the scan line 222 is electrically connected to the top gate G2 of the thin film transistor 2a
  • the data line 232 is electrically connected to the source S of the thin film transistor 2a.
  • an active layer ACT is also formed between the buffer layer 241 and the gate insulating layer 242.
  • the orthographic projection of the bottom gate G1 on the base substrate 1 covers the orthographic projection of the active layer ACT on the base substrate 1. It can prevent external light from adversely affecting the thin film transistor 2a; in addition, the top gate G2 is electrically connected to the bottom gate G1 through the third via hole H3.
  • the gate of the thin film transistor 2a adopts a double-layer wiring structure, which can reduce the connection with the gate. S is electrically connected to the load of scan line 222 .
  • the sub-pixel 31 includes a first electrode 311, a light-emitting structure and a second electrode that are stacked in sequence.
  • the first electrode 311 is electrically connected to the source S or the drain D of the thin film transistor 2a, and the second electrode is transparent. conductive layer.
  • first electrode 311 and the second electrode are the anode of the sub-pixel 31 , and the other one is the cathode of the sub-pixel 31 .
  • first electrode 311 is an anode for description.
  • the second electrode is a transparent conductive layer, that is, the cathode is a transparent conductive layer to facilitate the emission of light.
  • a sub-pixel 31 is arranged in each grid defined by the intersection of the voltage dividing line 211 and the power supply voltage signal line 231.
  • the first electrode 311 of the sub-pixel 31 is electrically connected to the drain D of the thin film transistor 2a.
  • the thin film transistor 2a The source S is electrically connected to the data line 232.
  • the display panel further includes a pixel defining layer located on a side of the driving array layer facing away from the base substrate 1 .
  • the pixel defining layer includes a plurality of pixel openings, and at least part of the sub-pixels 31 is located within the pixel openings. Specifically, the light-emitting structure and the second electrode of the sub-pixel 31 are located in the pixel opening, and the first electrode 311 corresponds to the pixel opening.
  • FIG. 5 shows a schematic top structural view of a display panel provided by the second embodiment of the present application.
  • the second embodiment of the present application also provides a display panel, which is similar in structure to the display panel provided in the first embodiment, except that the arrangement of the voltage dividing lines 211 is different.
  • the display panel includes a light-emitting layer 3 located on a side of the driving array layer facing away from the base substrate 1 .
  • the light-emitting layer 3 includes a plurality of sub-pixels 31 distributed in an array.
  • the voltage dividing trace 211 extends along the first direction X
  • the power supply voltage signal line 231 extends along the second direction Y intersecting the first direction
  • Two sub-pixels 31 are arranged inside.
  • the power supply voltage signal line 231 and the data line 232 both extend along the second direction Y and are arranged adjacently, and the voltage dividing line 211 and the scanning line (not shown in the figure) both extend along the first direction X.
  • the voltage dividing lines 211 are arranged at a predetermined distance from the scan lines, so that the grid defined by the voltage dividing lines 211 and the power supply voltage signal lines 231 intersecting each other is a large grid.
  • Two sub-pixels 31 are arranged in each large grid and are aligned and distributed along the second direction Y. Since there are no wirings between the two sub-pixels 31, wiring space is saved, and the size of the sub-pixels 31 can be designed to be larger, which improves the efficiency. Display panel aperture ratio.
  • sub-pixels 31 can be arranged in each grid defined by the intersections of the voltage dividing lines 211 and the power supply voltage signal lines 231. At the same time, because the greater the number of sub-pixels 31, the fewer the positions of intersection points. It is not conducive to reducing IR-Drop, so it is necessary to consider the balance between wiring space and IR-Drop, depending on the specific design requirements.
  • FIG. 6 shows a schematic top structural view of a display panel provided by the third embodiment of the present application.
  • the third embodiment of the present application also provides a display panel, which is similar in structure to the display panel provided in the first embodiment, except that the arrangement of the voltage dividing lines 211 is different.
  • each voltage dividing line 211 includes a plurality of voltage dividing line segments 211a spaced apart along the first direction are electrically connected, and the voltage dividing line segments 211a of each two adjacent voltage dividing lines 211 are staggered along the first direction X.
  • two aligned and distributed sub-pixels 31 are formed between two adjacent voltage dividing line segments 211a. Since there is no wiring between the two sub-pixels 31, the wiring space is saved, and the size of the sub-pixel 31 can be designed to be larger, thereby increasing the aperture ratio of the display panel.
  • the number of intersections is the same and the current sharing effect is the same, but the design space of the sub-pixel 31 can be increased and the aperture ratio can be improved.
  • the number of cross points is larger, which reduces the load on the power supply voltage signal line 231, and the current sharing effect is better, which is beneficial to improving the uniformity of display brightness.
  • the voltage dividing traces 211 provided in this embodiment have the same number of intersections as the small grid structure, have the same current sharing effect, and can reduce the degree of IR-Drop; at the same time, the large grid can save space,
  • the advantage of increasing the aperture ratio takes into account the balance between wiring space and IR-Drop.
  • inventions of the present application also provide a display device, including any of the above-mentioned display panels.
  • the display device may be, for example, but not limited to, a wearable device, a mobile phone, a tablet, a television, a monitor, a laptop, an e-book, an electronic newspaper, a digital photo frame, a navigator, or any other product or component with a display function.
  • wearable devices include smart bracelets, smart watches, virtual reality (Virtual Reality, VR) and other devices.
  • base substrate refers to the material upon which subsequent layers of material are added.
  • the base substrate itself can be patterned. Material added atop the base substrate may be patterned, or may remain unpatterned.
  • the base substrate may include a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like.
  • the base substrate may be made of a non-conductive material (eg, glass, plastic, or sapphire wafer, etc.).
  • the term "layer” as used herein may refer to a portion of material that includes a region of thickness.
  • a layer may extend over the entire underlying or overlying structure, or may have an extent that is smaller than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure.
  • a layer may be located between the top and bottom surfaces of the continuous structure or between any pairs of transverse planes at the top and bottom surfaces.
  • the layers may extend laterally, vertically and/or along tapered surfaces.
  • the base substrate may be a layer, may include one or more layers therein, and/or may have one or more layers on, above, and/or below it.
  • a layer may include multiple layers.
  • interconnect layers may include one or more conductor and contact layers within which contacts, interconnect lines, and/or vias are formed, and one or more dielectric layers.

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Abstract

本申请涉及一种显示面板及显示装置，该显示面板包括衬底基板(1)和位于衬底基板(1)上的驱动阵列层，驱动阵列层包括薄膜晶体管(2a)和多条电源电压信号线(231)，薄膜晶体管(2a)包括相对设置的底栅(G1)和顶栅(G2)，以及位于顶栅(G2)两侧的源极(S)和漏极(D)，电源电压信号线(231)与源极(S)和漏极(D)同层布置，其中，驱动阵列层还包括与底栅(G1)同层布置的多条分压走线(211)，多条分压走线(211)与多条电源电压信号线(231)相互交叉呈网格状分布，且分压走线(211)与电源电压信号线(231)的至少部分交叉处通过过孔电连接。该显示面板在不增加工艺难度的基础上采用网状电源电压信号线设计，减少因IR Drop造成的显示不均等问题。

Description

显示面板及显示装置
相关申请的交叉引用
本申请要求享有于2022年04月24日提交的名称为“显示面板及显示装置”的中国专利申请202210435831.6的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及显示技术领域，特别是涉及一种显示面板及显示装置。
背景技术
为了提高显示面板的开口率，电源电压信号线(Vdd)的走线设计变窄，尤其电源电压信号线为纵向延伸的单根走线时，将会产生IR Drop(电流流过电源电压信号线造成的电压降)现象，使得显示面板的亮度不均一，极易产生目视可见的显示不均(Mura)问题。
为了解决上述问题，相关技术中通常在背板电路中额外增加一层金属层，使之与电源电压信号线所在的金属层搭接形成网状的电源电压信号线，以降低IR Drop。但是，增加一层金属层就会多一道光罩制程，增加了工艺难度。
发明内容
本申请的目的在于提供一种显示面板及显示装置，其可以在不增加工艺难度的基础上采用网状电源电压信号线设计，减少因IR Drop造成的显示不均等问题。
第一方面，本申请实施例提出了一种显示面板，包括衬底基板和位于衬底基板上的驱动阵列层，驱动阵列层包括薄膜晶体管和多条电源电压信号线，薄膜晶体管包括相对设置的底栅和顶栅，以及位于顶栅两侧的源极和漏极，电源电压信号线与源极和漏极同层布置，其中，驱动阵列层还包括与底栅同层布置的多条分压走线，多条分压走线与多条电源电压信号线 相互交叉呈网格状分布，且分压走线与电源电压信号线的至少部分交叉处通过过孔电连接。
第二方面，本申请实施例还提出了一种显示装置，包括如前所述的显示面板。
根据本申请实施例提供的显示面板及显示装置，通过在薄膜晶体管的底栅所在的金属层同层布置多条分压走线，并与多条电源电压信号线相互交叉呈网格状分布，且分压走线与电源电压信号线的至少部分交叉处通过过孔电连接，使得分压走线位于可以在不增加工艺难度的基础上采用网状电源电压信号线设计，减少因IR Drop造成的显示不均等问题。
附图说明
下面将参考附图来描述本申请示例性实施例的特征、优点和技术效果。在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例绘制，仅用于示意相对位置关系，某些部位的层厚采用了夸大的绘图方式以便于理解，附图中的层厚并不代表实际层厚的比例关系。
图1示出本申请第一实施例提供的显示面板的俯视结构示意图；
图2示出图1中的区域A的放大结构图；
图3示出图2沿B-B方向的剖面图；
图4示出图2沿C-C方向的剖面图；
图5示出本申请第二实施例提供的显示面板的俯视结构示意图；
图6示出本申请第三实施例提供的显示面板的俯视结构示意图。
附图标记说明：
1、衬底基板；X、第一方向；Y、第二方向；
2a、薄膜晶体管；G1、底栅；G2、顶栅；S、源极；D、漏极；ACT、半导体层；H、过孔；
21、第一金属层；211、分压走线；211a、分压走线段；
22、第二金属层；221、连接部；222、扫描线；
23、第三金属层；231、电源电压信号线；232、数据线；
24、第一绝缘层；241、缓冲层；242、栅绝缘层；H1、第一过孔；H3、第三过孔；
25、第二绝缘层；H2、第二过孔；26、钝化层；27、平坦化层；
3、发光层；31、子像素；311、第一电极。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例。在下面的详细描述中，提出了许多具体细节，以便提供对本申请的全面理解。但是，对于本领域技术人员来说很明显的是，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请的更好的理解。在附图和下面的描述中，至少部分的公知结构和技术没有被示出，以便避免对本申请造成不必要的模糊；并且，为了清晰，可能夸大了区域结构的尺寸。此外，下文中所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。
本申请实施例提供的显示面板，可以在不增加工艺难度的基础上采用网状电源电压信号线设计，减少因IR Drop造成的显示不均等问题。下面结合附图详细描述各实施例提供的显示面板的具体结构。
第一实施例
图1示出本申请第一实施例提供的显示面板的俯视结构示意图，图2示出图1中的区域A的放大结构图，图3示出图2沿B-B方向的剖面图，图4示出图2沿C-C方向的剖面图。
如图1至图4所示，本申请第一实施例提供的显示面板，包括衬底基板1和位于衬底基板1上的驱动阵列层，驱动阵列层包括薄膜晶体管2a和多条电源电压信号线231，薄膜晶体管2a包括相对设置的底栅G1和顶栅G2，以及位于顶栅G2两侧的源极S和漏极D，电源电压信号线231与源极S和漏极D同层布置。
驱动阵列层还包括与底栅G1同层布置的多条分压走线211，多条分压走线211与多条电源电压信号线231相互交叉呈网格状分布，且分压走线211与电源电压信号线231的至少部分交叉处通过过孔H电连接。
具体来说，驱动阵列层包括沿远离衬底基板1的方向依次层叠布置的第一金属层21、第二金属层22和第三金属层23，第一金属层21包括薄膜晶体管2a的底栅，第二金属层22包括薄膜晶体管2a的顶栅；第三金属层23包括多条电源电压信号线231。可选地，衬底基板1的材质可以为玻璃、透明树脂、石英、蓝宝石等。可选地，第一金属层21、第二金属层22和第三金属层23的材质包括铝或铝合金，提升了金属走线的电导率和弯折特性，降低了动态弯折的断线风险。
本申请实施例中，位于第三金属层23的多条电源电压信号线231与位于第一金属层21的多条分压走线211相互交叉呈网格状分布，且分压走线211与电源电压信号线231的至少部分交叉处通过过孔H电连接，形成双层走线结构。可选地，分压走线211与电源电压信号线231的每个交叉处均设置过孔H，且过孔H的数量越多，电流的分摊效果越好，从而可以降低电源电压信号线231的电阻值，降低电压损耗下降值，提高整个显示面板内的电阻均一性，进而提升显示面板的亮度均一性。
另外，电源电压信号线231采用双层走线结构，且分压走线211与电源电压信号线231并联，当某一层电路断路时，可通过另一层电路导通，提高了显示面板的可靠性。
进一步地，分压走线211和薄膜晶体管2a的底栅G1均位于第一金属层21，可以同层制备，一方面，与相关技术中额外增加一层金属层来布置分压走线211的技术方案相比，可以减少一道光罩制程，不会增加工艺难度，有利于降低制作成本。第二方面，底栅G1作为薄膜晶体管2a的一部分，在第一金属层21整层中的占用面积较小，有足够的空间布置分压走线211，对开口率的影响相对较小。如果将分压走线211布置于其他膜层，例如第二金属层22，由于第二金属层22需要布置各种信号线，分压走线211将会占据更多的布线空间，影响显示面板的开口率。第三方面，由于第一金属层21与第三金属层23之间相隔有第二金属层22等多个膜层，第一金属层21与第三金属层23之间的距离较远，二者之间的寄生电容较小，有利于减小电源电压信号线231的负载，提高显示面板的显示性能。
本申请实施例提供的一种显示面板，通过在薄膜晶体管2a的底栅所在 的金属层同层布置多条分压走线211，并与多条电源电压信号线231相互交叉呈网格状分布，且分压走线211与电源电压信号线231的至少部分交叉处通过过孔H电连接，使得分压走线211可以在不增加工艺难度的基础上采用网状电源电压信号线设计，减少因IR Drop造成的显示不均等问题。
在一些实施例中，显示面板还包括位于驱动阵列层背离衬底基板1一侧的发光层3，发光层3包括阵列分布的多个子像素31。分压走线211沿第一方向X延伸，电源电压信号线231沿与第一方向X相交的第二方向Y延伸，分压走线211与电源电压信号线231相互交叉限定的每个网格内布置有至少一个子像素31。
如图1所示，多个子像素31沿第一方向X和第二方向Y阵列排布，分压走线211与电源电压信号线231相互交叉限定的每个网格内布置有一个子像素31，即多个网格与多个子像素31一一对应。每个网格由相邻的两条电源电压信号线231与相邻的两条分压走线211交叉而成，且每个网格的四个交叉处分别设置有一个过孔H，使得分压走线211可以分摊电源电压信号线231的电流，减小电源电压信号线231的IR-Drop程度。
也就是说，多条电源电压信号线231与多条分压走线211交叉设置后形成阵列分布的多个交叉点，交叉点处设置的过孔H的数量越多，电流的分摊效果越好，从而可以在显示面板的整个面内分摊电流，进而减小整个面内的IR-Drop程度，提升显示面板的亮度均一性。
在一些实施例中，驱动阵列层还包括与顶栅G2同层布置的连接部221，连接部221与分压走线211和电源电压信号线231在衬底基板1上的正投影分别至少部分交叠，过孔H与连接部221搭接设置。本文中，“搭接”指的是，过孔H在第三金属层23与第一金属层21之间的深度方向上填充有金属，位于第二金属层22的连接部221将过孔H内的金属分为两部分，该两部分金属通过连接部221相互连接，以实现分压走线211与电源电压信号线231之间的电连接。其中，过孔H在深度方向上位于连接部221两侧的通孔可以对齐设置，也可以错位设置。
如图3和图4所示，由于第一金属层21与第三金属层23之间相隔有第二金属层22等多个膜层，第一金属层21与第三金属层23之间的距离较 远，过孔H的深度较深，很难保证各膜层之间的过孔H的对准精度，进而影响电源电压信号线231与分压走线211的电连接性能。为了提高二者的电连接性能，简化制作工艺，可以在第二金属层22布置连接部221，并将过孔H与连接部221搭接连接。这样，第二金属层22的连接部221与第一金属层21的分压走线211之间距离以及连接部221与第三金属层23的电源电压信号线231之间的距离相对较小，减小了过孔H在连接部221两侧的深度，有利于提高电源电压信号线231与分压走线211的电连接性能。
进一步地，驱动阵列层还包括第一绝缘层24和第二绝缘层25，第一绝缘层24位于分压走线211与连接部221之间，第二绝缘层25位于连接部221与电源电压信号线231之间，过孔H包括分别与连接部221搭接的第一过孔H1和第二过孔H2，第一过孔H1贯穿第一绝缘层24，第二过孔H2贯穿第二绝缘层25。
在一个示例中，第一绝缘层24包括缓冲层241和栅绝缘层242，第一过孔H1贯穿缓冲层241和栅绝缘层242设置。第二绝缘层25为层间绝缘层，第二过孔H2贯穿层间绝缘层设置。由于第一过孔H1和第二过孔H2分别与连接部221搭接设置实现电性连接，第一过孔H1和第二过孔H2不必在深度方向对齐设置，简化了制作工艺。
在一些实施例中，第一过孔H1在衬底基板1上的正投影与第二过孔H2在衬底基板1上的正投影重叠。当第一过孔H1和第二过孔H2在深度方向对齐设置时，可以减少占用空间，有利于提高开口率。
在一些实施例中，第一绝缘层24还设置有第三过孔H3，顶栅G2通过第三过孔H3与底栅G1电连接。
如图2所示，第二金属层22还包括沿第一方向X延伸的扫描线222，第三金属层23还包括沿第二方向Y延伸的数据线232，数据线232与电源电压信号线231相邻设置。扫描线222与薄膜晶体管2a的顶栅G2电连接，数据线232与薄膜晶体管2a的源极S电连接。
如图4所示，缓冲层241与栅绝缘层242之间还形成有源层ACT，底栅G1在衬底基板1上的正投影覆盖有源层ACT在衬底基板1上的正投影，可以防止外界光线对薄膜晶体管2a产生不良的影响；另外，顶栅G2通过 第三过孔H3与底栅G1电连接，薄膜晶体管2a的栅极采用双层走线结构，可以减小与栅极S电连接的扫描线222的负载。
在一些实施例中，子像素31包括依次层叠设置的第一电极311、发光结构和第二电极，第一电极311与薄膜晶体管2a的源极S或者漏极D电连接，第二电极为透明导电层。
第一电极311和第二电极中的任一者为子像素31的阳极，另一者为子像素31的阴极。本申请中以第一电极311为阳极为例进行说明，第二电极为透明导电层，即阴极为透明导电层，便于出射光线。
分压走线211与电源电压信号线231相互交叉限定的每个网格内布置有一个子像素31，该子像素31的第一电极311与薄膜晶体管2a的漏极D电连接，薄膜晶体管2a的源极S与数据线232电连接。
另外，显示面板还包括像素限定层，像素限定层位于驱动阵列层背离衬底基板1的一侧，像素限定层包括多个像素开口，子像素31的至少部分位于像素开口内。具体来说，子像素31的发光结构和第二电极位于像素开口内，第一电极311与像素开口对应。
第二实施例
图5示出本申请第二实施例提供的显示面板的俯视结构示意图。
如图5所示，本申请第二实施例还提供了一种显示面板，其与第一实施例提供的显示面板的结构类似，不同之处在于，分压走线211的排布不同。
具体来说，显示面板包括位于驱动阵列层背离衬底基板1一侧的发光层3，发光层3包括阵列分布的多个子像素31。分压走线211沿第一方向X延伸，电源电压信号线231沿与第一方向X相交的第二方向Y延伸，分压走线211与电源电压信号线231相互交叉限定的每个网格内布置有两个子像素31。
如图5所示，电源电压信号线231与数据线232均沿第二方向Y延伸且相邻设置，分压走线211与扫描线(图中未示出)均沿第一方向X延伸，且分压走线211与扫描线间隔预定距离设置，从而使分压走线211与电源 电压信号线231相互交叉限定的网格为大网格。每个大网格内布置有沿第二方向Y对齐分布的两个子像素31，由于两个子像素31之间没有任何走线，节省布线空间，子像素31的尺寸可以设计得较大，提高了显示面板的开口率。
可以理解的是，分压走线211与电源电压信号线231相互交叉限定的每个网格内还可以布置更多个子像素31，同时由于子像素31数量越多，交叉点的位置越少，不利于减少IR-Drop，因此需要兼顾布线空间与IR-Drop之间的平衡，根据具体的设计需求而定。
第三实施例
图6示出本申请第三实施例提供的显示面板的俯视结构示意图。
如图6所示，本申请第三实施例还提供了一种显示面板，其与第一实施例提供的显示面板的结构类似，不同之处在于，分压走线211的排布不同。
具体来说，每条分压走线211包括沿第一方向X间隔分布的多条分压走线段211a，每条分压走线段211a的两端分别与相邻的两条电源电压信号线231电连接，且每相邻的两条分压走线211的各分压走线段211a沿第一方向X交错设置。
如图6右上角的箭头所示，从电源电压信号线231一侧流入的电流，经过其与分压走线段211a的交叉点处时，一部分电流通过过孔H导入至分压走线段211a中，另一部分电流继续沿电源电压信号线231流动，进入分压走线段211a中的电流在经过其与另一条电源电压信号线231的交叉点处断开，通过过孔H导入至另一条电源电压信号线231中，从而使得进入各条电源电压信号线231的电流在第三金属层23和第一金属层21之间流动，共同分摊电流。
进一步地，在第二方向Y上，相邻的两条分压走线段211a之间形成有对齐分布的两个子像素31。由于两个子像素31之间没有任何走线，节省布线空间，子像素31的尺寸可以设计得较大，提高了显示面板的开口率。
本实施例通过将分压走线211分段设计，可以将一列子像素31沿第一 方向X的横向走线减半，并且相邻的两列子像素31的横向间隔错位设计，与第一实施例的小网格设计相比，交叉点数量相同，电流的分摊效果相同，但可以增大子像素31的设计空间，提高开口率。与第二实施例的大网格设计相比，交叉点数量较多，减少了电源电压信号线231的负载，电流分摊效果更好，有利于提升显示亮度的均一性。
由此，本实施例提供的分压走线211，具有与小网格结构同样数量的交叉点，具备相同的电流分摊效果，可以减小IR-Drop程度；同时也具备大网格节省空间、提高开口率的优点，兼顾了布线空间与IR-Drop之间的平衡。
另外，本申请实施例还提供了一种显示装置，包括如前所述的任一种显示面板。该显示装置可以为例如但不限于可穿戴设备、手机、平板电脑、电视机、显示器、笔记本电脑、电子书、电子报纸、数码相框、导航仪等任何具有显示功能的产品或部件。其中，可穿戴设备包括智能手环、智能手表、虚拟现实(Virtual Reality，VR)等设备。
应当容易地理解，应当按照最宽的方式解释本申请中的“在……上”、“在……以上”和“在……之上”，以使得“在……上”不仅意味着“直接处于某物上”，还包括“在某物上”且其间具有中间特征或层的含义，并且“在……以上”或者“在……之上”不仅包括“在某物以上”或“之上”的含义，还可以包括“在某物以上”或“之上”且其间没有中间特征或层(即，直接处于某物上)的含义。
文中使用的术语“衬底基板”是指在其上添加后续材料层的材料。衬底基板本身可以被图案化。添加到衬底基板顶上的材料可以被图案化，或者可以保持不被图案化。此外，衬底基板可以包括宽范围内的一系列材料，例如，硅、锗、砷化镓、磷化铟等。替代地，衬底基板可以由非导电材料(例如，玻璃、塑料或者蓝宝石晶圆等)制成。
文中使用的术语“层”可以指包括具有一定厚度的区域的材料部分。层可以在整个的下层结构或上覆结构之上延伸，或者可以具有比下层或上覆结构的范围小的范围。此外，层可以是匀质或者非匀质的连续结构的一个区域，其厚度小于该连续结构的厚度。例如，层可以位于所述连续结构 的顶表面和底表面之间或者所述顶表面和底表面处的任何成对的横向平面之间。层可以横向延伸、垂直延伸和/或沿锥形表面延伸。衬底基板可以是层，可以在其中包括一个或多个层，和/或可以具有位于其上、其以上和/或其以下的一个或多个层。层可以包括多个层。例如，互连层可以包括一个或多个导体和接触层(在其内形成触点、互连线和/或过孔)以及一个或多个电介质层。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (13)

  1. 一种显示面板，包括衬底基板和位于所述衬底基板上的驱动阵列层，所述驱动阵列层包括薄膜晶体管和多条电源电压信号线，所述薄膜晶体管包括相对设置的底栅和顶栅以及位于所述顶栅两侧的源极和漏极，所述电源电压信号线与所述源极和所述漏极同层布置，其中，
    所述驱动阵列层还包括与所述底栅同层布置的多条分压走线，所述多条分压走线与所述多条电源电压信号线相互交叉呈网格状分布，且所述分压走线与所述电源电压信号线的至少部分交叉处通过过孔电连接。2.根据权利要求1所述的显示面板，其中，还包括位于所述驱动阵列层背离所述衬底基板一侧的发光层，所述发光层包括阵列分布的多个子像素；
    所述分压走线沿第一方向延伸，所述电源电压信号线沿与所述第一方向相交的第二方向延伸，所述分压走线与所述电源电压信号线相互交叉限定的每个网格内布置有至少一个所述子像素。
  2. 根据权利要求2所述的显示面板，其中，每条所述分压走线包括沿所述第一方向间隔分布的多条分压走线段，每条所述分压走线段的两端分别与相邻的两条所述电源电压信号线电连接，且每相邻的两条所述分压走线的各所述分压走线段沿所述第一方向交错设置。
  3. 根据权利要求3所述的显示面板，其中，在所述第二方向上，相邻的两条所述分压走线段之间形成有对齐分布的两个所述子像素。
  4. 根据权利要求1所述的显示面板，其中，所述驱动阵列层还包括与所述顶栅同层布置的连接部，所述连接部与所述分压走线和所述电源电压信号线在所述衬底基板上的正投影分别至少部分交叠，所述过孔与所述连接部搭接设置。
  5. 根据权利要求5所述的显示面板，其中，所述驱动阵列层还包括第一绝缘层和第二绝缘层，所述第一绝缘层位于所述分压走线与所述连接部之间，所述第二绝缘层位于所述连接部与所述电源电压信号线之间，所述过孔包括分别与所述连接部搭接的第一过孔和第二过孔，所述第一过孔贯穿所述第一绝缘层，所述第二过孔贯穿所述第二绝缘层。
  6. 根据权利要求6所述的显示面板，其中，所述第一过孔在所述衬底 基板上的正投影与所述第二过孔在所述衬底基板上的正投影重叠。
  7. 根据权利要求6所述的显示面板，其中，所述第一绝缘层还设置有第三过孔，所述顶栅通过所述第三过孔与所述底栅电连接。9.根据权利要求2所述的显示面板，其中，所述子像素包括依次层叠设置的第一电极、发光结构和第二电极，所述第一电极与所述薄膜晶体管的源极或者漏极电连接，所述第二电极为透明导电层。
  8. 根据权利要求1所述的显示面板，其中，每个网格由相邻的两条所述电源电压信号线与相邻的两条所述分压走线交叉而成，且每个网格的四个交叉处分别设置有一个所述过孔。
  9. 根据权利要求2所述的显示面板，其中，所述分压走线与所述电源电压信号线相互交叉限定的每个网格内布置有一个所述子像素。
  10. 根据权利要求2所述的显示面板，其中，所述分压走线与所述电源电压信号线相互交叉限定的每个网格内布置有两个所述子像素。
  11. 根据权利要求6所述的显示面板，其中，所述第一绝缘层包括缓冲层和栅绝缘层，所述缓冲层与所述栅绝缘层之间还形成有源层，所述底栅在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
  12. 根据权利要求2所述的显示面板，其中，所述显示面板还包括像素限定层，所述像素限定层位于所述驱动阵列层背离所述衬底基板的一侧，所述像素限定层包括多个像素开口，所述子像素的至少部分位于所述像素开口内。
  13. 一种显示装置，包括显示面板，所述显示面板包括衬底基板和位于所述衬底基板上的驱动阵列层，所述驱动阵列层包括薄膜晶体管和多条电源电压信号线，所述薄膜晶体管包括相对设置的底栅和顶栅以及位于所述顶栅两侧的源极和漏极，所述电源电压信号线与所述源极和所述漏极同层布置，其中，
    所述驱动阵列层还包括与所述底栅同层布置的多条分压走线，所述多条分压走线与所述多条电源电压信号线相互交叉呈网格状分布，且所述分压走线与所述电源电压信号线的至少部分交叉处通过过孔电连接。
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