Nothing Special   »   [go: up one dir, main page]

WO2023283994A1 - 液晶显示面板及显示装置 - Google Patents

液晶显示面板及显示装置 Download PDF

Info

Publication number
WO2023283994A1
WO2023283994A1 PCT/CN2021/108099 CN2021108099W WO2023283994A1 WO 2023283994 A1 WO2023283994 A1 WO 2023283994A1 CN 2021108099 W CN2021108099 W CN 2021108099W WO 2023283994 A1 WO2023283994 A1 WO 2023283994A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
sub
data line
pixels
liquid crystal
Prior art date
Application number
PCT/CN2021/108099
Other languages
English (en)
French (fr)
Inventor
严允晟
李利霞
彭邦银
赵迎春
龙芬
张琦琦
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/438,658 priority Critical patent/US11899325B2/en
Publication of WO2023283994A1 publication Critical patent/WO2023283994A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements

Definitions

  • the present application relates to the field of display technology, in particular to a liquid crystal display panel and a display device.
  • the purpose of the present invention is to provide a liquid crystal display panel and a display device to solve the technical problem of poor picture quality of the display screen.
  • the present invention provides a liquid crystal display panel, comprising: a pixel matrix consisting of more than two sub-pixels; the colors of three adjacent sub-pixels in the same row are different, and the colors of all the sub-pixels in the same column The same color; more than two data lines parallel to each other, each data line is located between two adjacent columns of sub-pixels; and more than two scan lines parallel to each other, each scan line is located between two adjacent rows of sub-pixels ; Wherein, each data line is connected to at least one pixel group in turn, and each pixel group includes three sub-pixels with different colors, which are respectively located on both sides of a data line; in a pixel group, each data line is sequentially connected to three subpixels.
  • the three sub-pixels in the same pixel group are located in three adjacent rows of the pixel matrix.
  • a pixel group includes: a first sub-pixel located on a first side of a data line; a second sub-pixel located on a second side of the data line; a third sub-pixel located on the first side of the data line or The second side: the data line is located between the first sub-pixel and the second sub-pixel adjacent to each other.
  • a pixel group includes: a first sub-pixel located on the first side or a second side of a data line; a second sub-pixel located on the first side of the data line; a third sub-pixel located on the data line
  • a pixel group includes: a first sub-pixel located on the first side of a data line; a second sub-pixel located on the first side or a second side of the data line; a third sub-pixel located on the data line The second side: the data line is located between the first sub-pixel and the third sub-pixel adjacent to each other.
  • the liquid crystal display panel further includes: a first driving unit, electrically connected to the data lines, and inputting grayscale voltages to a plurality of data lines; a second driving unit, electrically connected to the scanning lines, and Scan signals are input to a plurality of scan lines.
  • the grayscale voltages of the pixel groups connected to one data line have the same polarity, and the polarities of the pixel groups connected to the data lines on both sides of the data line The polarity of the grayscale voltage is opposite to that of the pixel group connected to the data line.
  • the liquid crystal display panel further includes: a thin film transistor, the gate of which is electrically connected to the corresponding scan line, the source of which is electrically connected to the corresponding data line, and the drain of which is electrically connected to the corresponding sub-pixel.
  • the present invention also provides a display device, comprising the above-mentioned liquid crystal display panel; a backlight module having a light-emitting surface, wherein the liquid crystal display panel is disposed on the light-emitting surface of the backlight module.
  • the technical effect of the present invention is to provide a liquid crystal display panel and a display device.
  • the liquid crystal display panel includes a pixel structure that can realize three times of pixel flipping. Sub-pixels with different colors and located in different columns are changed from the original charging sequence R (red sub-pixel) ⁇ G (green sub-pixel) to R (red sub-pixel) ⁇ G (green sub-pixel) ⁇ B (blue sub-pixel) pixels) to ensure the uniformity of sub-pixel charging, and also make the sub-pixels arranged in a staggered way after being coupled by data lines, which balances the brightness of the display, thus effectively solving the problem of color crosstalk and improving the performance of the liquid crystal display panel. quality.
  • FIG. 1 is a schematic structural diagram of a commonly used pixel structure at present.
  • FIG. 2 is a timing diagram when the red, green and blue (RGB) sub-pixels in FIG. 1 are coupled.
  • FIG. 3 is a schematic structural diagram of a pixel structure provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of driving a pixel structure provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 6 is a plan view of a pixel structure provided by an embodiment of the present application.
  • FIG. 7 is a timing diagram of the data lines D1 , D2 , D3 and D4 in FIG. 4 .
  • Pixel structure 10. Pixel matrix;
  • 110a the first pixel group
  • 110b the second pixel group
  • the second driving unit 40.
  • the thin film transistor 40.
  • Fig. 1 is a structural schematic diagram of a commonly used pixel structure at present;
  • Fig. 2 is a timing diagram when red, green and blue (RGB) sub-pixels in Fig. 1 are coupled.
  • RGB red, green and blue
  • the liquid crystal display panel includes m data lines D1'-Dm' (dataline) and n scanning lines G1'-Gn' (Gateline ), m data lines are arranged in the vertical direction, n scanning lines are arranged in the horizontal direction, and the data lines and the scanning lines intersect to form a plurality of sub-pixels arranged in an array.
  • the sub-pixels of the same color are in the vertical direction, and the red sub-pixels (R), green sub-pixels (G), and blue sub-pixels (B) are arranged circularly in the horizontal direction.
  • a data line is connected to the sub-pixels in the same column, and the gray-scale voltage transmitted on the data line (D1'-Dm'), with the common voltage Vcom as the reference voltage, can be divided into positive polarity gray-scale voltage (+) and Negative polarity grayscale voltage (-).
  • the positive gray-scale voltage means that the actual gray-scale voltage transmitted on the data line (D1'-Dm') is higher than the common voltage Vcom
  • the negative gray-scale voltage means that the actual gray-scale voltage transmitted on the data line (D1'-Dm') The transmitted actual gray scale voltage is lower than the common voltage Vcom.
  • the R subpixel maintains the grayscale voltage of L64+
  • the signal change of the data line D1' on the left side of the R subpixel is: L64 ⁇ L0+
  • the signal change of the data line D2' on the right side of the R subpixel is: L64- ⁇ L0-
  • the left and right data lines D1 ′, D2 ′ have the same amount of coupling to the R sub-pixel, so that the voltage of the R sub-pixel at A remains unchanged.
  • the G subpixel maintains the grayscale voltage of L64-
  • the signal change of the data line D2' on the left side of the G subpixel is: L64- ⁇ L0-
  • the signal change of the data line D3' on the right side of the G subpixel is: L64+ ⁇ L255+
  • the left and right data lines D2', D3' have a tendency to pull up the voltage of the G sub-pixel, making the G sub-pixel at A dark.
  • the B subpixel maintains the grayscale voltage of L64+
  • the signal change of the data line D3' on the left side of the B subpixel is: L64+ ⁇ L255+
  • the signal change of the data line D4' on the right side of the B subpixel is: L64+ ⁇ L0+
  • the amount of coupling (coupling) of the left and right data lines D3' and D4' to the B pixel is different, and the left data line D3' has a greater pull-up effect on the coupling of the B sub-pixel, so that the voltage of the B sub-pixel is pulled up (That is, the pull-up amount on the left side is greater than the pull-down amount on the right side), and the sub-pixel B at A becomes brighter.
  • the R sub-pixel maintains the grayscale voltage of L64+
  • the signal change of the data line D1' on the left side of the R pixel is: L64 ⁇ L0+
  • the signal change of the data line D2' on the right side of the R sub-pixel is: L64- ⁇ L0-
  • the left and right data lines D1 ′, D2 ′ have the same amount of coupling (coupling) to the R sub-pixel, so that the voltage of the R sub-pixel at A remains unchanged.
  • the G subpixel maintains the grayscale voltage of L64-
  • the signal change of the data line D2' on the left side of the G subpixel is: L64- ⁇ L0-
  • the signal change of the data line D3' on the right side of the G subpixel is: L64+ ⁇ L255+
  • the left and right data lines D2', D3' have a tendency to pull up the voltage of the G sub-pixel, making the G sub-pixel at A brighter.
  • the B subpixel maintains the grayscale voltage of L64+
  • the signal change of the data line D3' on the left side of the B subpixel is: L64+ ⁇ L255+
  • the signal change of the data line D4' on the right side of the B subpixel is: L64+ ⁇ L0+
  • the amount of coupling (coupling) of the left and right data lines D3' and D4' to the B pixel is different, and the left data line D3' has a greater pull-up effect on the coupling of the B sub-pixel, so that the voltage of the B sub-pixel is pulled up , sub-pixel B at A becomes darker.
  • D_L in FIG. 2 refers to the left side of the data line
  • D_R refers to the right side of the data line
  • This embodiment provides a liquid crystal display panel, which includes a pixel structure that can be flipped three times. Any data line of the pixel structure can simultaneously drive sub-pixels of three different colors and located in different columns by crossing the line.
  • Some charging sequence R (red sub-pixel) ⁇ G (green sub-pixel) is changed to R (red sub-pixel) ⁇ G (green sub-pixel) ⁇ B (blue sub-pixel) to ensure the uniformity of sub-pixel charging, It can also make the sub-pixels arranged alternately in bright and dark after being coupled by the data line, so as to balance the brightness of the display, thereby effectively solving the problem of color crosstalk, and further improving the quality of the liquid crystal display panel.
  • FIG. 3 is a schematic structural diagram of a pixel structure provided by an embodiment of the present application.
  • the pixel structure 100 includes a pixel matrix 10 composed of more than two sub-pixels, three adjacent sub-pixels in the same row have different colors, and all sub-pixels in the same column have the same color.
  • the sub-pixels include a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103 of different colors, the first sub-pixel 101 is a red pixel, and the second sub-pixel 102 is a green sub-pixel, so The third sub-pixel 103 is a blue sub-pixel.
  • the pixel structure 100 further includes m parallel data lines D1, D2, D3, ... (Dm-2), (Dm-1), Dm and n parallel scan lines G1, G2, G3, ... ...(Gn-2), (Gn-1), Gn, the data lines extend vertically and are arranged at intervals in the horizontal direction, and each data line is located between two adjacent columns of sub-pixels. Scanning lines perpendicular to the data lines extend horizontally and are arranged at intervals in the vertical direction, and each scanning line is located between two adjacent rows of sub-pixels.
  • a plurality of first sub-pixels 101 are arranged in a matrix in the first row of pixels and are located on the left side of the first data line D1
  • a plurality of second sub-pixels 102 are arranged in a matrix in a second row of pixels and are located in the second On the left side of the data line D2
  • a plurality of third sub-pixels 103 are arranged in a matrix to form a third column of pixels, and are located on the left side of the third data line D3
  • a plurality of first sub-pixels 101 are arranged in a matrix to form a fourth column of pixels, and are located in a matrix of On the left side of the fourth data line D4..., simply speaking, all the sub-pixels in the same column have the same color, and the three sub-pixels with different colors are arranged according to the first sub-pixel 101 and the second sub-pixel in the row direction.
  • the pixel 102 and the third sub-pixel 103 are arranged circularly, or the second sub-pixel 102, the third sub-pixel 103, and the first sub-pixel 101 are arranged circularly, or the third sub-pixel 103, the first sub-pixel 101 1.
  • the sequence of the second sub-pixels 102 is arranged circularly.
  • each data line is connected to at least one pixel group 110 in sequence, and each pixel group 110 includes three sub-pixels with different colors, and the three sub-pixels in the same pixel group 110 are located in the adjacent three pixels of the pixel matrix 10. in line.
  • the first sub-pixel 101 is located on the left side of the first data line D1
  • the second sub-pixel 102 is located on the right side of the first data line D1
  • the third sub-pixel 103 is also located on the first data line D1.
  • the right side of a data line D1 and the first data line D1 is located between the first sub-pixel 101 and the second sub-pixel 102 adjacent to each other.
  • the first data line D1 connects the two first pixel groups 110a. In each first pixel group 110a, the first data line D1 is first connected to the first sub-pixel 101 of the first row of pixels, then connected to the second sub-pixel 102 of the second row of pixels, and finally connected to the third sub-pixel 102 of the third row of pixels. sub-pixel 103 .
  • the first data line D1 is connected to at least one first pixel group 110a, and in each first pixel group 110a, the first data line D1 is connected according to the first sub-pixel 101, the second sub-pixel 102 and the third sub-pixel
  • the pixel 103 is sequentially connected to three sub-pixels of different colors.
  • the second sub-pixel 102 is located on the left side of the second data line D2
  • the third sub-pixel 103 is located on the right side of the second data line D2
  • the first sub-pixel 101 is also located on the right side of the second data line D2.
  • the second data line D2 is located between the second sub-pixel 102 and the third sub-pixel 103 adjacent to each other.
  • the second data line D2 is connected to the two second pixel groups 110b. In each second pixel group 110b, the second data line D2 is first connected to the second sub-pixel 102 of the second column of pixels, then connected to the third sub-pixel 103 of the third column of pixels, and finally connected to the first sub-pixel of the fourth column of pixels. sub-pixel 101 .
  • the second data line D2 is connected to at least one second pixel group 110b, and in each second pixel group 110b, the second data line D2 is connected according to the second sub-pixel 102, the third sub-pixel 103 and the first sub-pixel
  • the pixel 101 is sequentially connected to three sub-pixels of different colors.
  • the third sub-pixel 103 is located on the left side of the third data line D3, the first sub-pixel 101 is located on the right side of the third data line D3, and the second sub-pixel 102 is also located on the right side of the third data line D3 side, and the third data line D3 is located between the third sub-pixel 103 and the first sub-pixel 101 adjacent to each other.
  • the third data line D3 connects two third pixel groups 110c.
  • the third data line D3 is first connected to the third sub-pixel 103 of the third row of pixels, then connected to the first sub-pixel 101 of the fourth row of pixels, and finally connected to the second sub-pixel 101 of the fifth row of pixels. sub-pixel 102 .
  • the third data line D3 is connected to at least one third pixel group 110c, and in each third pixel group 110c, the third data line D3 is connected according to the third sub-pixel 103, the first sub-pixel 101 and the second sub-pixel The order of the pixels 102 is sequentially connected to three sub-pixels of different colors.
  • the numbers of the sub-pixels of the three colors are equal. That is, in one pixel group, the numbers of the first sub-pixels 101 , the second sub-pixels 102 and the third sub-pixels 103 are equal.
  • FIG. 4 is a schematic diagram of driving a pixel structure provided by an embodiment of the present application.
  • the pixel structure 100 further includes a first driving unit 20 and a second driving unit 30 .
  • the first driving unit 20 is a source driver
  • the second driving unit 30 is a gate driver, such as a GOA driving circuit.
  • the first driving unit 20 is electrically connected to the data lines, and inputs grayscale voltages to the data lines column by column.
  • the grayscale voltages include positive grayscale voltages (+) and negative grayscale voltages ( ⁇ ).
  • the second driving unit 30 is electrically connected to the scan lines, and inputs scan signals to a plurality of scan lines row by row.
  • the first driving unit 20 inputs a positive grayscale voltage to a data line
  • the pixel group connected to the data line is in a bright state.
  • the first driving unit 20 inputs a negative grayscale voltage to a data line
  • the pixel group connected to the data line is in a dark state.
  • the first driving unit 20 inputs grayscale voltages to the data lines and the second driving unit 30 supplies gray scale voltages to the scanning lines G1, G2, G3, ... (Gn-2) row by row.
  • Gn-1 when the scanning signal is input, the polarities of the grayscale voltages of the pixel groups connected by a data line are the same, and the polarities of the grayscale voltages of the pixel groups connected by the data lines on both sides of the data line are the same. polarity is opposite to that of the grayscale voltage of the pixel group connected to the data line.
  • the pixel structure 100 also includes a thin film transistor 40, which is arranged in the pixel area of each sub-pixel, its gate is electrically connected to the corresponding scanning line, its source is electrically connected to the corresponding data line, and its drain is electrically connected to the the corresponding sub-pixel.
  • a thin film transistor 40 which is arranged in the pixel area of each sub-pixel, its gate is electrically connected to the corresponding scanning line, its source is electrically connected to the corresponding data line, and its drain is electrically connected to the the corresponding sub-pixel.
  • FIG. 5 is a schematic structural diagram of an array substrate provided in an embodiment of the present application
  • FIG. 6 is a plan view of a pixel structure provided in an embodiment of the present application.
  • the display panel provided in this embodiment includes an array substrate having a plurality of thin film transistors 40, and the array substrate includes a substrate 51, a gate layer 52, a gate insulating layer 53, a first contact layer in sequence from bottom to top. layer 54 , a second contact layer 55 , a source-drain layer 56 , an insulating layer 57 and a pixel electrode 58 .
  • the gate layer 52 is disposed on the base 51 .
  • the gate insulating layer 53 covers the gate layer 52 and extends to the surface of the substrate 51 .
  • the active layer 54 is disposed on the gate insulating layer 53 and facing the gate layer 52 , wherein the gate layer 52 forms the scan lines of the display panel.
  • the second contact layer 55 is disposed on the first contact layer 54 and located on both sides of the first contact layer 54, so that the second contact layer 55 has a first through hole 61, wherein the The second contact layer 55 is a semiconductor layer, and the first contact layer 54 and the second contact layer form an active layer.
  • the source-drain layer 56 is disposed on the second contact layer 55 and extends from the surface of the second contact layer 55 to the surface of the gate insulating layer 53.
  • the source-drain layer 56 includes a The source and the drain on the right side are arranged at intervals through a second through hole 62, wherein the source and drain layers 56 form the data lines of the display panel.
  • the insulating layer 57 is disposed on the source-drain layer 56 and the gate insulating layer 53, and fills the first through hole 61 and the second through hole 62, and the insulating layer 57 also includes a The third through hole 63 , the third through hole 63 penetrates to the drain.
  • the pixel electrode 58 is disposed on the insulating layer 57 and connected to the drain through the third via hole 63, wherein the pixel electrode 58 is a common electrode of each sub-pixel, as shown in FIG.
  • the common electrode is connected to the data line (drain wiring) by crossing the line, that is to say, the common electrode is directly crossed to the data line (data) of the thin film transistor 40 (TFT) of the adjacent sub-pixel, for For the same data line, cross-column driving is realized without changing the winding of the data line.
  • the charging path of sub-pixels connected to the same data line can be: R ⁇ G ⁇ B ⁇ R ⁇ G ⁇ B, or G ⁇ B ⁇ R ⁇ G ⁇ B ⁇ R, or B ⁇ R ⁇ G ⁇ B ⁇ R ⁇ G.
  • the second driving unit 30 sequentially outputs scanning signals at 60 Hz to drive multiple scanning lines (Gate). That is, the driving sequence of GOA is: GOA: CK1 ⁇ CK2 ⁇ CK3 ⁇ CK4 ⁇ CK5 ⁇ CK6... ⁇ CKn. Gate opening sequence: G1 ⁇ G2 ⁇ G3 ⁇ G4 ⁇ G5 ⁇ G6... ⁇ Gn.
  • FIG. 7 is a timing diagram of the data lines D1 , D2 , D3 and D4 in FIG. 4 .
  • one data line transmits signals to at least one pixel group.
  • the signal of D1 changes as follows: L64+ ⁇ L0+ ⁇ L255+, the first sub-pixel 101, the second sub-pixel 102 and the third sub-pixel 103 are all kept at the gray level of L64+ step voltage.
  • the signal of D2 changes as follows: L64- ⁇ L255- ⁇ L0-, the second sub-pixel 102, the third sub-pixel 103 and the first sub-pixel 101 all maintain L64 - the gray scale voltage.
  • the signal of D3 changes to: L64+ ⁇ L0+ ⁇ L255+, and the third subpixel 103, the first subpixel 101 and the second subpixel 102 maintain the grayscale voltage of L64+ .
  • the signal of D4 changes as follows: L64- ⁇ L0- ⁇ L255-, the first sub-pixel 101, the second sub-pixel 102 and the third sub-pixel 103 all maintain L64 - the gray scale voltage.
  • This embodiment provides a liquid crystal display panel, including a pixel structure that can realize three times of pixel flipping. Any data line of the pixel structure can simultaneously drive three sub-pixels with different colors and located in different columns by crossing the line.
  • Some charging sequence R (red sub-pixel) ⁇ G (green sub-pixel) is changed to R (red sub-pixel) ⁇ G (green sub-pixel) ⁇ B (blue sub-pixel) to ensure the uniformity of sub-pixel charging, It can also make the sub-pixels arranged alternately in bright and dark after being coupled by the data line, so as to balance the brightness of the display, thereby effectively solving the problem of color crosstalk, and further improving the quality of the liquid crystal display panel.
  • This embodiment also provides a display device, including the above-mentioned liquid crystal display panel and a backlight module (not shown in the figure), and the liquid crystal display panel is configured on the light emitting surface of the backlight module.
  • the display device may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.
  • a pixel group includes a first sub-pixel, a second sub-pixel and a third sub-pixel.
  • the first sub-pixel is located on the first side of a data line
  • the second sub-pixel is located on the second side of the data line
  • the third sub-pixel is located on the first side of the data line
  • the data A line is located between the first sub-pixel and the second sub-pixel adjacent to each other.
  • the first sub-pixel is located on the second side of a data line
  • the second sub-pixel is located on the first side of the data line
  • the third sub-pixel is located on the second side of the data line
  • the data The line is located between the second and third sub-pixels adjacent to each other.
  • the first sub-pixel is located on the first side of a data line
  • the second sub-pixel is located on the second side of the data line
  • the third sub-pixel is located on the second side of the data line
  • the data line is located on the second side of the data line.
  • first side and the second side are relative to the two sides of a certain data line, and those skilled in the art can set them according to the actual situation, as long as one data line can connect three adjacent columns and Pixels of different colors located in three adjacent rows can be connected, and details will not be repeated here.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶显示面板及显示装置，液晶显示面板包括像素矩阵（10），由两个以上子像素组成，位于同一行的三个相邻子像素的颜色相异，位于同一列的所有子像素的颜色相同，每一数据线依次连接至少一像素组（110），每一像素组（110）包括颜色相异的三个子像素，分别位于一数据线两侧；在一像素组（110）中，每一数据线按顺序依次连接至三个子像素。

Description

液晶显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种液晶显示面板及显示装置。
 背景技术
在液晶显示（Liquid Crystal Display，LCD）面板中，由于数据线与像素之间存在耦合（coupling），RGB像素对应耦合的程度不同而出现色偏，导致色串扰（Color crosstalk）图框存在，从而严重影响了显示屏画面的品质。
 技术问题
本发明的目的在于，提供一种液晶显示面板及显示装置，以解决显示屏画面品质较差的技术问题。
 技术解决方案
为实现上述目的，本发明提供一种液晶显示面板，包括：像素矩阵，由两个以上子像素组成；位于同一行的三个相邻子像素的颜色相异，位于同一列的所有子像素的颜色相同；两条以上彼此平行的数据线，每一数据线位于相邻的两列子像素之间；以及两条以上彼此平行的扫描线，每一扫描线位于相邻的两行子像素之间；其中，每一数据线依次连接至少一像素组，每一像素组包括颜色相异的三个子像素，分别位于一数据线两侧；在一像素组中，每一数据线按顺序依次连接至三个子像素。
进一步地，同一像素组中的三个子像素位于所述像素矩阵的相邻三行内。
进一步地，一像素组包括：第一子像素，位于一数据线的第一侧；第二子像素，位于该数据线的第二侧；第三子像素，位于该数据线的第一侧或第二侧；该数据线位于彼此相邻的所述第一子像素与所述第二子像素之间。
进一步地，一像素组包括：第一子像素，位于一数据线的第一侧或第二侧；第二子像素，位于该数据线的第一侧；第三子像素，位于该数据线的第二侧；该数据线位于彼此相邻的第二子像素与第三子像素之间。
进一步地，一像素组包括：第一子像素，位于一数据线的第一侧；第二子像素，位于该数据线的第一侧或第二侧；第三子像素，位于该数据线的第二侧；该数据线位于彼此相邻的所述第一子像素与所述第三子像素之间。
进一步地，所述的液晶显示面板还包括：第一驱动单元，电连接至所述数据线，并向多条数据线输入灰阶电压；第二驱动单元，电连接至所述扫描线，并向多条扫描线输入扫描信号。
进一步地，所述第一驱动单元向所述数据线输入灰阶电压时，一数据线连接的像素组的灰阶电压的极性相同，位于该数据线两侧的数据线连接的像素组的灰阶电压的极性与该数据线连接的像素组的灰阶电压的极性相反。
进一步地，三种颜色的所述子像素的数量相等。
进一步地，所述的液晶显示面板还包括：薄膜晶体管，其栅极电连接至对应的扫描线，其源极电连接至对应的数据线，其漏极电连接至对应的子像素。
为实现上述目的，本发明还提供一种显示装置，包括如前文所述的液晶显示面板；背光模块，具有一出光面，其中所述液晶显示面板配置于该背光模块的该出光面。
 有益效果
本发明的技术效果在于，提供一种液晶显示面板及显示装置，所述液晶显示面板包括可实现三次像素翻转的像素结构，该像素结构的任一条数据线可以通过跨线的方式同时驱动三种颜色不同且位于不同列的子像素，由原有的充电顺序R（红色子像素）→G（绿色子像素）改为R（红色子像素）→G（绿色子像素）→B（蓝色子像素），以保证子像素充电的均一性，还能使子像素被数据线耦接之后亮暗交错排列，均衡了显示的亮度，从而有效地解决了颜色串扰的问题，进而提高了液晶显示面板的品质。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为目前常用的像素结构的结构示意图。
图2为图1中红绿蓝（RGB）子像素耦合时的时序图。
图3为本申请实施例提供的像素结构的结构示意图。
图4为本申请实施例提供的像素结构的驱动示意图。
图5为本申请实施例提供的阵列基板的结构示意图。
图6为本申请实施例提供的像素结构的平面图。
图7为图4中数据线D1、D2、D3及D4的时序图。
附图部件标识如下：
100、像素结构；10、像素矩阵；
101、第一子像素；102、第二子像素；
103、第三子像素；110、像素组；
110a、第一像素组；110b、第二像素组；
110c、第三像素组；20、第一驱动单元；
30、第二驱动单元；40、薄膜晶体管；
51、基底；52、栅极层；
53、栅极绝缘层；54、第一接触层；
55、第二接触层；56、源漏极层；
57、绝缘层；58、像素电极；
61、第一通孔；62、第二通孔；
63、第三通孔。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。在本申请的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
图1为目前常用的像素结构的结构示意图；图2为图1中红绿蓝（RGB）子像素耦合时的时序图。
如图1-图2所示，在纵条纹（Column+Stripe）的像素架构中，液晶显示面板包括m条数据线D1’-Dm’（dataline）和n条扫描线G1’-Gn’（Gateline），m条数据线沿竖直方向排列，n条扫描线沿水平方向排列，数据线和扫描线交叉形成多个阵列排布的子像素。
通常情况下，竖直方向为相同颜色的子像素，水平方向以红子像素（R）、绿子像素（G）、蓝子像素（B）的顺序循环排列。
其中，一条数据线连接同一列的子像素，在数据线(D1’-Dm’)上所传送的灰阶电压，以公共电压Vcom作为参考电压，可以分为正极性灰阶电压（+）和负极性灰阶电压（-）。其中，正极性灰阶电压是指数据线(D1’-Dm’)上所传送的实际灰阶电压高于公共电压Vcom，负极性灰阶电压是指数据线(D1’-Dm’)上所传送的实际灰阶电压低于公共电压Vcom。
具体的，在A处，R子像素保持L64+的灰阶电压，R子像素左侧数据线D1’的信号变化为：L64→L0+，R子像素右侧数据线D2’信号变化为：L64-→L0-，此时，左右数据线D1’、D2’对R子像素的耦合（coupling）的量相同，使得位于A处R子像素的电压保持不变。
在A处，G子像素保持L64-的灰阶电压，G子像素左侧数据线D2’的信号变化为：L64-→L0-，G子像素右侧数据线D3’的信号变化为：L64+→L255+，此时，左右数据线D2’、D3’对G子像素均有电压上拉趋势，使得位于A处G子像素变暗。
在A处，B子像素保持L64+的灰阶电压，B子像素左侧数据线D3’的信号变化为：L64+→L255+，B子像素右侧数据线D4’的信号变化为：L64+→L0+，此时，左右数据线D3’、D4’对B像素的耦合（coupling）的量不相同，左侧数据线D3’对B子像素耦合的上拉作用更大，使B子像素的电压向上拉（即左侧上拉的量大于右侧下拉的量），A处B子像素变亮。
在B处，R子像素保持L64+的灰阶电压，R像素左侧数据线D1’的信号变化为：L64→L0+，R子像素右侧数据线D2’信号变化为：L64-→L0-，此时，左右数据线D1’、D2’对R子像素的耦合（coupling）的量相同，使得位于A处R子像素的电压保持不变。
在B处，G子像素保持L64-的灰阶电压，G子像素左侧数据线D2’的信号变化为：L64-→L0-，G子像素右侧数据线D3’的信号变化为：L64+→L255+，此时，左右数据线D2’、D3’对G子像素均有电压上拉趋势，使得位于A处G子像素变亮。
在B处，B子像素保持L64+的灰阶电压，B子像素左侧数据线D3’的信号变化为：L64+→L255+，B子像素右侧数据线D4’的信号变化为：L64+→L0+，此时，左右数据线D3’、D4’对B像素的耦合（coupling）的量不相同，左侧数据线D3’对B子像素耦合的上拉作用更大，使B子像素的电压向上拉，A处B子像素变暗。
需要说明的是，图2中“D_L”指的是数据线的左侧，“D_R”指的是数据线的右侧。
因此，当像素结构以栅极（gate）开启顺序为：G1’、 G2’、G3’...Gn’的方式进行驱动时，RGB像素被数据线（dataline）耦合（couple）的程度不同使画面出现了区块颜色变化。
本实施例提供一种液晶显示面板，其包括可实现三次翻转的像素结构，该像素结构的任一条数据线可以通过跨线的方式同时驱动三种不同颜色且位于不同列的子像素，由原有的充电顺序R（红色子像素）→G（绿色子像素）改为R（红色子像素）→G（绿色子像素）→B（蓝色子像素），以保证子像素充电的均一性，还能使子像素被数据线耦接之后亮暗交错排列，均衡了显示的亮度，从而有效地解决了颜色串扰的问题，进而提高了液晶显示面板的品质。
图3为本申请实施例提供的像素结构的结构示意图。
如图3所示，所述像素结构100包括像素矩阵10，由两个以上子像素组成，位于同一行的三个相邻子像素的颜色相异，位于同一列的所有子像素的颜色相同。所述子像素包括不同颜色的第一子像素101、第二子像素102、第三子像素103，所述第一子像素101为红色像素，所述第二子像素102为绿色子像素，所述第三子像素103为蓝色子像素。
所述像素结构100还包括m条彼此平行的数据线D1、D2、D3、……（Dm-2）、（Dm-1）、Dm和n条彼此平行的扫描线G1、G2、G3、……（Gn-2）、（Gn-1）、Gn，数据线沿竖直方向延伸，在水平方向上间隔排列，每一数据线位于相邻的两列子像素之间。与所述数据线垂直的扫描线沿水平方向延伸，在竖直方向上间隔排列，每一扫描线位于相邻的两行子像素之间。
本实施例中，多个第一子像素101矩阵排成第一列像素，且位于第一数据线D1的左侧，多个第二子像素102矩阵排列成第二列像素，且位于第二数据线D2的左侧，多个第三子像素103矩阵排列成第三列像素，且位于第三数据线D3的左侧，多个第一子像素101矩阵排成第四列像素，且位于第四数据线D4的左侧……，简单地来说，同一列的所有子像素的颜色相同，且三个颜色相异的子像素在行的方向上按照第一子像素101、第二子像素102、第三子像素103的顺序循环排列，或者按照第二子像素102、第三子像素103、第一子像素101的顺序循环排列，或者按照第三子像素103、第一子像素101、第二子像素102的顺序循环排列。
本实施例中，每一数据线依次连接至少一像素组110，每一像素组110包括颜色相异的三个子像素，同一像素组110中的三个子像素位于所述像素矩阵10的相邻三行内。
结合图3所示，所述第一子像素101位于第一数据线D1的左侧，所述第二子像素102位于第一数据线D1的右侧，所述第三子像素103也位于第一数据线D1的右侧，且该第一数据线D1位于彼此相邻的所述第一子像素101与所述第二子像素102之间。
本实施例中，第一数据线D1连接两个第一像素组110a。在每一第一像素组110a中，第一数据线D1先连接第一列像素的第一子像素101，再连接第二列像素的第二子像素102，最后连接第三列像素的第三子像素103。总的来说，第一数据线D1连接至少一个第一像素组110a，在每一第一像素组110a中，第一数据线D1按照第一子像素101、第二子像素102及第三子像素103的顺序依次连接三个颜色不同的子像素。
所述第二子像素102位于第二数据线D2的左侧，所述第三子像素103位于第二数据线D2的右侧，所述第一子像素101也位于第二数据线D2的右侧，且该第二数据线D2位于彼此相邻的所述第二子像素102与所述第三子像素103之间。
本实施例中，第二数据线D2连接两个第二像素组110b。在每一第二像素组110b中，第二数据线D2先连接第二列像素的第二子像素102，再连接第三列像素的第三子像素103，最后连接第四列像素的第一子像素101。总的来说，第二数据线D2连接至少一个第二像素组110b，在每一第二像素组110b中，第二数据线D2按照第二子像素102、第三子像素103及第一子像素101的顺序依次连接三个颜色不同的子像素。
所述第三子像素103位于第三数据线D3的左侧，所述第一子像素101位于第三数据线D3的右侧，所述第二子像素102也位于第三数据线D3的右侧，且该第三数据线D3位于彼此相邻的所述第三子像素103与所述第一子像素101之间。
本实施例中，第三数据线D3连接两个第三像素组110c。在每一第三像素组110c中，第三数据线D3先连接第三列像素的第三子像素103，再连接第四列像素的第一子像素101，最后连接第五列像素的第二子像素102。总的来说，第三数据线D3连接至少一个第三像素组110c，在每一第三像素组110c中，第三数据线D3按照第三子像素103、第一子像素101及第二子像素102的顺序依次连接三个颜色不同的子像素。
在一个像素组中，三种颜色的所述子像素的数量相等。即，在一个像素组中，所述第一子像素101、所述第二子像素102及所述第三子像素103的数量均相等。
图4为本申请实施例提供的像素结构的驱动示意图。
如图4所示，本实施例中，所述像素结构100还包括第一驱动单元20和第二驱动单元30。所述第一驱动单元20为源极驱动器，所述第二驱动单元30为栅极驱动器，如GOA驱动电路。
所述第一驱动单元20电连接至所述数据线，并逐列向多条数据线输入灰阶电压。所述灰阶电压包括正极性灰阶电压（+）和负极性灰阶电压（-）。所述第二驱动单元30电连接至所述扫描线，并逐行向多条扫描线输入扫描信号。当所述第一驱动单元20向一数据线输入正极性灰阶电压时，与该数据线连接的像素组为亮态。当所述第一驱动单元20向一数据线输入负极性灰阶电压时，与该数据线连接的像素组为暗态。
本实施例中，所述第一驱动单元20向所述数据线输入灰阶电压和所述第二驱动单元30逐行地向所述扫描线G1、G2、G3、……（Gn-2）、（Gn-1）、Gn输入所述扫描信号时，一数据线连接的像素组的灰阶电压的极性相同，位于该数据线两侧的数据线连接的像素组的灰阶电压的极性与该数据线连接的像素组的灰阶电压的极性相反。
所述像素结构100还包括薄膜晶体管40，设于每一子像素的像素区内，其栅极电连接至对应的扫描线，其源极电连接至对应的数据线，其漏极电连接至对应的子像素。
图5为本申请实施例提供的阵列基板的结构示意图；图6为本申请实施例提供的像素结构的平面图。
如图5所示，本实施例提供的显示面板，包括具有多个薄膜晶体管40的阵列基板，该阵列基板从下至上依次包括基底51、栅极层52、栅极绝缘层53、第一接触层54、第二接触层55、源漏极层56、绝缘层57以及像素电极58。
具体的，所述栅极层52设于所述基底51上。所述栅极绝缘层53覆盖所述栅极层52，且延伸至所述基底51表面。所述有源层54设于所述栅极绝缘层53上，且正对着所述栅极层52，其中所述栅极层52形成显示面板的扫描线。所述第二接触层55设于所述第一接触层54上，且位于所述第一接触层54的两侧，使得所述第二接触层55具有一第一通孔61，其中所述第二接触层55为半导体层，所述第一接触层54与所述第二接触层形成有源层。所述源漏极层56设于所述第二接触层55上，且从所述第二接触层55表面延伸至所述栅极绝缘层53表面，所述源漏极层56包括位于左侧的源极和位于右侧的漏极，且通过一第二通孔62间隔设置，其中，所述源漏极层56形成显示面板的数据线。所述绝缘层57设于所述源漏极层56和所述栅极绝缘层53上，且填充所述第一通孔61和所述第二通孔62，所述绝缘层57还包括一第三通孔63，所述第三通孔63贯穿至所述漏极。所述像素电极58设于所述绝缘层57上，且通过所述第三通孔63连接至所述漏极，其中该像素电极58为每一子像素的公共电极，结合图6所示，该公共电极通过跨线的方式连接到数据线（漏极走线）上，也就是说该公共电极直接跨线到相邻子像素的薄膜晶体管40（TFT）的数据线（data）上，对于同一条数据线而言，在不改变数据线绕线的情况下，实现了跨列驱动。
本实施例中，连接同一条数据线的子像素的充电路径可以为：R→G→B→R→G→B，或者G→B→R→G→B→R，或者B→R→G→B→R→G。
下面将对本实施例所述像素结构100的工作状态进行详细的介绍。
所述第二驱动单元30（GOA驱动电路）以60Hz的动作顺序输出扫描信号以驱动多条扫描线（Gate）。即GOA的驱动顺序为：GOA：CK1→CK2→CK3→CK4→CK5→CK6……→CKn。Gate开启顺序：G1→G2→G3→G4→G5→G6……→Gn。
结合图4所示，在工作中，向数据线D1、D2、D3、……（Dm-2）、（Dm-1）、Dm输入数据信号，向扫描线G1、G2、G3、……（Gn-2）、（Gn-1）、Gn逐行输入扫描信号CK1、CK2、CK3……CKn，即依次打开与G1、G2、G3、……（Gn-2）、（Gn-1）、Gn连接的薄膜晶体管。
图7为图4中数据线D1、D2、D3及D4的时序图。
如图4及图7所示，当液晶显示面板显示L64白色画面为背景，L255蓝色图框时，一条数据线向至少一像素组传输信号。
当第一数据线D1接入正极性灰阶电压时，D1的信号变化为：L64+→L0+→L255+，第一子像素101、第二子像素102及第三子像素103均保持在L64+的灰阶电压。
当第二数据线D2接入负极性灰阶电压时，D2的信号变化为：L64-→L255-→L0-，第二子像素102、第三子像素103及第一子像素101均保持L64-的灰阶电压。
当第三数据线D3接入正极性灰阶电压时，D3的信号变化为：L64+→L0+→L255+，第三子像素103、第一子像素101及第二子像素102保持L64+的灰阶电压。
当第四数据线D4接入负极性灰阶电压时，D4的信号变化为：L64-→L0-→L255-，第一子像素101、第二子像素102及第三子像素103均保持L64-的灰阶电压。
当数据线D1、D2、D3、D4接入的灰阶电压极性为↓↑↑↓时，第三子像素103的亮暗变化的过程为：B-亮/暗/暗/亮……B+暗/亮/亮/暗……。
当数据线D1、D2、D3接入的灰阶电压极性为↓↑↓时，第一子像素101的亮暗变化的过程为：R-不变/亮/暗/亮……R+不变/暗/亮/暗……。
本实施例提供一种液晶显示面板，包括可实现三次像素翻转的像素结构，该像素结构的任一条数据线可以通过跨线的方式同时驱动三种颜色不同且位于不同列的子像素，由原有的充电顺序R（红色子像素）→G（绿色子像素）改为R（红色子像素）→G（绿色子像素）→B（蓝色子像素），以保证子像素充电的均一性，还能使子像素被数据线耦接之后亮暗交错排列，均衡了显示的亮度，从而有效地解决了颜色串扰的问题，进而提高了液晶显示面板的品质。
本实施例还提供一种显示装置，包括前文所述的液晶显示面板及背光模块（图未示），所述液晶显示面板配置于该背光模块的该出光面。该显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在其他实施例中，一像素组包括第一子像素、第二子像素及第三子像素。其中，在一像素组中，第一子像素位于一数据线的第一侧，第二子像素位于该数据线的第二侧，第三子像素位于该数据线的第一侧，其该数据线位于彼此相邻的所述第一子像素与所述第二子像素之间。或者，在一像素组中，第一子像素位于一数据线的第二侧，第二子像素位于该数据线的第一侧，第三子像素位于该数据线的第二侧，且该数据线位于彼此相邻的第二子像素与第三子像素之间。或者在一像素组中，第一子像素位于一数据线的第一侧，第二子像素位于该数据线的第二侧，第三子像素位于该数据线的第二侧，该数据线位于彼此相邻的所述第一子像素与所述第三子像素之间。需要说明的是，第一侧、第二侧是相对于某一数据线的两侧而言，本领域的技术人员可根据实际情况进行设定，只要使得一条数据线可以将相邻三列且位于相邻三行的不同颜色的像素连接起来即可，在此不一一赘述。
以上对本申请实施例所提供的一种显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种液晶显示面板，其包括：
    像素矩阵，由两个以上子像素组成；位于同一行的三个相邻子像素的颜色相异，位于同一列的所有子像素的颜色相同；
    两条以上彼此平行的数据线，每一数据线位于相邻的两列子像素之间；以及
    两条以上彼此平行的扫描线，每一扫描线位于相邻的两行子像素之间；
    其中，每一数据线依次连接至少一像素组，
    每一像素组包括颜色相异的三个子像素，分别位于一数据线两侧；
    在一像素组中，每一数据线按顺序依次连接至三个子像素。
  2. 根据权利要求1所述的液晶显示面板，其中，
    同一像素组中的三个子像素位于所述像素矩阵的相邻三行内。
  3. 根据权利要求1所述的液晶显示面板，其中，
    一像素组包括：
    第一子像素，位于一数据线的第一侧；
    第二子像素，位于该数据线的第二侧；
    第三子像素，位于该数据线的第一侧或第二侧；
    该数据线位于彼此相邻的所述第一子像素与所述第二子像素之间。
  4. 根据权利要求1所述的液晶显示面板，其中，
    一像素组包括：
    第一子像素，位于一数据线的第一侧或第二侧；
    第二子像素，位于该数据线的第一侧；
    第三子像素，位于该数据线的第二侧；
    该数据线位于彼此相邻的第二子像素与第三子像素之间。
  5. 根据权利要求1所述的液晶显示面板，其中，
    一像素组包括：
    第一子像素，位于一数据线的第一侧；
    第二子像素，位于该数据线的第一侧或第二侧；
    第三子像素，位于该数据线的第二侧；
    该数据线位于彼此相邻的所述第一子像素与所述第三子像素之间。
  6. 根据权利要求1所述的液晶显示面板，其还包括：
    第一驱动单元，电连接至所述数据线，并向多条数据线输入灰阶电压；
    第二驱动单元，电连接至所述扫描线，并向多条扫描线输入扫描信号。
  7. 根据权利要求6所述的液晶显示面板，其中，
    所述第一驱动单元向所述数据线输入灰阶电压时，一数据线连接的像素组的灰阶电压的极性相同，位于该数据线两侧的数据线连接的像素组的灰阶电压的极性与该数据线连接的像素组的灰阶电压的极性相反。
  8. 根据权利要求1所述的液晶显示面板，其中，
    三种颜色的所述子像素的数量相等。
  9. 根据权利要求1所述的液晶显示面板，其还包括：
    薄膜晶体管，其栅极电连接至对应的扫描线，其源极电连接至对应的数据线，其漏极电连接至对应的子像素。
  10. 一种显示装置，其中，包括如权利要求1所述的液晶显示面板；
    背光模块，具有一出光面，其中所述液晶显示面板配置于该背光模块的该出光面。
  11. 根据权利要求10所述的显示装置，其中，
    同一像素组中的三个子像素位于所述像素矩阵的相邻三行内。
  12. 根据权利要求10所述的显示装置，其中，
    一像素组包括：
    第一子像素，位于一数据线的第一侧；
    第二子像素，位于该数据线的第二侧；
    第三子像素，位于该数据线的第一侧或第二侧；
    该数据线位于彼此相邻的所述第一子像素与所述第二子像素之间。
  13. 根据权利要求10所述的显示装置，其中，
    一像素组包括：
    第一子像素，位于一数据线的第一侧或第二侧；
    第二子像素，位于该数据线的第一侧；
    第三子像素，位于该数据线的第二侧；
    该数据线位于彼此相邻的第二子像素与第三子像素之间。
  14. 根据权利要求10所述的显示装置，其中，
    一像素组包括：
    第一子像素，位于一数据线的第一侧；
    第二子像素，位于该数据线的第一侧或第二侧；
    第三子像素，位于该数据线的第二侧；
    该数据线位于彼此相邻的所述第一子像素与所述第三子像素之间。
  15. 根据权利要求10所述的显示装置，其还包括：
    第一驱动单元，电连接至所述数据线，并向多条数据线输入灰阶电压；
    第二驱动单元，电连接至所述扫描线，并向多条扫描线输入扫描信号。
  16. 根据权利要求15所述的显示装置，其中，
    所述第一驱动单元向所述数据线输入灰阶电压时，一数据线连接的像素组的灰阶电压的极性相同，位于该数据线两侧的数据线连接的像素组的灰阶电压的极性与该数据线连接的像素组的灰阶电压的极性相反。
  17. 根据权利要求16所述的显示装置，其中，
    当所述第一驱动单元向一数据线输入正极性灰阶电压时，与该数据线连接的像素组为亮态。
  18. 根据权利要求16所述的显示装置，其中，
    当所述第一驱动单元向一数据线输入负极性灰阶电压时，与该数据线连接的像素组为暗态。
  19. 根据权利要求10所述的显示装置，其中，
    三种颜色的所述子像素的数量相等。
  20. 根据权利要求10所述的显示装置，其中，还包括：
    薄膜晶体管，其栅极电连接至对应的扫描线，其源极电连接至对应的数据线，其漏极电连接至对应的子像素。
PCT/CN2021/108099 2021-07-13 2021-07-23 液晶显示面板及显示装置 WO2023283994A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/438,658 US11899325B2 (en) 2021-07-13 2021-07-23 Liquid crystal display panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110787207.8 2021-07-13
CN202110787207.8A CN113552752B (zh) 2021-07-13 2021-07-13 液晶显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2023283994A1 true WO2023283994A1 (zh) 2023-01-19

Family

ID=78131629

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/108099 WO2023283994A1 (zh) 2021-07-13 2021-07-23 液晶显示面板及显示装置

Country Status (3)

Country Link
US (1) US11899325B2 (zh)
CN (1) CN113552752B (zh)
WO (1) WO2023283994A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113936619B (zh) * 2021-10-28 2022-08-23 深圳市华星光电半导体显示技术有限公司 液晶显示面板及其驱动方法、终端
CN114114766B (zh) * 2021-11-30 2022-09-27 Tcl华星光电技术有限公司 液晶显示面板及其驱动方法、显示装置
CN114944110A (zh) * 2022-05-25 2022-08-26 Tcl华星光电技术有限公司 显示面板及显示终端

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101566744A (zh) * 2009-06-08 2009-10-28 友达光电股份有限公司 液晶显示器及其液晶显示面板
KR20130121388A (ko) * 2012-04-27 2013-11-06 엘지디스플레이 주식회사 액정표시장치
CN105788549A (zh) * 2016-04-22 2016-07-20 昆山龙腾光电有限公司 像素驱动结构、驱动方法及显示装置
CN106932988A (zh) * 2017-05-09 2017-07-07 京东方科技集团股份有限公司 一种像素结构、液晶显示面板及液晶显示装置
CN106991953A (zh) * 2017-05-11 2017-07-28 惠科股份有限公司 像素驱动电路、驱动方法及显示装置
CN109709735A (zh) * 2019-03-07 2019-05-03 昆山龙腾光电有限公司 像素排列结构、显示面板及其制作方法
KR20200050871A (ko) * 2018-11-02 2020-05-12 엘지디스플레이 주식회사 액정 표시 장치 및 그 구동 방식
CN112086077A (zh) * 2020-09-17 2020-12-15 Tcl华星光电技术有限公司 一种阵列基板及显示面板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000020918A1 (fr) * 1998-10-07 2000-04-13 Seiko Epson Corporation Dispositif a cristaux liquides et appareil electronique
US20040246280A1 (en) * 2003-06-06 2004-12-09 Credelle Thomas Lloyd Image degradation correction in novel liquid crystal displays
JP2005208522A (ja) * 2004-01-26 2005-08-04 Sharp Corp 表示装置
KR20080009889A (ko) * 2006-07-25 2008-01-30 삼성전자주식회사 액정 표시 장치
TWI481937B (zh) * 2012-08-27 2015-04-21 Au Optronics Corp 顯示面板
CN103969900B (zh) * 2013-01-25 2017-07-21 乐金显示有限公司 液晶显示装置及其驱动方法
CN103235431B (zh) * 2013-04-03 2015-06-17 深圳市华星光电技术有限公司 液晶显示面板及其驱动方法
KR102349500B1 (ko) * 2015-04-21 2022-01-12 엘지디스플레이 주식회사 액정표시장치
KR20180014337A (ko) * 2016-07-29 2018-02-08 엘지디스플레이 주식회사 액정표시장치
CN110208995B (zh) * 2019-06-29 2022-03-25 上海中航光电子有限公司 一种阵列基板、显示面板及显示装置
CN111123598A (zh) * 2020-01-19 2020-05-08 京东方科技集团股份有限公司 一种阵列基板及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101566744A (zh) * 2009-06-08 2009-10-28 友达光电股份有限公司 液晶显示器及其液晶显示面板
KR20130121388A (ko) * 2012-04-27 2013-11-06 엘지디스플레이 주식회사 액정표시장치
CN105788549A (zh) * 2016-04-22 2016-07-20 昆山龙腾光电有限公司 像素驱动结构、驱动方法及显示装置
CN106932988A (zh) * 2017-05-09 2017-07-07 京东方科技集团股份有限公司 一种像素结构、液晶显示面板及液晶显示装置
CN106991953A (zh) * 2017-05-11 2017-07-28 惠科股份有限公司 像素驱动电路、驱动方法及显示装置
KR20200050871A (ko) * 2018-11-02 2020-05-12 엘지디스플레이 주식회사 액정 표시 장치 및 그 구동 방식
CN109709735A (zh) * 2019-03-07 2019-05-03 昆山龙腾光电有限公司 像素排列结构、显示面板及其制作方法
CN112086077A (zh) * 2020-09-17 2020-12-15 Tcl华星光电技术有限公司 一种阵列基板及显示面板

Also Published As

Publication number Publication date
CN113552752B (zh) 2022-09-09
US11899325B2 (en) 2024-02-13
US20230205025A1 (en) 2023-06-29
CN113552752A (zh) 2021-10-26

Similar Documents

Publication Publication Date Title
KR100679521B1 (ko) 액정표시장치 제조방법
KR101204365B1 (ko) 액정 표시 패널 및 그 제조 방법
WO2018121307A1 (zh) 液晶显示器件
WO2023283994A1 (zh) 液晶显示面板及显示装置
KR102279353B1 (ko) 표시패널
US20160231605A1 (en) Rgbw tft lcd having reduced horizontal crosstalk
WO2018121304A1 (zh) 液晶显示器
WO2013159504A1 (zh) 液晶显示装置的母板和液晶显示装置检测方法
WO2016201724A1 (zh) 像素结构及液晶显示面板
US20080117348A1 (en) Liquid crystal display with sub-pixel zones and method for driving same
JPWO2007088656A1 (ja) 表示装置
CN1885399A (zh) 液晶显示装置及其驱动方法
WO2020237760A1 (zh) 像素驱动电路及像素驱动方法
WO2020107505A1 (zh) 显示驱动方法及液晶显示装置
WO2019037503A1 (zh) 像素结构及其制作方法、驱动方法、显示装置
WO2023019629A1 (zh) 显示面板及移动终端
KR101067555B1 (ko) 액정표시장치
US8188951B2 (en) Chip on glass type display device
US20090251403A1 (en) Liquid crystal display panel
CN114283759A (zh) 像素结构、像素结构的驱动方法和显示面板
WO2020098600A1 (zh) 显示基板、显示面板及其驱动方法
US9715859B2 (en) LCD panel of dot inversion mode
US11922895B2 (en) Liquid crystal display panel, driving method, and terminal thereof
US20180196299A1 (en) Pixel structure, liquid crystal display panel and the driving method thereof
CN114637147B (zh) 显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21949774

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21949774

Country of ref document: EP

Kind code of ref document: A1