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WO2023125677A1 - 独显插帧电路、方法、装置、芯片、电子设备及介质 - Google Patents

独显插帧电路、方法、装置、芯片、电子设备及介质 Download PDF

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Publication number
WO2023125677A1
WO2023125677A1 PCT/CN2022/142886 CN2022142886W WO2023125677A1 WO 2023125677 A1 WO2023125677 A1 WO 2023125677A1 CN 2022142886 W CN2022142886 W CN 2022142886W WO 2023125677 A1 WO2023125677 A1 WO 2023125677A1
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WO
WIPO (PCT)
Prior art keywords
data
chip
frame rate
independent display
frame
Prior art date
Application number
PCT/CN2022/142886
Other languages
English (en)
French (fr)
Inventor
张彪
熊建清
Original Assignee
维沃移动通信有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 维沃移动通信有限公司 filed Critical 维沃移动通信有限公司
Priority to EP22914929.9A priority Critical patent/EP4459978A1/en
Publication of WO2023125677A1 publication Critical patent/WO2023125677A1/zh
Priority to US18/756,538 priority patent/US20240345790A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005—Adapting incoming signals to the display format of the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication

Definitions

  • the application belongs to the technical field of communication, and in particular relates to an independent display frame insertion circuit, method, device, chip, electronic equipment and medium.
  • the purpose of the embodiments of the present application is to provide a circuit, method, device, chip, electronic device and medium for independent display frame insertion.
  • the embodiment of the present application provides an independent display frame insertion circuit
  • the independent display frame insertion circuit includes a system-on-chip and an independent display chip.
  • the system level chip is used to generate the first data based on the first content to be displayed, and send the first data to the independent display chip when receiving the target display frame rate synchronization TE signal sent by the independent display chip, the The frame rate of the first data is lower than the frame rate of the first content; the independent display chip is used to interpolate the first data to obtain the second data, and the frame rate of the second data is greater than or equal to the frame rate of the first content .
  • an embodiment of the present application provides a frame insertion method for an independent display, the method includes: generating first data based on the first content to be displayed by the electronic device through a system-on-a-chip in the electronic device, the The frame rate of the first data is lower than the frame rate of the first content; when the system-level chip receives the target display frame rate synchronous TE signal sent by the independent display chip in the electronic device, the system-level chip sends the first display to the independent display chip through the system-level chip One data; through the independent display chip, perform frame interpolation processing on the first data to obtain second data, the frame rate of the second data is greater than or equal to the frame rate of the first content.
  • the embodiment of the present application provides a frame insertion device for an independent display
  • the frame insertion device for an independent display includes: a generation module, a sending module, and a processing module.
  • the generating module is configured to generate the first data based on the first content to be displayed by the electronic device through the SoC in the electronic device, and the frame rate of the first data is lower than the frame rate of the first content.
  • the sending module is configured to send the first data to the independent display chip through the system-on-chip when the system-on-chip receives the target display frame rate synchronous TE signal sent by the independent display chip in the electronic device.
  • the processing module is used to perform frame interpolation processing on the first data through the independent display chip to obtain the second data, and the frame rate of the second data is greater than or equal to the frame rate of the first content.
  • the embodiment of the present application provides a system-on-a-chip
  • the system-on-a-chip includes a processor and a communication interface
  • the communication interface is coupled to the processor
  • the processor is used to display information based on the electronic device
  • the first content generates first data
  • the frame rate of the first data is lower than the frame rate of the first content
  • the communication interface is used to receive the target display frame rate synchronous TE signal sent by the independent display chip in the electronic device Next, send the first data to the independent display chip.
  • the embodiment of the present application provides an independent display chip, the independent display chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the communication interface is used to communicate with the electronic device
  • the system-on-chip sends the target display frame rate synchronous TE signal, and receives the first data sent by the system-on-chip.
  • the first data is the data generated by the system-on-chip based on the first content to be displayed by the electronic device.
  • the frame of the first data The frame rate of the second data is lower than the frame rate of the first content, and the processor is used to perform frame interpolation processing on the first data to obtain the second data, and the frame rate of the second data is greater than or equal to the frame rate of the first content.
  • the embodiment of the present application provides an electronic device, the electronic device includes the independent display frame insertion circuit as described in the first aspect, or includes the system-on-a-chip as described in the fourth aspect and the system-on-chip as described in the fifth aspect independent display chip.
  • the embodiment of the present application provides an electronic device, the electronic device includes a processor and a memory, the memory stores programs or instructions that can run on the processor, and the programs or instructions are processed by the When the controller is executed, the electronic device implements the steps of the method described in the second aspect.
  • the embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the electronic device realizes the electronic device as described in the second aspect. method steps.
  • an embodiment of the present application provides a computer program product, where the program product is stored in a storage medium, and the program product is executed by at least one processor so that an electronic device implements the method as described in the second aspect.
  • the system-on-a-chip can generate the first data based on the first content to be displayed, and the frame rate of the first data is lower than the frame rate of the first content.
  • the system-on-a-chip can send the first data to the independent display chip, so that the independent display chip performs frame insertion processing on the first data to obtain the second data, and the frame rate of the second data is greater than or Equal to the frame rate of the first content.
  • the independent display chip can insert frames for the first data processing to obtain the second data, so as to increase the frame rate of the content to be displayed by the electronic device or maintain the frame rate of the content to be displayed by the electronic device.
  • the output frame rate of the system-level chip the power consumption of the system-level chip is avoided. The problem that greatly affects the frame insertion function of the independent display, thereby improving the fluency of the picture displayed by the electronic device.
  • FIG. 1 is one of the schematic diagrams of an independent display frame insertion method provided by an embodiment of the present application
  • Fig. 2 is the second schematic diagram of an independent display frame insertion method provided by the embodiment of the present application.
  • Fig. 3 is a schematic structural diagram of an independent display frame insertion circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an independent display chip provided by an embodiment of the present application.
  • Fig. 5 is a signal interaction diagram provided by the embodiment of the present application when the independent display frame insertion function is not enabled
  • Fig. 6 is a signal interaction diagram when the independent display frame insertion function is enabled provided by the embodiment of the present application.
  • Fig. 7 is a flow chart of a method for interpolating frames of an independent display provided by an embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of an independent display frame insertion device provided by an embodiment of the present application.
  • FIG. 9 is one of the schematic diagrams of the hardware structure of an electronic device provided in the embodiment of the present application.
  • FIG. 10 is a second schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present application.
  • some electronic devices can support high frame rate display of video, game and other images.
  • the power consumption of electronic devices is large, which affects the display of electronic devices.
  • frame rate which leads to low fluency of the picture displayed by the electronic device.
  • the output frame rate of the System on a Chip can be reduced, and then the frame can be inserted to the target frame rate ( greater than or equal to the frame rate of the currently displayed content), so that while increasing or maintaining the frame rate of the content displayed by the electronic device, the power consumption of the SoC is reduced to stabilize the output frame rate of the SoC, thereby improving the picture displayed by the electronic device fluency.
  • SoC System on a Chip
  • the display frame rate of the Liquid Crystal Display Module is 90fps
  • the frame rate of the film source that is, the frame rate of the content to be displayed by the electronic device
  • the LCM sends a 90Hz TE signal to the independent display chip for frame synchronization
  • the independent display chip adjusts the TE signal to 45Hz and sends it to the SoC
  • the SoC processes the generated frame data from 60fps 45fps is transmitted to the independent display chip, so that the independent display chip inserts the frame data of 45fps into 90fps frame data, and transmits it to the LCM, so that the LCM displays the content corresponding to the 90fps frame data.
  • the power consumption of the SoC is reduced to stabilize the output frame rate of the SoC, thereby improving the smoothness of the
  • the display frame rate of the LCM is 90fps
  • the frame rate of the film source that is, the frame rate of the content to be displayed by the electronic device
  • the frame rate of the content to be displayed by the electronic device is maintained
  • the LCM sends a 90Hz TE signal to the independent display chip for frame synchronization.
  • the independent display chip adjusts the TE signal to 30Hz and sends it to the SoC.
  • the SoC processes the generated frame data from 60fps to 30fps and passes it to the independent display chip ( Or the independent display chip adjusts the TE signal to 45Hz and sends it to the SoC, and the SoC processes the generated frame data from 60fps to 45fps and transmits it to the independent display chip, which can be adjusted according to the requirements of power consumption and effect), so that the independent display chip will
  • the 30fps frame data is interpolated into the 60fps frame data and passed to the LCM, so that the LCM displays the content corresponding to the 60fps frame data. In this way, while maintaining the frame rate of the content to be displayed by the electronic device, the power consumption of the SoC is reduced to stabilize the output frame rate of the SoC, thereby improving the smoothness of the picture displayed by the electronic device.
  • FIG. 3 shows a schematic structural diagram of the independent display frame insertion circuit provided in the embodiment of the present application.
  • the independent display frame insertion circuit provided in the embodiment of the present application may include a system-on-a-chip and an independent display chip.
  • the SoC is used to generate the first data based on the first content to be displayed, and send the first data to the independent display chip when receiving the target TE signal sent by the independent display chip, and the frame of the first data rate is less than the frame rate of the first content.
  • the independent display chip is used to perform frame interpolation processing on the first data to obtain the second data, and the frame rate of the second data is greater than or equal to the frame rate of the first content.
  • the independent display chip can bring display enhancement effects such as higher frame rate, higher resolution, color saturation and contrast.
  • display enhancement effects such as higher frame rate, higher resolution, color saturation and contrast.
  • some electronic devices support high frame rate (such as 120/90Hz)
  • the actual displayed content does not achieve a real high frame rate, but simply relies on the image processing unit (Graphics Processing Unit, GPU) or display driver integrated circuit for simple processing.
  • the screen is repeated, and the actual experience is still a low frame rate.
  • the independent display chip can use the two frames of data before and after to calculate the motion characteristics of the picture, simulate and generate the middle picture, so as to realize dynamic supplementary frames, so that the content displayed by the electronic device can achieve a real high frame rate.
  • FIG 4 shows a schematic diagram of the architecture of the independent display chip.
  • the independent display chip has two display serial interfaces (Display Serial Interface, DSI), and realizes data transmission through the mobile industry processor interface (Mobile Industry Processor Interface, MIPI) protocol. Can work in dual MIPI mode and single MIPI mode. In the dual-channel mode, the display content can be divided into a user interface (UI) layer and a multimedia video layer. The UI layer and the video layer are respectively transmitted to the independent display chip through the DSI interface, and respectively passed through each functional module inside the independent display chip.
  • UI user interface
  • MIPI Mobile Industry Processor Interface
  • the frame data is synthesized, and after necessary color processing, it is passed to the display serial interface-transmitter (DSI-Transmit, DSI-Tx) 0 Display Module (Liquid Crystal Display Module, LCM).
  • the display content can be synthesized by the SoC and sent to the independent display chip through DSI 0, so that the independent display chip can perform corresponding processing and then pass it to the display module.
  • the content captured by the camera in the electronic device is transmitted to the SoC through the camera serial interface (CSI) 0, and the SoC transmits the captured content to the independent display chip through the DSI interface, and the independent display chip is processed by the chip
  • the CSI Tx0 and DSI Tx0 interfaces transmit the processed content to the SoC and the display module respectively
  • the SoC can store the processed content
  • the display module can preview and display the processed content in real time.
  • each interface is as follows:
  • DSI 0 output UI or video content
  • DSI 1 output UI or video content
  • DSI Rx1 Receive the content delivered by DSI 1;
  • CSI 0 Receive the content captured by the camera
  • CSI 1 Receive the content processed by the independent display chip
  • DSI Tx0 output display content to the display
  • CSI Tx0 Output the content processed by the independent display chip to SoC;
  • TE display frame rate synchronization signal
  • MIPI a signal transmission protocol
  • GPIO General-Purpose Input/Output
  • Kernel module processing module for internal functions of the independent display chip (such as frame insertion, super resolution, noise reduction, color enhancement, UI and video content overlay, etc.);
  • PMIC Power Management Integrated Circuit
  • Battery the battery of an electronic device
  • SoC system-level chip, including processor core, digital signal processor, storage module, communication interface, power management, RF front-end and other modules.
  • FIG. 5 shows a signal interaction diagram when the electronic device does not enable the independent display frame insertion function.
  • the frame rate of the display screen is 90fps.
  • the LCM sends a 90Hz TE signal to the independent display chip for frame synchronization, and the independent display chip also generates a 90Hz TE signal synchronously and sends it to the SoC.
  • the GPU Only 60fps, the GPU will generate 60fps frame data and pass it to the independent display chip, and then the independent display chip will directly pass it to the display screen.
  • the real content displayed on the display screen is only 60fps, which cannot reach the 90fps of the display screen.
  • FIG. 6 shows a signal interaction diagram when the electronic device enables the independent display frame insertion function.
  • the frame rate of the display screen is 90fps.
  • the LCM sends a 90Hz TE signal to the independent display chip for frame synchronization, and the independent display chip synchronously generates a 60Hz TE signal Send it to the SoC, the SoC will generate 60fps frame data and pass it to the independent display chip, and then the independent display chip will insert the 60fps frame data into 90fps, and pass it to the display screen, at this time, the content displayed on the display screen can reach the real 90fps.
  • the above-mentioned first content may be a video image, a game image, or the like.
  • the details can be determined according to actual usage requirements, and are not limited in this embodiment of the application.
  • the SoC may perform frame dropping processing on the first content, or perform any other possible processing on the first content, so as to obtain the first data.
  • the system-on-a-chip is specifically configured to perform frame dropping processing on the first content based on a preset frame rate, to obtain first data at a preset frame rate.
  • the preset frame rate is lower than the frame rate of the first content.
  • the aforementioned preset frame rate may be the default of the electronic device, or may be preset by the user. The details can be determined according to actual usage requirements, and are not limited in this embodiment of the application.
  • the system-on-a-chip will discard 1fps of data every time it processes 3fps of data.
  • the data is at 45fps.
  • the system-on-a-chip will discard 1fps of data every time it processes 1fps of data.
  • the lost frame of data does not need to be processed, and the system-on-chip actually processes The data is 30fps.
  • the system-level chip can perform frame-drop processing on the first content based on the preset frame rate to obtain the first data of the preset frame rate, that is, reduce the output frame rate of the system-level chip. In this way, the system-level chip can be reduced.
  • the power consumption of the chip is to stabilize the output frame rate of the system-level chip, avoiding the problem that the high power consumption of the system-level chip affects the frame insertion function of the independent display, thereby improving the fluency of the picture displayed by the electronic device.
  • the foregoing target TE signal may be one TE signal, or may include multiple TE signals.
  • the details can be determined according to actual usage requirements, and are not limited in this embodiment of the application.
  • the system-on-a-chip is further configured to send a first instruction to the independent graphics chip, and the first instruction includes a preset frame rate.
  • the independent display chip is also used to generate a target TE signal and send the target TE signal to the system-on-a-chip.
  • the frequency value of the target TE signal is equal to the value of the preset frame rate.
  • the SoC may send the first instruction including the preset frame rate to the independent display chip, so that the independent display chip generates a TE signal whose frequency value is equal to the value of the preset frame rate, and sends the TE signal to the system
  • the level chip sends the TE signal, so, because the system level chip sends the data of the preset frame rate to the independent display chip, and the preset frame rate is lower than the frame rate of the first content, that is, the electronic device reduces the output frame rate of the system level chip , so as to reduce the power consumption of the system-on-chip, stabilize the output frame rate of the system-on-chip, thereby improving the smoothness of the picture displayed by the electronic device.
  • the above first instruction further includes a target frame rate.
  • the independent display chip is specifically used to use the target frame rate to perform frame interpolation processing on the first data to obtain the second data.
  • the system-level chip sends the first instruction including the preset frame rate and the target frame rate to the independent display chip, so that the independent display chip enters the mode of "interpolating frames at the preset frame rate as the target frame rate".
  • the independent display chip can perform frame interpolation processing on the first data to obtain the second data at the target frame rate.
  • the independent display chip while the independent display chip performs frame insertion processing on the first data, it can also perform other processing on the first data (such as super-resolution, noise reduction, color enhancement, etc.), and finally obtains second data.
  • other processing on the first data such as super-resolution, noise reduction, color enhancement, etc.
  • the frame rate of the above second data may be preset by the user, or may be a default of the electronic device.
  • the details can be determined according to actual usage requirements, and are not limited in this embodiment of the application.
  • the frame rate of the second data when the high frame rate mode is enabled, may be greater than the frame rate of the first content; in another implementation manner, when the high frame rate mode is enabled In the case of the power saving mode, the frame rate of the second data may be equal to the frame rate of the first content.
  • the independent display chip can perform frame interpolation processing on the first data whose frame rate is lower than the frame rate of the first content to obtain the second data whose frame rate is greater than or equal to the frame rate of the first content. While reducing the power consumption of the SoC, the frame rate of the content displayed by the electronic device is increased or maintained, thereby improving the smoothness of the picture displayed by the electronic device.
  • the foregoing target TE signal includes multiple TE signals.
  • the system-on-a-chip is specifically configured to send one frame of data in the first data to the independent display chip every time a TE signal is received, so as to send multiple frames of data in the first data to the independent display chip.
  • the foregoing one TE signal is one TE signal among multiple TE signals.
  • the SoC when the SoC receives the first TE signal, the SoC may send the first frame of data in the first data to the independent display chip, and the SoC receives In the case of the second TE signal, the system-on-a-chip can send the second frame of data in the first data to the independent display chip, ..., and so on, until the system-on-chip sends all the data in the first data to the independent display chip frame data.
  • every time the independent display chip receives a frame of data in the first data it processes the one frame of data, and after the processing of the one frame of data is completed, the independent display chip sends One TE signal to realize the processing of all frame data in the first data. It can be understood that each TE signal corresponds to one frame of data in the first data.
  • the independent display chip can send a TE signal to the system-on-chip, and then the system-on-chip sends a frame of data to the independent display chip.
  • the system-on-chip receives a TE signal
  • the system The system-level chip sends a frame of data in the first data to the independent display chip
  • the system-level chip sends all the frame data in the first data to the independent display chip, avoiding receiving when the independent display chip has not processed a frame of data To the situation of the next frame of data, so as to ensure the timing of data processing by the system-on-chip and the independent display chip.
  • the above-mentioned independent display frame insertion circuit further includes a display unit.
  • the independent display chip is also used to send the second data to the display unit when receiving the first TE signal sent by the display unit, the value of the frequency of the first TE signal is greater than or equal to the value of the frame rate of the second data.
  • the display unit is used for displaying the second content based on the second data.
  • the above-mentioned first TE signal may be one TE signal, or may include multiple TE signals.
  • the details can be determined according to actual usage requirements, and are not limited in this embodiment of the application.
  • the independent display chip when the independent display chip receives one of the first TE signals, the independent display chip sends the first TE signal to the display unit.
  • One frame of data in the second data to send multiple frames of data in the second data to the display unit.
  • each TE signal in the first TE signal corresponds to one frame of data in the second data.
  • the independent display chip may sequentially send multiple frames of data to the display unit, and then the display unit sequentially displays the content corresponding to each frame of data, so as to realize The display unit displays the second content.
  • the display unit when the value of the frequency of the first TE signal is equal to the value of the frame rate of the second data, the display unit will display the content corresponding to the frame of data every time it receives a frame of data in the second data .
  • the display unit after the display unit sends one TE signal in the first TE signal, there may be a case where a frame of data in the second data is not received At this time, the display unit may display the content corresponding to the last frame data received by the display unit.
  • the display unit displays the last frame data received by the display unit corresponding content.
  • the display unit can receive the second data sent by the independent display chip, and display the second content corresponding to the second data, that is, display the content with a high frame rate or maintain the content displayed by the display unit, avoiding system-level Too much power consumption of the chip affects the frame insertion function of the independent display chip, thereby improving the smoothness of the picture displayed by the electronic device.
  • FIG. 7 shows a flow chart of the frame insertion method for an independent display provided in the embodiment of the present application.
  • the method can be applied to electronic devices.
  • the method for inserting frames for an independent display provided in the embodiment of the present application may include the following steps 201 to 203 .
  • step 201 the electronic device generates first data based on first content to be displayed by the electronic device through a SoC in the electronic device.
  • the frame rate of the first data is lower than the frame rate of the first content.
  • the electronic device may generate the first data based on the first content (such as a video picture or a game picture) to be displayed by the electronic device through a system-level chip, and the frame rate of the first data is lower than the frame rate of the first content rate, that is, reduce the output frame rate of the system-level chip, and then, when the system-level chip receives the target TE signal sent by the independent display chip in the electronic device, the electronic device sends the first data to the independent display chip through the system-level chip , so that the independent display chip performs frame insertion processing on the first data to obtain the second data, and the frame rate of the second data is greater than or equal to the frame rate of the first content, that is, to increase the frame rate of the content displayed by the electronic device or maintain The frame rate of content displayed by electronic devices.
  • the first content such as a video picture or a game picture
  • the electronic device may perform frame-drop processing on the first content through the system-on-a-chip, or perform any other possible processing on the first content through the system-on-a-chip to obtain the first data.
  • step 201 may specifically be implemented through the following step 201a.
  • step 201a the electronic device performs frame dropping processing on the first content based on a preset frame rate through a SoC, to obtain first data at a preset frame rate.
  • the preset frame rate is lower than the frame rate of the first content.
  • the electronic device can use the system-level chip to perform frame-drop processing on the first content based on the preset frame rate to obtain the first data of the preset frame rate, that is, reduce the output frame rate of the system-level chip, so,
  • the power consumption of the system-level chip can be reduced to stabilize the output frame rate of the system-level chip, avoiding the problem that the high power consumption of the system-level chip affects the frame insertion function of the independent display, thereby improving the smoothness of the picture displayed by the electronic device.
  • Step 202 When the system-on-a-chip receives the target TE signal sent by the independent display chip in the electronic device, the electronic device sends the first data to the independent display chip through the system-on-chip.
  • the independent display chip in the electronic device may send a target TE signal to the system-on-chip, so that the electronic device sends the first data to the independent display chip through the system-on-chip.
  • the foregoing target TE signal may be one TE signal, or may include multiple TE signals.
  • the details can be determined according to actual usage requirements, and are not limited in this embodiment of the application.
  • the foregoing target TE signal includes multiple TE signals.
  • the above step 202 may specifically be implemented through the following step 202a.
  • Step 202a when the system-on-chip receives a TE signal, the electronic device sends a frame of data in the first data to the independent display chip through the system-on-chip, so as to send the first data to the independent display chip through the system-on-chip Multi-frame data in .
  • the electronic device sends a TE signal to the system-level chip through the independent display chip, and then the electronic device can send a frame of data to the independent display chip through the system-level chip, so that every time the system-level chip receives a TE signal, the electronic device then sends a frame of data in the first data to the independent display chip through the system-level chip, and finally sends all the frame data in the first data to the independent display chip through the system-level chip, avoiding the The chip receives the next frame of data before processing one frame of data, so as to ensure the timing of data processing by the system-level chip and the independent display chip.
  • Step 203 the electronic device performs frame insertion processing on the first data through the independent display chip to obtain the second data.
  • the frame rate of the second data is greater than or equal to the frame rate of the first content.
  • the method for inserting frames for an independent display provided in the embodiment of the present application further includes the following steps 301 and 302.
  • Step 301 the electronic device sends a first instruction to the independent display chip through the SoC.
  • the above-mentioned first instruction includes a preset frame rate.
  • Step 302 the electronic device generates the target TE signal through the independent display chip, and sends the target TE signal to the system-level chip through the independent display chip.
  • the value of the frequency of the target TE signal is equal to the value of the preset frame rate.
  • the electronic device may send the first instruction including the preset frame rate to the independent display chip through the system-on-a-chip, so that the electronic device generates a frequency value equal to the value of the preset frame rate through the independent display chip.
  • TE signal and send the TE signal to the system-level chip through the independent display chip, so that the electronic device can send the data of the preset frame rate to the independent display chip through the system-level chip, because the preset frame rate is lower than the frame rate of the first content That is, the electronic device reduces the power consumption of the system-level chip by reducing the output frame rate of the system-level chip, and stabilizes the output frame rate of the system-level chip, thereby improving the fluency of the picture displayed by the electronic device.
  • the above first instruction further includes a target frame rate.
  • the above step 203 may specifically be implemented through the following step 203a.
  • Step 203a the electronic device performs frame interpolation processing on the first data by using the target frame rate through the independent display chip to obtain the second data.
  • the electronic device may use an independent display chip to perform frame insertion processing on the first data whose frame rate is lower than the frame rate of the first content to obtain second data whose frame rate is greater than or equal to the frame rate of the first content, In this way, the electronic device can increase or maintain the frame rate of the content displayed by the electronic device while reducing the power consumption of the SoC, thereby improving the smoothness of the picture displayed by the electronic device.
  • An embodiment of the present application provides a frame insertion method for an independent display.
  • the electronic device can generate first data based on the first content to be displayed by the electronic device through a system-level chip, and the frame rate of the first data is lower than the frame rate of the first content.
  • the electronic device can send the first data to the independent display chip through the system-on-chip, so that the independent display chip responds to the first data Perform frame insertion processing to obtain second data, and the frame rate of the second data is greater than or equal to the frame rate of the first content.
  • the independent display chip can process the first data Frame insertion processing to obtain the second data, so as to increase the frame rate of the content to be displayed by the electronic device or maintain the frame rate of the content to be displayed by the electronic device.
  • the output frame rate of the system-level chip the power of the system-level chip is avoided.
  • the method for inserting frames for the independent display provided in the embodiment of the present application further includes the following steps 401 and 402.
  • Step 401 when the independent display chip receives the first TE signal sent by the display unit in the electronic device, the electronic device sends the second data to the display unit through the independent display chip.
  • the value of the frequency of the first TE signal is greater than or equal to the value of the frame rate of the second data.
  • Step 402 the electronic device displays the second content based on the second data through the display unit.
  • the electronic device can receive the second data sent by the independent display chip through the display unit, and display the second content corresponding to the second data, that is, display the content with a high frame rate through the display unit or maintain the content displayed on the display unit.
  • the content avoids the problem that the power consumption of the system-level chip is too large to affect the frame insertion function of the independent display chip, thereby improving the smoothness of the picture displayed by the electronic device.
  • the independent display frame insertion method provided in the embodiment of the present application may be executed by an independent display frame insertion device.
  • the independent display frame insertion device is used as an example to illustrate the independent display frame insertion device provided in the embodiment of the present application.
  • FIG. 8 shows a possible structural schematic diagram of the device for inserting frames for an independent display in the embodiment of the present application.
  • the independent display frame insertion device 70 may include: a generating module 71 , a sending module 72 and a processing module 73 .
  • the generating module 71 is configured to generate first data based on the first content to be displayed by the electronic device through the SoC in the electronic device, and the frame rate of the first data is lower than the frame rate of the first content.
  • the sending module 72 is configured to send the first data to the independent display chip through the system-on-chip when the system-on-chip receives the target display frame rate synchronous TE signal sent by the independent display chip in the electronic device.
  • the processing module 73 is configured to perform frame interpolation processing on the first data through an independent display chip to obtain second data, and the frame rate of the second data is greater than or equal to the frame rate of the first content.
  • An embodiment of the present application provides an independent display frame insertion device. Since the frame rate of the first data generated by the system-level chip is lower than the frame rate of the first content displayed by the independent display frame insertion device, that is, the output frame rate of the system-level chip is reduced.
  • the independent display chip can perform frame interpolation processing on the first data to obtain the second data, so as to improve the frame rate of the content to be displayed by the independent display frame interpolation device or maintain the frame rate of the content to be displayed by the independent display frame interpolation device, so , by reducing the output frame rate of the system-level chip to avoid the problem that the high power consumption of the system-level chip affects the function of the independent display frame insertion, thereby improving the fluency of the picture displayed by the independent display frame insertion device.
  • the generating module 71 is specifically configured to perform frame dropping processing on the first content based on a preset frame rate through a system-on-a-chip to obtain first data at a preset frame rate.
  • the above-mentioned sending module 72 is also used to send the first Before the data, a first instruction is sent to the independent display chip through the system-on-a-chip, and the first instruction includes a preset frame rate.
  • the above generating module 71 is also used to generate the target TE signal through the independent display chip.
  • the above-mentioned sending module 72 is also used to send the target TE signal to the system-on-chip through the independent display chip, and the value of the frequency of the target TE signal is equal to the value of the preset frame rate.
  • the above-mentioned first instruction further includes a target frame rate.
  • the above-mentioned processing module 73 is specifically used to perform frame interpolation processing on the first data by using the target frame rate through the independent display chip to obtain the second data.
  • the foregoing target TE signal includes multiple TE signals.
  • the above-mentioned sending module 72 is specifically used to send a frame of data in the first data to the independent display chip through the system-level chip every time the system-level chip receives a TE signal, so as to send a frame of data to the independent display chip through the system-level chip Multi-frame data in the first data.
  • the above-mentioned independent display frame insertion device 70 further includes: a display module.
  • the above sending module 72 is also used to perform frame insertion processing on the first data through the independent display chip to obtain the second data, when the independent display chip receives the first TE signal sent by the display unit in the electronic device , sending the second data to the display unit through the independent display chip, and the value of the frequency of the first TE signal is greater than or equal to the value of the frame rate of the second data.
  • the display module is used for displaying the second content based on the second data through the display unit.
  • the independent display frame insertion device in the embodiment of the present application may be an electronic device, or may be a component in the electronic device, such as an integrated circuit or a chip.
  • the electronic device may be a terminal, or other devices other than the terminal.
  • the electronic device can be a mobile phone, a tablet computer, a notebook computer, a handheld computer, a vehicle electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR)/virtual reality (virtual reality, VR) ) equipment, robot, wearable device, ultra-mobile personal computer (ultra-mobile personal computer, UMPC), netbook or personal digital assistant (personal digital assistant, PDA), etc.
  • the embodiment of the present application does not specifically limit it.
  • the independent display frame insertion device in the embodiment of the present application may be a device with an operating system.
  • the operating system may be an Android operating system, an IOS operating system, or other possible operating systems, which are not specifically limited in this embodiment of the present application.
  • the independent display frame insertion device provided in the embodiment of the present application can realize the various processes realized in the above method embodiments, and can achieve the same technical effect. To avoid repetition, details are not repeated here.
  • the embodiment of the present application also provides a system-on-a-chip, the system-on-a-chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to display the first content based on the electronic device Generate first data, the frame rate of the first data is less than the frame rate of the first content, and the communication interface is used to send the target TE signal to the independent display chip in the case of receiving the target TE signal sent by the independent display chip in the electronic device first data.
  • the above processor is specifically configured to perform frame dropping processing on the first content based on a preset frame rate to obtain the first data at the preset frame rate.
  • the above-mentioned communication interface is also used to send a first instruction to the independent display chip, and the first instruction includes a preset frame rate.
  • the above-mentioned communication interface is also used to receive the target TE signal sent by the independent display chip, and the value of the frequency of the target TE signal is equal to the value of the preset frame rate.
  • the foregoing target TE signal includes multiple TE signals.
  • the above communication interface is specifically used to send one frame of data in the first data to the independent display chip every time a TE signal is received, so as to send multiple frames of data in the first data to the independent display chip.
  • the system-on-a-chip provided in the embodiment of the present application can realize various processes implemented by the system-on-a chip in the method embodiment, and can achieve the same technical effect. To avoid repetition, details are not repeated here.
  • the embodiment of the present application also provides an independent display chip, the independent display chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the communication interface is used to provide a system-on-a-chip in an electronic device Send the target TE signal, and receive the first data sent by the SoC, the first data is the data generated by the SoC based on the first content to be displayed by the electronic device, and the frame rate of the first data is lower than the frame rate of the first content rate, the processor is configured to perform frame interpolation processing on the first data to obtain second data, and the frame rate of the second data is greater than or equal to the frame rate of the first content.
  • the communication interface is further configured to receive a first instruction sent by the system-on-a-chip, where the first instruction includes a preset frame rate.
  • the aforementioned processor is also used to generate a target TE signal.
  • the above-mentioned communication interface is also used to send the target TE signal to the system-on-a-chip, and the value of the frequency of the target TE signal is equal to the value of the preset frame rate.
  • the above first instruction further includes a target frame rate.
  • the above-mentioned processor is specifically configured to use a target frame rate to perform frame interpolation processing on the first data to obtain the second data.
  • the foregoing target TE signal includes multiple TE signals.
  • the above communication interface is specifically used to receive one frame of data in the first data sent by the system-on-chip to receive multiple frames of data in the first data sent by the system-on-chip when sending a TE signal.
  • the above-mentioned communication interface is also used to send the second data to the display unit when the first TE signal sent by the display unit in the electronic device is received, and the frequency of the first TE signal is The value of is greater than or equal to the value of the frame rate of the second data.
  • the independent display chip provided in the embodiment of the present application can realize each process realized by the independent display chip in the method embodiment, and can achieve the same technical effect. To avoid repetition, details are not repeated here.
  • the embodiment of the present application further provides an electronic device 800, including a processor 801, a memory 802, and programs or instructions stored in the memory 802 and operable on the processor 801,
  • an electronic device 800 including a processor 801, a memory 802, and programs or instructions stored in the memory 802 and operable on the processor 801,
  • the program or instruction is executed by the processor 801
  • each step of the above-mentioned embodiment of the independent display frame insertion method can be realized, and the same technical effect can be achieved. To avoid repetition, details are not repeated here.
  • the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.
  • FIG. 10 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.
  • the electronic device 1000 includes, but is not limited to: a radio frequency unit 1001, a network module 1002, an audio output unit 1003, an input unit 1004, a sensor 1005, a display unit 1006, a user input unit 1007, an interface unit 1008, a memory 1009, and a processor 1010, etc. part.
  • the electronic device 1000 can also include a power supply (such as a battery) for supplying power to various components, and the power supply can be logically connected to the processor 1010 through the power management system, so that the management of charging, discharging, and function can be realized through the power management system. Consumption management and other functions.
  • a power supply such as a battery
  • the structure of the electronic device shown in FIG. 10 does not constitute a limitation to the electronic device.
  • the electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange different components, and details will not be repeated here. .
  • the processor 1010 is configured to use the system-on-a-chip in the electronic device to generate first data based on the first content to be displayed by the electronic device, and the frame rate of the first data is lower than the frame rate of the first content;
  • the first data is sent to the independent display chip through the system-level chip; through the independent display chip, the frame insertion processing is performed on the first data to obtain the second data,
  • the frame rate of the second data is greater than or equal to the frame rate of the first content.
  • An embodiment of the present application provides an electronic device. Since the frame rate of the first data generated by the system-level chip is lower than the frame rate of the first content displayed by the electronic device, that is, the output frame rate of the system-level chip is reduced. Then, the independent display chip can Perform frame insertion processing on the first data to obtain the second data, so as to increase the frame rate of the content displayed by the electronic device or maintain the frame rate of the content displayed by the electronic device. In this way, by reducing the output frame rate of the system-level chip, to avoid system The high power consumption of the advanced chip affects the frame insertion function of the independent display, thereby improving the smoothness of the picture displayed by the electronic device.
  • the processor 1010 is specifically configured to perform frame dropping processing on the first content based on a preset frame rate through a system-on-a-chip to obtain first data at a preset frame rate.
  • the processor 1010 is further configured to send the first Before the data, a first instruction is sent to the independent display chip through the system-on-a-chip, and the first instruction includes a preset frame rate.
  • the processor 1010 is also configured to generate a target TE signal through the independent display chip, and send the target TE signal to the system-on-chip through the independent display chip, and the frequency value of the target TE signal is equal to the value of the preset frame rate.
  • the above first instruction further includes a target frame rate.
  • the processor 1010 is specifically configured to perform frame interpolation processing on the first data at a target frame rate through an independent display chip to obtain second data.
  • the foregoing target TE signal includes multiple TE signals.
  • the processor 1010 is specifically configured to send a frame of data in the first data to the independent display chip through the system-on-chip every time the system-on-chip receives a TE signal, so as to send the first frame of data to the independent display chip through the system-on-chip. Multiple frames of data in one data.
  • the processor 1010 is also configured to perform frame insertion processing on the first data through the independent display chip to obtain the second data, and receive the display unit in the electronic device after the independent display chip receives the second data.
  • the second data is sent to the display unit through the independent display chip, and the value of the frequency of the first TE signal is greater than or equal to the value of the frame rate of the second data.
  • the display unit 1006 is configured to display the second content based on the second data.
  • the electronic device provided by the embodiment of the present application can realize each process realized by the above method embodiment, and can achieve the same technical effect, and to avoid repetition, details are not repeated here.
  • the input unit 1004 may include a graphics processor (Graphics Processing Unit, GPU) 10041 and a microphone 10042, and the graphics processor 10041 is used for the image capture device (such as the image data of the still picture or video obtained by the camera) for processing.
  • the display unit 1006 may include a display panel 10061, and the display panel 10061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the user input unit 1007 includes at least one of a touch panel 10071 and other input devices 10072 .
  • the touch panel 10071 is also called a touch screen.
  • the touch panel 10071 may include two parts, a touch detection device and a touch controller.
  • Other input devices 10072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, switch buttons, etc.), trackballs, mice, and joysticks, which will not be repeated here.
  • the memory 1009 can be used to store software programs as well as various data.
  • the memory 1009 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required by at least one function (such as a sound playing function, image playback function, etc.), etc.
  • memory 1009 may include volatile memory or nonvolatile memory, or, memory 1009 may include both volatile and nonvolatile memory.
  • the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electronically programmable Erase Programmable Read-Only Memory (Electrically EPROM, EEPROM) or Flash.
  • ROM Read-Only Memory
  • PROM programmable read-only memory
  • Erasable PROM Erasable PROM
  • EPROM erasable programmable read-only memory
  • Electrical EPROM Electrical EPROM
  • EEPROM electronically programmable Erase Programmable Read-Only Memory
  • Volatile memory can be random access memory (Random Access Memory, RAM), static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (Synch link DRAM , SLDRAM) and Direct Memory Bus Random Access Memory (Direct Rambus RAM, DRRAM).
  • RAM Random Access Memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM Double Data Rate SDRAM
  • DDRSDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM, ESDRAM enhanced synchronous dynamic random access memory
  • Synch link DRAM , SLDRAM
  • Direct Memory Bus Random Access Memory Direct Rambus
  • the processor 1010 may include one or more processing units; optionally, the processor 1010 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to the operating system, user interface, and application programs, etc., Modem processors mainly process wireless communication signals, such as baseband processors. It can be understood that the foregoing modem processor may not be integrated into the processor 1010 .
  • the embodiment of the present application also provides a readable storage medium, the readable storage medium stores a program or an instruction, and when the program or instruction is executed by the processor, the electronic device implements the various processes of the above-mentioned embodiment of the independent display frame insertion method , and can achieve the same technical effect, in order to avoid repetition, it will not be repeated here.
  • the processor is the processor in the electronic device described in the above embodiments.
  • the readable storage medium includes a computer-readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk, and the like.
  • An embodiment of the present application provides a computer program product, the program product is stored in a storage medium, and the program product is executed by at least one processor so that the electronic device implements the various processes in the above-mentioned embodiment of the independent display frame insertion method, and can To achieve the same technical effect, in order to avoid repetition, no more details are given here.
  • the term “comprising”, “comprising” or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase “comprising a " does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.
  • the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved. Functions are performed, for example, the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

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Abstract

本申请公开了一种独显插帧电路、方法、装置、芯片、电子设备及介质。该独显插帧电路包括系统级芯片和独显芯片。其中，该系统级芯片用于基于待显示的第一内容生成第一数据，并在接收到独显芯片发送的目标TE信号的情况下，向独显芯片发送第一数据，该第一数据的帧率小于第一内容的帧率；该独显芯片用于对第一数据进行插帧处理，得到第二数据，该第二数据的帧率大于或等于第一内容的帧率。

Description

独显插帧电路、方法、装置、芯片、电子设备及介质
相关申请的交叉引用
本申请主张在2021年12月28日在中国提交的中国专利申请号No.202111630090.9的优先权，其全部内容通过引用包含于此。
技术领域
本申请属于通信技术领域，具体涉及一种独显插帧电路、方法、装置、芯片、电子设备及介质。
背景技术
随着终端技术的发展，用户对电子设备显示的画面的质量要求越来越高。目前，一些电子设备可以支持高帧率显示视频、游戏等画面，然而，在电子设备采用高帧率显示视频、游戏等画面的过程中，由于电子设备的功耗较大，影响电子设备的显示帧率，如此导致电子设备显示的画面的流畅度较低。
发明内容
本申请实施例的目的是提供一种独显插帧电路、方法、装置、芯片、电子设备及介质。
第一方面，本申请实施例提供了一种独显插帧电路，该独显插帧电路包括系统级芯片和独显芯片。其中，该系统级芯片用于基于待显示的第一内容生成第一数据，并在接收到独显芯片发送的目标显示帧率同步TE信号的情况下，向独显芯片发送第一数据，该第一数据的帧率小于第一内容的帧率；该独显芯片用于对第一数据进行插帧处理，得到第二数据，该第二数据的帧率大于或等于第一内容的帧率。
第二方面，本申请实施例提供了一种独显插帧方法，该独显插帧方法包括：通过电子设备中的系统级芯片，基于电子设备待显示的第一内容生成第一数据，该第一数据的帧率小于第一内容的帧率；在系统级芯片接收到电子设备中的独显芯片发送的目标显示帧率同步TE信号的情况下，通过系统级芯片向独显芯片发送第一数据；通过独显芯片，对第一数据进行插帧处理，得到第二数据，该第二数据的帧率大于或等于第一内容的帧率。
第三方面，本申请实施例提供了一种独显插帧装置，该独显插帧装置包括：生成模块、发送模块和处理模块。其中，生成模块，用于通过电子设备中的系统级芯片，基于电子设备待显示的第一内容生成第一数据，该第一数据的帧率小于第一内容的帧率。发送模块，用于在系统级芯片接收到电子设备中的独显芯片发送的目标显示帧率同步TE信号的情况下，通过系统级芯片向独显芯片发送第一数据。处理模块，用于通过独显芯片，对第一数据进行插帧处理，得到第二数据，该第二数据的帧率大于或等于第一内容的帧率。
第四方面，本申请实施例提供了一种系统级芯片，所述系统级芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于基于电子设备待显示的第一内容生成第一数据，该第一数据的帧率小于第一内容的帧率，所述通信接口用于在接收到电子设备中的独显芯片发送的目标显示帧率同步TE信号的情况下，向独显芯片发送第一数据。
第五方面，本申请实施例提供了一种独显芯片，所述独显芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述通信接口用于向电子设备中的系统级芯片发送目标显示帧率同步TE信号，并接收系统级芯片发送的第一数据，该第一数据为系统级芯片基于电子设备待显示的第一内容生成的数据，该第一数据的帧率小于第一内容的帧率，所述处理器用于对第一数据进行插帧处理，得到第二数据，该第二数据的帧率大于或等于第一内容的帧率。
第六方面，本申请实施例提供了一种电子设备，该电子设备包括如第一方面所述的独显插帧电路，或者包括如第四方面所述的系统级芯片和第五方面所述的独显芯片。
第七方面，本申请实施例提供了一种电子设备，该电子设备包括处理器和存储器，所述存储器存储可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时使得电子设备实现如第二方面所述的方法的步骤。
第八方面，本申请实施例提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时使得电子设备实现如第二方面所述的方法的步骤。
第九方面，本申请实施例提供一种计算机程序产品，该程序产品被存储在存储介质中，该程序产品被至少一个处理器执行以使得电子设备实现如第二方面所述的方法。
在本申请实施例中，系统级芯片可以基于待显示的第一内容生成第一数据，且第一数据的帧率小于第一内容的帧率，然后，在系统级芯片接收到独显芯片发送的目标TE信号的情况下，系统级芯片可以向独显芯片发送第一数据，以使得独显芯片对第一数据进行插帧处理，得到第二数据，且该第二数据的帧率大于或等于第一内容的帧率。本方案中，由于系统级芯片生成的第一数据的帧率小于待显示的第一内容的帧率，即降低系统级芯片的输出帧率，然后，独显芯片可以对第一数据进行插帧处理，得到第二数据，以提升电子设备待显示的内容的帧率或者维持电子设备待显示的内容的帧率，如此，通过降低系统级芯片的输出帧率，以避免系统级芯片功耗较大影响独显插帧功能的问题，从而提升了电子设备显示的画面的流畅度。
附图说明
图1是本申请实施例提供的一种独显插帧方法的示意图之一；
图2是本申请实施例提供的一种独显插帧方法的示意图之二；
图3是本申请实施例提供的一种独显插帧电路的结构示意图；
图4是本申请实施例提供的一种独显芯片的架构示意图；
图5是本申请实施例提供的一种未开启独显插帧功能时的信号交互图；
图6是本申请实施例提供的一种开启独显插帧功能时的信号交互图；
图7是本申请实施例提供的一种独显插帧方法的流程图；
图8是本申请实施例提供的一种独显插帧装置的结构示意图；
图9是本申请实施例提供的一种电子设备的硬件结构示意图之一；
图10是本申请实施例提供的一种电子设备的硬件结构示意图之二。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例， 本领域普通技术人员获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的独显插帧方法进行详细地说明。
目前，一些电子设备可以支持高帧率显示视频、游戏等画面，然而，在电子设备采用高帧率显示视频、游戏等画面的过程中，由于电子设备的功耗较大，影响电子设备的显示帧率，如此导致电子设备显示的画面的流畅度较低。
为了解决上述技术问题，本申请实施例中，可以通过降低系统级芯片(System on a Chip，SoC)的输出帧率，然后再通过独立显示芯片(即独显芯片)插帧到目标帧率(大于或等于当前显示的内容的帧率)，如此，在提高或维持电子设备显示的内容的帧率的同时，降低SoC的功耗，以稳定SoC的输出帧率，从而提升电子设备显示的画面的流畅度。
一种场景下，如图1所示，显示模组(Liquid Crystal Display Module，LCM)的显示帧率为90fps，片源的帧率(即电子设备待显示的内容的帧率)为60fps，在需要提高电子设备待显示的内容的帧率时，LCM发出90Hz的TE信号给独显芯片进行帧同步，独显芯片将TE信号调整为45Hz发送给SoC，同时SoC将生成的帧数据从60fps处理为45fps传递给独显芯片，以使得独显芯片将该45fps的帧数据插帧为90fps的帧数据，并传递给LCM，从而LCM显示该90fps的帧数据对应的内容。如此，在提高电子设备待显示的内容的帧率的同时，降低SoC的功耗，以稳定SoC的输出帧率，从而提升电子设备显示的画面的流畅度。
另一种场景下，如图2所示，LCM的显示帧率为90fps，片源的帧率(即电子设备待显示的内容的帧率)为60fps，在维持电子设备待显示的内容的帧率不变时，LCM发出90Hz的TE信号给独显芯片进行帧同步，独显芯片将TE信号调整为30Hz发送给SoC，同时SoC将生成的帧数据从60fps处理为30fps传递给独显芯片(或者独显芯片将TE信号调整为45Hz发送给SoC，SoC将生成的帧数据从60fps处理为45fps传递给独显芯片，根据功耗和效果的需求可以进行调整)，以使得独显芯片将该30fps的帧数据插帧为60fps的帧数据，并传递给LCM，从而LCM显示该60fps的帧数据对应的内容。如此，在维持电子设备待显示的内容的帧率的同时，降低SoC的功耗，以稳定SoC的输出帧率，从而提升电子设备显示的画面的流畅度。
实施例一
本申请实施例提供一种独显插帧电路，图3示出了本申请实施例提供的一种独显插帧电路的结构示意图。如图3所示，本申请实施例提供的独显插帧电路可以包括系统级芯片和独显芯片。
其中，系统级芯片用于基于待显示的第一内容生成第一数据，并在接收到独显芯片发送的目标TE信号的情况下，向独显芯片发送第一数据，该第一数据的帧率小于第一内容的帧率。独显芯片用于对第一数据进行插帧处理，得到第二数据，该第二数据的帧率大于或等于第一内容的帧率。
需要说明的是，独显芯片作为外置的专用图像处理单元可以带来更高帧率、更高分辨率、色彩饱和度及对比度等显示增强效果。某些电子设备虽然支持高帧率(例如120/90Hz)，但实际显示的内容并没有实现真正的高帧率，只是依靠图像处理单元(Graphics Processing Unit，GPU)或者显示驱动集成电路进行简单的画面重复，实际体验还是低帧率。独显芯片可以利用前后两帧数据计算画面的运动特征，模拟产生中间的画面，以实现动态补帧，以使得电子设备显示的内容实现真正的高帧率。
图4示出了独显芯片的架构示意图，独显芯片具有两个显示串行接口(Display Serial Interface，DSI)，通过移动行业处理器接口(Mobile Industry Processor Interface，MIPI)协议实现数据传输，其可以工作于双路MIPI模式和单路MIPI模式。在双路模式下，显示内容可以分成用户界面(User Interface，UI)层和多媒体video层，UI层和video层分别通过DSI接口传递给独显芯片，并分别经由独显芯片内部的各个功能模块处理(例如插帧、超分辨率、降噪、色彩增强等)后合成得到帧数据，在进行必要的色彩处理后通过显示串行接口-发送端(DSI-Transmit，DSI-Tx)0传递给显示模组(Liquid Crystal Display Module，LCM)。在单路模式下，显示内容可以由SoC合成帧数据后一起经由DSI 0发送给独显芯片，以使得独显芯片进行相应的处理后传递给显示模组。
在拍照场景下，电子设备中的摄像头拍摄的内容通过摄像头串行接口(Camera Serial Interface，CSI)0传递给SoC，SoC通过DSI接口将拍摄的内容传递给独显芯片，独显芯片经过芯片处理后再分别由CSI Tx0和DSI Tx0接口把处理后的内容传递给SoC和显示模组，SoC可以存储处理后的内容，同时显示模组可以实时预览显示处理后的内容。
其中，各个接口的功能如下：
DSI 0：输出UI或video内容；
显示串行接口-接收端(DSI-Receive，DSI-Rx)0：接收DSI 0传递的内容；
DSI 1：输出UI或video内容；
DSI Rx1：接收DSI 1传递的内容；
CSI 0：接收摄像头拍摄的内容；
CSI 1：接收独显芯片处理后的内容；
DSI Tx0：输出显示内容给显示屏；
CSI Tx0：输出独显芯片处理后的内容给SoC；
TE：显示帧率同步信号；
MIPI：一种信号传输协议；
通用型输入输出端口(General-Purpose Input/Output，GPIO)：传输独显芯片与处理器之间的其他控制信号、数据信号等；
内核模块(Intellectual Property，IP)：独显芯片内部的功能(例如插帧、超分辨率、降噪、色彩增强、UI与video内容叠加等功能)处理模块；
电源管理集成电路(Power Management Integrated Circuit，PMIC)：包括电池管理芯片、独显供电电源管理芯片及其他模块电源管理芯片/模块等；
Battery：电子设备的电池；
SoC：系统级芯片，包含处理器内核、数字信号处理器、存储模块、通信接口、电源管理、射频前端等模块。
图5示出了电子设备未开启独显插帧功能时的信号交互图。显示屏的帧率为90fps，电子 设备未开启独显插帧功能时，LCM发出90Hz的TE信号给独显芯片进行帧同步，独显芯片也同步产生90Hz的TE信号发送给SoC，由于片源只有60fps，GPU会生成60fps的帧数据传递给独显芯片，然后独显芯片直接传递给显示屏，此时显示屏显示的真实内容只有60fps，无法达到显示屏的90fps。
图6示出了电子设备开启独显插帧功能时的信号交互图。显示屏的帧率为90fps，电子设备开启独显插帧功能(例如将60fps插帧为90fps)时，LCM发出90Hz的TE信号给独显芯片进行帧同步，独显芯片同步产生60Hz的TE信号发送给SoC，SoC会生成60fps的帧数据传递给独显芯片，然后独显芯片将60fps插帧为90fps，并传递给显示屏，此时显示屏显示的内容可以达到真实的90fps。
可选地，本申请实施例中，上述第一内容可以为视频画面、游戏画面等。具体的可以根据实际使用需求确定，本申请实施例不做限制。
可选地，本申请实施例中，系统级芯片可以对第一内容进行丢帧处理，也可以对第一内容进行其他任意可能的处理，以得到第一数据。
可选地，本申请实施例中，上述系统级芯片具体用于基于预设帧率对第一内容进行丢帧处理，得到预设帧率的第一数据。
可选地，本申请实施例中，上述预设帧率小于第一内容的帧率。并且，上述预设帧率可以为电子设备默认的，也可以为用户预先设置的。具体的可以根据实际使用需求确定，本申请实施例不做限制。
示例性地，假设预设帧率为45fps，第一内容的帧率为60fsp，则系统级芯片每处理3fps数据就丢掉1fps数据，丢掉的这一帧数据不需要处理，系统级芯片实际处理的数据为45fps。
又示例性地，假设预设帧率为30fps，第一内容的帧率为60fsp，则系统级芯片每处理1fps数据就丢掉1fps数据，丢掉的这一帧数据不需要处理，系统级芯片实际处理的数据为30fps。
本申请实施例中，系统级芯片可以基于预设帧率对第一内容进行丢帧处理，得到预设帧率的第一数据，即降低系统级芯片的输出帧率，如此，可以降低系统级芯片的功耗，以稳定系统级芯片的输出帧率，避免了系统级芯片功耗较大影响独显插帧功能的问题，从而提升电子设备显示的画面的流畅度。
可选地，本申请实施例中，上述目标TE信号可以为一个TE信号，也可以包括多个TE信号。具体的可以根据实际使用需求确定，本申请实施例不做限制。
可选地，本申请实施例中，上述系统级芯片还用于向独显芯片发送第一指令，该第一指令中包括预设帧率。独显芯片还用于生成目标TE信号，并向系统级芯片发送目标TE信号，该目标TE信号的频率的数值等于预设帧率的数值。
本申请实施例中，系统级芯片可以向独显芯片发送包括预设帧率的第一指令，以使得独显芯片生成频率的数值与该预设帧率的数值相等的TE信号，并向系统级芯片发送该TE信号，如此，由于系统级芯片向独显芯片发送预设帧率的数据，且预设帧率小于第一内容的帧率，即电子设备通过降低系统级芯片的输出帧率，以降低系统级芯片的功耗，稳定了系统级芯片的输出帧率，从而提升电子设备显示的画面的流畅度。
可选地，本申请实施例中，上述第一指令中还包括目标帧率。独显芯片具体用于采用目标帧率，对第一数据进行插帧处理，得到第二数据。
可以理解，系统级芯片向独显芯片发送包括预设帧率和目标帧率的第一指令，以使得独显芯片进入“预设帧率插帧为目标帧率”模式，在独显芯片接收到第一数据的情况下，独显 芯片可以对第一数据进行插帧处理，得到目标帧率的第二数据。
可选地，本申请实施例中，独显芯片在对第一数据进行插帧处理的同时，还可以对第一数据进行其他处理(例如超分辨率、降噪、色彩增强等)，最终得到第二数据。
可选地，本申请实施例中，上述第二数据的帧率可以为用户预先设置的，也可以为电子设备默认的。具体的可以根据实际使用需求确定，本申请实施例不做限制。
可选地，本申请实施例中，一种实现方式中，在开启高帧率模式的情况下，第二数据的帧率可以大于第一内容的帧率；另一种实现方式中，在开启省电模式的情况下，第二数据的帧率可以等于第一内容的帧率。
本申请实施例中，独显芯片可以对帧率小于第一内容的帧率的第一数据进行插帧处理，得到帧率大于或等于第一内容的帧率的第二数据，如此，在降低系统级芯片的功耗的同时，提高或维持电子设备显示的内容的帧率，从而提升电子设备显示的画面的流畅度。
可选地，本申请实施例中，上述目标TE信号包括多个TE信号。系统级芯片具体用于在每接收到一个TE信号的情况下，向独显芯片发送第一数据中的一帧数据，以向独显芯片发送第一数据中的多帧数据。
可选地，本申请实施例中，上述一个TE信号为多个TE信号中的一个TE信号。
可选地，本申请实施例中，在系统级芯片接收到第一个TE信号的情况下，系统级芯片可以向独显芯片发送第一数据中的第一帧数据，在系统级芯片接收到第二个TE信号的情况下，系统级芯片可以向独显芯片发送第一数据中的第二帧数据，……，依此类推，直至系统级芯片向独显芯片发送第一数据中的所有帧数据。
可选地，本申请实施例中，独显芯片每接收到第一数据中的一帧数据，就处理该一帧数据，并在该一帧数据处理完成之后，独显芯片向系统级芯片发送一个TE信号，以实现处理第一数据中的所有帧数据。可以理解，每个TE信号对应第一数据中的一帧数据。
本申请实施例中，独显芯片可以向系统级芯片发送一个TE信号，然后，系统级芯片向独显芯片发送一帧数据，如此，在系统级芯片每接收到一个TE信号的情况下，系统级芯片向独显芯片发送第一数据中的一帧数据，最终系统级芯片向独显芯片发送第一数据中的所有帧数据，避免了在独显芯片还未处理完一帧数据时就接收到下一帧数据的情况，从而保证系统级芯片和独显芯片处理数据的时序性。
可选地，本申请实施例中，上述独显插帧电路还包括显示单元。独显芯片还用于在接收到显示单元发送的第一TE信号的情况下，向显示单元发送第二数据，该第一TE信号的频率的数值大于或等于第二数据的帧率的数值。显示单元用于基于第二数据显示第二内容。
可选地，本申请实施例中，上述第一TE信号可以为一个TE信号，也可以包括多个TE信号。具体的可以根据实际使用需求确定，本申请实施例不做限制。
可选地，本申请实施例中，若第一TE信号包括多个TE信号，则在独显芯片每接收到第一TE信号中的一个TE信号的情况下，独显芯片向显示单元发送第二数据中的一帧数据，以向显示单元发送第二数据中的多帧数据。
需要说明的是，针对独显芯片向显示单元发送第二数据的方法，具体可以参见上述实施例中系统级芯片向独显芯片发送第一数据的方法，此处不再赘述。
可选地，本申请实施例中，第一TE信号中的每个TE信号对应第二数据中的一帧数据。
可选地，本申请实施例中，在第二数据包括多帧数据的情况下，独显芯片可以依次向显示单元发送多帧数据，然后，显示单元依次显示每帧数据对应的内容，以实现显示单元显示 第二内容。
需要说明的是，在第一TE信号的频率的数值等于第二数据的帧率的数值的情况下，显示单元每接收到第二数据中的一帧数据，就显示该一帧数据对应的内容。在第一TE信号的频率的数值大于第二数据的帧率的数值的情况下，显示单元发送第一TE信号中的一个TE信号之后，可能存在未接收到第二数据中的一帧数据的情况，此时，显示单元可以显示显示单元最后一次接收到的帧数据对应的内容。
可以理解，在第二数据包括多帧数据的情况下，针对多帧数据中的目标帧数据，在显示单元未接收到目标帧数据的情况下，显示单元显示显示单元最后一次接收到的帧数据对应的内容。
本申请实施例中，显示单元可以接收独显芯片发送的第二数据，并显示该第二数据对应的第二内容，即显示高帧率的内容或者维持显示单元显示的内容，避免了系统级芯片功耗太大影响独显芯片插帧功能的问题，从而提升了电子设备显示的画面的流畅度。
实施例二
本申请实施例提供一种独显插帧方法，图7示出了本申请实施例提供的一种独显插帧方法的流程图，该方法可以应用于电子设备。如图7所示，本申请实施例提供的独显插帧方法可以包括下述的步骤201至步骤203。
步骤201、电子设备通过电子设备中的系统级芯片，基于电子设备待显示的第一内容生成第一数据。
本申请实施例中，上述第一数据的帧率小于第一内容的帧率。
本申请实施例中，电子设备可以通过系统级芯片，基于电子设备待显示的第一内容(例如视频画面或者游戏画面)，生成第一数据，且第一数据的帧率小于第一内容的帧率，即降低系统级芯片的输出帧率，然后，在系统级芯片接收到电子设备中的独显芯片发送的目标TE信号的情况下，电子设备通过系统级芯片向独显芯片发送第一数据，以使得独显芯片对第一数据进行插帧处理，得到第二数据，且该第二数据的帧率大于或等于第一内容的帧率，即提高电子设备显示的内容的帧率或者维持电子设备显示的内容的帧率。
需要说明的是，针对独显芯片、系统级芯片、第一内容等的说明，具体可以参见上述实施例一的相关描述，此处不再赘述。
可选地，本申请实施例中，电子设备可以通过系统级芯片对第一内容进行丢帧处理，也可以通过系统级芯片对第一内容进行其他任意可能的处理，以得到第一数据。
可选地，本申请实施例中，上述步骤201具体可以通过下述的步骤201a实现。
步骤201a、电子设备通过系统级芯片，基于预设帧率对第一内容进行丢帧处理，得到预设帧率的第一数据。
本申请实施例中，上述预设帧率小于第一内容的帧率。
需要说明的是，针对预设帧率、丢帧处理等的说明，具体可以参见上述实施例一的相关描述，此处不再赘述。
本申请实施例中，电子设备可以通过系统级芯片，基于预设帧率对第一内容进行丢帧处理，得到预设帧率的第一数据，即降低系统级芯片的输出帧率，如此，可以降低系统级芯片的功耗，以稳定系统级芯片的输出帧率，避免了系统级芯片功耗较大影响独显插帧功能的问题，从而提升电子设备显示的画面的流畅度。
步骤202、在系统级芯片接收到电子设备中的独显芯片发送的目标TE信号的情况下，电 子设备通过系统级芯片向独显芯片发送第一数据。
可选地，本申请实施例中，电子设备中的独显芯片可以向系统级芯片发送目标TE信号，以使得电子设备通过系统级芯片向独显芯片发送第一数据。
可选地，本申请实施例中，上述目标TE信号可以为一个TE信号，也可以包括多个TE信号。具体的可以根据实际使用需求确定，本申请实施例不做限制。
可选地，本申请实施例中，上述目标TE信号包括多个TE信号。上述步骤202具体可以通过下述的步骤202a实现。
步骤202a、在系统级芯片每接收到一个TE信号的情况下，电子设备通过系统级芯片向独显芯片发送第一数据中的一帧数据，以通过系统级芯片向独显芯片发送第一数据中的多帧数据。
需要说明的是，针对TE信号、第一数据等的说明，具体可以参见上述实施例一的相关描述，此处不再赘述。
本申请实施例中，电子设备通过独显芯片向系统级芯片发送一个TE信号，然后，电子设备可以通过系统级芯片向独显芯片发送一帧数据，如此，在系统级芯片每接收到一个TE信号的情况下，电子设备再通过系统级芯片向独显芯片发送第一数据中的一帧数据，最终通过系统级芯片向独显芯片发送第一数据中的所有帧数据，避免了在独显芯片还未处理完一帧数据时就接收到下一帧数据的情况，从而保证系统级芯片和独显芯片处理数据的时序性。
步骤203、电子设备通过独显芯片，对第一数据进行插帧处理，得到第二数据。
本申请实施例中，上述第二数据的帧率大于或等于第一内容的帧率。
需要说明的是，针对插帧处理、第二数据等的说明，具体可以参见上述实施例一的相关描述，此处不再赘述。
可选地，本申请实施例中，在上述步骤202之前，本申请实施例提供的独显插帧方法还包括下述的步骤301和步骤302。
步骤301、电子设备通过系统级芯片，向独显芯片发送第一指令。
本申请实施例中，上述第一指令中包括预设帧率。
步骤302、电子设备通过独显芯片生成目标TE信号，并通过独显芯片向系统级芯片发送目标TE信号。
本申请实施例中，上述目标TE信号的频率的数值等于预设帧率的数值。
本申请实施例中，电子设备可以通过系统级芯片向独显芯片发送包括预设帧率的第一指令，以使得电子设备通过独显芯片生成频率的数值与该预设帧率的数值相等的TE信号，并通过独显芯片向系统级芯片发送该TE信号，如此，电子设备可以通过系统级芯片向独显芯片发送预设帧率的数据，由于预设帧率小于第一内容的帧率，即电子设备通过降低系统级芯片的输出帧率，以降低系统级芯片的功耗，稳定了系统级芯片的输出帧率，从而提升电子设备显示的画面的流畅度。
可选地，本申请实施例中，上述第一指令中还包括目标帧率。上述步骤203具体可以通过下述的步骤203a实现。
步骤203a、电子设备通过独显芯片，采用目标帧率，对第一数据进行插帧处理，得到第二数据。
需要说明的是，针对目标帧率等的说明，具体可以参见上述实施例一的相关描述，此处不再赘述。
本申请实施例中，电子设备可以通过独显芯片，对帧率小于第一内容的帧率的第一数据进行插帧处理，得到帧率大于或等于第一内容的帧率的第二数据，如此，电子设备可以在降低系统级芯片的功耗的同时，提高或维持电子设备显示的内容的帧率，从而提升电子设备显示的画面的流畅度。
本申请实施例提供一种独显插帧方法，电子设备可以通过系统级芯片，基于电子设备待显示的第一内容，生成第一数据，且第一数据的帧率小于第一内容的帧率，然后，在系统级芯片接收到电子设备中的独显芯片发送的目标TE信号的情况下，电子设备可以通过系统级芯片向独显芯片发送第一数据，以使得独显芯片对第一数据进行插帧处理，得到第二数据，且该第二数据的帧率大于或等于第一内容的帧率。本方案中，由于系统级芯片生成的第一数据的帧率小于电子设备待显示的第一内容的帧率，即降低系统级芯片的输出帧率，然后，独显芯片可以对第一数据进行插帧处理，得到第二数据，以提升电子设备待显示的内容的帧率或者维持电子设备待显示的内容的帧率，如此，通过降低系统级芯片的输出帧率，以避免系统级芯片功耗较大影响独显插帧功能的问题，从而提升了电子设备显示的画面的流畅度。
可选地，本申请实施例中，在上述步骤203之后，本申请实施例提供的独显插帧方法还包括下述的步骤401和步骤402。
步骤401、在独显芯片接收到电子设备中的显示单元发送的第一TE信号的情况下，电子设备通过独显芯片，向显示单元发送第二数据。
本申请实施例中，上述第一TE信号的频率的数值大于或等于第二数据的帧率的数值。
需要说明的是，针对显示单元、第一TE信号等的说明，具体可以参见上述实施例一的相关描述，此处不再赘述。
步骤402、电子设备通过显示单元，基于第二数据显示第二内容。
需要说明的是，针对第二数据、第二内容等的说明，具体可以参见上述实施例一的相关描述，此处不再赘述。
本申请实施例中，电子设备可以通过显示单元接收独显芯片发送的第二数据，并显示该第二数据对应的第二内容，即通过显示单元显示高帧率的内容或者维持显示单元显示的内容，避免了系统级芯片功耗太大影响独显芯片插帧功能的问题，从而提升了电子设备显示的画面的流畅度。
本申请实施例提供的独显插帧方法，执行主体可以为独显插帧装置。本申请实施例中以独显插帧装置执行独显插帧方法为例，说明本申请实施例提供的独显插帧装置。
图8示出了本申请实施例中涉及的独显插帧装置的一种可能的结构示意图。如图8所示，该独显插帧装置70可以包括：生成模块71、发送模块72和处理模块73。
其中，生成模块71，用于通过电子设备中的系统级芯片，基于电子设备待显示的第一内容生成第一数据，该第一数据的帧率小于第一内容的帧率。发送模块72，用于在系统级芯片接收到电子设备中的独显芯片发送的目标显示帧率同步TE信号的情况下，通过系统级芯片向独显芯片发送第一数据。处理模块73，用于通过独显芯片，对第一数据进行插帧处理，得到第二数据，该第二数据的帧率大于或等于第一内容的帧率。
本申请实施例提供一种独显插帧装置，由于系统级芯片生成的第一数据的帧率小于独显插帧装置显示的第一内容的帧率，即降低系统级芯片的输出帧率，然后，独显芯片可以对第一数据进行插帧处理，得到第二数据，以提升独显插帧装置待显示的内容的帧率或者维持独显插帧装置待显示的内容的帧率，如此，通过降低系统级芯片的输出帧率，以避免系统级芯 片功耗较大影响独显插帧功能的问题，从而提升了独显插帧装置显示的画面的流畅度。
在一种可能的实现方式中，上述生成模块71，具体用于通过系统级芯片，基于预设帧率对第一内容进行丢帧处理，得到预设帧率的第一数据。
在一种可能的实现方式中，上述发送模块72，还用于在系统级芯片接收到电子设备中的独显芯片发送的目标TE信号的情况下，通过系统级芯片向独显芯片发送第一数据之前，通过系统级芯片，向独显芯片发送第一指令，该第一指令中包括预设帧率。上述生成模块71，还用于通过独显芯片生成目标TE信号。上述发送模块72，还用于通过独显芯片向系统级芯片发送目标TE信号，该目标TE信号的频率的数值等于预设帧率的数值。
在一种可能的实现方式中，上述第一指令中还包括目标帧率。上述处理模块73，具体用于通过独显芯片，采用目标帧率，对第一数据进行插帧处理，得到第二数据。
在一种可能的实现方式中，上述目标TE信号包括多个TE信号。上述发送模块72，具体用于在系统级芯片每接收到一个TE信号的情况下，通过系统级芯片向独显芯片发送第一数据中的一帧数据，以通过系统级芯片向独显芯片发送第一数据中的多帧数据。
在一种可能的实现方式中，上述独显插帧装置70还包括：显示模块。上述发送模块72，还用于在通过独显芯片，对第一数据进行插帧处理，得到第二数据之后，在独显芯片接收到电子设备中的显示单元发送的第一TE信号的情况下，通过独显芯片，向显示单元发送第二数据，该第一TE信号的频率的数值大于或等于第二数据的帧率的数值。显示模块，用于通过显示单元，基于第二数据显示第二内容。
本申请实施例中的独显插帧装置可以是电子设备，也可以是电子设备中的部件，例如集成电路或芯片。该电子设备可以是终端，也可以为除终端之外的其他设备。示例性的，电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、移动上网装置(Mobile Internet Device，MID)、增强现实(augmented reality，AR)/虚拟现实(virtual reality，VR)设备、机器人、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，本申请实施例不作具体限定。
本申请实施例中的独显插帧装置可以为具有操作系统的装置。该操作系统可以为安卓(Android)操作系统，可以为IOS操作系统，还可以为其他可能的操作系统，本申请实施例不作具体限定。
本申请实施例提供的独显插帧装置能够实现上述方法实施例实现的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
本申请实施例还提供了一种系统级芯片，所述系统级芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于基于电子设备待显示的第一内容生成第一数据，该第一数据的帧率小于第一内容的帧率，所述通信接口用于在接收到电子设备中的独显芯片发送的目标TE信号的情况下，向独显芯片发送第一数据。
可选地，本申请实施例中，上述处理器具体用于基于预设帧率对第一内容进行丢帧处理，得到预设帧率的第一数据。
可选地，本申请实施例中，上述通信接口还用于向独显芯片发送第一指令，该第一指令中包括预设帧率。上述通信接口还用于接收独显芯片发送的目标TE信号，该目标TE信号的频率的数值等于预设帧率的数值。
可选地，本申请实施例中，上述目标TE信号包括多个TE信号。上述通信接口具体用于在每接收到一个TE信号的情况下，向独显芯片发送第一数据中的一帧数据，以向独显芯片 发送第一数据中的多帧数据。
本申请实施例提供的系统级芯片能够实现方法实施例中系统级芯片实现的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
本申请实施例还提供了一种独显芯片，所述独显芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述通信接口用于向电子设备中的系统级芯片发送目标TE信号，并接收系统级芯片发送的第一数据，该第一数据为系统级芯片基于电子设备待显示的第一内容生成的数据，该第一数据的帧率小于第一内容的帧率，所述处理器用于对第一数据进行插帧处理，得到第二数据，该第二数据的帧率大于或等于第一内容的帧率。
可选地，本申请实施例中，上述通信接口还用于接收系统级芯片发送的第一指令，该第一指令中包括预设帧率。上述处理器还用于生成目标TE信号。上述通信接口还用于向系统级芯片发送目标TE信号，该目标TE信号的频率的数值等于预设帧率的数值。
可选地，本申请实施例中，上述第一指令中还包括目标帧率。上述处理器具体用于采用目标帧率，对第一数据进行插帧处理，得到第二数据。
可选地，本申请实施例中，上述目标TE信号包括多个TE信号。上述通信接口具体用于在每发送一个TE信号的情况下，接收系统级芯片发送第一数据中的一帧数据，以接收系统级芯片发送的第一数据中的多帧数据。
可选地，本申请实施例中，上述通信接口还用于在接收到电子设备中的显示单元发送的第一TE信号的情况下，向显示单元发送第二数据，该第一TE信号的频率的数值大于或等于第二数据的帧率的数值。
本申请实施例提供的独显芯片能够实现方法实施例中独显芯片实现的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
可选地，如图9所示，本申请实施例还提供一种电子设备800，包括处理器801，存储器802，存储在存储器802上并可在所述处理器801上运行的程序或指令，该程序或指令被处理器801执行时实现上述独显插帧方法实施例的各个步骤，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，本申请实施例中的电子设备包括上述所述的移动电子设备和非移动电子设备。
图10为实现本申请实施例的一种电子设备的硬件结构示意图。
该电子设备1000包括但不限于：射频单元1001、网络模块1002、音频输出单元1003、输入单元1004、传感器1005、显示单元1006、用户输入单元1007、接口单元1008、存储器1009、以及处理器1010等部件。
本领域技术人员可以理解，电子设备1000还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器1010逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图10中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，在此不再赘述。
其中，处理器1010，用于通过电子设备中的系统级芯片，基于电子设备待显示的第一内容生成第一数据，该第一数据的帧率小于第一内容的帧率；在系统级芯片接收到电子设备中的独显芯片发送的目标TE信号的情况下，通过系统级芯片向独显芯片发送第一数据；通过独显芯片，对第一数据进行插帧处理，得到第二数据，该第二数据的帧率大于或等于第一内 容的帧率。
本申请实施例提供一种电子设备，由于系统级芯片生成的第一数据的帧率小于电子设备显示的第一内容的帧率，即降低系统级芯片的输出帧率，然后，独显芯片可以对第一数据进行插帧处理，得到第二数据，以提升电子设备显示的内容的帧率或者维持电子设备显示的内容的帧率，如此，通过降低系统级芯片的输出帧率，以避免系统级芯片功耗较大影响独显插帧功能的问题，从而提升了电子设备显示的画面的流畅度。
可选地，本申请实施例中，处理器1010，具体用于通过系统级芯片，基于预设帧率对第一内容进行丢帧处理，得到预设帧率的第一数据。
可选地，本申请实施例中，处理器1010，还用于在系统级芯片接收到电子设备中的独显芯片发送的目标TE信号的情况下，通过系统级芯片向独显芯片发送第一数据之前，通过系统级芯片，向独显芯片发送第一指令，该第一指令中包括预设帧率。处理器1010，还用于通过独显芯片生成目标TE信号，并通过独显芯片向系统级芯片发送目标TE信号，该目标TE信号的频率的数值等于预设帧率的数值。
可选地，本申请实施例中，上述第一指令中还包括目标帧率。处理器1010，具体用于通过独显芯片，采用目标帧率，对第一数据进行插帧处理，得到第二数据。
可选地，本申请实施例中，上述目标TE信号包括多个TE信号。处理器1010，具体用于在系统级芯片每接收到一个TE信号的情况下，通过系统级芯片向独显芯片发送第一数据中的一帧数据，以通过系统级芯片向独显芯片发送第一数据中的多帧数据。
可选地，本申请实施例中，处理器1010，还用于在通过独显芯片，对第一数据进行插帧处理，得到第二数据之后，在独显芯片接收到电子设备中的显示单元发送的第一TE信号的情况下，通过独显芯片，向显示单元发送第二数据，该第一TE信号的频率的数值大于或等于第二数据的帧率的数值。显示单元1006，用于基于第二数据显示第二内容。
本申请实施例提供的电子设备能够实现上述方法实施例实现的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
本实施例中各种实现方式具有的有益效果具体可以参见上述方法实施例中相应实现方式所具有的有益效果，为避免重复，此处不再赘述。
应理解的是，本申请实施例中，输入单元1004可以包括图形处理器(Graphics Processing Unit，GPU)10041和麦克风10042，图形处理器10041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。显示单元1006可包括显示面板10061，可以采用液晶显示器、有机发光二极管等形式来配置显示面板10061。用户输入单元1007包括触控面板10071以及其他输入设备10072中的至少一种。触控面板10071，也称为触摸屏。触控面板10071可包括触摸检测装置和触摸控制器两个部分。其他输入设备10072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
存储器1009可用于存储软件程序以及各种数据。存储器1009可主要包括存储程序或指令的第一存储区和存储数据的第二存储区，其中，第一存储区可存储操作系统、至少一个功能所需的应用程序或指令(比如声音播放功能、图像播放功能等)等。此外，存储器1009可以包括易失性存储器或非易失性存储器，或者，存储器1009可以包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、 电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synch link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本申请实施例中的存储器1009包括但不限于这些和任意其它适合类型的存储器。
处理器1010可包括一个或多个处理单元；可选的，处理器1010集成应用处理器和调制解调处理器，其中，应用处理器主要处理涉及操作系统、用户界面和应用程序等的操作，调制解调处理器主要处理无线通信信号，如基带处理器。可以理解的是，上述调制解调处理器也可以不集成到处理器1010中。
本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时使得电子设备实现上述独显插帧方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，所述处理器为上述实施例中所述的电子设备中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器ROM、随机存取存储器RAM、磁碟或者光盘等。
本申请实施例提供一种计算机程序产品，该程序产品被存储在存储介质中，该程序产品被至少一个处理器执行以使得电子设备实现如上述独显插帧方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以计算机软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (26)

  1. 一种独显插帧电路，所述独显插帧电路包括系统级芯片和独显芯片；
    其中，所述系统级芯片用于基于待显示的第一内容生成第一数据，并在接收到所述独显芯片发送的目标显示帧率同步TE信号的情况下，向所述独显芯片发送所述第一数据，所述第一数据的帧率小于所述第一内容的帧率；所述独显芯片用于对所述第一数据进行插帧处理，得到第二数据，所述第二数据的帧率大于或等于所述第一内容的帧率。
  2. 根据权利要求1所述的电路，其中，所述系统级芯片具体用于基于预设帧率对所述第一内容进行丢帧处理，得到所述预设帧率的第一数据。
  3. 根据权利要求1或2所述的电路，其中，所述系统级芯片还用于向所述独显芯片发送第一指令，所述第一指令中包括预设帧率；所述独显芯片还用于生成所述目标TE信号，并向所述系统级芯片发送所述目标TE信号，所述目标TE信号的频率的数值等于所述预设帧率的数值。
  4. 根据权利要求3所述的电路，其中，所述第一指令中还包括目标帧率；所述独显芯片具体用于采用所述目标帧率，对所述第一数据进行插帧处理，得到所述第二数据。
  5. 根据权利要求1所述的电路，其中，所述目标TE信号包括多个TE信号；所述系统级芯片具体用于在每接收到一个TE信号的情况下，向所述独显芯片发送所述第一数据中的一帧数据，以向所述独显芯片发送所述第一数据中的多帧数据。
  6. 根据权利要求1所述的电路，其中，所述独显插帧电路还包括显示单元；所述独显芯片还用于在接收到所述显示单元发送的第一TE信号的情况下，向所述显示单元发送所述第二数据，所述第一TE信号的频率的数值大于或等于所述第二数据的帧率的数值；所述显示单元用于基于所述第二数据显示第二内容。
  7. 一种独显插帧方法，应用于电子设备，所述方法包括：
    通过所述电子设备中的系统级芯片，基于所述电子设备待显示的第一内容生成第一数据，所述第一数据的帧率小于所述第一内容的帧率；
    在所述系统级芯片接收到所述电子设备中的独显芯片发送的目标显示帧率同步TE信号的情况下，通过所述系统级芯片向所述独显芯片发送所述第一数据；
    通过所述独显芯片，对所述第一数据进行插帧处理，得到第二数据，所述第二数据的帧率大于或等于所述第一内容的帧率。
  8. 根据权利要求7所述的方法，其中，所述通过所述电子设备中的系统级芯片，基于所述电子设备待显示的第一内容生成第一数据，包括：
    通过所述系统级芯片，基于预设帧率对所述第一内容进行丢帧处理，得到所述预设帧率的第一数据。
  9. 根据权利要求7或8所述的方法，其中，所述在所述系统级芯片接收到所述电子设备中的独显芯片发送的目标TE信号的情况下，通过所述系统级芯片向所述独显芯片发送所述第一数据之前，所述方法还包括：
    通过所述系统级芯片，向所述独显芯片发送第一指令，所述第一指令中包括预设帧率；
    通过所述独显芯片生成所述目标TE信号，并通过所述独显芯片向所述系统级芯片发送所述目标TE信号，所述目标TE信号的频率的数值等于所述预设帧率的数值。
  10. 根据权利要求9所述的方法，其中，所述第一指令中还包括目标帧率；
    所述通过所述独显芯片，对所述第一数据进行插帧处理，得到第二数据，包括：
    通过所述独显芯片，采用所述目标帧率，对所述第一数据进行插帧处理，得到所述第二数据。
  11. 根据权利要求7所述的方法，其中，所述目标TE信号包括多个TE信号；
    所述在所述系统级芯片接收到所述电子设备中的独显芯片发送的目标TE信号的情况下，通过所述系统级芯片向所述独显芯片发送所述第一数据，包括：
    在所述系统级芯片每接收到一个TE信号的情况下，通过所述系统级芯片向所述独显芯片发送所述第一数据中的一帧数据，以通过所述系统级芯片向所述独显芯片发送所述第一数据中的多帧数据。
  12. 根据权利要求7所述的方法，其中，所述通过所述独显芯片，对所述第一数据进行插帧处理，得到第二数据之后，所述方法还包括：
    在所述独显芯片接收到所述电子设备中的显示单元发送的第一TE信号的情况下，通过所述独显芯片，向所述显示单元发送所述第二数据，所述第一TE信号的频率的数值大于或等于所述第二数据的帧率的数值；
    通过所述显示单元，基于所述第二数据显示第二内容。
  13. 一种独显插帧装置，所述独显插帧装置包括：生成模块、发送模块和处理模块；
    所述生成模块，用于通过电子设备中的系统级芯片，基于所述电子设备待显示的第一内容生成第一数据，所述第一数据的帧率小于所述第一内容的帧率；
    所述发送模块，用于在所述系统级芯片接收到所述电子设备中的独显芯片发送的目标显示帧率同步TE信号的情况下，通过所述系统级芯片向所述独显芯片发送所述第一数据；
    所述处理模块，用于通过所述独显芯片，对所述第一数据进行插帧处理，得到第二数据，所述第二数据的帧率大于或等于所述第一内容的帧率。
  14. 一种系统级芯片，所述系统级芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于基于电子设备待显示的第一内容生成第一数据，所述第一数据的帧率小于所述第一内容的帧率，所述通信接口用于在接收到所述电子设备中的独显芯片发送的目标显示帧率同步TE信号的情况下，向所述独显芯片发送所述第一数据。
  15. 根据权利要求14所述的系统级芯片，其中，所述处理器具体用于基于预设帧率对所述第一内容进行丢帧处理，得到所述预设帧率的第一数据。
  16. 根据权利要求14或15所述的系统级芯片，其中，所述通信接口还用于向所述独显芯片发送第一指令，所述第一指令中包括预设帧率；所述通信接口还用于接收所述独显芯片发送的目标TE信号，所述目标TE信号的频率的数值等于所述预设帧率的数值。
  17. 根据权利要求14所述的系统级芯片，其中，所述目标TE信号包括多个TE信号；所述通信接口具体用于在每接收到一个TE信号的情况下，向所述独显芯片发送所述第一数据中的一帧数据，以向所述独显芯片发送所述第一数据中的多帧数据。
  18. 一种独显芯片，所述独显芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述通信接口用于向电子设备中的系统级芯片发送目标显示帧率同步TE信号，并接收所述系统级芯片发送的第一数据，所述第一数据为所述系统级芯片基于所述电子设备待显示的第一内容生成的数据，所述第一数据的帧率小于所述第一内容的帧率，所述处理器用于对所述第一数据进行插帧处理，得到第二数据，所述第二数据的帧率大于或等于所述第一内 容的帧率。
  19. 根据权利要求18所述的独显芯片，其中，所述通信接口还用于接收所述系统级芯片发送的第一指令，所述第一指令中包括预设帧率；所述处理器还用于生成所述目标TE信号；所述通信接口还用于向所述系统级芯片发送所述目标TE信号，所述目标TE信号的频率的数值等于所述预设帧率的数值。
  20. 根据权利要求19所述的独显芯片，其中，所述第一指令中还包括目标帧率；所述处理器具体用于采用所述目标帧率，对所述第一数据进行插帧处理，得到所述第二数据。
  21. 根据权利要求18所述的独显芯片，其中，所述目标TE信号包括多个TE信号；所述通信接口具体用于在每发送一个TE信号的情况下，接收所述系统级芯片发送所述第一数据中的一帧数据，以接收所述系统级芯片发送的所述第一数据中的多帧数据。
  22. 根据权利要求18所述的独显芯片，其中，所述通信接口还用于在接收到所述电子设备中的显示单元发送的第一TE信号的情况下，向所述显示单元发送所述第二数据，所述第一TE信号的频率的数值大于或等于所述第二数据的帧率的数值。
  23. 一种电子设备，包括如权利要求1至6任一项所述的独显插帧电路，或者包括如权利要求14至17任一项所述的系统级芯片和权利要求18至22任一项所述的独显芯片。
  24. 一种电子设备，包括处理器和存储器，所述存储器存储可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时使得所述电子设备实现如权利要求7至12中任一项所述的独显插帧方法的步骤。
  25. 一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时使得电子设备实现如权利要求7至12中任一项所述的独显插帧方法的步骤。
  26. 一种独显插帧装置，所述装置用于执行如权利要求7至12中任一项所述的独显插帧方法。
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