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WO2023142393A1 - 集成高速续流二极管的碳化硅分离栅mosfet及制备方法 - Google Patents

集成高速续流二极管的碳化硅分离栅mosfet及制备方法 Download PDF

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WO2023142393A1
WO2023142393A1 PCT/CN2022/106142 CN2022106142W WO2023142393A1 WO 2023142393 A1 WO2023142393 A1 WO 2023142393A1 CN 2022106142 W CN2022106142 W CN 2022106142W WO 2023142393 A1 WO2023142393 A1 WO 2023142393A1
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type doped
layer
silicon carbide
source region
ion implantation
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PCT/CN2022/106142
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English (en)
French (fr)
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顾航
高巍
戴茂州
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成都蓉矽半导体有限公司
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Publication of WO2023142393A1 publication Critical patent/WO2023142393A1/zh
Priority to US18/785,583 priority Critical patent/US20240387722A1/en

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    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D62/221—Channel regions of field-effect devices of FETs
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    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
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    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/035—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon carbide [SiC] technology
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    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/143—VDMOS having built-in components the built-in components being PN junction diodes
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    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation

Definitions

  • the invention belongs to the technical field of power semiconductor devices, and in particular relates to a silicon carbide split-gate MOSFET integrated with a high-speed freewheeling diode and a preparation method thereof.
  • SiC a wide bandgap semiconductor material
  • SiC materials have high breakdown electric field strength (4 ⁇ 10 6 V/cm), and high carrier saturation drift velocity (2 ⁇ 10 7 cm/s), high thermal conductivity, and good thermal stability, so it is especially suitable for high-power, high-pressure, high-temperature and radiation-resistant electronic devices.
  • SiC VDMOS is a commonly used device in SiC power devices. Compared with bipolar devices, SiC VDMOS has better frequency characteristics and lower switching losses because it has no charge storage effect. At the same time, the wide bandgap of SiC material makes the working temperature of SiC VDMOS up to 300°C.
  • planar SiC VDMOS there are two problems in the planar SiC VDMOS.
  • One is that the density of the JFET area is relatively high, which introduces a large Miller capacitance, which increases the dynamic loss of the device; the other is that the conduction voltage drop of the parasitic SiC body diode is too high. , and it is a bipolar device with a large reverse recovery current, so it cannot be used directly as a freewheeling diode.
  • a SiC split-gate MOSFET with integrated high-speed freewheeling diode adopts a split gate structure, and shields the electric field at the edge of the polysilicon through the P-type buried layer, which ensures the long-term reliability of the device while fully reducing the Miller capacitance.
  • a high-speed freewheeling diode on the other side of the MOSFET, which is formed by the diode connection method of the split-gate MOSFET (that is, the source-drain is short-circuited).
  • the conduction voltage drop of the diode is adjusted to greatly reduce the conduction voltage drop of the MOSFET body diode.
  • the diode is a unipolar device with no reverse recovery current, which can be turned off quickly and greatly reduces the dynamic loss of the switch.
  • the object of the present invention is to address the problems existing in the prior art and to meet the high-frequency switch application requirements of silicon carbide power semiconductors, and to provide a silicon carbide split-gate MOSFET with integrated high-speed freewheeling diode and a preparation method thereof.
  • a silicon carbide split-gate MOSFET integrating a high-speed freewheeling diode comprising a rear ohmic contact alloy (1), an N-type doped silicon carbide substrate (2), an N-type doped silicon carbide epitaxial layer (3), a P-type doped Miscellaneous well region (4), the first N-type doped source region (51), the second N-type doped source region (52), the P-type doped source region (6), the first P-type doped buried layer ( 71), the second P-type doped buried layer (72), P-type doped diode channel region (8), the first N-type doped conduction layer (91), the second N-type doped conduction layer ( 92), the first gate oxide layer (101), the second gate oxide layer (102), the first interlayer dielectric (111), the second interlayer dielectric (112), the first polysilicon (121), the second polysilicon (122), source metal (13);
  • the N-type doped silicon carbide substrate (2) is located above the back ohmic contact alloy (1); the N-type doped silicon carbide epitaxial layer (3) is located on the N-type doped silicon carbide substrate ( 2) above; the P-type doped well region (4) is located directly above the inside of the N-type doped silicon carbide epitaxial layer (3); the P-type doped source region (6) is located on the P-type doped Right above the inside of the miscellaneous well region (4); the right boundary of the first N-type doped source region (51) is in contact with the left boundary of the P-type doped source region (6); the second N-type doped The left boundary of the impurity source region (52) is in contact with the right boundary of the P-type doped source region (6); the right boundary of the first P-type doped buried layer (71) is in contact with the P-type doped well region (4) left lower boundary contact; the left boundary of the second P-type doped buried layer (72) is in contact with the right lower boundary of the
  • the doping concentration of the N-type doped silicon carbide epitaxial layer (3) ranges from 1E15cm-3 to 1E17cm-3.
  • the first P-type doped buried layer (71) is formed by Al ion implantation, its right boundary is located in the coverage area of the first polysilicon (121), and its left boundary is located in the first polysilicon (121) coverage area. Outside the lateral coverage area of the crystalline silicon (121).
  • the second P-type doped buried layer (72) is formed by Al ion implantation, its left boundary is located in the coverage area of the second polysilicon (122), and its right boundary is located in the second polysilicon (122) coverage area. outside the lateral coverage area of the crystalline silicon (122).
  • the P-type doped diode channel region (8) and the first P-type doped buried layer (71) are implanted at the same plate, and the P-type doped diode channel region (8)
  • the concentration depends on the concentration of the first P-type doped buried layer (71) trailing to the surface.
  • the P-type doped diode channel region (8) is actually the first P-type doped
  • the surface concentration of the doped buried layer (71) therefore, only needs to control the peak concentration of the first P-type doped buried layer (71) to control the concentration of the P-type doped diode channel region (8).
  • the first P-type doped buried layer (71) and the second P-type doped buried layer (72) are implanted in the same plate.
  • the first N-type doped guide layer (91) is formed by P ion implantation, and the right boundary of the first N-type doped guide layer (91) is located in the first P-type doped buried layer In the lateral area covered by (71), its left border is located outside the lateral area covered by the first P-type doped buried layer (71).
  • the second N-type doped guide layer (92) is formed by P ion implantation, and the left boundary of the second N-type doped guide layer (92) is located at the second P-type doped buried layer ( 72) within the lateral region covered by the second P-type doped buried layer (72), and its right border is located outside the lateral region covered by the second P-type doped buried layer (72).
  • the first polysilicon (121) is short-circuited with the source metal (13) in a layout.
  • the present invention also provides a method for preparing a silicon carbide split-gate MOSFET integrated with a high-speed freewheeling diode, comprising the following steps:
  • Step 1 epitaxially forming an N-type doped silicon carbide epitaxial layer (3) on an N-type silicon carbide substrate (2);
  • Step 2 Forming a first barrier layer (21) on the surface of the N-type doped silicon carbide epitaxial layer (3) by chemical vapor deposition, and photoetching the first barrier layer (21) to form a first ion implantation window (1-1) , using high-temperature Al ion implantation to form a P-type doped well region (4); the high temperature refers to a temperature greater than 773K;
  • Step 3 Form a second barrier layer (22) on the surface of the first barrier layer (21) and the P-type doped well region (4) by chemical vapor deposition, and leave the sidewall of the second barrier layer (22) by etching Forming a second ion implantation window (1-2), using high-temperature P ion implantation to form a first N-type doped source region (51) and a second N-type doped source region (52); the high temperature refers to a temperature greater than 773K;
  • Step 4 removing the first barrier layer (21) and the second barrier layer (22), and forming a third barrier layer ( 31), and forming a third ion implantation window (1-3) by photolithography, and forming a P-type doped source region (6) by high temperature Al ion implantation;
  • the high temperature refers to a temperature greater than 773K;
  • Step 5 removing the third barrier layer (31); forming a fourth barrier layer (41) by chemical vapor deposition, forming a fourth ion implantation window (1-4) by photolithography, and forming a fourth barrier layer (1-4) by high temperature Al ion implantation
  • the surface tailing concentration forms the P-type doped diode channel region (8);
  • the high temperature refers to a temperature greater than 773K;
  • Step 6 removing the fourth barrier layer (41); forming the fifth barrier layer (61) by chemical vapor deposition, forming the fifth ion implantation window (1-5) by photolithography, and forming the fifth barrier layer (1-5) by high temperature P ion implantation
  • Step 7 removing the fifth barrier layer (61), and performing high-temperature annealing; the temperature of high-temperature annealing is 1600° C. to 1800° C.; using thermal oxygen oxidation to form a gate oxide layer and annealing, then depositing polysilicon, and performing photolithography forming a first polysilicon (121) and a second polysilicon (122), forming an interlayer dielectric by chemical vapor deposition, forming a first gate oxide layer (101), a second gate oxide layer (102), The first interlayer medium (111), the second interlayer medium (112);
  • Step 8 Deposit Ni alloy, rapid thermal annealing to form ohmic contact, sputter metal Al to form source metal (13), and form back ohmic contact alloy (1).
  • the optimized split gate structure is adopted, which fully reduces the Miller capacitance of the device, thereby reducing the switching loss of the device.
  • a P-type buried layer is used for the gate of the split gate. The fringe electric field of the oxide layer is weakened, thereby improving the long-term reliability of the device;
  • a P-type buried layer is used to form another channel different from the MOSFET channel on the other side of the cell.
  • This channel has the characteristics of low threshold voltage.
  • a channel is made using this channel.
  • a rectifier based on the MOSFET diode connection method compared with the traditional MOSFET body diode, the rectifier has the advantages of reduced conduction voltage, unipolar conduction (no reverse recovery current, no bipolar degradation), which makes this rectifier can be used As the freewheeling diode of MOSFET, the dynamic loss is greatly reduced;
  • MOSFET of the present invention integrates high-speed freewheeling diodes, and they adopt common JFET area and termination area, and this has fully reduced the utilization efficiency of device area, has reduced system cost;
  • Fig. 1 is a schematic structural diagram of a silicon carbide split-gate MOSFET integrating a high-speed freewheeling diode according to an embodiment of the present invention
  • Fig. 2 is the equivalent circuit schematic diagram of a kind of silicon carbide split-gate MOSFET of integrated high-speed freewheeling diode of the embodiment of the present invention
  • FIG. 3 is a schematic diagram of a forward conduction current path of a silicon carbide split-gate MOSFET integrating a high-speed freewheeling diode according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a reverse freewheeling current path of a silicon carbide split-gate MOSFET integrating a high-speed freewheeling diode according to an embodiment of the present invention
  • 5 to 12 are schematic structural diagrams obtained after each process step is completed in a method for manufacturing a silicon carbide split-gate MOSFET integrated with a high-speed freewheeling diode according to an embodiment of the present invention.
  • 1 is the back ohmic contact alloy
  • 2 is the N-type doped silicon carbide substrate
  • 3 is the N-type doped silicon carbide epitaxial layer
  • 4 is the P-type doped well region
  • 51 is the first N-type doped source region
  • 52 is the second N-type doped source region
  • 6 is the P-type doped source region
  • 71 is the first P-type doped buried layer
  • 72 is the second P-type doped buried layer
  • 8 is the P-type doped diode channel 91 is the first N-type doped guide layer
  • 92 is the second N-type doped guide layer
  • 101 is the first gate oxide layer
  • 102 is the second gate oxide layer
  • 111 is the first interlayer dielectric
  • 112 is the second interlayer dielectric
  • 121 is the first polysilicon
  • 122 is the second polysilicon
  • 13 is the source metal
  • 21 is the first barrier layer
  • 1-1 is the first ion implantation window
  • 22 is the
  • this embodiment provides a silicon carbide split-gate MOSFET integrating high-speed freewheeling diodes, including a back ohmic contact alloy (1), an N-type doped silicon carbide substrate (2), an N-type doped carbon Silicon epitaxial layer (3), P-type doped well region (4), first N-type doped source region (51), second N-type doped source region (52), P-type doped source region (6) , the first P-type doped buried layer (71), the second P-type doped buried layer (72), the P-type doped diode channel region (8), the first N-type doped diversion layer (91), The second N-type doped conduction layer (92), the first gate oxide layer (101), the second gate oxide layer (102), the first interlayer dielectric (111), the second interlayer dielectric (112), the second One polysilicon (121), the second polysilicon (122), source metal (13);
  • the N-type doped silicon carbide substrate (2) is located above the back ohmic contact alloy (1); the N-type doped silicon carbide epitaxial layer (3) is located on the N-type doped silicon carbide substrate ( 2) above; the P-type doped well region (4) is located directly above the inside of the N-type doped silicon carbide epitaxial layer (3); the P-type doped source region (6) is located on the P-type doped Right above the inside of the miscellaneous well region (4); the right boundary of the first N-type doped source region (51) is in contact with the left boundary of the P-type doped source region (6); the second N-type doped The left boundary of the impurity source region (52) is in contact with the right boundary of the P-type doped source region (6); the right boundary of the first P-type doped buried layer (71) is in contact with the P-type doped well region (4) left lower boundary contact; the left boundary of the second P-type doped buried layer (72) is in contact with the right lower boundary of the
  • the doping concentration of the N-type doped silicon carbide epitaxial layer (3) ranges from 1E15cm-3 to 1E17cm-3.
  • the first P-type doped buried layer (71) is formed by Al ion implantation, its right boundary is located in the coverage area of the first polysilicon (121), and its left boundary is located in the first polysilicon (121) coverage area. outside the lateral footprint of silicon (121).
  • the second P-type doped buried layer (72) is formed by Al ion implantation, its left boundary is located in the coverage area of the second polysilicon (122), and its right boundary is located in the second polysilicon (122) coverage area. outside the lateral footprint of silicon (122).
  • the P-type doped diode channel region (8) and the first P-type doped buried layer (71) are implanted at the same plate, and the P-type doped diode channel region (8)
  • the concentration depends on the concentration of the first P-type doped buried layer (71) trailing to the surface.
  • the P-type doped diode channel region (8) is actually the first P-type doped
  • the surface concentration of the doped buried layer (71) therefore, only needs to control the peak concentration of the first P-type doped buried layer (71) to control the concentration of the P-type doped diode channel region (8).
  • the first P-type doped buried layer (71) and the second P-type doped buried layer (72) are implanted in the same plate.
  • the first N-type doped guide layer (91) is formed by P ion implantation, and the right boundary of the first N-type doped guide layer (91) is located in the first P-type doped buried layer ( In the lateral region covered by 71), its left boundary is outside the lateral region covered by the first P-type doped buried layer (71).
  • the second N-type doped guide layer (92) is formed by P ion implantation, and the left boundary of the second N-type doped guide layer (92) is located at the second P-type doped buried layer (72 ) within the lateral region covered by the second P-type doped buried layer (72), and its right boundary is outside the lateral region covered by the second P-type doped buried layer (72).
  • the first polysilicon (121) is short-circuited with the source metal (13) in the layout.
  • FIG. 2 An equivalent circuit diagram of a silicon carbide split-gate MOSFET integrated with a high-speed freewheeling diode in this embodiment is shown in FIG. 2 .
  • the gate of the right MOSFET region is applied with a forward bias voltage, the channel is opened, and electrons flow from the source to the drain under the action of the electric field, forming a current Ids from the drain to the source, as shown in the figure 3; when the device is turned off and enters the third quadrant working state, the positive potential difference from the source to the drain makes the diode region conduct, forming a current Isd from the source to the drain, as shown in Figure 4.
  • the present embodiment provides a kind of preparation method of described a kind of silicon carbide split-gate MOSFET of integrated high-speed freewheeling diode, comprises the following steps:
  • Step 1 Epitaxially forming an N-type doped silicon carbide epitaxial layer (3) on an N-type silicon carbide substrate (2); obtaining the structure shown in Figure 5;
  • Step 2 Forming a first barrier layer (21) on the surface of the N-type doped silicon carbide epitaxial layer (3) by chemical vapor deposition, and photoetching the first barrier layer (21) to form a first ion implantation window (1-1)
  • a P-type doped well region (4) is formed by high-temperature Al ion implantation; the structure shown in Figure 6 is obtained; the high-temperature means that the temperature is greater than 773K;
  • Step 3 Form a second barrier layer (22) on the surface of the first barrier layer (21) and the P-type doped well region (4) by chemical vapor deposition, and leave the sidewall of the second barrier layer (22) by etching
  • the second ion implantation window (1-2) is formed, and the first N-type doped source region (51) and the second N-type doped source region (52) are formed by high-temperature P ion implantation; the structure shown in Fig. 7 is obtained; High temperature refers to the temperature greater than 773K;
  • Step 4 removing the first barrier layer (21) and the second barrier layer (22), and forming a third barrier layer ( 31), and form a third ion implantation window (1-3) by photolithography, and form a P-type doped source region (6) by high-temperature Al ion implantation; obtain the structure shown in Figure 8; the high temperature means that the temperature is greater than 773K;
  • Step 5 removing the third barrier layer (31); forming a fourth barrier layer (41) by chemical vapor deposition, forming a fourth ion implantation window (1-4) by photolithography, and forming a fourth barrier layer (1-4) by high temperature Al ion implantation
  • the surface tailing concentration forms the P-type doped diode channel region (8); the structure shown in Figure 9 is obtained; the high temperature refers to a temperature greater than 773K;
  • Step 6 removing the fourth barrier layer (41); forming the fifth barrier layer (61) by chemical vapor deposition, forming the fifth ion implantation window (1-5) by photolithography, and forming the fifth barrier layer (1-5) by high temperature P ion implantation
  • High temperature refers to the temperature greater than 773K;
  • Step 7 removing the fifth barrier layer (61), and performing high-temperature annealing; the temperature of high-temperature annealing is 1600° C. to 1800° C.; using thermal oxygen oxidation to form a gate oxide layer and annealing, then depositing polysilicon, and performing photolithography forming a first polysilicon (121) and a second polysilicon (122), forming an interlayer dielectric by chemical vapor deposition, forming a first gate oxide layer (101), a second gate oxide layer (102), The first interlayer medium (111), the second interlayer medium (112); obtain the structure as shown in Figure 11;
  • Step 8 Deposit Ni alloy, rapid thermal annealing to form ohmic contact, sputter metal Al to form source metal (13), and form back ohmic contact alloy (1), to obtain the structure shown in Fig. 12 .

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及一种集成高速续流二极管的碳化硅分离栅MOSFET及其制备方法，属于功率半导体器件技术领域。本发明的MOSFET采用分离栅的设计，以降低器件的开关损耗。为了防止分离栅结构所带来的栅氧可靠性问题，加入了P型埋层降低多晶硅边缘栅氧化层的电场强度。进一步地，加入了N型导流层，将电流从沟道引入到器件的漂移区。此外，为了降低碳化硅MOSFET寄生体二极管的导通压降以及引入单极导电模式，在MOSFET的元胞另一边引入了一种基于MOS结构的高速续流二极管，相对于传统做法，本发明的高速续流二极管采用P型埋层的表面拖尾形成沟道区，即在不增加额外版次的情况下尽量降低了高速续流二极管的导通压降。

Description

集成高速续流二极管的碳化硅分离栅MOSFET及制备方法 技术领域
本发明属于功率半导体器件技术领域，具体涉及一种集成高速续流二极管的碳化硅分离栅MOSFET及其制备方法。
背景技术
宽禁带半导体材料SiC是制备高压电力电子器件的理想材料，相对于Si材料，SiC材料具有击穿电场强度高(4×10 6V/cm)、载流子饱和漂移速度高(2×10 7cm/s)、热导率高、热稳定性好等优点，因此特别适合用于大功率、高压、高温和抗辐射的电子器件中。
SiC VDMOS是SiC功率器件中较为常用的一种器件，相对于双极型的器件，由于SiC VDMOS没有电荷存储效应，所以其拥有更好的频率特性以及更低的开关损耗。同时SiC材料的宽禁带使得SiC VDMOS的工作温度可以高达300℃。
但是平面型SiC VDMOS存在两个问题，其一是JFET区的密度较大，引入了较大的密勒电容，增加了器件的动态损耗；其二是寄生的SiC体二极管导通压降太高，并且其为双极型器件，存在较大的反向恢复电流，无法直接作为续流二极管使用。
为了解决这两个问题，我们提出了一种集成高速续流二极管的碳化硅分离栅MOSFET。该结构采用分离栅结构，并通过P型埋层屏蔽了多晶硅边缘的电场，在充分降低密勒电容的同时保证了器件的长期可靠性。此外，我们在MOSFET的另一侧集成了一种高速续流二极管，该二极管采用分离栅MOSFET的二极管接法(即源漏短接)形成，我们通过调节P型埋层的注入剂量可以方便地调节该二极管的导通压降，从而大幅度降低MOSFET体二极管的导通压降，另外，该二极管为单极型器件，无反向恢复电流，可以快速开断，大幅降低开断动态损耗。
发明内容
本发明的目的是针对现有技术存在的问题，针对碳化硅功率半导体的高频开关应用 需求，提供一种集成高速续流二极管的碳化硅分离栅MOSFET及其制备方法。
为解决上述技术问题，本发明技术方案如下：
一种集成高速续流二极管的碳化硅分离栅MOSFET，包括背面欧姆接触合金(1)，N型掺杂碳化硅衬底(2)，N型掺杂碳化硅外延层(3)，P型掺杂井区(4)，第一N型掺杂源区(51)，第二N型掺杂源区(52)，P型掺杂源区(6)，第一P型掺杂埋层(71)，第二P型掺杂埋层(72)，P型掺杂二极管沟道区(8)，第一N型掺杂导流层(91)，第二N型掺杂导流层(92)，第一栅氧化层(101)，第二栅氧化层(102)，第一层间介质(111)，第二层间介质(112)，第一多晶硅(121)，第二多晶硅(122)，源极金属(13)；
所述N型掺杂碳化硅衬底(2)位于所述背面欧姆接触合金(1)上方；所述N型掺杂碳化硅外延层(3)位于所述N型掺杂碳化硅衬底(2)上方；所述P型掺杂井区(4)位于所述N型掺杂碳化硅外延层(3)内部正上方；所述P型掺杂源区(6)位于所述P型掺杂井区(4)的内部正上方；所述第一N型掺杂源区(51)的右边界和所述P型掺杂源区(6)左边界接触；所述第二N型掺杂源区(52)的左边界和所述P型掺杂源区(6)右边界接触；所述第一P型掺杂埋层(71)的右边界和所述P型掺杂井区(4)左侧下方边界接触；所述第二P型掺杂埋层(72)的左边界和所述P型掺杂井区(4)的右侧下方边界接触；所述P型掺杂二极管沟道区(8)的右边界和所述第一N型掺杂源区(51)左边界接触；所述第一N型掺杂导流层(91)的右边界和所述P型掺杂二极管沟道区(8)左边界接触；所述第二N型掺杂导流层(92)的左边界和所述P型井区(4)的右侧上方边界接触；所述第一栅氧化层(101)位于所述N型掺杂碳化硅外延层(3)、第一N型掺杂导流层(91)、P型掺杂二极管沟道区(8)、第一N型掺杂源区(51)上方；所述第二栅氧化层(102)位于所述N型掺杂碳化硅外延层(3)、第二N型掺杂导流层(92)、第二N型掺杂源区(52)上方；所述第一层间介质(111)位于所述第一栅氧化层(101)的上方；所述第二层间介质(112)位于所述第二栅氧化层(102)的上方；所述第一多晶硅(121)位于所述第一层间介质(111)的内部下方与所述第一栅氧化层 (101)接触，且位于第一N型掺杂导流层(91)、P型掺杂二极管沟道区(8)、第一N型掺杂源区(51)上方；所述第二多晶硅(122)位于所述第二层间介质(112)的内部下方与所述第二栅氧化层(102)接触，且位于第二N型掺杂导流层(92)、P型掺杂井区(4)、第二N型掺杂源区(52)上方；所述源极金属(13)位于所述第一层间介质(111)、第二层间介质(112)、第一N型掺杂源区(51)、第二N型掺杂源区(52)、P型掺杂源区(6)上方。
作为优选方式，所述N型掺杂碳化硅外延层(3)的掺杂浓度范围为1E15cm-3～1E17cm-3。
作为优选方式，所述第一P型掺杂埋层(71)为Al离子注入形成，其右边界位于所述第一多晶硅(121)的覆盖区域内，左边界位于所述第一多晶硅(121)的横向覆盖区域外。
作为优选方式，所述第二P型掺杂埋层(72)为Al离子注入形成，其左边界位于所述第二多晶硅(122)的覆盖区域内，右边界位于所述第二多晶硅(122)的横向覆盖区域外。
作为优选方式，所述P型掺杂二极管沟道区(8)与所述第一P型掺杂埋层(71)同版注入形成，且所述P型掺杂二极管沟道区(8)的浓度取决于所述第一P型掺杂埋层(71)拖尾至表面的浓度。因为第一P型掺杂埋层(71)是通过离子注入形成，而离子注入在纵向上的浓度分布类似于高斯分布，P型掺杂二极管沟道区(8)实则就是第一P型掺杂埋层(71)的表面浓度，因此只需要控制第一P型掺杂埋层(71)的峰值浓度即可控制P型掺杂二极管沟道区(8)的浓度。
作为优选方式，所述第一P型掺杂埋层(71)与所述第二P型掺杂埋层(72)同版注入形成。
作为优选方式，所述第一N型掺杂导流层(91)为P离子注入形成，第一N型掺杂导流层(91)的右边界位于所述第一P型掺杂埋层(71)所覆盖的横向区域内、其左边界位于所述第一P型掺杂埋层(71)所覆盖的横向区域外。
作为优选方式，所述第二N型掺杂导流层(92)为P离子注入形成，第二N型掺杂导流层(92)左边界位于所述第二P型掺杂埋层(72)所覆盖的横向区域内、其右边界位于所述第二P型掺杂埋层(72)所覆盖的横向区域外。
作为优选方式，所述第一多晶硅(121)在版图与所述源极金属(13)短接。
本发明还提供一种所述的一种集成高速续流二极管的碳化硅分离栅MOSFET的制备方法，包括以下步骤：
步骤1：在N型碳化硅衬底(2)上外延形成N型掺杂碳化硅外延层(3)；
步骤2：在N型掺杂碳化硅外延层(3)表面通过化学气相淀积形成第一阻挡层(21)，光刻第一阻挡层(21)形成第一离子注入窗口(1-1)，采用高温Al离子注入形成P型掺杂井区(4)；所述高温指温度大于773K；
步骤3：采用化学气象淀积在第一阻挡层(21)及P型掺杂井区(4)表面形成第二阻挡层(22)，通过刻蚀留下第二阻挡层(22)侧壁形成第二离子注入窗口(1-2)，采用高温P离子注入形成第一N型掺杂源区(51)和第二N型掺杂源区(52)；所述高温指温度大于773K；
步骤4：去除所述第一阻挡层(21)和所述第二阻挡层(22)，采用化学气象淀积在所述N型掺杂碳化硅外延层(3)表面形成第三阻挡层(31)，并通过光刻形成第三离子注入窗口(1-3)，采用高温Al离子注入形成P型掺杂源区(6)；所述高温指温度大于773K；
步骤5：去除所述第三阻挡层(31)；采用化学气相淀积形成第四阻挡层(41)，通过光刻形成第四离子注入窗口(1-4)，采用高温Al离子注入形成第一P型掺杂埋层(71)和第二P型掺杂埋层(72)，且所述第一P型掺杂埋层(71)和第二P型掺杂埋层(72)的表面拖尾浓度形成所述P型掺杂二极管沟道区(8)；所述高温指温度大于773K；
步骤6：去除所述第四阻挡层(41)；采用化学气相淀积形成第五阻挡层(61)，采用光刻形成第五离子注入窗口(1-5)，采用高温P离子注入形成第一N型掺杂导流层(91)和第二N型掺杂导流层(92)，并且将第一N型掺杂源区(51)的宽度拓展；所述高温 指温度大于773K；
步骤7：去除所述第五阻挡层(61)，并进行高温退火；高温退火的温度为1600℃～1800℃；采用热氧氧化形成栅氧化层并退火，然后淀积形多晶硅，通过光刻形成第一多晶硅(121)和第二多晶硅(122)，通过化学气相淀积形成层间介质，光刻形成第一栅氧化层(101)、第二栅氧化层(102)、第一层间介质(111)、第二层间介质(112)；
步骤8：淀积Ni合金，快速热退火形成欧姆接触，溅射金属Al形成源极金属(13)，形成背面欧姆接触合金(1)。
与现有技术相比，本发明的有益效果是：
(1)采用了优化的分离栅结构，充分减小了器件的密勒电容，从而降低了器件的开关损耗，另外，为了保护分离栅的栅氧化层，采用P型埋层对分离栅的栅氧化层的边缘电场进行了削弱，从而提高了器件的长期可靠性；
(2)用P型埋层在元胞的另一侧形成了不同于MOSFET沟道的另一沟道，该沟道具有低阈值电压的特点，在此基础上利用这一沟道制作了一种基于MOSFET二极管接法的整流器，相比于传统MOSFET的体二极管，该整流器具有导通压降低、单极导通(无反向恢复电流、无双极退化)的优点，这使得此整流器可以用作MOSFET的续流二极管，大幅度降低了动态损耗；
(3)本发明的MOSFET集成了高速的续流二极管，它们采用公用的JFET区和终端区，这充分降低了器件面积的利用效率，降低了系统成本；
(4)MOSFET与高速续流二极管的集成使得芯片面积被放大(大于单颗MOSFET或单颗二极管)，这让器件在过流的时候可以承受更大的功率，从而提高了器件的鲁棒性。
附图说明
图1为本发明实施例的一种集成高速续流二极管的碳化硅分离栅MOSFET的结构示意图；
图2为本发明实施例的一种集成高速续流二极管的碳化硅分离栅MOSFET的等效 电路示意图；
图3为本发明实施例的一种集成高速续流二极管的碳化硅分离栅MOSFET的正向导通电流路径示意图；
图4为本发明实施例的一种集成高速续流二极管的碳化硅分离栅MOSFET的反向续流电流路径示意图；
图5～图12为本发明实施例的一种集成高速续流二极管的碳化硅分离栅MOSFET的制备方法中各工艺步骤完成后得到的结构示意图。
1为背面欧姆接触合金，2为N型掺杂碳化硅衬底，3为N型掺杂碳化硅外延层，4为P型掺杂井区，51为第一N型掺杂源区，52为第二N型掺杂源区，6为P型掺杂源区，71为第一P型掺杂埋层，72为第二P型掺杂埋层，8为P型掺杂二极管沟道区，91为第一N型掺杂导流层，92为第二N型掺杂导流层，101为第一栅氧化层，102为第二栅氧化层，111为第一层间介质，112为第二层间介质，121为第一多晶硅，122为第二多晶硅，13为源极金属；21为第一阻挡层，1-1为第一离子注入窗口，22为第二阻挡层，1-2为第二离子注入窗口，31为第三阻挡层，1-3为第三离子注入窗口，41为第四阻挡层，1-4为第四离子注入窗口，61为第五阻挡层)，1-5为第五离子注入窗口。
具体实施方式
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。
实施例1
如图1所示，本实施例提供一种集成高速续流二极管的碳化硅分离栅MOSFET，包括背面欧姆接触合金(1)，N型掺杂碳化硅衬底(2)，N型掺杂碳化硅外延层(3)，P型掺杂井区(4)，第一N型掺杂源区(51)，第二N型掺杂源区(52)，P型掺杂源区(6)，第一P型掺杂埋层(71)，第二P型掺杂埋层(72)，P型掺杂二极管沟道区(8)，第一N型掺杂导流层(91)，第二N型掺杂导流层(92)，第一栅氧化层(101)，第二栅氧化层(102)，第一层间介质(111)，第二层间介质(112)，第一多晶硅(121)， 第二多晶硅(122)，源极金属(13)；
所述N型掺杂碳化硅衬底(2)位于所述背面欧姆接触合金(1)上方；所述N型掺杂碳化硅外延层(3)位于所述N型掺杂碳化硅衬底(2)上方；所述P型掺杂井区(4)位于所述N型掺杂碳化硅外延层(3)内部正上方；所述P型掺杂源区(6)位于所述P型掺杂井区(4)的内部正上方；所述第一N型掺杂源区(51)的右边界和所述P型掺杂源区(6)左边界接触；所述第二N型掺杂源区(52)的左边界和所述P型掺杂源区(6)右边界接触；所述第一P型掺杂埋层(71)的右边界和所述P型掺杂井区(4)左侧下方边界接触；所述第二P型掺杂埋层(72)的左边界和所述P型掺杂井区(4)的右侧下方边界接触；所述P型掺杂二极管沟道区(8)的右边界和所述第一N型掺杂源区(51)左边界接触；所述第一N型掺杂导流层(91)的右边界和所述P型掺杂二极管沟道区(8)左边界接触；所述第二N型掺杂导流层(92)的左边界和所述P型井区(4)的右侧上方边界接触；所述第一栅氧化层(101)位于所述N型掺杂碳化硅外延层(3)、第一N型掺杂导流层(91)、P型掺杂二极管沟道区(8)、第一N型掺杂源区(51)上方；所述第二栅氧化层(102)位于所述N型掺杂碳化硅外延层(3)、第二N型掺杂导流层(92)、第二N型掺杂源区(52)上方；所述第一层间介质(111)位于所述第一栅氧化层(101)的上方；所述第二层间介质(112)位于所述第二栅氧化层(102)的上方；所述第一多晶硅(121)位于所述第一层间介质(111)的内部下方与所述第一栅氧化层(101)接触，且位于第一N型掺杂导流层(91)、P型掺杂二极管沟道区(8)、第一N型掺杂源区(51)上方；所述第二多晶硅(122)位于所述第二层间介质(112)的内部下方与所述第二栅氧化层(102)接触，且位于第二N型掺杂导流层(92)、P型掺杂井区(4)、第二N型掺杂源区(52)上方；所述源极金属(13)位于所述第一层间介质(111)、第二层间介质(112)、第一N型掺杂源区(51)、第二N型掺杂源区(52)、P型掺杂源区(6)上方。
具体的，所述N型掺杂碳化硅外延层(3)的掺杂浓度范围为1E15cm-3～1E17cm-3。
具体的，所述第一P型掺杂埋层(71)为Al离子注入形成，其右边界位于所述第一 多晶硅(121)的覆盖区域内，左边界位于所述第一多晶硅(121)的横向覆盖区域外。
具体的，所述第二P型掺杂埋层(72)为Al离子注入形成，其左边界位于所述第二多晶硅(122)的覆盖区域内，右边界位于所述第二多晶硅(122)的横向覆盖区域外。
具体的，所述P型掺杂二极管沟道区(8)与所述第一P型掺杂埋层(71)同版注入形成，且所述P型掺杂二极管沟道区(8)的浓度取决于所述第一P型掺杂埋层(71)拖尾至表面的浓度。因为第一P型掺杂埋层(71)是通过离子注入形成，而离子注入在纵向上的浓度分布类似于高斯分布，P型掺杂二极管沟道区(8)实则就是第一P型掺杂埋层(71)的表面浓度，因此只需要控制第一P型掺杂埋层(71)的峰值浓度即可控制P型掺杂二极管沟道区(8)的浓度。
具体的，所述第一P型掺杂埋层(71)与所述第二P型掺杂埋层(72)同版注入形成。
具体的，所述第一N型掺杂导流层(91)为P离子注入形成，第一N型掺杂导流层(91)的右边界位于所述第一P型掺杂埋层(71)所覆盖的横向区域内、其左边界位于所述第一P型掺杂埋层(71)所覆盖的横向区域外。
具体的，所述第二N型掺杂导流层(92)为P离子注入形成，第二N型掺杂导流层(92)左边界位于所述第二P型掺杂埋层(72)所覆盖的横向区域内、其右边界位于所述第二P型掺杂埋层(72)所覆盖的横向区域外。
具体的，所述第一多晶硅(121)在版图与所述源极金属(13)短接。
本实施例的一种集成高速续流二极管的碳化硅分离栅MOSFET的等效电路图如图2所示。当器件正常工作时右边MOSFET区域的栅极被施加以正向偏置电压，沟道开启，电子在电场的作用下从源极流向漏极，形成自漏极向源极的电流Ids，如图3所示；当器件关断进入第三象限工作状态时，源极到漏极的正电势差使得二极管区域导通，形成自源极至漏极的电流Isd，如图4所示。
实施例2
本实施例提供一种所述的一种集成高速续流二极管的碳化硅分离栅MOSFET的制备 方法，包括以下步骤：
步骤1：在N型碳化硅衬底(2)上外延形成N型掺杂碳化硅外延层(3)；得到如图5结构；
步骤2：在N型掺杂碳化硅外延层(3)表面通过化学气相淀积形成第一阻挡层(21)，光刻第一阻挡层(21)形成第一离子注入窗口(1-1)，采用高温Al离子注入形成P型掺杂井区(4)；得到如图6结构；所述高温指温度大于773K；
步骤3：采用化学气象淀积在第一阻挡层(21)及P型掺杂井区(4)表面形成第二阻挡层(22)，通过刻蚀留下第二阻挡层(22)侧壁形成第二离子注入窗口(1-2)，采用高温P离子注入形成第一N型掺杂源区(51)和第二N型掺杂源区(52)；得到如图7结构；所述高温指温度大于773K；
步骤4：去除所述第一阻挡层(21)和所述第二阻挡层(22)，采用化学气象淀积在所述N型掺杂碳化硅外延层(3)表面形成第三阻挡层(31)，并通过光刻形成第三离子注入窗口(1-3)，采用高温Al离子注入形成P型掺杂源区(6)；得到如图8结构；所述高温指温度大于773K；
步骤5：去除所述第三阻挡层(31)；采用化学气相淀积形成第四阻挡层(41)，通过光刻形成第四离子注入窗口(1-4)，采用高温Al离子注入形成第一P型掺杂埋层(71)和第二P型掺杂埋层(72)，且所述第一P型掺杂埋层(71)和第二P型掺杂埋层(72)的表面拖尾浓度形成所述P型掺杂二极管沟道区(8)；得到如图9结构；所述高温指温度大于773K；
步骤6：去除所述第四阻挡层(41)；采用化学气相淀积形成第五阻挡层(61)，采用光刻形成第五离子注入窗口(1-5)，采用高温P离子注入形成第一N型掺杂导流层(91)和第二N型掺杂导流层(92)，并且将第一N型掺杂源区(51)的宽度拓展；得到如图10结构；所述高温指温度大于773K；
步骤7：去除所述第五阻挡层(61)，并进行高温退火；高温退火的温度为1600℃～1800℃；采用热氧氧化形成栅氧化层并退火，然后淀积形多晶硅，通过光刻形成第一多 晶硅(121)和第二多晶硅(122)，通过化学气相淀积形成层间介质，光刻形成第一栅氧化层(101)、第二栅氧化层(102)、第一层间介质(111)、第二层间介质(112)；得到如图11结构；
步骤8：淀积Ni合金，快速热退火形成欧姆接触，溅射金属Al形成源极金属(13)，形成背面欧姆接触合金(1)，得到如图12结构。

Claims (10)

  1. 一种集成高速续流二极管的碳化硅分离栅MOSFET，其特征在于，包括背面欧姆接触合金(1)，N型掺杂碳化硅衬底(2)，N型掺杂碳化硅外延层(3)，P型掺杂井区(4)，第一N型掺杂源区(51)，第二N型掺杂源区(52)，P型掺杂源区(6)，第一P型掺杂埋层(71)，第二P型掺杂埋层(72)，P型掺杂二极管沟道区(8)，第一N型掺杂导流层(91)，第二N型掺杂导流层(92)，第一栅氧化层(101)，第二栅氧化层(102)，第一层间介质(111)，第二层间介质(112)，第一多晶硅(121)，第二多晶硅(122)，源极金属(13)；
    所述N型掺杂碳化硅衬底(2)位于所述背面欧姆接触合金(1)上方；所述N型掺杂碳化硅外延层(3)位于所述N型掺杂碳化硅衬底(2)上方；所述P型掺杂井区(4)位于所述N型掺杂碳化硅外延层(3)内部正上方；所述P型掺杂源区(6)位于所述P型掺杂井区(4)的内部正上方；所述第一N型掺杂源区(51)的右边界和所述P型掺杂源区(6)左边界接触；所述第二N型掺杂源区(52)的左边界和所述P型掺杂源区(6)右边界接触；所述第一P型掺杂埋层(71)的右边界和所述P型掺杂井区(4)左侧下方边界接触；所述第二P型掺杂埋层(72)的左边界和所述P型掺杂井区(4)的右侧下方边界接触；所述P型掺杂二极管沟道区(8)的右边界和所述第一N型掺杂源区 (51)左边界接触；所述第一N型掺杂导流层(91)的右边界和所述P型掺杂二极管沟道区(8)左边界接触；所述第二N型掺杂导流层(92)的左边界和所述P型井区(4)的右侧上方边界接触；所述第一栅氧化层(101)位于所述N型掺杂碳化硅外延层(3)、第一N型掺杂导流层(91)、P型掺杂二极管沟道区(8)、第一N型掺杂源区(51)上方；所述第二栅氧化层(102)位于所述N型掺杂碳化硅外延层(3)、第二N型掺杂导流层(92)、第二N型掺杂源区(52)上方；所述第一层间介质(111)位于所述第一栅氧化层(101)的上方；所述第二层间介质(112)位于所述第二栅氧化层(102)的上方；所述第一多晶硅(121)位于所述第一层间介质(111)的内部下方与所述第一栅氧化层(101)接触，且位于第一N型掺杂导流层(91)、P型掺杂二极管沟道区(8)、第一N型掺杂源区(51)上方；所述第二多晶硅(122)位于所述第二层间介质(112)的内部下方与所述第二栅氧化层(102)接触，且位于第二N型掺杂导流层(92)、P型掺杂井区(4)、第二N型掺杂源区(52)上方；所述源极金属(13)位于所述第一层间介质(111)、第二层间介质(112)、第一N型掺杂源区(51)、第二N型掺杂源区(52)、P型掺杂源区(6)上方。
  2. 根据权利要求1所述的一种集成高速续流二极管的碳化硅分离栅MOSFET，其特征在于：所述N型掺杂碳化硅外延层(3)的掺杂浓度范围为1E15cm-3～1E17cm-3。
  3. 根据权利要求1所述的一种集成高速续流二极管的碳化硅分离栅MOSFET，其特征在于：所述第一P型掺杂埋层(71)为Al离子注入形成，其右边界位于所述第一多晶硅(121)的覆盖区域内，左边界位于所述第一多晶硅(121)的横向覆盖区域外。
  4. 根据权利要求1所述的一种集成高速续流二极管的碳化硅分离栅MOSFET，其特征在于：所述第二P型掺杂埋层(72)为Al离子注入形成，其左边界位于所述第二多晶硅(122)的覆盖区域内，右边界位于所述第二多晶硅(122)的横向覆盖区域外。
  5. 根据权利要求1所述的一种集成高速续流二极管的碳化硅分离栅MOSFET，其特征在于：所述P型掺杂二极管沟道区(8)与所述第一P型掺杂埋层(71)同版注入形成，且所述P型掺杂二极管沟道区(8)的浓度取决于所述第一P型掺杂埋层(71)拖尾至表 面的浓度。
  6. 根据权利要求1所述的一种集成高速续流二极管的碳化硅分离栅MOSFET，其特征在于：所述第一P型掺杂埋层(71)与所述第二P型掺杂埋层(72)同版注入形成。
  7. 根据权利要求1所述的一种集成高速续流二极管的碳化硅分离栅MOSFET，其特征在于：所述第一N型掺杂导流层(91)为P离子注入形成，第一N型掺杂导流层(91)的右边界位于所述第一P型掺杂埋层(71)所覆盖的横向区域内、其左边界位于所述第一P型掺杂埋层(71)所覆盖的横向区域外。
  8. 根据权利要求1所述的一种集成高速续流二极管的碳化硅分离栅MOSFET，其特征在于：所述第二N型掺杂导流层(92)为P离子注入形成，第二N型掺杂导流层(92)左边界位于所述第二P型掺杂埋层(72)所覆盖的横向区域内、其右边界位于所述第二P型掺杂埋层(72)所覆盖的横向区域外。
  9. 根据权利要求1所述的一种集成高速续流二极管的碳化硅分离栅MOSFET，其特征在于：所述第一多晶硅(121)在版图与所述源极金属(13)短接。
  10. 根据权利要求1至9任意一项所述的一种集成高速续流二极管的碳化硅分离栅MOSFET的制备方法，其特征在于包括以下步骤：
    步骤1：在N型碳化硅衬底(2)上外延形成N型掺杂碳化硅外延层(3)；
    步骤2：在N型掺杂碳化硅外延层(3)表面通过化学气相淀积形成第一阻挡层(21)，光刻第一阻挡层(21)形成第一离子注入窗口(1-1)，采用高温Al离子注入形成P型掺杂井区(4)；所述高温指温度大于773K；
    步骤3：采用化学气象淀积在第一阻挡层(21)及P型掺杂井区(4)表面形成第二阻挡层(22)，通过刻蚀留下第二阻挡层(22)侧壁形成第二离子注入窗口(1-2)，采用高温P离子注入形成第一N型掺杂源区(51)和第二N型掺杂源区(52)；所述高温指温度大于773K；
    步骤4：去除所述第一阻挡层(21)和所述第二阻挡层(22)，采用化学气象淀积在所述N型掺杂碳化硅外延层(3)表面形成第三阻挡层(31)，并通过光刻形成第三离子 注入窗口(1-3)，采用高温Al离子注入形成P型掺杂源区(6)；所述高温指温度大于773K；
    步骤5：去除所述第三阻挡层(31)；采用化学气相淀积形成第四阻挡层(41)，通过光刻形成第四离子注入窗口(1-4)，采用高温Al离子注入形成第一P型掺杂埋层(71)和第二P型掺杂埋层(72)，且所述第一P型掺杂埋层(71)和第二P型掺杂埋层(72)的表面拖尾浓度形成所述P型掺杂二极管沟道区(8)；所述高温指温度大于773K；
    步骤6：去除所述第四阻挡层(41)；采用化学气相淀积形成第五阻挡层(61)，采用光刻形成第五离子注入窗口(1-5)，采用高温P离子注入形成第一N型掺杂导流层(91)和第二N型掺杂导流层(92)，并且将第一N型掺杂源区(51)的宽度拓展；所述高温指温度大于773K；
    步骤7：去除所述第五阻挡层(61)，并进行高温退火；高温退火的温度为1600℃～1800℃；采用热氧氧化形成栅氧化层并退火，然后淀积形多晶硅，通过光刻形成第一多晶硅(121)和第二多晶硅(122)，通过化学气相淀积形成层间介质，光刻形成第一栅氧化层(101)、第二栅氧化层(102)、第一层间介质(111)、第二层间介质(112)；
    步骤8：淀积Ni合金，快速热退火形成欧姆接触，溅射金属Al形成源极金属(13)，形成背面欧姆接触合金(1)。
PCT/CN2022/106142 2022-01-26 2022-07-16 集成高速续流二极管的碳化硅分离栅mosfet及制备方法 WO2023142393A1 (zh)

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