WO2023065272A1

WO2023065272A1 - Phase-change memory device and operation method thereof

Info

Publication number: WO2023065272A1
Application number: PCT/CN2021/125507
Authority: WO
Inventors: Xiaojun Sun; Xiang FU; Jianping Li; Mingchao Ma; Shuze ZHANG; Jigang DU; Shuai Gao
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2021-10-22
Filing date: 2021-10-22
Publication date: 2023-04-27
Also published as: CN115843380A

Abstract

A memory device includes a plurality of banks, each bank including memory cells, a plurality of cache modules, each cache module configured to store an address and a data of the respective bank, and a plurality of control modules, each control module configured to determine whether each cache module has any address and data stored therein, in response to determining that each cache module has stored address and stored data therein, retrieve the stored address and the stored data from the cache module and execute a write operation to the respective memory cells of the bank, and in response to retrieving the stored address and the stored data from the cache module, allow the bank to receive a next controlling signal.

Description

PHASE-CHANGE MEMORY DEVICE AND OPERATION METHOD THEREOF

BACKGROUND

The present disclosure relates to phase-change memory (PCM) devices and operation methods thereof.

A PCM cell can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change material in the PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data.

The write operation of a memory cell in a bank of a memory cell array, such as a PCM cell, can be triggered according to a write command, and an address coincided with the write command. The data is then sent to the memory cell in a respective row and column according to the address.

SUMMARY

In one aspect, a memory device includes a plurality of banks, each bank including memory cells being arranged into rows and columns, a plurality of cache modules, each cache module is configured to store an address and a data of the respective bank, and a plurality of control modules, each control module is configured to determine whether each cache module has any address and data stored therein, in response to determining that each cache module has stored address and stored data therein, retrieve the stored address and the stored data from the cache module and execute a write operation to the respective memory cells of the bank according to the stored address, and in response to retrieving the stored address and the stored data from the cache module, allow the bank to receive a next controlling signal.

In another aspect, a system includes a memory device including a plurality of banks, each bank includes memory cells being arranged into rows and columns, an interface configured to direct a controlling signal including a command, an address, and a data into the banks, a plurality of cache modules, and a plurality of control modules, and a memory controller coupled to the memory device and configured to control the memory device. Each cache module is configured to store the address and the data of the respective bank. Each control module is configured to determine whether each cache module has any address and data stored therein, in response to determining that each cache module has stored address and stored data therein, retrieve the stored address and the stored data from the cache module, and execute a write operation to the respective memory cells of the bank according to the stored address, and in response to retrieving the stored address and the stored data from the cache module, allow the bank to receive a next controlling signal.

In yet another aspect, a method for operating a memory device, the memory device including a plurality of banks, each bank including memory cells being arranged into rows and columns, a cache module, and a control module coupled to the cache module, the method including in response to receiving a controlling signal including a command, an address, and a data, determining whether the command corresponds to a write operation, in response to determining that the command corresponds to the write operation, send the address and the data to the cache module of the bank, determining whether each cache module has any address and data stored therein, and in response to determining that each cache module has the stored address and the stored data therein, retrieve the stored address and the stored data from the cache module, and execute the write operation to the respective memory cells of the bank.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a block diagram of an exemplary system having a memory device, according to some aspects of the present disclosure.

FIG. 2 illustrates a schematic diagram of an exemplary memory device including peripheral circuits, according to some aspects of the present disclosure.

FIG. 3 illustrates a schematic diagram of an exemplary memory device including a phase-change memory (PCM) cell, according to some aspects of the present disclosure.

FIG. 4 illustrates a block diagram of an exemplary memory device including a memory cell array and peripheral circuits, according to some aspects of the present disclosure.

FIG. 5 illustrates a block diagram of an exemplary memory device including banks having control modules and first-in-first-out (FIFO) modules, according to some aspects of the present disclosure.

FIG. 6 illustrates a flowchart of an exemplary method for operating a memory device in a write operation, according to some aspects of the present disclosure.

FIG. 7 illustrates a timing chart showing an exemplary write operation of a memory device, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. In addition, the term “couple” , “coupled to” , or “coupled between” may be understood as not necessarily intended to be “physically joined or attached, ” i.e., direct attachment, but can also be interpreted by indirect connection through an intermediate component.

Phase-change memory (PCM) cells are non-volatile memory devices that store data using a phase-change material. PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials, e.g., chalcogenide alloys, based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. A “set” state is a low resistance state of the PCM cell that can be obtained by creating crystalline regions in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated at a crystallization temperature for a sufficient duration. A “reset” state, on the contrary, is a high resistance state of the PCM cell that can be obtained by creating amorphous regions in the chalcogenide material. Amorphous can be created when the chalcogenide material is heated above its melting temperature and then quickly quenched to create a formation of amorphous. The “set” state can be referred to as an “on” state, while the “reset” state can be referred to as an “off” state.

A memory cell array may include multiple banks. Each bank may include multiple rows and columns of storage units (e.g., memory cells) . Each bank in the memory cell array can start a read or write operation according to a read or write command. And then, the selected memory cells of respective rows and columns in the bank are read or written according to addresses following the respective command. A data is then sent to selected memory cells according to the addresses. During the operations, the transmission of commands, addresses, and data are triggered during one or more clock cycles or clock edges (e.g., rising edge or falling edge) . However, the commands, addresses, and data for read or write operations to memory devices are not coincident during the same clock cycle or clock edge because the data is read from/written to the memory devices after receiving a read/write command and a read/write address, thus creating a delay to queue for the data being read from/written to the memory array during the read or write operation. The delay may include one or more clock cycles and may significantly increase the operation time when executing multiple operations continuously. This delay is especially significant in a write operation of a memory device such as a phase-change random access memory (PCRAM) application.

A write operation of a memory device, such as a PCM device, can be triggered according to a write command, and an address coincided with the write command. The data is then sent to a memory cell of the memory device in a respective row and column according to the address. However, because each bank can only be accessed by a write operation once at a time, the switching between write operations may require additional time to queue before triggering the subsequent write operation. The time delay between the switching reduces the overall performance of the memory device.

Generally, a write operation of a bank in a PCM device may require 500 nanosecond (ns) to complete a cycle of a write operation, which is much longer than a Dynamic Random Access Memory (DRAM) device or NAND device. As such, it requires approximately 500 ns from one write command to a subsequent write command. Theses write commands, corresponding addresses, and data are controlled and sent to each bank by a memory controller of the PCM device via a data input/output (I/O) . The write command, addresses, and data may occupy the data I/O as it is transported from the memory controller to the respective bank. The long write request to the memory cell of the bank may block the read requests or other requests on the critical paths (e.g., the data I/O or any buffers or caches therebefore or thereafter) , incurring adverse impact on the performance of the entire memory device.

To address one or more of the aforementioned issues, the present disclosure introduces a solution in which a cache module, such as a first-in-first-out (FIFO) module, and a control module coupled to the cache module, are introduced into each bank of a memory cell array of a PCM device. The control module is configured to determine whether the FIFO module in each bank has a new address and data to be retrieved. In response to the FIFO module has a new address and data to be retrieved, the control module is configured to take out the new address and data and execute the write operation to the bank according to the new address and data. The control module is configured to iterate or repeat the processes until the FIFO module becomes empty (i.e., no address and data being stored in the FIFO module) . Also, a memory controller of the PCM device is configured to send a write command, addresses, and data into each bank. And the control module is configured to receive a new (i.e., next) controlling signal having a new command, address, and data, and to store the new addresses and the data in the FIFO module of the respective bank in response to the old (i.e., previous) address and data stored in the FIFO module has been retrieved. By storing addresses and data in the FIFO module of each bank and automatically executing the write operation (i.e., write data) into the memory cells of each bank after the address and data are retrieved, the memory controller and the data I/O that originally occupied by the write command, addresses, and data may be relieved and available to other operations because the write command, address, and data have been saved in the FIFO module of each bank, and also because the memory controller and the data I/O need not to wait for the completion of the write operation and can proceed to other operations. As a result, the process of write operations can be less time-consuming and thus increase the overall efficiency and performance of the memory device.

FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device, according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in FIG. 1, system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor of an electronic device, such as a central processing unit (CPU) , or a system-on-chip (SoC) , such as an application processor (AP) . In some implementations, host 108 can be configured to send or receive data to or from memory devices 104. In some implementations, the host can be a user logic, or a user interface such that the user may give instructions to the host and transmit the instructions to the memory devices or the memory array.

Memory device 104 can be any memory device disclosed in the present disclosure. As disclosed below in detail, memory device 104, such as PCRAM, DRAM, or NAND Flash memory device, can include a clock input, a command bus, an address bus, a data input, multiple banks, multiple interface module, and multiple finite state machine (FSM) modules, according to some implementations.

Memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104, according to some implementations. Memory controller 106 can manage the data stored in memory device 104 and communicate with host 108. In some implementations, memory controller 106 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 106 is designed for operating in a high duty-cycle environment solid-state drives (SSDs) or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller 106 can be configured to control operations of memory device 104, such as read, erase, and program operations. Memory controller 106 can also be configured to manage various functions with respect to the data stored or to be stored in memory device 104 including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device 104. Any other suitable functions may be performed by memory controller 106 as well, for example, formatting memory device 104. Memory controller 106 can communicate with an external device (e.g., host 108) according to a particular communication protocol. For example, memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc. Furthermore, memory controller 106 can also be configured to control operations of memory device 104 to perform methods in accordance with some implementations of the present disclosure.

FIG. 2 illustrates a schematic circuit diagram of an exemplary memory device 200 including peripheral circuits, according to some aspects of the present disclosure. Memory device 200 can be an example of memory device 104 in FIG. 1. Memory device 200 can include a memory cell array 201 and peripheral circuits 202 coupled to memory cell array 201. Memory cell array 201 can include one or more banks 204. Each bank 204 includes word lines 214, bit lines 216, and memory cells 208 formed between word lines 214 and bit lines 216. In some implementations, each memory cells 208 can include a PCM element (not shown) in series with a selector (not shown) . In some implementations, the memory cells 208 can also be a DRAM cell which includes a paired transistor and capacitor. To operate each bank 204 of memory cell array 201, a word line voltage (V _w) can be applied to each word line 214, and a bit line voltage (V _b) can be applied to each bit line 216.

FIG. 3 illustrates a side view of a cross-section of a memory device 300 having a PCM element in series with a selector. Memory device 300 includes one or more parallel bit lines 304 (i.e., corresponding to bit line 216 in FIG. 2) above a substrate 302 and one or more parallel word lines 316 (i.e., corresponding to word line 214 in FIG. 2) above bit lines 304. Memory device 300 also includes one or more PCM cells 301 (i.e., corresponding to memory cell 208 in FIG. 2) each disposed at an intersection of a respective pair of bit line 304 and word line 316. Adjacent PCM cells 301 are separated by an insulating structure 322. Each PCM cell 301 includes a selector 308 and a PCM element 312 above selector 308. Each PCM cell 301 further includes three

electrodes

306, 310, and 314 vertically (e.g., in the z-direction) between a respective bit line 304, selector 308, PCM element 312, and a respective word line 316, respectively.

Selector 308 may include an ovonic threshold switch (OTS) selector having an OTS material, such as zinc telluride (ZnTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage (Va) is higher than the threshold voltage is applied (Vth) . At lower voltage (|Va| < Vth) , the high resistance of the OTS selector in its off-state keeps the off-state current (Ioff) low. At higher voltage (|Va| > Vth) , the OTS selector undergoes the OTS phenomenon and switches to the on-state with low resistance; thus, the current through the OTS selector in the on-state (Ion) increases. The volatile on-state is maintained as long as high voltage is supplied.

It is noted that PCM element 312 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change element can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. Therefore, as mentioned above, a write operation of a memory cell may become the bottleneck of the performance of the memory device, which requires the longest time in operations. This is because, during the “set” or “reset” process of a write operation, the PCM cell sustains for a long time until the amorphous-crystalline transformation completes and the resistance reaches the targeted range.

FIG. 4 illustrates a block diagram of an exemplary memory device 400 (e.g., corresponding to 104 in FIG. 1) including a memory cell array 401 (e.g., corresponding to 201 in FIG. 2) , and peripheral circuits, according to some aspects of the present disclosure. Memory cell array 401 may include one or more banks 404 (e.g., corresponding to 204 in FIG. 2) , such as bank 0, bank 1, bank 2, bank 3, etc. In some implementations, memory cells 405 of memory cell array 401 includes PCM cells 301 as in FIG. 3.

As shown in FIG. 4, page buffer/sense amplifier 402 can be coupled to memory cells 405 and configured to read and program (write) data from and to memory cells 405 according to the control signals from control module 411. In one example, page buffer/sense amplifier 402 may store one page of program data (write data) to be programmed into one page of memory cell array 201 (e.g., in FIG. 2) . In another example, page buffer/sense amplifier 402 may perform program verify operations to ensure that the data has been properly programmed into memory cells 208 coupled to selected word line 214. In still another example, page buffer/sense amplifier 402 may also sense the low power signals from selected bit line 216 that represents a data bit stored in memory cells 208 and amplify the small voltage swing to recognizable logic levels in a read operation.

Column decoder/bit line driver 406 can be coupled to memory cells 405 and control module 411 and configured to be controlled by control module 411 and select one or more memory cells (e.g., selected memory cell 208) and bit lines (e.g., selected bit line 216) . Column decoder/bit line driver 406 can be further configured to drive selected bit line 216.

Input/output (I/O) data bus 418 can be coupled to page buffer/sense amplifier 402 and/or column decoder/bit line driver 406 and configured to direct (route) the data input to the selected memory cells 208 of memory cell array 201, as well as the data output from the selected memory cells.

Row decoder/word line driver 408 can be coupled to control module 411 and memory cells 405 and configured to be controlled by control module 411 and select one or more memory cells (e.g., selected memory cell 208) of memory cell array 201 and a selected word line (e.g., selected word line 214) . Row decoder/word line driver 408 can be further configured to drive selected word line 214.

Interface 416 is configured to receive a controlling signal including a clock signal, a command signal, an address signal, or a data signal from a host (e.g., 108 in FIG, 1) . The clock signal is received via a clock bus 421 coupled to interface 416. The command signal is received via a command bus 423 coupled to interface 416. The address signal is received via an address bus 425 coupled to interface 416. The data signal is received via a data bus 427 coupled to interface 416.

Control modules 411 may include a fixed logic unit such as a logic gate, a multiplexer, a flip-flop, a state machine, or a discrete hardware circuit performing a given logic function that is known at the time of device manufacture. In some implementations, control module 411 can be implemented by microprocessors, microcontrollers (a.k.a. microcontroller units (MCUs) ) , digital signal processors (DSPs) , application-specific integrated circuits (ASICs) , field-programmable gate arrays (FPGAs) , programmable logic devices (PLDs) , state machines, gated logic, discrete hardware circuits, and other suitable hardware, firmware, and/or software configured to perform the various functions described. In some implementations, control module 411 is coupled to word line driver 408 and configured to direct the controlling signal received from interface 416 into banks 404 of memory cell array 401 via word line driver 408.

Cache modules/registers 413 can be coupled to control module 411 or included in the control module 411. Control modules/registers 413 can include state registers, command registers, and address registers for storing state information, command operation codes (OP codes) , and command addresses. In some implementations, the address and data received from I/O data bus 418 may be stored in cache modules/registers 413. Each cache module/register 413 may include one or more caches (not shown) . Each cache includes at least two cache pages (not shown) , for instance, a first cache page and a second cache page. Each cache page may at least store an address and a data in a single write operation. The address and data stored in cache module/register 413 may be retrieved by control module 411 and executed to be written into respective memory cells 405.

Each bank 404 can further include a clock path 420 coupled to and from page buffer/sense amplifier 402 and configured to transfer clock signals to and from page buffer/sense amplifier 402. Clock path 420 can be coupled to interface 416 as well to transfer clock signals to interface 416 in order to synchronize the input and output of the data to and from I/O data bus 418 in read or write operations.

Each bank 404 includes memory cells 405 being arranged in rows and columns, one or more cache modules/registers 413 coupled to memory cells 405, and one or more control modules 411coupled to respective cache modules/registers 413, according to some aspects of the present disclosure. It is noted that each control module 411 and each cache modules/registers 413 may be included in each bank 404 or coupled to each bank 404.

FIG. 5 illustrates a block diagram of a memory device 500 (e.g., corresponding to 104 in FIG. 1) including one or more banks 504 (e.g., corresponding to banks 204 in FIG. 2 or 404 in FIG. 4) in a memory cell array 501 (e.g., corresponding to memory cell array 201 in FIG. 2 or memory cell array 401 in FIG. 4) . Each bank 504 include a control module 511 (e.g., corresponding to control module 411) , and a FIFO module 513 (e.g., corresponding to cache module 413) coupled to respective control module 511, according to some aspects of the present disclosure. As shown in FIG. 5, a plurality of banks 504 of memory cell array 501 are coupled to an interface 416 to which clock bus 421, command bus 423, address bus 425, and data bus 427 are connected.

Each control module 511 may include a fixed logic unit such as a logic gate, a multiplexer, a flip-flop, a state machine, or a discrete hardware circuit performing a given logic function that is known at the time of device manufacture. In some implementations, each control module 511 is configured to determine whether each FIFO module 513 in the respective bank 504 has address and data stored. And, in response to each FIFO module 513 has address and data stored, each control module 511 is configured to retrieve the address and the data stored in each FIFO module 513 and execute the write operation to write the data into respective memory cells (e.g., memory cells 405 in FIG. 4) of the respective bank 504 according to the address. After the address and the data being retrieved from the FIFO module 513, each control module 511 is configured to allow receiving the next controlling signal from interface 416 to bank 504. Once the next controlling signal is allowed to be received by bank 504, control module 511 may again control to store a new address and data to FIFO module 513. In some implementations, each control module 511 may also include a programable logic unit such as a programable logic array (PLA) . Each PLA may include multiple programmable AND gate arrays linking to multiple programmable OR gate arrays, where the connections therebetween can be modified or altered by the user to perform the intended functions.

Each FIFO module 513 may include one or more FIFO caches. In some implementations, FIFO module 513 may include a FIFO cache (not shown) which includes at least two cache pages (not shown) , for instance, a first cache page and a second cache page. Each cache page may at least store an address and data in a single write operation. When the stored address and the stored data in the first cache page are retrieved from the FIFO cache of FIFO module 513 because the first cache page is the oldest cache page, the new address and data received from I/O data bus 418 may replace or overwrite the first cache page and thus become the newest cache page. And the second cache page now becomes the oldest cache page. In some implementations, the new address and data received from I/O data bus 418 may be stored in the second cache page if the second cache page is empty. It is noted that the oldest cache page refers to a cache page having the address and the data stored in such cache page for the longest time among all the cache pages, while the newest cache page refers to a cache page having the address and the data stored in such cache page for the shortest time among all the cache pages. It is also noted that there may be more than two cache pages in the FIFO caches and more than a FIFO cache in each FIFO module 513, such that more write commands, addresses, and data may be stored in FIFO module 513 of bank 404 rather than in memory controller 106, interface 416 or any other buffers therebefore, thereafter. Therefore, the originally occupied memory controller 106, interface 416 or any other buffers therebefore, thereafter, may be relieved and available. The number of FIFO caches in each FIFO module and the number of cache pages in each FIFO cache may depend on the hardware overhead in each bank 504. For instance, each FIFO module 513 may include no more than 4 cache pages such that the hardware overhead and the complexity of designing such FIFO module may not be too high. It is also noted that the cache pages herein refer to any suitable storage units that are used to speed up the access simply by page replacement. Therefore, each cache page may have a fixed size, for instance, a size of 16 bits for storing the data.

Each bank 504 of memory cell array 501 may include an array FSM (not shown) configured to execute a write operation for each bank 504. That is, the array FSM is configured to write data into memory cells of bank 504. In some implementations, the array FSM includes a state register, and a flip-flop coupled to the state register.

FIG. 6 illustrates a flowchart of an exemplary method 600 for operating a memory device, according to some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein. Method 600 may be implemented by control module 411, control modules 511, and FIFO modules 513. It is understood that the operations shown in method 600 may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 6. FIGs. 5-6 may be discussed together.

Referring to FIG. 6, method 600 starts at operation 602 in which, in response to receiving a controlling signal including a command, an address, and data, the command that corresponds to a write operation is determined. For example, control module 411 (e.g., in FIG. 4) is configured to identify that the controlling signal includes a write operation command before starting the subsequent write operation to bank 504. The write operation includes writing the data into memory cells 405 of respective rows and columns of bank 504 according to the address.

Method 600 proceeds to operation 604, as illustrated in FIG. 6 in which, in response to determining that the command corresponds to the write operation, the address and the data are sent to a respective FIFO module of a respective bank. For example, after the command is determined to be corresponding to the write operation, the address and the data are sent to and stored in a respective FIFO module 513 of a respective bank 504, as shown in FIG. 5. The address and the data may be stored in an empty cache page or the oldest cache page after the stored address and stored data being retrieved out.

Method 600 proceeds to operation 606, as illustrated in FIG. 6 in which, whether each FIFO module has any address and data (e.g., the stored address and the stored data, this includes the newly received address and data stored in the empty cache page) stored therein is determined, and in response to determining that each FIFO module has the stored address and the stored data therein, the write operation to respective memory cells of the bank is executed. The write operation to respective memory cells may include setting or resetting the respective memory cells. For example, each control module 511 is configured to determine whether each FIFO module 513 has stored address and stored data therein. And in response to determining that each FIFO module 513 has the stored address and the stored data therein, each control module 511 is configured to retrieve the stored address and the stored data from FIFO module 513 and execute the write operation (e.g., write the retrieved data) to respective memory cells 405 of bank 404 according to the retrieved address. If there is no pre-existed stored address and data in FIFO module 513, the newly received address and data stored in the empty cache page may also be retrieved from FIFO module 513.

Method 600 proceeds to operation 608, as illustrated in FIG. 6 in which, in response to retrieving the stored address and the stored data from the FIFO module, the bank is allowed to receive the next controlling signal. For example, in response to retrieving the stored address and the stored data from FIFO module 513, bank 504 is allowed to receive the next controlling signal. Because the previous address and data have being retrieved, the next address and data in the next controlling signal may be then stored in FIFO module 513 and replace or overwrite the previous address and data or being stored in the empty cache pages. In some implementations, the above-mentioned processes may be repeated or iterated until FIFO module 513 becomes empty (i.e., no command, address, and data are stored in FIFO module 513) . After that, the array FSM of bank 504 becomes idle.

FIG. 7 illustrates a timing chart showing the exemplary method 600 of the write operation of the memory device, according to some aspects of the present disclosure. As shown in FIG. 7, the data (i.e., data queue a. k. a. DQ) is transmitted following the command and address (i.e., CA) via the interface (e.g., interface 416 in FIG. 5) . During the receiving of the controlling signal, the FIFO module (e.g., FIFO module 513) and the array FSM of the respective bank 504 may stay in the idle state. After the address and the data are sent to a respective FIFO module (e.g., FIFO module 513) of a respective bank (e.g., bank 504) , a FIFO push FSM, which is labeled as FIFO_push, may be triggered to start FIFO module 513. After the FIFO push FSM is triggered, it may store the address and data in the FIFO caches of FIFO module 513. And in response to that an array FSM of respective bank 504 is in the idle state, or the previous write operation is completed, the FIFO push FSM may be triggered to execute the next write operation, which is to write the data into memory cells of the respective bank 504 according to the address. In some implementations, the FIFO push FSM may also represent to start the FIFO and forward to a next state, for instance, from empty state to in-use state. FIFO module 513 may also include a FIFO count FSM, which is labeled as FIFO_cnt, configured to record and count the number of storing the address and the data being performed. This FIFO count FSM allows users to monitor how many times the address and the data being stored, modify the process by inserting other operations therebetween, or stop the write operation at a certain number of times based on the number of addresses and the data being stored. FIFO module 513 may also include a FIFO pop FSM, which is labeled as FIFO_pop, configured to function as a switch to terminate the previous write operation and activate the next write operation. In some implementations, the FIFO pop FSM may also represent to end a previous state and to forward to a next state, for instance, from in-use state to empty state. The FIFO push FSM, the FIFO count FSM, and the FIFO pop FSM can be controlled by control module 511 of respective bank 504. In some implementations, the FIFO push FSM, the FIFO count FSM, or the FIFO pop FSM may include a state register, and a flip-flop coupled to the state register.

Furthermore, as shown in FIG. 7, the command and the address may require 8 clock cycles (i.e., one cycle for the command and seven cycles for addresses) for each write operation, according to some implementations. And the data may require 8 clock cycles for 16 bits data for each write operation. Also, as shown in FIG. 7, since there are 16 clock cycles between two consecutive commands, a minimum 16 ns time interval is required before receiving the next command. However, the write operation may require 500 ns which consequently becomes the bottleneck of continuous operations. Conventionally, the next command may have to wait until the completion of the previous write operation and block the read requests or other requests on the critical paths (e.g., interface 416 or any buffers or caches therebefore or thereafter) , resulting in an adverse effect on the performance of the entire memory device. In the present disclosure, the next command may not have to wait until the completion of the previous write operation and can be received and stored in FIFO module 513 of respective bank 504 immediately after the previous command, address, and data are retrieved out of FIFO module 513 and executing the previous write operation. The next command, address, and data may be then stored in FIFO module 513 of respective bank 504 after the previous command, address, and data are retrieved out of FIFO module 513 to be executed in the write operation of memory cells and therefore leave the cache page (e.g., the oldest cache page) of FIFO module 513 empty or ready to be replaced or overwritten by the next command, address, and data. By using solutions provided in the present disclosure, the bottleneck problem is relieved, and the performance of the memory device can be significantly improved.

According to one aspect of the present disclosure, a memory device includes a plurality of banks, each bank including memory cells being arranged into rows and columns, a plurality of cache modules, each cache module is configured to store an address and a data of the respective bank, and a plurality of control modules, each control module is configured to determine whether each cache module has any address and data stored therein, in response to determining that each cache module has stored address and stored data therein, retrieve the stored address and the stored data from the cache module and execute a write operation to the respective memory cells of the bank according to the stored address, and in response to retrieving the stored address and the stored data from the cache module, allow the bank to receive a next controlling signal.

In some implementations, the cache module includes a first-in-first-out (FIFO) module.

In some implementations, the FIFO module includes a FIFO cache having at least two cache pages capable of storing the address and the data.

In some implementations, the two cache pages include a first cache page and a second cache page. The address and the data of the controlling signal are stored in the first cache page, and a next address and a next data of the next controlling signal are stored in the second cache page.

In some implementations, each FIFO module includes a FIFO push finite state machine (FSM) configured to be triggered to start the FIFO module and to store the address and the data in the FIFO module.

In some implementations, each FIFO module includes a FIFO count FSM configured to record a number of storing the address and the data being performed.

In some implementations, each FIFO module includes a FIFO pop FSM configured to terminate a previous write operation and activate a next write operation.

In some implementations, each bank includes a respective cache module of the plurality of cache modules, and a respective control module of the plurality of control modules coupled to the respective cache module.

In some implementations, each bank includes an array FSM configured to write the data into the memory cells of the bank.

In some implementations, the memory cell includes a phase-change memory (PCM) device.

In some implementations, the write operation includes setting or resetting the PCM device.

According to another aspect of the present disclosure, a system includes a memory device including a plurality of banks, each bank includes memory cells being arranged into rows and columns, an interface configured to direct a controlling signal including a command, an address, and a data into the banks, a plurality of cache modules, and a plurality of control modules, and a memory controller coupled to the memory device and configured to control the memory device. Each cache module is configured to store the address and the data in the respective bank. Each control module is configured to determine whether each cache module has any address and data stored therein, in response to determining that each cache module has stored address and stored data therein, retrieve the stored address and the stored data from the cache module and execute a write operation to the respective memory cells of the bank according to the stored address, and in response to retrieving the stored address and the stored data from the cache module, allow the bank to receive a next controlling signal.

In some implementations, the system further includes a host coupled to the memory controller and configured to transmit the data to and from the memory device.

In some implementations, the control module is configured to, in response to receiving the controlling signal, determine that the command corresponds to the write operation, and direct the address and the data to be stored in the cache module.

In some implementations, the system further includes a clock bus configured to transmit a clock signal, an address bus configured to transmit the address, and a data bus configured to transmit the data. The clock bus, the address bus, and the data bus are coupled to the interface.

In some implementations, the two cache pages include a first cache page and a second cache page, the address and the data of the controlling signal are stored in the first cache page, and a next address and a next data of the next controlling signal are stored in the second cache page.

According to yet another aspect of the present disclosure, a method for operating a memory device, the memory device including a plurality of banks, each bank including memory cells being arranged into rows and columns, a cache module, and a control module coupled to the cache module, the method including in response to receiving a controlling signal including a command, an address, and a data, determining whether the command corresponds to a write operation, in response to determining that the command corresponds to the write operation, send the address and the data to the cache module of the bank, determining whether each cache module has any address and data stored therein, and in response to determining that each cache module has the stored address and the stored data therein, retrieve the stored address and the stored data from the cache module, and execute the write operation to the respective memory cells of the bank.

In some implementations, the method further includes receiving a next controlling signal and repeating processes until the cache module becomes empty. The processes repeated includes in response to receiving the next controlling signal comprising a next command, a next address, and a next data, determining whether the next command corresponds to the write operation, in response to determining that the next command corresponds to the write operation, send the next address and the next data to the cache module of the bank, determining whether each cache module has any address and data stored therein, and in response to determining that each cache module has the stored address and the stored data therein, retrieve the stored address and the stored data from the cache module, and execute the write operation to the respective memory cells of the bank.

In some implementations, the two cache pages include a first cache page and a second cache page, and when the stored address and the stored data in the first cache page are retrieved from the cache module, the first cache page is the oldest cache page.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

A memory device, comprising:

a plurality of banks, each bank comprising memory cells being arranged into rows and columns;

a plurality of cache modules, wherein each cache module is configured to store an address and a data of a respective one of the banks; and

a plurality of control modules, wherein each control module is configured to:

determine whether each cache module has any address and data stored therein;

in response to determining that each cache module has stored address and stored data therein, retrieve the stored address and the stored data from the cache module and execute a write operation to the respective memory cells of the bank according to the stored address; and

in response to retrieving the stored address and the stored data from the cache module, allow the bank to receive a next controlling signal.
The memory device of claim 1, wherein the cache module comprises a first-in-first-out (FIFO) module.
The memory device of claim 2, wherein the FIFO module comprises a FIFO cache having at least two cache pages capable of storing the address and the data.
The memory device of claim 3, wherein the two cache pages comprise a first cache page and a second cache page, the address and the data are stored in the first cache page, and a next address and a next data of the next controlling signal are stored in the second cache page.
The memory device of any one of claims 2-4, wherein each FIFO module comprises a FIFO push FSM configured to be triggered to start the FIFO module and to store the address and the data in the FIFO module.
The memory device of any one of claims 2-5, wherein each FIFO module comprises a FIFO count finite state machine (FSM) configured to record a number of storing the address and the data being performed.
The memory device of any one of claims 2-6, wherein each FIFO module comprises a FIFO pop FSM configured to terminate a previous write operation and activate a next write operation.
The memory device of any one of claims 1-7, wherein each bank comprises:

a respective cache module of the plurality of cache modules; and

a respective control module of the plurality of control modules coupled to the respective cache module.
The memory device of any one of claims 1-8, wherein each bank comprises:

an array FSM configured to write the data into the memory cells of the bank.
The memory device of any one of claims 1-9, wherein the memory cell comprises a phase-change memory (PCM) device.
The memory device of claim 10, wherein the write operation comprises setting or resetting the PCM device.
A system, comprising:

a memory device comprising:

a plurality of banks, each bank comprising memory cells being arranged into rows and columns;

an interface configured to direct a controlling signal comprising a command, an address, and a data into the plurality of banks;

a plurality of cache modules, wherein each cache module is configured to store the address and the data of a respective one of the banks; and

a plurality of control modules, wherein each control module is configured to:

determine whether each cache module has any address and data stored therein;

in response to determining that each cache module has stored address and stored data therein, retrieve the stored address and the stored data from the cache module and execute a write operation to the respective memory cells of the bank according to the stored address; and

in response to retrieving the stored address and the stored data from the cache module, allow the bank to receive a next controlling signal; and

a memory controller coupled to the memory device and configured to control the memory device.
The system of claim 12, further comprising a host coupled to the memory controller and configured to transmit the data to and from the memory device.
The system of claim 12 or 13, wherein the interface is configured to, in response to receiving the controlling signal, determine that the command corresponds to the write operation, and direct the address and the data to be stored in the respective cache module.
The system of any one of claims 12-14, further comprises:

a clock bus configured to transmit a clock signal;

an address bus configured to transmit the address; and

a data bus configured to transmit the data, wherein the clock bus, the address bus, and the data bus are coupled to the interface.
The system of any one of claims 12-15, wherein the cache module comprises a first-in-first-out (FIFO) module.
The system of claim 16, wherein the FIFO module comprises a FIFO cache having at least two cache pages capable of storing the address and the data.
The system of claim 17, wherein the two cache pages comprise a first cache page and a second cache page, the address and the data of the controlling signal are stored in the first cache page, and a next address and a next data of the next controlling signal are stored in the second cache page.
The system of any one of claims 16-18, wherein each FIFO module comprises a FIFO push finite state machine (FSM) configured to be triggered to start the FIFO module and to store the address and the data in the FIFO module.
The system of any one of claims 16-19, wherein each FIFO module comprises a FIFO count FSM configured to record a number of storing the address and the data being performed.
The system of any one of claims 16-20, wherein each FIFO module comprises a FIFO pop FSM configured to terminate a previous write operation and activate a next write operation.
The system of any one of claims 11-21, wherein each bank comprises:

a respective cache module of the plurality of cache modules; and

a respective control module of the plurality of control modules coupled to the respective cache module.
The system of any one of claims 11-22, wherein each bank comprises:

an array FSM configured to write the data into the memory cells of the bank.
The system of any one of claims 11-23, wherein the memory cell comprises a phase-change memory (PCM) device.
The system of claim 24, wherein the write operation comprises setting or resetting the PCM device.
A method for operating a memory device, the memory device comprising a plurality of banks, each bank comprising memory cells being arranged into rows and columns, a cache module coupled to the memory cells, and a control module coupled to the cache module, the method comprising:

in response to receiving a controlling signal comprising a command, an address, and a data, determining whether the command corresponds to a write operation;

in response to determining that the command corresponds to the write operation, send the address and the data to the cache module of the bank;

determining whether the cache module has any address and data stored therein; and

in response to determining that the cache module has the stored address and the stored data therein, retrieve the stored address and the stored data from the cache module, and execute the write operation to the respective memory cells of the bank.
The method of claim 26, further comprising:

receiving a next controlling signal and repeating processes until the cache module becomes empty, wherein the processes comprise:

in response to receiving the next controlling signal comprising a next command, a next address, and a next data, determining whether the next command corresponds to the write operation;

in response to determining that the next command corresponds to the write operation, send the next address and the next data to the cache module of the bank;

determining whether the cache module has any address and data stored therein; and

in response to determining that the cache module has the stored address and the stored data therein, retrieve the stored address and the stored data from the cache module, and execute the write operation to the respective memory cells of the bank.
The method of claim 26 or 27, wherein the cache module comprises a first-in-first-out (FIFO) module.
The method of claim 28, wherein the FIFO module comprises a FIFO cache having at least two cache pages capable of storing the address and the data.
The method of claim 29, wherein the two cache pages comprise a first cache page and a second cache page, and when the stored address and the stored data in the first cache page are retrieved from the cache module, the first cache page is the oldest cache page.