WO2022236467A1

WO2022236467A1 - Input/output module and memory

Info

Publication number: WO2022236467A1
Application number: PCT/CN2021/092357
Authority: WO
Inventors: 潘越; 周浩阳; 布明恩
Original assignee: 华为技术有限公司
Priority date: 2021-05-08
Filing date: 2021-05-08
Publication date: 2022-11-17
Also published as: CN116745846A

Abstract

An input/output module and a memory, used for shortening the data write time and improving the data write efficiency of the memory. The input/output module is coupled to a storage array. The input/output module comprises a drive circuit and a write assist circuit, wherein the drive circuit is used for generating a drive signal according to a write signal and data to be written; the drive signal is used for driving the storage array to write the data to be written; the write assist circuit is coupled to an output end of the drive circuit, and is used for outputting a write assist current when the storage array writes the data to be written, and stopping outputting the write assist current when a write current flowing through the storage array reaches a first threshold.

Description

A kind of input and output module and memory

technical field

The present application relates to the technical field of storage, in particular to an input-output module and a memory.

Background technique

With the development of storage technology and the increasingly prominent problem of storage wall (memory performance limits processor performance), various new types of memory have attracted more and more attention, such as magnetic random access memory (MRAM) , resistive random access memory (RRAM), phase change memory (phase change memory, PCM) and ferroelectric random access memory (FeRAM), etc.

The structure of this new type of memory is generally shown in Figure 1. The memory includes multiple input/output (input/output, IO) modules and a storage array, the storage array includes multiple storage units, and each IO module is responsible for writing and reading data in the correspondingly connected storage array. Each IO module includes a write driver (WD) circuit and a sense amplifier (SA), the WD circuit is used to write data in parallel, and the SA is used to read data in parallel.

Specifically, when writing data, a voltage is applied to WL, so that the switch tube in the storage unit is turned on; at the same time, the WD circuit generates a write current or a write voltage at the output terminal WD_OUT according to the write signal WT, through the multiplex gate The multiplexer (MUX) selects the memory cell that needs to write data, applies the write current or write voltage to the memory cell through the bit line (BL)/source line (SL), and writes the corresponding data. It is not difficult to see that the data writing process will involve charging and discharging nodes such as MUX/BL/SL.

There are two types of write drive circuits: current source type and voltage source type.

The current source type write drive circuit can be shown in FIG. 2 , M1 and M2 form a current mirror, and M2 is used as a current source to generate the current required for writing data, and is connected in series with M3. When writing, the M3 switch tube is turned on, and the current generated by the write drive circuit is applied to the corresponding BL or SL through the output terminal WD_OUT through the MUX, and further applied to the memory cell to be written. For the current source write drive circuit, due to the large parasitic capacitance of nodes such as MUX/BL/SL, nodes such as MUX/BL/SL need to go through a long charging time at the beginning of writing, and the power flowing through the storage unit after charging is completed Only when the current I _cell reaches a stable value, the effective writing time begins, as shown in FIG. 3 . A long charging time at the beginning of writing will lead to a longer total writing time, which is not conducive to high-speed writing of the memory.

The voltage source type write drive circuit can be shown in Figure 4, which provides the voltage required to write data, usually the voltage is generated by a low dropout regulator (low dropout regulator, LDO) and shared by each IO module . The write drive circuit in each IO module may be a switch tube connected to the LDO. During the writing process, the switch tube is turned on under the control of the writing signal WT, and the voltage V LDO generated by the _LDO will be applied to the MUX through the writing drive circuit, and then applied to the BL/SL through the MUX, and further applied to the to-be-written on the storage unit. For the voltage source write drive circuit, at the beginning of writing, because the nodes such as MUX/BL/SL need to be charged and discharged first, a large instantaneous current will be drawn to the LDO in a short time, and the voltage V _{LDO output by the LDO} will be A drop occurs and slowly recovers to stability. After the charge and discharge are completed, the voltage V _cell on the memory cell can reach a stable value, and the effective writing time begins, as shown in Figure 5. Therefore, the writing process needs to go through a stable period before the effective writing time. An excessively long stabilization time will also result in a longer total writing time, which is not conducive to high-speed writing of the memory.

To sum up, using the input and output modules provided in the prior art to write data has the problems of long writing time and low data writing efficiency.

Contents of the invention

The embodiment of the present application provides an input and output module and a memory, which are used to reduce the data writing time and improve the data writing efficiency of the memory.

In a first aspect, the embodiment of the present application provides an input-output module, the input-output module is coupled with a storage array, and includes a driving circuit and a write auxiliary circuit. Wherein, the drive circuit is used to generate a drive signal according to the write signal and the data to be written, and the drive signal is used to drive the storage array to write the data to be written; the write auxiliary circuit is coupled to the output end of the drive circuit for writing When the data to be written is input, the write assist current is output; when the write current flowing through the memory array reaches the first threshold, the write assist current is stopped outputting.

The process of the drive circuit driving the storage array to write the data to be written may be: the drive circuit receives the write signal, and when the write signal is valid, the drive circuit outputs different currents or voltages according to the value of the data to be written to drive Write different data in the storage array.

Using the input and output module provided in the first aspect, the write assist circuit can output write assist current when the memory array is writing data to be written, and stop outputting the write assist current when the write current flowing through the memory array reaches the first threshold. That is to say, the write assist circuit can provide a write assist current for the drive circuit at the beginning of the write phase, thereby shortening the charging and discharging time for the parasitic capacitance at the initial stage of the write phase, so that the current or voltage actually flowing through the memory cell can be stabilized quickly value, thereby reducing the data writing time and increasing the data writing rate.

In a possible design, the write assist circuit includes a write assist current generating circuit and a control circuit. Wherein, the write assist current generating circuit is used to generate the write assist current; the control circuit is used to control the write assist current generate circuit to output the write assist current when the memory array is writing data to be written.

In addition, the control circuit can also be used to control the write assist current generating circuit to stop outputting the write assist current when the write current flowing through the memory array reaches the first threshold.

With the above solution, the write assist current generating circuit is used to generate the write assist current, and the control circuit is used to control when the write assist current generator circuit provides the write assist current to the output terminal of the driving circuit 601 .

In a possible design, the control circuit includes an inverter, a delay device and a NAND gate circuit. The inverter is used to invert the write signal to obtain an inverted signal; the delayer is used to delay the write signal to obtain a delayed signal, and the delay time of the delayer is shorter than that of the write signal Effective duration; the NAND gate circuit is used to perform NAND operation on the inversion signal and the delay signal to obtain the enable signal, which is used to enable the write auxiliary current generation circuit; when the enable signal is valid, the write auxiliary current is generated The circuit outputs the write assist current.

With the above scheme, the enable signal is a short pulse triggered by the falling edge or rising edge of the write signal, and its pulse width is determined by the delay time of the delayer. Therefore, the enable signal is valid at the beginning of the writing stage, thereby triggering the write assist current generating circuit to output the write assist current at the beginning of the write stage, so as to accelerate the charging and discharging rate of nodes such as MUX/BL/SL.

In another possible design, the control circuit includes a comparator and an OR gate circuit. The comparator is used to compare the reference voltage and the voltage value of the drive signal, and output the comparison signal; the OR gate circuit is used to OR the comparison signal and the write signal to obtain the enable signal, which is used to enable the write auxiliary current A generating circuit; when the enable signal is valid, the write auxiliary current generating circuit outputs the write auxiliary current.

With the above solution, the enable signal is a short pulse triggered by the falling edge or rising edge of the write signal, and its pulse width is determined by the magnitude of the reference voltage. Therefore, the enable signal is valid at the beginning of the writing stage, thereby triggering the write assist current generating circuit to output the write assist current at the beginning of the write stage, so as to accelerate the charging and discharging rate of nodes such as MUX/BL/SL.

Further, the control circuit may also include a reference voltage generating module. The reference voltage generation module is coupled with the comparator and is used to output the reference voltage.

With the above solution, the reference voltage generation module can generate a reference voltage for providing a reference voltage for the comparator in the control circuit.

Specifically, the reference voltage generating module may include an analog driving circuit, an analog storage array and a voltage output module. The analog drive circuit is used to generate the module drive signal, and the analog drive signal is used to drive the analog storage array to write analog data; the analog storage array is used to write analog data under the drive of the analog drive signal; the voltage output module is used to When the output voltage reaches a stable value, the stable value is output as a reference voltage.

By adopting the above solution, the process of writing data into the memory array driven by the driving circuit can be simulated, and the stable voltage value of the driving signal when the driving circuit 601 writes data can be obtained. After reaching the stable value, enter the effective writing time, and output the stable value as a reference voltage to the control circuit. When the voltage value of the driving signal does not reach the reference voltage, the control module circuit can control the write auxiliary current generation circuit to output the write auxiliary current, when the voltage value of the driving signal reaches the reference voltage, the write assist current generating circuit is controlled to stop outputting the write assist current.

In a possible design, the write auxiliary current generating circuit includes a first switch tube, the control electrode of the first switch tube is coupled to the control circuit, and is used to turn on or off under the control of the control circuit; the first switch tube The first electrode is coupled to the voltage source, and the second electrode of the first switch tube is coupled to the output terminal of the driving circuit.

With the above solution, when the enable signal output by the control circuit is valid, the first switch tube is turned on, and the current output by the voltage source can be output to the output terminal of the drive circuit through the first switch tube, so that the drive circuit provides write assist current.

In a possible design, the write auxiliary current generating circuit includes a second switch tube and a current source. The control electrode of the second switch tube is coupled to the control circuit for turning on or off under the control of the control circuit; the current source is coupled to the second switch tube for switching the output current output to the output terminal of the drive circuit.

With the above scheme, when the enable signal output by the control circuit is valid, the second switch tube is turned on, and the output current of the current source can be output to the output terminal of the drive circuit, thereby providing the drive circuit with write auxiliary current at the initial stage of the write phase. .

In a possible design, the input-output module provided in the first aspect may further include a multiplexer. The multiplexer is coupled with the drive circuit, and is used for writing data to be written into all or part of the memory cells in the memory array according to the drive signal.

When writing data, only some storage units in the storage array may need to write data, while other storage units do not need to write data. Using the above scheme, through the multiplexer, only the storage units that need to write data can be sent. unit to write data.

In a possible design, the input-output module provided in the first aspect may further include a sense amplifier SA. The SA is used to read the data to be read stored in the storage array.

In a second aspect, the embodiment of the present application provides an input-output module, the input-output module is coupled with a storage array, and includes a driving circuit and a control circuit. Wherein, the drive circuit is used to generate a drive signal according to the write signal and the data to be written, and the drive signal is used to drive the memory array to write the data to be written; the control circuit includes an inverter, a delayer and a NAND gate circuit; wherein , the inverter is used to invert the written signal to obtain an inverted signal; the delayer is used to delay the written signal to obtain a delayed signal; the NAND gate circuit is used to invert the signal and delay An NAND operation is performed on the signal to obtain an enable signal, and the enable signal is used to control the output of the write auxiliary current to the output terminal of the driving signal.

In a third aspect, the embodiment of the present application provides an input-output module, the input-output module is coupled with a storage array, and includes a driving circuit and a control circuit. Wherein, the drive circuit is used to generate a drive signal according to the write signal and the data to be written, and the drive signal is used to drive the memory array to write the data to be written; the control circuit includes a comparator and an OR circuit; the comparator is used to compare the reference voltage and the data to be written. The voltage values of the drive signals are compared to output a comparison signal; the OR gate circuit is used to perform an OR operation on the comparison signal and the write signal to obtain an enable signal, and the enable signal is used to control the output of the write auxiliary current to the output terminal of the drive signal.

In addition, the control circuit may further include a reference voltage generating circuit, which is coupled to the comparator for outputting a reference voltage.

In a fourth aspect, the embodiment of the present application provides a memory. The memory includes a storage array and the input/output module provided in the first aspect to the third aspect and any possible design thereof, the input/output module is coupled with the storage array, and is used to drive the storage array to write data to be written.

In addition, it should be understood that the technical effects brought about by the second aspect to the fourth aspect and any possible design methods thereof may refer to the technical effects brought about by different design methods in the first aspect, which will not be repeated here.

Description of drawings

FIG. 1 is a schematic structural diagram of a memory provided by the prior art;

FIG. 2 is a schematic structural diagram of a write drive circuit provided by the prior art;

FIG. 3 is a waveform diagram of a current flowing through a memory cell when data is written in the prior art;

FIG. 4 is a schematic structural diagram of another write drive circuit provided by the prior art;

FIG. 5 is a waveform diagram of a voltage on a memory cell when data is written in the prior art;

FIG. 6 is a schematic structural diagram of the first input and output module provided by the embodiment of the present application;

FIG. 7 is a schematic structural diagram of a second input and output module provided in the embodiment of the present application;

FIG. 8 is a schematic structural diagram of a control circuit provided by an embodiment of the present application;

FIG. 9 is a waveform diagram of a write signal, an inversion signal, a delay signal, and an enable signal provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of the comparison between the current I _cell flowing through the memory cell provided by the embodiment of the present application and the prior art;

FIG. 11 is a schematic structural diagram of another control circuit provided by the embodiment of the present application;

FIG. 12 is a waveform diagram of a write signal, a drive signal, a comparison signal and an enable signal provided by an embodiment of the present application;

FIG. 13 is a schematic diagram comparing the current V _cell of a memory cell provided in the embodiment of the present application with that in the prior art;

FIG. 14 is a schematic structural diagram of a write assist current generating circuit provided by an embodiment of the present application;

FIG. 15 is a schematic structural diagram of another write assist current generating circuit provided by an embodiment of the present application;

FIG. 16 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application;

FIG. 17 is a schematic structural diagram of another driving circuit provided by an embodiment of the present application;

FIG. 18 is a schematic structural diagram of a third input and output module provided by the embodiment of the present application;

FIG. 19 is a schematic structural diagram of a fourth input and output module provided in the embodiment of the present application;

FIG. 20 is a schematic structural diagram of a fifth input and output module provided by the embodiment of the present application;

FIG. 21 is a schematic structural diagram of a sixth input and output module provided by the embodiment of the present application;

FIG. 22 is a schematic structural diagram of a reference voltage generating module provided in an embodiment of the present application;

FIG. 23 is a schematic structural diagram of a memory provided by an embodiment of the present application.

Detailed ways

In the following, the application scenarios of the embodiments of the present application are firstly introduced.

The embodiment of the present application can be applied to the memory shown in FIG. 1 . The memory shown in FIG. 1 includes multiple IO modules and a storage array. The storage array includes multiple storage units. Each IO module is responsible for writing and reading part of data in the storage array. Each IO module includes a write drive circuit and an SA, the write drive circuit is used to write data in parallel, and the SA is used to read data in parallel.

When writing data, the data writing process will involve charging and discharging nodes such as MUX/BL/SL, which will cause the current I _cell flowing through the storage cell and the voltage V _cell on the storage cell to stabilize after a period of time. When it reaches a stable value, it enters the effective writing time. In the embodiment of the present application, by improving the structure of the IO module, the stabilization time of the I _cell and the V _cell when writing data is reduced, and the data writing efficiency of the memory is improved.

The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

It should be noted that, in the embodiments of the present application, a plurality refers to two or more. In addition, in the description of the present application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. The "coupling" mentioned in the embodiments of the present application refers to electrical connection, which may specifically include direct connection or indirect connection.

An embodiment of the present application provides an input-output module. Referring to FIG. 6 , the input-output module 600 is coupled to a storage array. The input-output module 600 includes a driving circuit 601 and a writing auxiliary circuit 602 .

Specifically, the drive circuit 601 is used to generate a drive signal according to the write signal and the data to be written, and the drive signal is used to drive the memory array to write the data to be written; the write auxiliary circuit 602 is coupled to the output terminal of the drive circuit 601 for When the data to be written is written in the memory array, the write assist current is output; when the write current flowing through the memory array reaches a first threshold, the write assist current is stopped.

In the embodiment of the present application, the structure of the driving circuit 601 is the same as that of the writing driving circuit in the prior art, and will not be repeated here. The storage array can be composed of multiple storage units, as shown in FIG. 6 , and the specific structure of the storage units can also refer to the description in the prior art. In addition, the write current flowing through the memory array is the write current flowing through the memory cells in the memory array, as shown in FIG. 6 . In the subsequent drawings, the specific structure of the storage array will not be shown in detail.

The process of the drive circuit 601 driving the storage array to write the data to be written may be: the drive circuit 601 receives the write signal, and when the write signal is valid, the drive circuit 601 outputs different currents or voltages according to the value of the data to be written , to drive writing different data in the storage array.

Different from the prior art, in the embodiment of the present application, the input and output module 600 also includes a write assist circuit 602, which is used to output a write assist current when the storage array writes data to be written; When the input current reaches the first threshold, the output of the write assist current is stopped. That is to say, the write assist circuit 602 can provide write assist current for the driving circuit 601 at the beginning of the writing stage, thereby shortening the charging and discharging time for the parasitic capacitance at the beginning of the writing stage, so that the current or voltage actually flowing through the memory cell can be faster. A stable value is reached, thereby reducing the data writing time and increasing the data writing rate.

Specifically, the write assist circuit 602 may be composed of a write assist current generating circuit and a control circuit, as shown in FIG. 7 . The write assist current generating circuit is used to generate the write assist current; the control circuit is used to control the write assist current generate circuit to output the write assist current when the memory array is writing data to be written. In addition, the control circuit is also used to control the write assist current generating circuit to stop outputting the write assist current when the write current flowing through the memory array reaches the first threshold.

That is to say, the write assist current generating circuit is used to generate the write assist current, and the control circuit is used to control when the write assist current generate circuit supplies the write assist current to the output end of the driving circuit 601 .

The specific structures of the control circuit and the write auxiliary current generating circuit will be introduced in detail below.

1. Control circuit

The composition of the control circuit is described in detail below through two specific examples.

example one

In Example 1, the control circuit includes an inverter, a delayer (also called a delay chain, delay) and a NAND circuit, as shown in FIG. 8 . The inverter is used to invert the write signal to obtain an inverted signal; the delayer is used to delay the write signal to obtain a delayed signal, and the delay time of the delayer can be shorter than that of the write signal. input effective time; the NAND gate circuit is used to perform NAND operation on the inversion signal and the delay signal to obtain the enable signal, and the enable signal is used to enable the write auxiliary current generating circuit; when the enable signal is valid, the write auxiliary current The generating circuit outputs a write assist current.

Assuming that the write signal is active at low level, the waveforms of the write signal, inverted signal, delay signal and enable signal can be shown in FIG. 9 . It can be seen from FIG. 9 that the enable signal is a short pulse triggered by the falling edge of the write signal, and its pulse width is determined by the delay time of the delayer. Therefore, the enable signal is valid at the beginning of the writing stage, thereby triggering the write assist current generating circuit to output the write assist current at the beginning of the write stage, so as to accelerate the charging and discharging rate of nodes such as MUX/BL/SL.

As mentioned above, when the write current flowing through the memory array reaches the first threshold, the control circuit controls the write assist circuit generating circuit to stop outputting the write assist current. In Example 1, the control circuit controls the write assist current generating circuit to stop outputting the write assist current after the write assist circuit generating circuit outputs the write assist current for a set duration. In this regard, it can be understood as follows: in the embodiment of the present application, it can be determined by testing how long the write current flowing through the memory cell can reach the first threshold when the write assist current is superimposed on the memory array. Furthermore, the duration obtained by the test is used as the aforementioned set duration.

The control circuit shown in FIG. 9 is used to enable the write assist current generating circuit to output the write assist current. Compared with the prior art solution, the current I _cell flowing through the memory cell can reach a stable value in a short period of time. Exemplary Ground, the current I _cell flowing through the memory cell can be shown in FIG. 10 .

It should be noted that the structure of the control circuit shown in Example 1 is only for illustration. In practical applications, the control circuit can use other logic gate circuits and/or other devices to operate on the write signal to obtain the rise of the write signal. A short pulse triggered by an edge (the write signal is active at high level) or a falling edge (the write signal is active at low level), through which the write assist current generating circuit is enabled to output the write assist current at the initial stage of the write phase.

It should also be noted that when the input-output module 600 is applied to the memory shown in FIG. 1 , the control circuit may be unique to each input-output module, or a control circuit may be shared by multiple input-output modules. This is not specifically limited in the embodiments of the present application.

Example two

In Example 2, the control circuit includes a comparator and an OR gate circuit, as shown in FIG. 11 . Among them, the comparator is used to compare the reference voltage and the voltage value of the drive signal, and output the comparison signal; the OR gate circuit is used to perform OR operation on the comparison signal and the write signal to obtain the enable signal, and the enable signal is used to enable A writing auxiliary current generating circuit; when the enable signal is valid, the writing auxiliary current generating circuit outputs a writing auxiliary current.

Assuming that the write signal is active at low level, the waveforms of the write signal, the drive signal, the comparison signal and the enable signal can be shown in FIG. 12 . It can be seen from Figure 12 that the enable signal is a short pulse triggered by the falling edge of the write signal, and its pulse width is determined by the magnitude of the reference voltage. Therefore, the enable signal is valid at the beginning of the writing stage, thereby triggering the write assist current generating circuit to output the write assist current at the beginning of the write stage, so as to accelerate the charging and discharging rate of nodes such as MUX/BL/SL.

As mentioned above, when the write current flowing through the memory array reaches the first threshold, the control circuit controls the write assist circuit generating module to stop outputting the write assist current. In Example 2, the control circuit controls the write assist current generating circuit to stop outputting the write assist current when the voltage value of the output signal of the drive circuit reaches the reference voltage value. In this regard, it can be understood as follows: in the embodiment of the present application, when the voltage value of the output signal of the driving circuit can be determined by the test method, the write current flowing through the storage unit can reach the first threshold, and then the test can be obtained The voltage is used as the aforementioned reference voltage.

Using the control circuit shown in FIG. 11 to enable the write assist current generating circuit to generate the write assist current, compared with the solution in the prior art, the voltage V _cell of the memory cell can be stabilized in a short period of time. Exemplarily, the storage The cell voltage V _cell may be as shown in FIG. 13 .

In addition, in Example 2, the control circuit may further include a reference voltage generation module, the reference voltage generation module is coupled to the comparator, and is configured to output the reference voltage to the comparator.

Specifically, the reference voltage generating module may include an analog driving circuit, an analog storage array and a voltage output module. Among them, the analog driving circuit is used to generate a module driving signal, and the analog driving signal is used to drive the analog storage array to write analog data; the analog storage array is used to write analog data under the drive of the analog driving signal; the voltage output module is used to When the output voltage of the analog drive circuit reaches a stable value, the stable value is output as a reference voltage.

That is to say, in the embodiment of the present application, the process of driving the memory array to write data by simulating the driving circuit 601 can be used to obtain the stable voltage value of the driving signal when the driving circuit 601 writes data. After reaching the stable value, enter the valid The writing time, for example, the stable value may be the value of the corresponding WD_OUT signal when the I _cell enters the valid writing time in the waveform diagram shown in FIG. 3 . The stable value is output to the control circuit as a reference voltage, and the control circuit can control the writing auxiliary current generating circuit to output the writing auxiliary current when the voltage value of the driving signal does not reach the reference voltage, and control the writing auxiliary current generating circuit when the voltage value of the driving signal reaches the reference voltage. The write assist current generating circuit stops outputting the write assist current.

It should be noted that the control circuit shown in Example 2 is only for illustration, and in practical applications, the control circuit may use other logic gate circuits and/or other devices to operate on the write signal to obtain the write signal determined by the rising edge ( write signal high level active) or a short pulse triggered by a falling edge (write signal high level active), through which the write assist current generating circuit is enabled to output write assist current at the initial stage of the write phase.

It should also be noted that when the I/O module 600 is applied to the memory shown in FIG. 1 , the control circuit in Example 2 can be unique to each I/O module, or can be shared by multiple I/O modules. A control circuit, or part of the structure in the control circuit is shared by multiple input and output modules, and part of the structure is unique to each input and output module, for example, multiple input and output modules share the reference voltage generation module, and each input and output module Comparators and OR gate circuits are configured in each of the control circuits, and the ownership of the control circuits is not specifically limited in the embodiment of the present application.

2. Write auxiliary current generating circuit

The composition of the write assist current generating circuit will be described in detail below through two specific examples.

example one

In Example 1, the write auxiliary current generating circuit is composed of a first switch tube, as shown in FIG. 14 . Wherein, the control electrode of the first switch tube is coupled with the control circuit for turning on or off under the control of the control circuit; the first electrode of the first switch tube is coupled with the voltage source, and the second electrode of the first switch tube is coupled with the The output terminal of the driving circuit 601 is coupled.

It should be noted that, in the example of FIG. 14 , the first switch transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET) as an example for illustration. In practical applications, the switching tube in the embodiment of the present application may also be a gallium nitride (GaN) transistor, an insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT), a bipolar junction transistor (bipolar junction transistor, BJT). The control electrode of the switch tube is an electrode that controls the switch tube to be turned on and off, such as a grid; the first electrode and the second electrode of the switch tube are two electrodes through which a conduction current flows when the switch tube is turned on.

In Example 1, when the enable signal output by the control circuit is valid, the first switch is turned on, and the current output by the voltage source can be output to the output terminal of the driving circuit 601 through the first switch, so that in the initial phase of writing A write assist current is provided to the drive circuit 601 .

Example two

In Example 2, the write auxiliary current generating circuit is composed of a second switch tube and a current source, as shown in FIG. 15 . Wherein, the control electrode of the second switch tube is coupled with the control circuit, and is used for turning on or off under the control of the control circuit; the current source is coupled with the second switch tube, and is used for turning on the second switch tube when it is turned on. The output current is output to the output end of the driving circuit 601 .

Wherein, the current source can be implemented by a switch tube with a gate bias voltage of a fixed voltage, or the current source can also be implemented by means of a current mirror.

In Example 2, when the enable signal output by the control circuit is valid, the second switch tube is turned on, and the output current of the current source can be output to the output terminal of the driving circuit 601, thereby providing the driving circuit 601 with Write Auxiliary Current.

As mentioned above, in the embodiment of the present application, the specific structure of the driving circuit 601 may refer to the prior art. Two specific structures of the driving circuit 601 are listed below.

Exemplarily, a possible structural schematic diagram of the driving circuit 601 may be shown in FIG. 16 . The driving circuit shown in FIG. 16 is a current source driving circuit, M1 and M2 form a current mirror, and M2 is used as a current source of the driving circuit 601 to generate the current required for writing data, and is connected in series with M3. When writing data, M3 is turned on when the write signal is valid, and the current in M2 can be output to WD_OUT through M3; when the data to be written is different, the output current of WD_OUT is different to write different data.

Exemplarily, a possible structural diagram of the driving circuit 601 may be shown in FIG. 17 . The drive circuit 601 shown in FIG. 17 is a voltage source drive circuit, which is composed of a switch tube M1. LDO output voltage V _LDO provides voltage for M1. When writing data, M1 is turned on when the write signal is valid, and V _LDO is output through the output terminal WD_OUT; when the data to be written is different, the voltage of WD_OUT is different to write different data.

It should be noted that, in the embodiment of the present application, the specific structure of the driving circuit 601 is not limited to the structures shown in the above two examples, and the structures of other write driving circuits in the prior art are also applicable in the embodiment of the present application.

In addition, in the embodiment of the present application, the input-output module 600 may further include a multiplexer, as shown in FIG. 18 . The multiplexer is coupled with the driving circuit 601 and is used for writing data to be written into all or part of the memory cells in the memory array according to the driving signal.

That is to say, when writing data, only some storage units in the storage array may need to write data, while other storage units do not need to write data. unit to write data.

In addition, in the embodiment of the present application, the input and output module 600 may further include a sense amplifier, as shown in FIG. 19 . The sense amplifier is used to read the data to be read stored in the storage array.

The specific structures and functions of the above multiplexer and sense amplifier can refer to the description in the prior art, and will not be repeated here.

To sum up, using the input and output module 600 provided by the embodiment of the present application, through the write auxiliary circuit 602, an additional write auxiliary current can be provided at the beginning of the write phase of the storage array, thereby shortening the charging and discharging time of the parasitic capacitance at the beginning of the write phase , so that the current or voltage actually flowing through the memory cell can quickly reach a stable value, thereby reducing the data writing time and increasing the data writing rate.

The input and output modules provided by the embodiments of the present application are introduced below through two specific examples.

As shown in FIG. 20 , it is a specific example of the IO module provided by the embodiment of the present application. The IO module includes WD circuit, write auxiliary circuit, SA and MUX. Among them, the write auxiliary current generating circuit of the write auxiliary circuit is composed of a PMOS switch, and its gate is connected to the enable signal (WA signal) sent from the control circuit; the control circuit is shared by the write auxiliary circuits of all IO modules, and its input signal It is the write signal WT, and the output signal is the WA signal. The WA signal is output from a NAND gate, one input terminal of the NAND gate is connected to the signal generated by the WT signal passing through the inverter, and the other input terminal is connected to the signal generated by the WT signal passing through the delay chain. Therefore, the role of the control circuit is to generate a short pulse triggered by the falling edge of WT, and its pulse width is determined by the delay chain.

In the example in Figure 20, the WD circuit is a voltage source type. When the write operation starts, the write assist circuit will generate a write assist current and charge nodes such as MUX/BL/SL at the same time, thereby reducing the current drawn by the WD circuit to the LDO. The current or voltage on the chip can also reach a stable value faster, thereby increasing the writing speed.

As shown in FIG. 21, it is a specific example of the IO module provided by the embodiment of the present application. The IO module includes WD circuit, write auxiliary circuit, SA and MUX. The write assist circuit includes a control circuit and a write assist current generating circuit.

The write auxiliary current generating circuit in the write auxiliary circuit is composed of a PMOS switch tube and a PMOS current source, and its control circuit is divided into two parts, and a part of the control circuit is located in each IO module, which is a comparator and an OR gate, wherein The comparator compares the WD_OUT signal with the reference voltage V _REF , and performs an OR operation on the result with the WT signal, and the operation result is output to the gate of the PMOS switch in the write auxiliary current generation circuit; the other part of the control circuit is outside the IO module, Shared by all write assist circuits, it is used to output a reference voltage V _REF .

In the example in Figure 21, the WD circuit is a current source type. When the write operation starts, the write auxiliary circuit will generate a write auxiliary current and charge the nodes such as MUX/BL/SL at the same time, so that each node can quickly reach a stable voltage and store The current or voltage on the cell is also able to reach a stable value faster, thereby increasing the writing speed.

A circuit for generating a reference voltage V _REF is shown in Fig. 22 . It consists of a dummy WD circuit and a dummy array. The dummy write drive current is applied to the dummy array, and the voltage generated at the output of the dummy WD circuit is approximately the stable voltage value of the WD circuit during writing. When , the stable voltage value can be used as the reference voltage V _REF .

In addition, the embodiment of the present application further provides an input-output module, which is coupled with the storage array and includes a driving circuit and a control circuit. As shown in Figure 8, the drive circuit is used to generate a drive signal according to the write signal and the data to be written, and the drive signal is used to drive the memory array to write the data to be written; the control circuit includes an inverter, a delayer and a NAND Gate circuit; wherein, the inverter is used to invert the write signal to obtain an inverted signal; the delayer is used to delay the write signal to obtain a delayed signal; the NAND gate circuit is used to invert An NAND operation is performed on the signal and the delayed signal to obtain an enable signal, and the enable signal is used to control the output of the write auxiliary current to the output terminal of the drive signal.

It should be noted that the specific structure and working principle of the input and output module can refer to the relevant description in FIG. 8 , and will not be repeated here.

It should also be noted that the specific structure of the control circuit is not limited to the structure shown in FIG. 8 . In the embodiment of the present application, the control circuit may generate a short pulse triggered by a rising edge or a falling edge of the write signal, and the specific structure of the control circuit is not limited.

In addition, the embodiment of the present application further provides an input-output module, which is coupled with the storage array and includes a driving circuit and a control circuit. As shown in Figure 11, the drive circuit is used to generate a drive signal according to the write signal and the data to be written, and the drive signal is used to drive the memory array to write the data to be written; the control circuit includes a comparator and an OR circuit; the comparator is used for Compare the reference voltage and the voltage value of the drive signal, and output the comparison signal; the OR gate circuit is used to OR the comparison signal and the write signal to obtain the enable signal, and the enable signal is used to control the output to the output terminal of the drive signal Write Auxiliary Current.

It should be noted that, for the specific structure and working principle of the input and output module, reference may be made to the relevant description in FIG. 11 , which will not be repeated here.

It should also be noted that the specific structure of the control circuit is not limited to the structure shown in FIG. 11 . In the embodiment of the present application, the control circuit may generate a short pulse triggered by a rising edge or a falling edge of the write signal, and the specific structure of the control circuit is not limited.

Based on the same inventive concept, an embodiment of the present application further provides a memory, as shown in FIG. 23 . The memory 2300 includes a storage array 2301 and the aforementioned input-output module 600, the input-output module 600 is coupled with the storage array 2301, and is used to drive the storage array 2301 to write data to be written.

It should be noted that for implementations and technical effects not described in detail in the memory 2300 , reference may be made to relevant descriptions in the aforementioned input/output module 600 , which will not be repeated here.

Apparently, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the scope of the embodiments of the present application. In this way, if the modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and equivalent technologies, the present application also intends to include these modifications and variations.

Claims

An input-output module, characterized in that the input-output module is coupled with a storage array, comprising:

A drive circuit, configured to generate a drive signal according to the write signal and the data to be written, the drive signal is used to drive the memory array to write the data to be written;

A write assist circuit, coupled to the output end of the drive circuit, for outputting a write assist current when the memory array writes the data to be written; when the write current flowing through the memory array reaches a first threshold , stop outputting the write assist current.
The input-output module according to claim 1, wherein the write auxiliary circuit comprises:

A write assist current generating circuit, configured to generate the write assist current;

a control circuit, configured to control the write assist current generating circuit to output the write assist current when the storage array writes the data to be written; and control the write assist current generating circuit to flow through the storage array When the writing current of the array reaches the first threshold, outputting the writing auxiliary current is stopped.
The input-output module according to claim 1 or 2, wherein the control circuit comprises:

an inverter, configured to perform an inversion operation on the write signal to obtain an inversion signal;

a delayer, configured to perform a delay operation on the write signal to obtain a delayed signal;

A NAND gate circuit, configured to perform a NAND operation on the inverted signal and the delayed signal to obtain an enable signal, and the enable signal is used to enable the write auxiliary current generating circuit; the enable When the signal is valid, the write assist current generating circuit outputs the write assist current.
The input-output module according to claim 1 or 2, wherein the control circuit comprises:

a comparator, used to compare the reference voltage with the voltage value of the driving signal, and output a comparison signal;

An OR gate circuit, configured to perform an OR operation on the comparison signal and the write signal to obtain an enable signal, and the enable signal is used to enable the write auxiliary current generating circuit; when the enable signal is valid , the write assist current generating circuit outputs the write assist current.
The input-output module according to claim 4, wherein the control circuit further comprises:

A reference voltage generating module, coupled to the comparator, for outputting the reference voltage.
The input-output module according to claim 5, wherein the reference voltage generating module comprises:

An analog driving circuit, used to generate a module driving signal, and the analog driving signal is used to drive the analog storage array to write analog data;

The analog storage array is used to write the analog data driven by the analog driving signal;

A voltage output module, configured to output the stable value as the reference voltage when the output voltage of the analog driving circuit reaches a stable value.
The input-output module according to any one of claims 2-6, wherein the write auxiliary current generating circuit comprises:

The first switch tube, the control electrode of the first switch tube is coupled to the control circuit, and is used to turn on or off under the control of the control circuit; the first electrode of the first switch tube is connected to the voltage source Coupling, the second electrode of the first switch tube is coupled to the output terminal of the driving circuit.
The input-output module according to any one of claims 2-6, wherein the write auxiliary current generating circuit comprises:

a second switch tube, the control electrode of the second switch tube is coupled to the control circuit, and is used to be turned on or off under the control of the control circuit;

A current source, coupled to the second switch tube, is used to output an output current to the output terminal of the drive circuit when the second switch tube is turned on.
The input-output module according to any one of claims 1-8, further comprising:

A multiplexer, coupled to the drive circuit, is used to write the data to be written into all or part of the memory cells in the memory array according to the drive signal.
The input-output module according to any one of claims 1-9, further comprising:

The sense amplifier SA is used to read the data to be read stored in the storage array.
An input-output module, characterized in that the input-output module is coupled with a storage array, comprising:

A drive circuit, configured to generate a drive signal according to the write signal and the data to be written, the drive signal is used to drive the memory array to write the data to be written;

A control circuit, the control circuit includes an inverter, a delayer and a NAND gate circuit; wherein, the inverter is used to perform an inversion operation on the write signal to obtain an inverted signal; the delayer uses performing a delay operation on the write signal to obtain a delayed signal; the NAND gate circuit is used to perform a NAND operation on the inverted signal and the delayed signal to obtain an enable signal, and the enable signal The enable signal is used to control the output of the write auxiliary current to the output end of the drive signal.
An input-output module, characterized in that the input-output module is coupled with a storage array, comprising:

A drive circuit, configured to generate a drive signal according to the write signal and the data to be written, the drive signal is used to drive the memory array to write the data to be written;

A control circuit, the control circuit includes a comparator and an OR gate circuit; the comparator is used to compare the reference voltage with the voltage value of the drive signal, and outputs a comparison signal; the OR gate circuit is used to compare the comparison signal performing an OR operation with the write signal to obtain an enable signal, and the enable signal is used to control output of a write assist current to the output end of the drive signal.
The input-output module according to claim 12, wherein the control circuit further comprises:

A reference voltage generation circuit, coupled to the comparator, for outputting the reference voltage.
A memory, characterized by comprising a storage array and the input-output module according to any one of claims 1 to 13, the input-output module is coupled to the storage array, and is used to drive the storage array to write data input.