WO2022241660A1

WO2022241660A1 - Three-dimensional phase-change memory devices and forming method thereof

Info

Publication number: WO2022241660A1
Application number: PCT/CN2021/094492
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2021-05-19
Filing date: 2021-05-19
Publication date: 2022-11-24
Also published as: CN113454786B; CN113454786A

Abstract

A three-dimensional (3D) memory device includes a plurality of bit lines extending laterally, a common plate extending laterally, a plurality of word lines extending laterally and being disposed between the plurality of bit lines and the common plate, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a PCM structure between the respective word line and the common plate, and a selector extending vertically through the respective word line and being disposed between the PCM structure and the respective bit line.

Description

[Title established by the ISA under Rule 37.2] THREE-DIMENSIONAL PHASE-CHANGE MEMORY DEVICES AND FORMING METHOD THEREOF

BACKGROUND

The present disclosure relates to phase-change memory (PCM) devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. PCM array cells can be vertically stacked in 3D to form a 3D PCM.

SUMMARY

In an aspect, a 3D memory device includes a plurality of bit lines extending laterally, a common plate extending laterally, a plurality of word lines extending laterally and being disposed between the plurality of bit lines and the common plate, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a PCM structure between the respective word line and the common plate, and a selector extending vertically through the respective word line and being disposed between the PCM structure and the respective bit line.

In another aspect, a PCM cell includes a PCM structure, and a gate all around (GAA) transistor stacked over one another. One of a source or a drain of the GAA transistor is electrically connected to one node of the PCM structure.

In still another aspect, a system includes a 3D memory device configured to store data, and a memory controller coupled to the 3D memory device and configured to control operations of a plurality of PCM cells through a plurality of bit lines and a plurality of word lines. The 3D memory device includes the plurality of bit lines extending laterally, a common plate extending laterally, the plurality of word lines extending laterally and being disposed between the plurality of bit lines and the common plate, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a PCM structure between the respective word line and the common plate, and a selector extending vertically through the respective word line and being disposed between the PCM structure and the respective bit line.

In yet another aspect, a method for forming a 3D memory device is disclosed. A plurality of bit lines are formed. A plurality of word lines are formed above the plurality of bit lines. A plurality of selectors are formed. Each of the plurality of selectors extends vertically through one of the plurality of word lines and is in contact with one of the plurality of bit lines. A plurality of PCM structures are formed above and in contact with the plurality of selectors, respectively. A common plate is formed above and in contact with the plurality of PCM structures.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate implementations of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a perspective view of a 3D cross-point (XPoint) memory device.

FIGs. 2A and 2B illustrate a side view and a perspective view of cross-sections of an exemplary 3D PCM device, respectively, according to some aspects of the present disclosure.

FIGs. 3A–3C illustrate plan views of cross-sections of various exemplary GAA transistors in the 3D PCM device of FIGs. 2A and 2B, according to various aspects of the present disclosure.

FIG. 4 illustrates a circuit diagram of an exemplary 3D PCM device, according to some aspects of the present disclosure.

FIGs. 5A–5F illustrate an exemplary fabrication process for forming a 3D PCM device, according to some aspects of the present disclosure.

FIG. 6 illustrates a flowchart of an exemplary method for forming a 3D PCM device, according to some aspects of the present disclosure.

FIG. 7 illustrates a block diagram of an exemplary system having a 3D memory device, according to some aspects of the present disclosure.

FIG. 8A illustrates a diagram of an exemplary memory card having a 3D memory device, according to some aspects of the present disclosure.

FIG. 8B illustrates a diagram of an exemplary solid-state drive (SSD) having a 3D memory device, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) , and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term “3D memory device” refers to a semiconductor device with memory cells that can be arranged vertically on a laterally-oriented substrate so that the number of memory cells can be scaled up in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means perpendicular to the lateral surface of a substrate.

A PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data.

Conventional PCM uses a planar transistor as a selection device (a.k.a. a selector) for PCM cell to form a two-dimensional memory array. Because of its low current drive, the planar transistors have to be very large, or multiple planar transistors need to be used in order to provide a sufficient program (write) current, thereby increasing the memory cell size (footprint) and reducing the data storage density.

Alternatively, diode selectors, such as bipolar junction transistors (BJTs) , or ovonic threshold switch (OTS) selectors have been used to replace the planar transistors as the selectors. In the case of diode selection devices, the current drive is typically low and thus, cannot meet the program current requirement without struggle. As to the OTS selectors, new materials have to be used, and the process and integration of the selection devices with the PCM structures can be difficult to achieve without cross-contamination while providing sufficient current drive.

PCM cells can be vertically stacked in 3D to form a 3D PCM. 3D PCMs using OTS selectors as selection devices include 3D cross-point (XPoint) memory, which stores data based on a change in resistance of the bulk material property (e.g., in a high-resistance state or a low-resistance state) , in conjunction with a stackable cross-point data access array to be bit-addressable. For example, FIG. 1 illustrates a perspective view of a 3D XPoint memory device 100. 3D XPoint memory device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersections of perpendicular conductors, according to some implementations. 3D XPoint memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 in the same plane above lower bit lines 102.3D XPoint memory device 100 also includes a plurality of parallel word lines 106 in the same plane vertically between lower bit lines 102 and upper bit lines 104. As shown in FIG. 1, each lower bit line 102 and each upper bit line 104 extends laterally along the bit line direction in the plan view (parallel to the wafer plane) , and each word line 106 extends laterally in the word line direction in the plan view. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

It is noted that x and y axes are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. It is noted that z-axis is also included in FIG. 1 to further illustrate the spatial relationship of the components in 3D XPoint memory device 100. The substrate (not shown) of 3D XPoint memory device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the backside opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D XPoint memory device 100) is determined relative to the substrate of the semiconductor device in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing the spatial relationships is applied throughout the present disclosure.

As shown in FIG. 1, 3D XPoint memory device 100 includes a plurality of memory cells 108 each disposed at an intersection of lower or

upper bit line

102 or 104 and respective word line 106. Each memory cell 108 has a vertical square pillar shape. Each memory cell 108 includes at least a PCM structure 110 and a selector 112 stacked vertically. Each memory cell 108 stores a single bit of data and can be written or read by varying the voltage applied to respective selector 112, which replaces the need for transistors. Each memory cell 108 is accessed individually by a current applied through the top and bottom conductors in contact with each memory cell 108, e.g., respective word line 106 and lower or

upper bit line

102 or 104. Memory cells 108 in 3D XPoint memory device 100 are arranged in a memory array.

As described above, new materials, such as materials, such as zinc telluride (ZnTe) , germanium telluride (GeTe) , niobium oxide (NbO) , or silicon arsenic telluride (SiAsTe) , have to be used to form selectors 112, and the process and integration of selectors 112 with PCM structures 110 can be difficult to achieve without cross-contamination while providing sufficient current drive.

To address one or more of the aforementioned issues, the present disclosure introduces a novel architecture of 3D PCM devices with sufficient current drive, reduced memory bit size and cost, and increased data storage density. In the architecture disclosed herein, selectors and parts of the word lines circumscribing the selectors can form vertical GAA transistors for controlling the on and off of the current applied to the PCM structures. The vertical GAA transistors can provide higher current drive compared with the planar transistors with the size dimensions or maintain the same current drive with reduced dimensions. The architecture disclosed herein can be easily scaled up, for example, vertically with more stacks, to further increase the memory bit density and reduce the memory bit size and cost.

FIGs. 2A and 2B illustrate a side view and a perspective view of cross-sections of an exemplary 3D PCM device 200, respectively, according to some aspects of the present disclosure. As shown in FIG. 2A, 3D PCM device 200 can include a substrate 202, which can include silicon (e.g., single crystalline silicon) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , germanium on insulator (GOI) , or any other suitable materials. In some implementations, substrate 202 is a thinned substrate (e.g., a semiconductor layer) , which was thinned by grinding, wet/dry etching, chemical mechanical polishing (CMP) , or any combination thereof. In some implementations, one or more peripheral devices (not shown) are formed on and/or in substrate 202. The peripheral devices can include any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D PCM device 200. For example, the peripheral devices can include one or more of a data buffer, a decoder (e.g., a row decoder and a column decoder) , a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors) .

3D PCM device 200 can also include a memory array device formed on substrate 202, such as a lower PCM stack 201 and an upper PCM stack 203 that are stacked vertically, as shown in FIG. 2A. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D PCM device 200) is determined relative to the substrate of the semiconductor device (e.g., substrate 202) in the z-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

As shown in FIGs. 2A and 2B, lower PCM stack 201 can include a plurality of parallel bit lines 204 extending laterally (e.g., in the x-direction) . In some implementations, lower and upper PCM stacks 201 and 203 share a common plate 206 extending laterally (e.g., in the x-direction and y-direction) . That is, in lower PCM stack 201, common plate 206 is parallel to and above bit lines 204, according to some implementations. In some implementations, common plate 206 is grounded. For example, all common plates 206 of 3D PCM device 200 may be all electrically connected to the ground, i.e., 0 V. Bit lines 204 and common plate 206 can include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , doped polycrystalline silicon (polysilicon) , silicides, or any combination thereof. In some implementations, bit lines 204 and common plate 206 include a metal, such as W or Cu.

Lower PCM stack 201 can also include a plurality of parallel word lines 208 vertically between bit lines 204 and common plate 206. In some implementations, word lines 208 extend laterally (e.g., in the y-direction) . That is, word lines 208, bit lines 204, and common plate 206 are parallel to one another in different planes in the vertical direction, while word lines 208 and bit lines 204 are perpendicular to one another in the same plane, according to some implementations. In other words, parallel word lines 208 and parallel bit lines 204 can be in a cross-point architecture. Word lines 208 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicides, or any combination thereof. In some implementations, word lines 208 include polysilicon, such as doped polysilicon. That is, word lines 208 may have a different material (e.g., doped polysilicon) from bit lines 204 and common plate 206 (e.g., W or Cu) .

As shown in FIGs. 2A and 2B, lower PCM stack 201 can further include a plurality of PCM cells 210 each disposed at an intersection of a respective one of bit lines 204 and a respective one of word lines 208. In some implementations, the cross-point architecture of parallel word lines 208 and parallel bit lines 204 defines a plurality of intersections of each pair of word line 208 and bit line 204. A PCM cell 210 can be formed at each intersection of the cross-point architecture and vertically between bit line 204 and common plate 206. That is, the lower end of each PCM cell 210 is in contact with a respective bit line 204, and the upper end of each PCM cell 210 is in contact with common plate 206, according to some implementations. The middle portion of each PCM cell 210 is in contact with a respective word line 208, according to some implementations. As used herein, the “upper end” of a component (e.g., PCM cell 210) is the end farther away from substrate 202 in the z-direction, and the “lower end” of the component (e.g., PCM cell 210) is the end closer to substrate 202 in the z-direction when substrate 202 is positioned in the lowest plane of 3D PCM device 200.

In some implementations, each PCM cell 210 includes a PCM structure 212 vertically between a respective word line 208 and common plate 206. PCM structure 212 can include a PCM element 214. PCM element 214 can include a phase change material. The phase change material may include chalcogenide-based alloys (chalcogenide glass) , such as germanium antimony telluride (GeSbTe or GST) alloy, or any other suitable phase-change materials. PCM element 214 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase change materials based on heating and quenching of the phase change materials electrothermally. Electrical currents can be applied to switch the phase change material (or at least a fraction of it that blocks the current path) of PCM element 214repeatedly between the two phases to store data. In some implementations, PCM structure 212 further includes two

electrodes

216 and 218. As shown in FIGs. 2A and 2B, for example, PCM element 214 may be disposed vertically between

electrodes

216 and 218, i.e., sandwiched between

electrodes

216 and 218 in the z-direction. That is, PCM element 214 can be separated from word line 208 and common plate 206 by electrode 216 and electrode 218, respectively.

Electrodes

216 and 218 can include conductive materials including, but not limited to, W, Co, Cu, Al, carbon, doped polysilicon, silicides, or any combination thereof. In one example, each of

electrodes

216 and 218 may include carbon, such as amorphous carbon (a-C) . It is understood that in some examples, one or both of

electrodes

216 and 218 may be omitted in PCM structure 212.

In some implementations, each PCM cell 210 also includes a selector 220 extending vertically through a respective word line 208. Each selector 220 can be disposed vertically between a respective PCM structure 212 and a respective bit line 204. As shown in FIG. 2B, each selector 220 can be circumscribed by part of a respective word line 208, i.e., a gate electrode. That is, word line 208 can include a plurality of gate electrodes each circumscribing a respective selector 220 of PCM cell 210. Consistent with the scope of the present disclosure, in each PCM cell 210, selector 220 and the respective gate electrode of word line 208 that circumscribes selector 220 can form a GAA transistor 222 extending vertically (also referred to herein as a vertical GAA transistor) . In other words, each PCM cell 210 can include a PCM structure 212 and a GAA transistor 222 stacked over one another.

For example, FIGs. 3A–3C illustrate plan views of cross-sections of various exemplary GAA transistors 222 in 3D PCM device 200 of FIGs. 2A and 2B, according to various aspects of the present disclosure. GAA transistor 222 can have a gate electrode 302 (e.g., part of word line 208) circumscribing selector 220. The same as the word lines, gate electrodes 302 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicides, or any combination thereof. In one example, gate electrode 302 may include polysilicon, such as doped polysilicon. As shown in FIGs. 3A and 3B, selector 220 can have a circular shape in the plan view. Selector 220 can include a gate dielectric 304 and a channel 306. In some implementations as shown in FIG. 3B, selector 220 can further include a cap layer 308. As shown in FIGs. 3A and 3B, gate dielectric 304 can have a ring shape and be disposed between gate electrode 302 and channel 306. In some implementations, gate dielectric 304 includes dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combinations thereof. In one example, gate dielectric 304 may include silicon oxide. Channel 306 can have a circular shape if selector 220 does not include cap layer 308 (e.g., shown in FIG. 3A) or have a ring shape if selector 220 includes cap layer 308 (e.g., shown in FIG. 3B) . Nevertheless, channel 306 can include semiconductor materials, such as single crystalline silicon, polysilicon, amorphous silicon, or any combinations thereof. In one example, channel 306 may include polysilicon. Cap layer 308 can include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectrics, or any combinations thereof. In one example, cap layer 308 may include silicon oxide. It is understood that the shape of selector 220 in the plan view is not limited to circular and can be any other shapes, such as rectangular, square, oval, etc. For example, in FIG. 3C, selector 220 may have a square shape or a rectangular shape without or with cap layer 308 (not shown) . Nevertheless, in each vertical GAA transistor 222, gate electrode 302, gate dielectric 304, and channel 306 are disposed radially, e.g., in a radially inward direction toward the center of selector 220.

As described above, vertical GAA transistors 222 can replace the conventional planar transistors, diodes, or OTS selectors, as the selection devices to control the on/off current applied to PCM structures 212. Compared with the conventional planar transistors, diodes, or OTS selectors, vertical GAA transistors 222 can provide larger current drive and/or smaller memory bit size, in particular, in a 3D architecture that can be easily scaled up vertically.

Referring back to FIGs. 2A and 2B, upper PCM stack 203 can have similar structures as lower PCM stack 201, including parallel bit lines 224 extending laterally, common plate 206 shared with lower PCM stack 201, parallel word lines 226 extending laterally and disposed between bit lines 224 and common plate 206, and PCM cells 228 each disposed at an intersection of a respective bit line 224 and a respective word line 226. Each PCM cell 228 in upper PCM stack 203 can include a PCM structure 230 between a respective word line 226 and common plate 206, as well as a selector 232 extending vertically through a respective word line 226 and disposed vertically between PCM structure 230 and a respective bit line 224. In each PCM cell 228 in upper PCM stack 203, a gate electrode (i.e., part of a respective word line 226) circumscribing selector 232, and selector 232 can form a vertical GAA transistor 234. The details of each component in upper PCM stack 203 (e.g., structures, materials, functions, etc. ) may be the same as their counterparts in lower PCM stack 201 described above and thus, may not be repeated.

As shown in FIG. 2B, bit lines 204 in lower PCM stack 201 and bit lines 224 in upper PCM stack 203 extend in the same lateral direction, e.g., the x-direction and thus, are parallel to one another laterally, according to some implementations. Similarly, word lines 208 in lower PCM stack 201 and word lines 226 in upper PCM stack 203 extend in the same lateral direction, e.g., the y-direction and thus, are parallel to one another laterally, according to some implementations. It is understood that in some examples (not shown) , bit lines 204 in lower PCM stack 201 and bit lines 224 in upper PCM stack 203 may extend in different lateral directions, e.g., bit lines 204 in the x-direction while bit lines 224 in the y-direction thus, are perpendicular to one another laterally, according to some implementations. Similarly, word lines 208 in lower PCM stack 201 and word lines 226 in upper PCM stack 203 may extend in different lateral directions, e.g., word lines 208 in the y-direction while word lines 226 in the x-direction thus, are perpendicular to one another laterally, according to some implementations. The perpendicularly arranged bit lines 204/224 or word lines 208/226 in lower and upper PCM stacks 201 and 203 can reduce the coupling effect between adjacent PCM stacks. It is also understood that the number of PCM stacks may be further increased by stacking more PCM stacks over upper PCM stack 203 with shared common plates of adjacent PCM stacks.

FIG. 4 illustrates a circuit diagram of an exemplary 3D PCM device 400, according to some aspects of the present disclosure. 3D PCM device 400 may be one example of 3D PCM device 200 in FIGs. 2A and 2B. As shown in FIG. 4, bit lines (BL) and word lines (WL) can be in a cross-point architecture. Word lines WL1, n WL 1, n+1, WL1, n+2, and WL 1, n+3 may correspond to word lines 208 in lower PCM stack 201 in FIGs. 2A and 2B, and word lines WL2, n WL 2, n+1, WL2, n+2, and WL 2, n+3 may correspond to word lines 226 in upper PCM stack 203. Bit lines BL 1, m and BL 1, m+1 may correspond to bit lines 204 in lower PCM stack 201 in FIGs. 2A and 2B, and Bit lines BL 2, m and BL 2, m+1 may correspond to bit lines 224 in upper PCM stack 203. PCM cells 402 (e.g., corresponding to

PCM cells

210 and 228 in FIGs. 2A and 2B) can be formed at each intersection of a respective bit line and a respective word line. Each PCM cell 402 can include a PCM structure 404 (corresponding to

PCM structures

212 and 230 in FIGs. 2A and 2B) and a GAA transistor 406 (corresponding to

GAA transistors

222 and 234 in FIGs. 2A and 2B) . As shown in FIG. 4, one of the source or drain of GAA transistor 406 can be electrically connected to one node of PCM structure 404, and another one of the source or drain of GAA transistor 406 can be electrically connected to the respective bit line (e.g., BL 1, m) of PCM cell 402. The gate of GAA transistor 406 can be electrically connected to the respective word line (e.g., WL 1, n) . Another node of PCM structure 404 can be grounded through a respective command plate.

FIG. 7 illustrates a block diagram of an exemplary system 700 having a 3D memory device, according to some aspects of the present disclosure. System 700 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in FIG. 7, system 700 can include a host 708 and a memory system 702 having one or more 3D memory devices 704 and a memory controller 706. Host 708 can be a processor of an electronic device, such as a central processing unit (CPU) , or a system-on-chip (SoC) , such as an application processor (AP) . Host 708 can be configured to send or receive data to or from 3D memory devices 704.

3D memory device 704 can be any 3D memory devices disclosed herein, such as

3D PCM devices

200 and 400 shown in FIGs. 2A, 2B, and 4. Consistent with the scope of the present disclosure, a novel architecture of

3D PCM devices

200 and 400 is provided with sufficient current drive, reduced memory bit size and cost, and increased data storage density. In the architecture disclosed herein, selectors and parts of the word lines circumscribing the selectors can form vertical GAA transistors for controlling the on and off of the current applied to the PCM structures. The vertical GAA transistors can provide higher current drive compared with the planar transistors with the size dimensions or maintain the same current drive with reduced dimensions. The architecture disclosed herein can be easily scaled up, for example, vertically with more stacks, to further increase the memory bit density and reduce the memory bit size and cost.

Memory controller 706 (a.k.a., a controller circuit) is coupled to 3D memory device 704 and host 708 and is configured to control 3D memory device 704, according to some implementations. For example, memory controller 706 may be configured to control operations of

PCM cells

210, 228, and 402 through

bit lines

204 and 224 and

word lines

208 and 226. Memory controller 706 can manage the data stored in 3D memory device 704 and communicate with host 708. In some implementations, memory controller 706 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 706 is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller 706 can be configured to control operations of 3D memory device 704, such as read, erase, and program operations. Memory controller 706 can also be configured to manage various functions with respect to the data stored or to be stored in 3D memory device 704 including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 706 is further configured to process error correction codes (ECCs) with respect to the data read from or written to 3D memory device 704. Any other suitable functions may be performed by memory controller 706 as well, for example, formatting 3D memory device 704. Memory controller 706 can communicate with an external device (e.g., host 708) according to a particular communication protocol. For example, memory controller 706 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

Memory controller 706 and one or more 3D memory devices 704 can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system 702 can be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 8A, memory controller 706 and a single 3D memory device 704 may be integrated into a memory card 802. Memory card 802 can include a PC card (PCMCIA, personal computer memory card international association) , a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro) , an SD card (SD, miniSD, microSD, SDHC) , a UFS, etc. Memory card 802 can further include a memory card connector 804 electrically coupling memory card 802 with a host (e.g., host 708 in FIG. 7) . In another example as shown in FIG. 8B, memory controller 706 and multiple 3D memory devices 704 may be integrated into an SSD 806. SSD 806 can further include an SSD connector 808 electrically coupling SSD 806 with a host (e.g., host 708 in FIG. 7) . In some implementations, the storage capacity and/or the operation speed of SSD 806 is greater than those of memory card 802.

FIGs. 5A–5F illustrate an exemplary fabrication process for forming a 3D PCM device, according to some implementations of the present disclosure. FIG. 6 illustrates a flowchart of an exemplary method 600 for forming a 3D PCM device, according to some implementations of the present disclosure. Examples of the 3D PCM device depicted in FIGs. 5A–5F and 6 include 3D PCM device 200 depicted in FIGs. 2A and 2B. FIGs. 5A–5F and 6 will be described together. It is understood that the operations shown in method 600 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 6.

Referring to FIG. 6, method 600 starts at operation 602, in which a plurality of bit lines are formed. The plurality of bit lines can be parallel to one another and extend laterally. As shown in FIG. 5A, a plurality of bit lines 502 are formed through a dielectric layer (not shown) . To form bit lines 502, the dielectric layer having a dielectric material, such as silicon oxide, can be first formed on a substrate (not shown) using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , or any combination thereof. The trenches (not shown) of bit lines 502 can be etched through the dielectric layer using dry etching and/or wet etching, such as reactive ion etch (RIE) . After the formation of the trenches, bit lines 502 can be formed by depositing one or more conductive materials, such as W, to fill the trenches using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bit lines 502 can be further planarized by chemical mechanical polishing (CMP) and/or etching such that the upper ends (the tops surface) of bit lines 502 are planarized.

Method 600 proceeds to operation 604, as illustrated in FIG. 6, in which a plurality of word lines are formed above the plurality of bit lines. The plurality of word lines can be parallel to one another and extend laterally. In some implementations, to form the plurality of word lines, the plurality of word lines are patterned, such that the plurality of word lines and the plurality of bit lines are in a cross-point architecture. The word line can include polysilicon.

As shown in FIG. 5B, a plurality of word lines 504 are formed through another dielectric layer (not shown) above bit lines 502. Word lines 504 and bit lines 502 can be spaced apart vertically by a dielectric layer to avoid direct contact. Word lines 504 and bit lines 502 can also be in a cross-point architecture, i.e., perpendicular to one another laterally. To form word lines 504, one or more dielectric layers having a dielectric material, such as silicon oxide, can be formed on bit lines 502 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The trenches (not shown) of word lines 504 can be patterned to be perpendicular to bit lines 502 (i.e., along perpendicular lateral directions, e.g., x-direction and y-direction) using lithography and then be etched through the dielectric layers using dry etching and/or wet etching, such as RIE. After the formation of the trenches, word lines 504 can be formed by depositing one or more conductive materials, such as doped polysilicon, to fill the trenches using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Word lines 504 can be further planarized by CMP and/or etching such that the upper ends (the tops surface) of word lines 504 are planarized.

Method 600 proceeds to operation 606, as illustrated in FIG. 6, in which a plurality of selectors are formed. Each of the plurality of selectors can extend vertically through one of the plurality of word lines and is in contact with one of the plurality of bit lines. In some implementations, to form the plurality of selectors, a plurality of holes are etched through the plurality of word lines. Each of the plurality of holes can be etched at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. In some implementations, to form the plurality of selectors, a gate dielectric layer and a channel layer are subsequentially deposited along a sidewall of each of the plurality of holes. The gate dielectric layer can include silicon oxide, and the channel layer can include polysilicon.

As shown in FIG. 5C, a plurality of selectors 506 are formed. Each selector 506 can extend vertically through one of word lines 504 and be in contact with one of bit lines 502. For example, each selector 506 may be formed at a respective intersection of one word line 504 and one bit line 502. To form selectors 506, another dielectric layer (not shown) having a dielectric material, such as silicon oxide, can be formed on word lines 504 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. A plurality of holes (not shown) can be etched through word lines 504 as well as the dielectric layers above word lines 504 and between word lines 504 and bit lines 502. The holes can be patterned at intersections of word lines 504 and bit lines 502 using lithography and etched using dry etching and/or wet etching, such as RIE, until being stopped by bit lines 502. After the formation of the holes, selectors 506 can be formed by sequentially depositing a gate dielectric layer (e.g., silicon oxide) and a channel layer (e.g., polysilicon) along the sidewall of each hole using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, a cap layer (e.g., silicon oxide) is deposited after the channel layer as well to fill the hole. Selectors 506 can be further planarized by CMP and/or etching such that the upper ends (the tops surface) of selectors 506 are planarized.

Method 600 proceeds to operation 608, as illustrated in FIG. 6, in which a plurality of PCM structures are formed above and in contact with the plurality of selectors, respectively. In some implementations, to form the plurality of PCM structures, a first electrode layer, a PCM element layer, and a second electrode layer are subsequentially deposited on the plurality of selectors, and the first electrode layer, the PCM element layer, and the second electrode layers are patterned to form a first electrode, a PCM element, and a second electrode stacked on each of the plurality of selectors. The PCM element layer can include a chalcogenide-based alloy, and the first and second electrode layers can include carbon.

As illustrated in FIG. 5D, a plurality of PCM structures 514 are formed above and in contact with selectors 506, respectively. Each PCM structure 514 can include two

electrodes

508 and 512, and a PCM element 510 sandwiched vertically between

electrodes

508 and 512. To form PCM structures 514, a first electrode layer (e.g., carbon) , a PCM element layer (e.g., a chalcogenide-based alloy) , and a second electrode layer (e.g., carbon) can sequentially be deposited on selectors 506 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The electrode and PCM element layers can then be patterned and etched to form a first electrode, a PCM element, and a second electrode stacked on each selector 506 using lithography and etching (e.g., dry etching and/or wet etching) .

Method 600 proceeds to operation 610, as illustrated in FIG. 6, in which a common plate is formed above and in contact with the plurality of PCM structures. As illustrated in FIG. 5E, a common plate 516 is formed above and in contact with PCM structures 514. To form common plate 516, one or more dielectric layers having a dielectric material, such as silicon oxide, can be formed surrounding PCM structures 514 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, such that the top surfaces of PCM structures 514 are flush with the top surface of the dielectric layers. Common plate 516 can then be formed on PCM structures 514 by depositing a conductive layer (e.g., W or Cu) using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As a result, a PCM stack including bit lines 502, word lines 504, selectors 506, PCM structures 514, and common plate 516 can be formed.

It is understood that the similar fabrication processes of

operations

602, 604, 606, 608, and 610 may be repeated to form additional PCM stack (s) . For example, as shown in FIG. 5F, PCM structures 518, word lines 520, selectors 522, and bit lines 524 may be sequentially formed on common plate 516 to form another PCM stack using the similar fabrication processes described above with respect to FIGs. 5A–5E and 6.

According to one aspect of the present disclosure, a 3D memory device includes a plurality of bit lines extending laterally, a common plate extending laterally, a plurality of word lines extending laterally and being disposed between the plurality of bit lines and the common plate, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a PCM structure between the respective word line and the common plate, and a selector extending vertically through the respective word line and being disposed between the PCM structure and the respective bit line.

In some implementations, the respective word line includes a gate electrode circumscribing the selector.

In some implementations, the selector includes a gate dielectric and a channel, and the gate electrode, the gate dielectric, and the channel are disposed radially.

In some implementations, at least the gate electrode, the gate dielectric, and the channel form a GAA transistor extending vertically.

In some implementations, the common plate is grounded.

In some implementations, the bit lines and the common plate include a metal, and the word lines include polysilicon.

In some implementations, the PCM structure includes two electrodes and a PCM element vertically between the two electrodes.

In some implementations, the PCM element includes a chalcogenide-based alloy, and the electrodes include carbon.

In some implementations, the plurality of word lines and the plurality of bit lines are in a cross-point architecture.

According to another aspect of the present disclosure, a PCM cell includes a PCM structure, and a GAA transistor stacked over one another. One of a source or a drain of the GAA transistor is electrically connected to one node of the PCM structure.

In some implementations, the GAA transistor includes a gate electrode, a gate dielectric, and a channel disposed radially.

In some implementations, the gate electrode is part of a word line of the PCM cell.

In some implementations, a gate of the GAA transistor is electrically connected to the word line.

In some implementations, another one of the source or the drain of the GAA transistor is electrically connected to a bit line of the PCM cell.

In some implementations, another node of the PCM structure is grounded.

According to still another aspect of the present disclosure, a system includes a 3D memory device configured to store data, and a memory controller coupled to the 3D memory device and configured to control operations of a plurality of PCM cells through a plurality of bit lines and a plurality of word lines. The 3D memory device includes the plurality of bit lines extending laterally, a common plate extending laterally, the plurality of word lines extending laterally and being disposed between the plurality of bit lines and the common plate, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a PCM structure between the respective word line and the common plate, and a selector extending vertically through the respective word line and being disposed between the PCM structure and the respective bit line.

According to yet another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A plurality of bit lines are formed. A plurality of word lines are formed above the plurality of bit lines. A plurality of selectors are formed. Each of the plurality of selectors extends vertically through one of the plurality of word lines and is in contact with one of the plurality of bit lines. A plurality of PCM structures are formed above and in contact with the plurality of selectors, respectively. A common plate is formed above and in contact with the plurality of PCM structures.

In some implementations, to form the plurality of word lines, the plurality of word line are patterned, such that the plurality of word lines and the plurality of bit lines are in a cross-point architecture.

In some implementations, to form the plurality of selectors, a plurality of holes are etched through the plurality of word lines. Each of the plurality of holes is etched at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. In some implementations, to form the plurality of selectors, a gate dielectric layer and a channel layer are subsequentially deposited along a sidewall of each of the plurality of holes.

In some implementations, the word lines include polysilicon, the gate dielectric layer includes silicon oxide, and the channel layer includes polysilicon.

In some implementations, to form the plurality of PCM structures, a first electrode layer, a PCM element layer, and a second electrode layer are subsequentially deposited on the plurality of selectors, and the first electrode layer, the PCM element layer, and the second electrode layers are patterned to form a first electrode, a PCM element, and a second electrode stacked on each of the plurality of selectors.

In some implementations, the PCM element layer includes a chalcogenide-based alloy, and the first and second electrode layers include carbon.

The foregoing description of the specific implementations will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications of such specific implementations, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

A three-dimensional (3D) memory device, comprising:

a plurality of bit lines extending laterally;

a common plate extending laterally;

a plurality of word lines extending laterally and being disposed between the plurality of bit lines and the common plate; and

a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines,

wherein each of the plurality of memory cells comprises:

a phase-change memory (PCM) structure between the respective word line and the common plate; and

a selector extending vertically through the respective word line and being disposed between the PCM structure and the respective bit line.
The 3D memory device of claim 1, wherein the respective word line comprises a gate electrode circumscribing the selector.
The 3D memory device of claim 2, wherein

the selector comprises a gate dielectric and a channel; and

the gate electrode, the gate dielectric, and the channel are disposed radially.
The 3D memory device of claim 3, wherein at least the gate electrode, the gate dielectric, and the channel form a gate all around (GAA) transistor extending vertically.
The 3D memory device of any one of claims 1-4, wherein the common plate is grounded.
The 3D memory device of any one of claims 1-5, wherein the bit lines and the common plate comprise a metal, and the word lines comprise polysilicon.
The 3D memory device of any one of claims 1-6, wherein the PCM structure comprises two electrodes and a PCM element vertically between the two electrodes.
The 3D memory device of claim 7, wherein the PCM element comprises a chalcogenide-based alloy, and the electrodes comprise carbon.
The 3D memory device of any one of claims 1-8, wherein the plurality of word lines and the plurality of bit lines are in a cross-point architecture.
A phase-change memory (PCM) cell, comprising:

a PCM structure, and a gate all around (GAA) transistor stacked over one another,

wherein one of a source or a drain of the GAA transistor is electrically connected to one node of the PCM structure.
The PCM cell of claim 10, wherein the GAA transistor comprises a gate electrode, a gate dielectric, and a channel disposed radially.
The PCM cell of claim 11, wherein the gate electrode is part of a word line of the PCM cell.
The PCM cell of claim 12, wherein a gate of the GAA transistor is electrically connected to the word line.
The PCM cell of any one of claims 10-13, wherein another one of the source or the drain of the GAA transistor is electrically connected to a bit line of the PCM cell.
The PCM cell of any one of claims 10-14, wherein another node of the PCM structure is grounded.
The PCM cell of any one of claims 10-15, wherein the PCM structure comprises two electrodes and a PCM element vertically between the two electrodes.
The PCM cell of claim 16, wherein the PCM element comprises a chalcogenide-based alloy, and the electrodes comprise carbon.
A system, comprising:

a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising:

a plurality of bit lines extending laterally;

a common plate extending laterally;

a plurality of word lines extending laterally and being disposed between the plurality of bit lines and the common plate;

a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines,

wherein each of the plurality of memory cells comprises:

a phase-change memory (PCM) structure between the respective word line and the common plate; and

a selector extending vertically through the respective word line and being disposed between the PCM structure and the respective bit line; and

a memory controller coupled to the 3D memory device and configured to control operations of the plurality of memory cells through the plurality of bit lines and the plurality of word lines.
A method for forming a three-dimensional (3D) memory device, comprising:

forming a plurality of bit lines;

forming a plurality of word lines above the plurality of bit lines;

forming a plurality of selectors, wherein each of the plurality of selectors extends vertically through one of the plurality of word lines and is in contact with one of the plurality of bit lines;

forming a plurality of phase-change memory (PCM) structures above and in contact with the plurality of selectors, respectively; and

forming a common plate above and in contact with the plurality of PCM structures.
The method of claim 19, wherein forming the plurality of word lines comprises patterning the plurality of word line, such that the plurality of word lines and the plurality of bit lines are in a cross-point architecture.
The method of claim 20, wherein forming the plurality of selectors comprises:

etching a plurality of holes through the plurality of word lines, wherein each of the plurality of holes is etched at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines; and

subsequentially depositing a gate dielectric layer and a channel layer along a sidewall of each of the plurality of holes.
The method of claim 21, wherein the word lines comprise polysilicon, the gate dielectric layer comprises silicon oxide, and the channel layer comprises polysilicon.
The method of any one of claims 19-22, wherein forming the plurality of PCM structures comprises:

subsequentially depositing a first electrode layer, a PCM element layer, and a second electrode layer on the plurality of selectors; and

patterning the first electrode layer, the PCM element layer, and the second electrode layers to form a first electrode, a PCM element, and a second electrode stacked on each of the plurality of selectors.
The method of claim 23, wherein the PCM element layer comprises a chalcogenide-based alloy, and the first and second electrode layers comprise carbon.