Nothing Special   »   [go: up one dir, main page]

WO2022126638A1 - 一种驱动背板及其制作方法、显示装置 - Google Patents

一种驱动背板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2022126638A1
WO2022126638A1 PCT/CN2020/137722 CN2020137722W WO2022126638A1 WO 2022126638 A1 WO2022126638 A1 WO 2022126638A1 CN 2020137722 W CN2020137722 W CN 2020137722W WO 2022126638 A1 WO2022126638 A1 WO 2022126638A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal line
substrate
conductive layer
pair
layer
Prior art date
Application number
PCT/CN2020/137722
Other languages
English (en)
French (fr)
Inventor
王文涛
史大为
王培�
赵东升
杨璐
霍亮
段岑鸿
黄灿
温宵松
Original Assignee
京东方科技集团股份有限公司
重庆京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/137722 priority Critical patent/WO2022126638A1/zh
Priority to CN202080003445.9A priority patent/CN115176342A/zh
Priority to US17/621,176 priority patent/US12057455B2/en
Publication of WO2022126638A1 publication Critical patent/WO2022126638A1/zh

Links

Images

Classifications

    • H01L27/124—
    • H01L27/1244—
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H01L27/1259—
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving backplane, a manufacturing method thereof, and a display device.
  • the display device has the characteristics of lightness, thinness, power saving, and diversified application scenarios, and has broad application prospects.
  • LCD liquid crystal display devices
  • ELD inorganic electroluminescent display devices
  • OLED organic electroluminescent display devices
  • LCD liquid crystal display devices
  • ELD inorganic electroluminescent display devices
  • OLED organic electroluminescent display devices
  • LCD liquid crystal display devices
  • ELD Electroluminescent Display
  • OLED organic electroluminescent display devices
  • LCD liquid crystal display devices
  • FED Field Emission Display
  • FED Field Effection Display
  • Each type of display device can be applied to various scenarios to meet different image display requirements.
  • a driving backplane in one aspect, includes: a substrate; a first conductive layer disposed on the substrate, a first insulating layer disposed on a side of the first conductive layer away from the substrate, and a The first insulating layer is away from the second conductive layer on the side of the first conductive layer.
  • the first conductive layer includes at least one first signal line; the second conductive layer includes at least one second signal line.
  • Each first signal line and one second signal line form a signal line pair; in the same signal line pair, the first signal line and the second signal line extend in the same direction, and the orthographic projection of the first signal line on the substrate is the same as that of the second signal line.
  • the orthographic projection of the two signal lines on the substrate has a first overlapping area, and the second signal line is coupled to the first signal line.
  • the driving backplane further includes: a second insulating layer disposed on a side of the second conductive layer away from the substrate, and a third conductive layer disposed on a side of the second insulating layer away from the substrate.
  • the third conductive layer includes at least one first conductive pattern; each first conductive pattern penetrates the second insulating layer and is coupled to the second signal line, and the first conductive pattern penetrates the second insulating layer and the first insulating layer and the first The signal line is coupled.
  • the driving backplane further includes: at least one first via hole provided on the first insulating layer; at least one second via hole provided on the second insulating layer.
  • each first via hole and a second via hole form a via hole pair, and in the same via hole pair, the first via hole is communicated with the second via hole.
  • the part of the first signal line exposed by the via hole pair is the first connection part; the part of the second signal line exposed by the second via hole in the via hole pair is the second connection part, and the second connection part is on the substrate
  • the orthographic projection of and the first overlapping area have a second overlapping area; the first conductive pattern is in contact with the second connection part through the second via hole, and is in contact with the first connection part through the via hole pair.
  • the first via has an opposite first opening and a second opening, the first opening is farther from the substrate than the second opening; the second via has an opposite third opening The opening and the fourth opening. Compared with the fourth opening, the third opening is away from the substrate.
  • the combination of the orthographic projection of the first opening on the substrate and the orthographic projection of the second connecting portion on the substrate substantially coincides with the orthographic projection of the fourth opening on the substrate.
  • the orthographic projection of the via pair on the substrate is contained within the boundaries of the orthographic projection of the signal line pair on the substrate.
  • the first signal line in the same signal line pair, is coupled to the second signal line through a plurality of via hole pairs, and the plurality of via hole pairs are arranged along the extending direction of the first signal line.
  • the orthographic projection of the first conductive pattern on the substrate completely covers the orthographic projection of the via pair on the substrate.
  • the minimum distance between the edge of the orthographic projection of the first conductive pattern on the substrate and the edge of the orthographic projection of the via pair on the substrate is greater than or equal to 1/1 of the width of the first signal line 6.
  • the ratio of the width of the first overlapping region to the width of the first signal line is 1/3 ⁇ 1/2.
  • the second conductive layer further includes: a second conductive pattern. Wherein, in a pair of signal lines adjacent to the second conductive pattern, the first signal line is closer to the second conductive pattern than the second signal line.
  • the second conductive layer includes at least two second conductive patterns, and the at least two second conductive patterns include: one electrode plate of a capacitor in a pixel circuit included in the driving backplane and/or an initialization signal line.
  • the widths of the first signal line and the second signal line are equal.
  • the driving backplane further includes two driving circuits respectively coupled to both ends of the first signal line.
  • the at least one first signal line includes at least one of a gate line, a light emission control signal line and a reset signal line.
  • the driving backplane further includes an active pattern layer, and the active pattern layer is disposed on a side of the first conductive layer close to the substrate.
  • the active pattern layer includes at least one semiconductor pattern and a plurality of conductorization patterns, wherein each semiconductor pattern separates two conductorization patterns of the plurality of conductorization patterns.
  • the third conductive layer when the driving backplane includes a third conductive layer, the third conductive layer further includes: a power supply voltage line.
  • the extension directions of the data lines and the power supply voltage lines are the same, and the orthographic projection of the data lines on the substrate and the orthographic projection of the power supply voltage lines on the substrate have no overlapping area.
  • a display device in another aspect, includes: the driving backplane according to any of the above embodiments.
  • a method for manufacturing a driving backplane including: forming a first conductive layer on a substrate, and forming a first insulating layer and a second conductive layer on the substrate on which the first conductive layer is formed.
  • the first conductive layer includes at least one first signal line;
  • the second conductive layer is located on the side of the first insulating layer away from the first conductive layer, and the second conductive layer includes at least one second signal line; each first signal line A signal line pair is formed with a second signal line; in the same signal line pair, the first signal line and the second signal line extend in the same direction, and the orthographic projection of the first signal line on the substrate is the same as that of the second signal line on the substrate.
  • the orthographic projection on has a first overlapping area, and the second signal line is coupled with the first signal line.
  • the manufacturing method of the driving backplane further includes: forming a second insulating layer on a side of the second conductive layer away from the substrate, and forming a third conductive layer on a side of the second insulating layer away from the substrate.
  • the third conductive layer includes at least one first conductive pattern; the first insulating layer has at least one first via hole; the second insulating layer has at least one second via hole; each first via hole and one second via hole A via pair is formed. In the same via pair, the first via is communicated with the second via.
  • the part of the first signal line exposed by the via hole pair is the first connection part; the part of the second signal line exposed by the second via hole in the via hole pair is the second connection part, and the second connection part is on the substrate
  • the orthographic projection of the and the first overlapping area have a second overlapping area; the first conductive pattern is in contact with the second connection part through the second via hole, and is in contact with the first connection part through the via hole pair.
  • the step of forming the first insulating layer, the second conductive layer and the second insulating layer includes: on the substrate on which the first conductive layer is formed, forming a first insulating film; on the substrate on which the first insulating film is formed; On the substrate formed with the second conductive layer, a second conductive layer is formed; on the substrate formed with the second conductive layer, a second insulating film is formed, and the second insulating film and the first insulating film are patterned to form a second via hole A second insulating layer and a first insulating layer including a first via.
  • the second conductive layer includes at least one second signal line.
  • FIG. 1 is a waveform diagram of a voltage signal at a position A close to a signal source and a voltage signal at a position B away from the signal source according to some embodiments of the present disclosure
  • FIG. 2 is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 3 is a structural diagram of a 7T1C pixel circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a structural diagram of a display panel including a GOA driving circuit according to some embodiments of the present disclosure
  • FIG. 5 is a diagram of a substrate structure according to some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of a drive backplane according to some embodiments of the present disclosure.
  • Fig. 7 is a sectional view of the drive backplane in Fig. 6 along the A-A' direction;
  • FIG. 8 is an enlarged structural view of the B area of the driving backplane in FIG. 6;
  • FIG. 9 is a diagram of a via pair structure according to some embodiments of the present disclosure.
  • FIG. 10 is a structural diagram of a first conductive layer according to some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of a second conductive layer according to some embodiments of the present disclosure.
  • FIG. 12 is a structural diagram of an active layer according to some embodiments of the present disclosure.
  • FIG. 13 is a diagram of a third conductive layer and via structure according to some embodiments of the present disclosure.
  • FIG. 14 is a structural diagram of a third conductive layer and a fourth conductive layer according to some embodiments of the present disclosure.
  • FIG. 15 is a flow chart of manufacturing a drive backplane according to some embodiments of the present disclosure.
  • FIG. 16 is a flow chart of the fabrication of a drive backplane according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implying the number of indicated technical features.
  • a feature defined as “first”, “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if it is detected that" are optionally interpreted to mean “on determining" or “in response to determining" or “on detecting... When! or "In response to detection of".
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the display device includes a plurality of sub-pixels with different light-emitting colors, and most of them use a driving backplane to control the light-emitting brightness of each sub-pixel to realize corresponding image display.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the existing AMOLED display devices are no longer limited to small and medium-sized mobile phones.
  • the application scope is gradually expanding to medium and large-sized products such as folding display devices, notebook computers (Notebook), and vehicle-mounted display devices.
  • some signal lines increase accordingly. At this time, the resistance of the signal lines increases.
  • the signal lines are close to the signal source (ie, the circuit that outputs the signal).
  • the voltage values at the location and the location far from the signal source are inconsistent, resulting in the problem of uneven color (such as purple) in the direction of signal transmission.
  • the voltage value of the voltage signal at position A close to the signal source in the signal line is not equal to the voltage value of the voltage signal at position B far away from the signal source, and the absolute value of the difference between the voltage signals at position A is greater than the voltage at position B
  • the absolute value of the signal difference that is, during the transmission of the voltage signal from position A to position B, due to the influence of the surface resistance of the signal line, signal attenuation occurs, which adversely affects the display effect.
  • the display device may be: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a Personal Digital Assistant (PDA), a digital camera, a camcorder, Viewfinders, navigators, vehicles, large-area walls, home appliances, information inquiry equipment (such as business inquiry equipment in e-government, banks, hospitals, electric power and other departments, etc.
  • PDA Personal Digital Assistant
  • Viewfinders navigators
  • vehicles large-area walls
  • home appliances information inquiry equipment (such as business inquiry equipment in e-government, banks, hospitals, electric power and other departments, etc.
  • the display device includes a display panel 100 .
  • the display panel has a display area (active area, AA area for short) and a peripheral area S.
  • the peripheral area S is located on at least one side of the display area.
  • the peripheral area S may be arranged in a circle around the display area.
  • the display panel may be an OLED (Organic Light Emitting Diode) panel, a QLED (Quantum Dot Light Emitting Diodes) panel, an LCD (Liquid Crystal Display, liquid crystal display) panel, a micro LED ( Including: miniLED or microLED) panels, etc.
  • OLED Organic Light Emitting Diode
  • QLED Quadantum Dot Light Emitting Diodes
  • LCD Liquid Crystal Display, liquid crystal display
  • micro LED Including: miniLED or microLED
  • the display panel 100 may include a plurality of sub-pixels P, and the plurality of sub-pixels P are located in the AA area.
  • the plurality of sub-pixels P may be arranged in an array.
  • the sub-pixels P arranged in a row in the X direction are referred to as the same pixel
  • the sub-pixels P arranged in a row in the Y direction are referred to as the same column of pixels.
  • the plurality of sub-pixels P include first-color sub-pixels P, second-color sub-pixels P, and third-color sub-pixels P; for example, the first color, the second color, and the third color are three primary colors; The first, second, and third colors are red, green, and blue, respectively; that is, the plurality of subpixels P include red subpixels P, green subpixels P, and blue subpixels P.
  • the display device may further include a driver chip.
  • the driver chip is a driver IC, for example, the driver IC includes a source driver.
  • the driving chip is configured to provide a driving signal to each sub-pixel P in the display panel; for example, the driving signal includes a data signal.
  • the display device may further include: a touch panel (also referred to as a touch screen, a touch structure or a touch layer).
  • the touchpad is used for sensing the touch position, and the image displayed on the display panel can be controlled according to the touch position sensed by the touchpad, thereby realizing human-computer interaction.
  • the display panel 100 includes a driving backplane 1 and a to-be-driven element (eg, a light-emitting device L), and the to-be-driven element is disposed on the driving backplane 1 and is driven by the driving backplane 1 Work.
  • a driving backplane 1 and a to-be-driven element (eg, a light-emitting device L)
  • the to-be-driven element is disposed on the driving backplane 1 and is driven by the driving backplane 1 Work.
  • the driving backplane 1 can be used to drive the light-emitting device L to emit light, including a plurality of pixel circuits 210 .
  • at least one sub-pixel P (eg, each sub-pixel P) of the display panel includes a pixel circuit 210 and a light-emitting device L.
  • the pixel circuit 210 is coupled to the light emitting device L.
  • the pixel circuit 210 is configured to drive the light emitting device L to emit light.
  • the plurality of pixel circuits are arranged in an array.
  • the embodiments of the present disclosure do not limit the specific structure of the pixel circuit, which can be designed according to actual conditions.
  • the pixel circuit is composed of electronic devices such as thin film transistors (Thin Film Transistor, TFT for short), capacitors (Capacitance, C for short).
  • a pixel circuit may include two thin film transistors (a switching transistor and a driving transistor) and a capacitor to form a 2T1C structure; of course, the pixel circuit may also include more than two thin film transistors (multiple switching transistors and a driving transistor) 3, the pixel circuit 210 may include a storage capacitor Cst and seven transistors (six switching transistors M1, M2, M3, M4, M5 and M6 and one driving transistor MD), forming a 7T1C structure.
  • the driving backplane 1 also includes a plurality of signal lines, for example, gate lines (Gate Line, GL), data lines (Data Line, DL), light-emitting control signal lines EM, initialization signal lines Init and reset signal lines Reset and Reset' etc.
  • gate lines Gate Line, GL
  • data lines Data Line, DL
  • light-emitting control signal lines EM initialization signal lines Init and reset signal lines Reset and Reset' etc.
  • the gate line GL can be used to transmit gate driving signals;
  • the data line DL is configured to provide a data signal (data current or data voltage) for the to-be-driven element to drive the to-be-driven element to work;
  • a driving control signal line (such as a lighting control signal) Line EM) may be used to transmit a driving control signal (eg, a lighting control signal);
  • an initialization signal line Init may be used to transmit an initialization signal; and, a reset signal line may be used to transmit a reset signal.
  • each pixel circuit in the same row may be coupled with one gate line GL, one reset signal line Reset, one reset signal line Reset', and one light emission control signal line EM.
  • the reset signal line Reset and reset signal line Reset' coupled to each pixel circuit in the same row can be two signal lines that transmit different reset signals respectively; they can also be the same signal line.
  • the pixel circuits of the same column may be coupled to the same data line DL.
  • control electrodes (gates) of a part of the switching transistors are used to receive the reset signal.
  • Control electrodes of another part of the switching transistors are used to receive gate driving signals.
  • the control electrodes of another part of the switching transistors are used for receiving driving control signals such as lighting control signals.
  • the transistor M5 and the transistor M6 are turned on in response to the reset signal, and the initialization signal is transmitted through the transistor M5 and the transistor M6 to the control electrode of the driving transistor MD and the anode of the light-emitting device L, respectively, reaching the anode of the light-emitting device L and the driving transistor MD.
  • the control pole is reset for the purpose.
  • the transistors M1 and M2 are turned on, the control electrode (g) and the drain electrode (d) of the driving transistor MD are coupled, and the driving transistor MD is in a diode-on state.
  • a data signal is written to the source (s) of the drive transistor MD through the transistor M1, and a compensation signal obtained from the data signal and the threshold voltage of the drive transistor MD is applied to the gate (g) of the drive transistor MD.
  • the transistor M3 and the transistor M4 are turned on, and the current path between the first power supply voltage line VDD and the second power supply voltage terminal VSS is turned on.
  • the driving current generated based on the difference between the voltage of the gate (g) of the driving transistor MD and the first power supply voltage signal (signal provided by VDD) is transmitted to the light emitting device L through the above current path to drive the light emitting device L to emit light.
  • one pole (eg anode) of the light emitting device L is coupled to the pixel circuit, and the other pole (eg cathode) of the light emitting device L is coupled to the second power supply voltage terminal VSS; for example, the second power supply voltage terminal VSS Configured to transmit DC voltage, such as DC low voltage.
  • the light-emitting device L may adopt a light-emitting device including LED (Light Emitting Diode), OLED (Organic Light Emitting Diode), or QLED.
  • the light-emitting device L includes a cathode and an anode, and a light-emitting functional layer between the cathode and the anode.
  • the light-emitting functional layer may include, for example, a light-emitting layer E, a hole transport layer (Hole Transporting Layer, HTL) located between the light-emitting layer E and the anode, and an electron transport layer (Election Transporting Layer, located between the light-emitting layer E and the cathode, ETL).
  • HIL hole injection layer
  • HIL electron injection layer
  • EIL election Injection Layer
  • the anode may be formed of, for example, a transparent conductive material with a high work function
  • the electrode material may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO) oxide Zinc (ZnO), indium oxide (In2O3), aluminum zinc oxide (AZO), carbon nanotubes, etc.
  • the cathode can be formed of materials with high conductivity and low work function, for example, and the electrode materials can include magnesium aluminum alloy (MgAl) and lithium Alloys such as aluminum alloy (LiAl) or simple metals such as magnesium (Mg), aluminum (Al), lithium (Li), and silver (Ag).
  • the material of the light-emitting layer can be selected according to the color of the emitted light.
  • the material of the light-emitting layer includes a fluorescent light-emitting material or a phosphorescent light-emitting material.
  • the light-emitting layer may adopt a doping system, that is, mixing a doping material into a host light-emitting material to obtain a usable light-emitting material.
  • a doping system that is, mixing a doping material into a host light-emitting material to obtain a usable light-emitting material.
  • metal compound materials, derivatives of anthracene, aromatic diamine compounds, triphenylamine compounds, aromatic triamine compounds, biphenyl diamine derivatives, triarylamine polymers, and the like can be used as the host light-emitting material.
  • the driving backplane 1 may further include: a GOA (Gate Driver On Array) circuit connected to the gate line GL, for providing a gate driving signal to the gate line GL, and/or for supplying a light-emitting
  • the control signal line EM provides a lighting control signal.
  • the GOA driving circuit may include at least one of the light emission driver 22 and the scan driver 23 .
  • the scan driver 23 has N+1 signal output terminals (ie, signal sources for providing gate driving signals and reset signals), which are connected with the first row of sub-pixels to the N-th row of sub-pixels.
  • the gate lines GL (ie N gate lines GL) coupled to the pixel circuit 210 in the N gate lines GL are respectively coupled to the N first signal output terminals of the scan driver 23 in a one-to-one correspondence;
  • the pixel circuit is also electrically connected to the reset signal line RE0, the reset signal line RE0 is electrically connected to the scan driver 23, and the pixel drive circuit in the first row of sub-pixels is reset under the control of the initial reset signal line RE0; the second row
  • the reset signals from the sub-pixels to the sub-pixels in the Nth row are transmitted by the gate lines GL coupled to the sub-pixels in the previous row, that is, the gate lines GL coupled to the sub-pixels in the previous row are multiplexed into the reset signal lines of the sub-pixels in the current row, or
  • the gate lines GL of one row of sub-pixels are coupled to the reset signal lines of the current row of sub-pixels.
  • the emission control signal lines EM coupled to the pixel circuits 210 in the sub-pixels in the first row to the Nth row sub-pixels are coupled to the first to Nth first signal output terminals of the scan driver 23 in a one-to-one correspondence.
  • the light-emitting driver 22 has N second signal output terminals (ie, signal sources for providing light-emitting control signals), which are respectively Q 1 , Q 2 , . . . , Q N ;
  • the light-emitting control signal lines EM ie N light-emitting control signal lines EM electrically connected to the pixel circuit 210 in the sub-pixel are respectively EM(1), EM(2), ...
  • the lines EM are respectively coupled to the N second signal output terminals of the light-emitting driver 22 .
  • the setting of the GOA circuit can not only reduce the voltage attenuation on the signal line, but also reduce the bonding process of the external IC. display effect.
  • the driving backplane 1 may adopt a bilateral driving manner, that is, the driving backplane 1 includes two GOA circuits arranged opposite to each other in the row direction, for example, in FIG.
  • the scan driver 23 on the left side and the scan driver 23 on the right side contain the same number of first signal output terminals; the signals output by the first signal output terminals in the same order on the left and right sides are the same, and are identical with the same gate line. Coupling; for example, the signals output by the fifth first signal output terminal on the left and the fifth first signal output terminal on the right are the same, and both are coupled to the gate line GL(5).
  • the light-emitting driver 22 on the left side and the light-emitting driver 22 on the right side contain the same number of second signal output terminals; A light-emitting control line is coupled.
  • the two scan drivers 23 can simultaneously scan a plurality of gate lines and a plurality of reset signal lines Reset row by row, and the two light-emitting drivers 22 can simultaneously scan a plurality of lighting control signal lines row by row, because each signal line Signals on the (gate line or light-emitting control signal line) are respectively input from both ends of the signal line, which can reduce the signal attenuation on the signal line to a certain extent. For medium and large size display devices, the effect of reducing signal attenuation is more prominent.
  • the driving backplane 1 may also adopt a unilateral driving method, that is, a GOA circuit is only provided on one side of the driving backplane 1, and the GOA circuit is used for multiple gate lines, multiple reset signal lines, and multiple reset signal lines. At least one of the light emission control lines is scanned row by row.
  • the structure of the driving backplane 1 will be described in detail by taking the driving backplane 1 including the above-mentioned pixel circuit 210 as an example.
  • the driving backplane 1 includes a substrate 11 , a first conductive layer 13 disposed on the substrate 11 , and the first conductive layer 13 is disposed away from the substrate 11 .
  • the first insulating layer 12 on the side of the first insulating layer 12, and the second conductive layer 14 disposed on the side of the first insulating layer 12 away from the first insulating layer.
  • the substrate 11 is configured to carry a plurality of film layers of the driving backplane 1, which may be a blank base substrate.
  • the base substrate may be a rigid base substrate; for example, the rigid base substrate may be a glass base substrate or a PMMA (Polymethyl methacrylate, polymethyl methacrylate) base substrate, or the like.
  • the base substrate may be a flexible base substrate; for example, the flexible base substrate may be a PET (Polyethylene terephthalate, polyethylene terephthalate) base substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate substrate or PI (Polyimide, polyimide) substrate substrate, etc. Referring to FIG.
  • the substrate 11 may further include a base substrate and at least one film layer formed on the base substrate, for example, a barrier layer (Barrier), a buffer layer (Buffer) and the like.
  • the substrate 11 may include a plurality of (for example, two) stacked substrate units, and an amorphous silicon layer may be disposed between two adjacent substrate units, so as to increase the gap between the two adjacent substrate units. adhesion between.
  • Each substrate unit may include a substrate substrate and a barrier layer disposed on the substrate substrate.
  • the first conductive layer 13, the second conductive layer 14 and the like are all pattern layers.
  • the pattern layer refers to a film layer formed by one patterning process.
  • the patterning process refers to a process capable of forming at least one pattern having a certain shape.
  • a thin film is formed on the substrate 11 by any of various film forming processes such as deposition, coating, sputtering, etc., and then the thin film is patterned to form a film layer including at least one pattern, which is called a pattern layer .
  • the patterning steps include: coating photoresist, exposing, developing, etching and stripping photoresist, etc.
  • the positional relationship of a plurality of patterns belonging to the same pattern layer is referred to as the same-layer arrangement.
  • the first conductive layer 13 includes at least one first signal line 131 .
  • the first conductive layer 13 includes a plurality of first signal lines 131 extending in the same direction, and there is a gap between two adjacent first signal lines 131 .
  • Each of the first signal lines 131 may be used to transmit one kind of signal, and the driving signal may be a gate driving signal, a light-emitting control signal, a reset signal, or the like.
  • the material of the first conductive layer 13 is not limited, and can be selected from at least one of metals, metal alloys, metal oxide conductive materials, organic conductive materials, carbon nanotubes, and graphene.
  • the material of the first conductive layer 13 may be molybdenum (Mo).
  • the first conductive layer 13 may include at least two first signal lines 131, and the at least two first signal lines 131 include: gate lines GL, light emission control signal lines EM and At least one of reset signal lines (Reset and Reset').
  • the first conductive layer 13 includes three kinds of first signal lines: a plurality of gate lines GL, a plurality of light emission control signal lines EM, and a plurality of reset signal lines (Reset and Reset').
  • all or part of the first signal line 131 is located in the display area. Referring to FIG. 4 , in some implementations, along the extending direction (X direction) of the first signal line 131 , both ends of the first signal line 131 may extend beyond two opposite edges of the AA area.
  • one end of the first signal line 131 exceeds the edge of the AA area, and the other end is flush with the edge of the AA area or within the AA area.
  • both ends of the first signal line 131 are flush with two opposite edges of the AA area, respectively.
  • the second conductive layer 14 includes at least one second signal line 141 .
  • the second conductive layer 14 includes a plurality of second signal lines 141 extending in parallel with the extending direction of the first signal lines 131 , and there is a gap between two adjacent second signal lines 141 .
  • both the second signal line 141 and the first signal line 131 extend parallel to the X direction.
  • the material of the second conductive layer 14 can be referred to the description of the above-mentioned first conductive layer 13 , which will not be repeated here. It can be understood that the materials of the first conductive layer 13 and the second conductive layer 14 may be the same or different.
  • each of the first signal lines 131 and one of the second signal lines 141 form a signal line pair 15 .
  • the extending directions of the first signal line 131 and the second signal line 141 are parallel. All or part of the second signal line 141 is located in the display area.
  • both ends of the second signal line 141 may be flush with both ends of the first signal line 131, and at this time
  • the second signal line 141 and the first signal line 131 have the same length.
  • the second signal line 141 in the same signal line pair 15, along the extension direction of the second signal line 141 (ie, the X direction), at least one of the two ends of the second signal line 141 is located inside the first signal line 131, That is, the length of the second signal line 141 is smaller than the length of the first signal line 131; for example, the left end of the second signal line 141 is on the right side of the left end of the first signal line 131, and the right end of the second signal line 141 is on the first signal line 131 to the left of the right end.
  • the second signal line 141 may include a plurality of signal sub-lines distributed at intervals along the extending direction thereof.
  • the orthographic projection of the first signal line 131 on the substrate 11 and the orthographic projection of the second signal line 141 on the substrate 11 have a first overlapping area 111 .
  • the orthographic projection of the second signal line 141 on the substrate 11 may be completely covered by the orthographic projection of the first signal line 131 on the substrate 11 , or may be partially within the orthographic projection of the first signal line 131 on the substrate 11 .
  • FIG. 1 For example, referring to FIG.
  • the second signal line 141 in the display area, along the width direction of the second signal line 141 (ie, the Y direction), the second signal line 141 is in two opposite edges of the orthographic projection of the substrate 11 , and all of one edge is or partially located between two opposite edges of the orthographic projection of the first signal line 131 on the substrate 11 , and the other edge is located beyond the two opposite edges of the orthographic projection of the first signal line 131 on the substrate 11 , or One of the two edges opposite to the orthographic projection of the first signal line 131 on the substrate 11 is flush.
  • the two opposite edges of the orthographic projection of the second signal line 141 on the substrate 11 and the first signal line 131 on the substrate are flush.
  • the orthographic projection of the first signal line 131 on the substrate 11 is the projection of the first signal line 131 on the substrate 11 along the vertical direction of the substrate 11 .
  • first signal line 131 and the second signal line 141 are coupled.
  • the coupling between the first signal line 131 and the second signal line 141 may be a direct connection, for example, the second signal line 141 is coupled to the first signal line 131 through the first insulating layer 12; it may also be an indirect connection through other conductive structures .
  • the first insulating layer 12 is located between the first conductive layer 13 and the second conductive layer 14 for making the first signal line 131 and the second signal line 141 corresponding to the outside of the first overlapping region 111 part of the electrical insulation.
  • the material of the first insulating layer 12 can be selected from silicon nitride, silicon oxide, and the like.
  • coupling the first signal line 131 and the second signal line 141 is equivalent to connecting the first signal line 131 and the second signal line 141 in parallel.
  • the sheet resistance of the signal line pair is reduced compared to the sheet resistance of the first signal line 131 .
  • the load caused by the RC (resistor-capacitor circuit) formed by the signal line pair is reduced.
  • the transmission distance is constant, the voltage attenuation caused by the surface resistance is reduced. , the probability of abnormal color of each pixel along the extension direction of the signal line pair is reduced, so that a better display effect can be achieved.
  • the orthographic projection of the first signal line 131 on the substrate 11 and the orthographic projection of the second signal line 141 on the substrate 11 have a first overlapping area 111, and the space occupied by the wiring is small. , can effectively avoid space wiring constraints.
  • the driving backplane 1 may further include: a second insulating layer 16 disposed on a side of the second conductive layer 14 away from the substrate 11 , and a second insulating layer 16 disposed on the second insulating layer 16 .
  • the third conductive layer 17 on the side of the layer 16 remote from the substrate 11 .
  • the third conductive layer 17 includes at least one (eg, there may be a plurality of) first conductive patterns 171 , each of the first conductive patterns 171 is coupled to a second signal line 141 through the second insulating layer 16 , and each of the first conductive patterns 171 is coupled to a second signal line 141 .
  • the pattern 171 penetrates through the second insulating layer 16 and the first insulating layer 12 and is coupled to a first signal line 131 .
  • the first signal line 131 and the second signal line 141 in the same signal line pair are coupled through the first conductive pattern 171, so as to reduce the resistance and improve the display effect. It can be understood that when the first conductive pattern 171 is coupled with a first signal line 131, the penetration position on the second insulating layer 16 and the first insulating layer 12 is the same as that of the first conductive pattern 171 and a second signal line 141.
  • the penetration positions on the second insulating layer 16 during coupling may be the same or different.
  • the first conductive layer 13, the first insulating film (a whole layer of insulating material), the second conductive layer 14, and the second insulating film can be sequentially formed on the substrate. (a whole layer of insulating material), and then through a patterning process, corresponding via holes are formed in the above-mentioned through positions, so that the corresponding electrical connection can be realized after the third conductive layer 17 is formed. Since the via holes of the two insulating layers can be formed by one patterning process, the process is simpler while the resistance is reduced, and accordingly, the production cost is more saved. In some embodiments of the present disclosure, referring to FIG.
  • the first insulating layer 12 has at least one first via 121
  • the second insulating layer 16 has at least one second via 161 ; each of the first vias 121 and one The second via holes 161 form a via hole pair 18 , and in the same via hole pair 18 , the first via hole 121 communicates with the second via hole 161 .
  • the portion of the first signal line 161 exposed by the via hole pair 18 is the first connection portion 1311
  • the portion of the second signal line 141 exposed by the second via hole 161 of the via hole pair 18 is the second connection portion 1411 .
  • the position of the via pair 18 should be at the position where the first signal line 161 and the second signal line 141 overlap. , that is, the orthographic projection on the substrate 11 has a second overlapping area 112 with the first overlapping area 111 .
  • the first conductive pattern 171 is in contact with the second connection portion 1411 through the second via hole 161 of the at least one via hole pair 18 , and is in contact with the first connection portion 1311 through each via hole pair 18 of the via hole pair 18 .
  • the first conductive pattern 171 can be connected to both the first signal line 161 and the second signal line 141 through the same via pair 18, which can reduce the number of vias, and the size of the two sides connected through the vias can be Make it smaller, so that although the first conductive pattern 171 is added in this embodiment, it is not necessary to increase the size of one sub-pixel accordingly.
  • the shape of the first via hole 121 and the second via hole 161 can be a circle, a triangle, a square, etc.; the shape of the first via hole 121 and the second via hole 161 can be the same or different;
  • the via hole 121 and the second via hole 161 may be formed in the same patterning process, or may be formed in two patterning processes.
  • the first via 121 has an opposite first opening 1211 and a second opening 1212 .
  • the first opening 1211 is away from the substrate 11 .
  • the second via hole 161 has an opposite third opening 1611 and a fourth opening 1612 .
  • the third opening 1611 is farther away from the substrate 11 .
  • the combination of the orthographic projection of the first opening 1211 on the substrate 11 and the orthographic projection of the second connecting portion 1411 on the substrate 11 substantially coincides with the orthographic projection of the fourth opening 1612 on the substrate 11 .
  • a first conductive layer 13, a first insulating film, a second conductive layer 14, and a second insulating layer can be sequentially formed on the substrate. film, and then through a patterning process, the above-mentioned via hole pair 18 is formed on the first insulating film and the second insulating film. Since only one mask (mask) needs to be used in one patterning process, the effect of reducing the production cost can also be achieved.
  • the via pair 18 referring to FIG.
  • the first conductive pattern 171 realizes the coupling of the first signal line 131 and the second signal line 141 through the via pair 18, and achieves the purpose of reducing the resistance and improving the display effect.
  • the above-mentioned orthographic projection of the via pair 18 on the substrate 11 is included within the boundary of the orthographic projection of the signal line pair 15 on the substrate 11 , that is, the via pair 18
  • the orthographic projection on the substrate 11 is located within the boundary of the orthographic projection of the signal line pair 15 on the substrate 11, or the orthographic projection of the signal line pair 15 on the substrate 11 completely covers the above-mentioned via hole pair 18 on the substrate.
  • Orthographic projection on 11, a gap can be left between the two orthographic projections.
  • the orthographic projection of the via pair 18 on the substrate 11 is the orthographic projection of the largest opening (eg, the third opening 1611 ) of the via pair 18 on the substrate 11 .
  • the orthographic projection of the signal line pair 15 on the substrate 11 refers to the combination of the orthographic projection of the first signal line 131 on the substrate 11 and the orthographic projection of the second signal line 141 on the substrate 11 in the signal line pair 15 .
  • the size of the via pair 18 is relatively large, and a part of its orthographic projection on the substrate 11 is located at the boundary of the orthographic projection of the signal line pair 15 on the substrate 11
  • the inorganic film layer at the edge of the signal line pair 15 will be etched together to form a chamfer 70 (also called undercut).
  • the existence of the chamfer 70 makes the signal line pair 15 For example, there is a step difference between the edge of the second signal line 141 and the first insulating layer 12 below it, and the edge of the second signal line 141 is suspended. It increases the resistance of the 15-plane, and finally has an adverse effect on the display effect.
  • the orthographic projection of the via pair 18 on the substrate 11 may only be located on the first signal line 131 or the second signal line 141 on the substrate 11 In the orthographic projection on the top, the first conductive pattern 171 can only be coupled with one of the signal lines, the parallel connection of the first signal line 131 and the second signal line 141 cannot be realized, and the effect of reducing the resistance cannot be realized.
  • the first signal line 131 is coupled to the second signal line 141 through a plurality of via pairs 18 , and the plurality of via pairs 18 They are arranged along the extending direction of the first signal lines 131 . It can be understood that, since there are multiple via pairs 18 for realizing electrical connection, even if one of the first conductive patterns 171 is poorly connected, the other first conductive patterns 171 still use the corresponding via pairs 18 to realize the first conductive pattern.
  • the coupling of the first signal line 131 and the second signal line 141 improves the reliability of the display device.
  • the orthographic projection of the first conductive pattern 171 on the substrate 11 completely covers the orthographic projection of the via pair 18 on the substrate 11 . It can be understood that, if the orthographic projection of the first conductive pattern 171 on the substrate 11 does not completely cover the orthographic projection of the via pair 18 on the substrate 11, the first conductive pattern 171 does not fill the via pair 18, resulting in a connection. The probability of failure increases and the connection reliability decreases, so the solution in this embodiment can avoid the above problems.
  • each film layer of the driving backplane 1 is formed by mechanical equipment, and subject to the existing technological level, it is difficult for mechanical equipment to achieve complete accurate alignment, and it is only possible to achieve accurate alignment.
  • Bit precision is controlled within a preset range.
  • the alignment accuracy is the positional alignment error of the etched pattern between the layers that need to be aligned on the display panel.
  • the orthographic projection of the first conductive pattern 171 formed by etching on the substrate 11 has the first geometric center
  • the orthographic projection of the via pair 18 completely covered by the first conductive pattern 171 on the substrate 11 has the first geometric center.
  • the first geometric center and the second geometric center are completely coincident, and the alignment accuracy is 0 ⁇ m; while under non-ideal conditions, subject to the technological level and process equipment, the first geometric center and the second geometric center The centers may not coincide.
  • the maximum value of the straight-line distance between the first geometric center and the second geometric center is the alignment accuracy.
  • the orthographic projection of the first conductive pattern 171 on the substrate 11 may be greater than or equal to the alignment accuracy of the device. For example, when the device alignment accuracy is 0.5 ⁇ m, it is necessary to ensure the minimum distance between the edge of the orthographic projection of the first conductive pattern 171 on the substrate 11 and the edge of the orthographic projection of the via pair 18 on the substrate 11 The distance d is greater than or equal to 0.5 ⁇ m.
  • the minimum distance d between the edge of the orthographic projection of the first conductive pattern 171 on the substrate 11 and the edge of the orthographic projection of the via pair 18 on the substrate 11 will vary with the alignment accuracy of the device.
  • the change of changes accordingly, as long as the complete coverage of the via pair 18 is finally achieved, and it is not limited to a specific value.
  • the alignment accuracy is related to the process level and process equipment. Exemplarily, when the process level is improved and more advanced process equipment is used, the alignment of the operating position during the process will be more accurate, and the alignment accuracy will be higher. The value will also be smaller. In some embodiments of the present disclosure, referring to FIG.
  • the orthographic projection of the first signal line 131 on the substrate 11 and the orthographic projection of the second signal line 141 on the substrate 11 have the first An overlapping area 111, the ratio of the width of the first overlapping area 111 to the width of the first signal line is 1/3 ⁇ 1/2.
  • the width of the first overlapping region 111 may be 1 ⁇ m.
  • the width h of the first overlapping area 111 may be the width of the first signal line 131 .
  • the width of the first overlapping area 111 may be 1 ⁇ 0.5 ⁇ m, that is, the width of the first overlapping area 111 is 1 ⁇ 0.5 ⁇ m.
  • the value range of the width h is 0.5 ⁇ m ⁇ 1.5 ⁇ m, and the ratio to the width of the first signal line is between 1/3 ⁇ 1/2.
  • the width of the first signal line 131 here can be understood as the average width of the portion of the first signal line 131 corresponding to the first overlapping region 111 .
  • the value range of the width h of the first overlapping region 111 may still be 0.5 ⁇ m ⁇ 1.5 ⁇ m.
  • the width w1 of the first signal line 131 and the width w2 of the second signal line 141 in the same signal line pair 15 are equal, for example, both are 3 ⁇ m.
  • the width may be 1 ⁇ 0.5 ⁇ m.
  • the orthographic projection of the via pair 18 coupling the first signal line 131 and the second signal line 141 on the substrate 11 may be a circle, and the diameter of the circle may be 2 ⁇ m, ensuring that the via pair 18 is on the substrate 11
  • the orthographic projection on the substrate 11 is located within the boundary of the orthographic projection of the signal line pair 15 on the substrate 11; the orthographic projection of the first conductive pattern 171 on the substrate 11 may be a square, and the side length of the square may be 3 ⁇ m, so that the The hole pair 18 is completely covered to ensure the connection effect. It can be understood that the above numerical values can be changed according to process conditions and design requirements, and are not limited to a specific numerical value, as long as the corresponding effects can be achieved.
  • the pixel circuit 210 further includes at least one capacitor C (eg, a storage capacitor C), each capacitor C including two plates, a first plate 43 and a second plate 44, wherein , the second electrode plate 44 is located on the side of the first electrode plate 43 away from the substrate 11 .
  • the first pole plate 43 and the first signal line 131 are arranged in the same layer, and both are included in the first conductive layer 13, and the second pole plate 44 and the second signal line 141 are arranged in the same layer, both of which are included. in the second conductive layer 14 .
  • the second conductive layer 14 in addition to the second signal lines 141 , the second conductive layer 14 further includes at least two second conductive patterns 142 , and the at least two second conductive patterns 142 include: a pixel circuit 210 One plate of the capacitor C and/or the initialization signal line Init.
  • the second conductive layer 14 includes two types of second conductive patterns 142 , which are the second plate 44 of the capacitor C in the pixel circuit 210 and the initialization signal line Init, wherein the extension direction of the initialization signal line Init may be the same as that of the gate line. GL extends in the same direction.
  • the first signal line 131 in one signal line pair 15 adjacent to the second conductive pattern 142 , is closer to the second conductive pattern than the second signal line 141 Pattern 142 . That is, there are no other second conductive patterns 142 or other signal line pairs 15 between adjacent signal line pairs 15 and second conductive patterns 142.
  • the first signal line 131 in the signal line pair 15 has a first edge 1312 and a second edge 1313 opposite along its width direction, wherein, compared with the orthographic projection of the second edge 1313 on the substrate 11 , the first edge 1312 The orthographic projection on the substrate 11 is closer to the orthographic projection of the second conductive pattern 142 on the substrate 11 .
  • the second signal line 141 in the signal line pair 15 has a third edge 1412 and a fourth edge 1413, wherein, compared with the orthographic projection of the fourth edge 1313 on the substrate 11, the third edge 1412 on the substrate 11
  • the orthographic projection is closer to the orthographic projection of the second conductive pattern 142 on the substrate 11 .
  • the first signal line 131 is closer to the second conductive pattern 142 than the second signal line 141 , that is, in one signal line pair 15 , compared to the orthographic projection of the third edge 1412 on the substrate 11 , the first edge 1312 is in the
  • the orthographic projection on the substrate 11 is closer to the orthographic projection of the second conductive pattern 142 on the substrate 11 .
  • the second signal line 141 is farther away from the second conductive pattern 142 than the first signal line 131 , in the width direction of the second signal line 141 , the second signal line 141 and the second conductive pattern 142 There is a gap between them, the existence of the gap can ensure that the second signal line 141 and the second conductive pattern 142 arranged on the same layer are insulated from each other, and the second signal line 141 and the second conductive pattern 142 will not be caused by the existence of equipment alignment accuracy.
  • the patterns 142 are connected to each other and short-circuit occurs, which requires relatively low alignment accuracy of the device, and is easier to implement under the existing technological level.
  • the driving backplane 1 further includes an active pattern layer 40 .
  • the active pattern layer 40 is disposed on the side of the first conductive layer 13 close to the substrate 11 .
  • the active pattern layer 40 is insulated from the first conductive layer 13 ; for example, a gate insulating layer GI is provided between the active pattern layer 40 and the first conductive layer 13 .
  • the active pattern layer 40 includes a semiconductor pattern 41 and a conductor pattern 42 .
  • a semiconductor material film is formed on the substrate 11, and a part of the semiconductor material film is conductive, such as ion-doping, to obtain a conductive pattern 42, and the unconducted part of the semiconductor material film is the semiconductor pattern. 41 , each of the semiconductor patterns 41 separates two conductor patterns of the plurality of conductor patterns 42 .
  • the pixel circuit includes a plurality of transistors, each transistor includes an active layer, the active layer includes a channel region, a first electrode region and a second electrode region, and the first electrode region and the second electrode region are respectively located in the channel. Both sides of the region; for example, one of the first electrode region and the second electrode region is a source region, and the other is a drain region.
  • the semiconductor pattern includes a channel region in the active layer, a conductor pattern includes a first pole region or a second pole region in the active layer, and correspondingly, the conductor pattern is located on both sides of the semiconductor pattern.
  • the plurality of transistors in the pixel circuit includes a drive transistor MD.
  • the portion of the active pattern layer 40 that overlaps with the orthographic projection of the first electrode plate 43 on the substrate 11 serves as the channel region 411a in the active layer ACTa of the driving transistor in the pixel circuit.
  • a portion of the first plate 43 corresponding to the channel region 411a in the active layer ACTa of the driving transistor serves as the control electrode (ie, the gate electrode) 251a of the driving transistor.
  • the plurality of transistors in the pixel circuit 210 include a first transistor M1 and a second transistor M2 .
  • the portion of the active pattern layer 40 that overlaps with the orthographic projection of the gate line GL on the substrate 11 is used as the channel region 411b in the active layer ACTb of the first transistor and the active layer of the second transistor, respectively.
  • Channel regions 411c1 and 411c2 in ACTc are used as the channel regions 411c1 and 411c2 in ACTc.
  • the second electrode region 422b in the active layer 411b of the first transistor is connected to the first electrode region 421a in the active layer ACTa of the driving transistor, and the second electrode region 422c in the active layer ACTc of the second transistor is connected to The second electrode region 422a in the active layer ACTa of the driving transistor is connected.
  • the light emitting control lines EM are arranged at intervals from the gate lines GL; the extending direction of the light emitting control lines EM is parallel to the extending direction of the gate lines GL.
  • the plurality of transistors in the pixel circuit further include a third transistor M3 and a fourth transistor M4.
  • the portion of the active pattern layer 40 that overlaps with the orthographic projection of the light emission control line EM on the substrate 11 is used as the channel region 411d in the active layer ACTd of the third transistor and the active layer ACTe of the fourth transistor, respectively. in the channel region 411e.
  • a portion of the light emission control line EM corresponding to the channel region (411d) in the active layer of the third transistor may serve as the gate electrode 251d of the third transistor; the light emission control line EM corresponding to the channel region (411d) in the active layer of the fourth transistor
  • a portion of the channel region (411e) may serve as the gate electrode 251e of the sixth transistor.
  • the second electrode region 422d in the active layer ACTd of the third transistor is connected to the first electrode region 421a in the active layer ACTa of the driving transistor and the second electrode region 422b in the active layer ACTb of the first transistor, and has no
  • the gaps, for example, the active layer ACTd of the third transistor, the active layer ACTa of the driving transistor, and the active layer ACTb of the first transistor are connected in an integral structure.
  • the first electrode region 421e in the active layer ACTe of the fourth transistor is connected to the second electrode region 422a in the active layer ACTa of the driving transistor and the second electrode region 422c in the active layer ACTc of the second transistor, and no
  • the gaps, for example, the active layer ACTe of the fourth transistor, the active layer ACTa of the driving transistor, and the active layer ACTc of the second transistor are connected in an integral structure.
  • the third conductive layer 17 further includes at least one third conductive pattern 31 ; for example, the third conductive layer 17 may include a plurality of third conductive patterns 31 , each A third conductive pattern 31 is included in the pixel circuit.
  • the third conductive pattern 31 can electrically connect the first electrode plate 43 and the first electrode region 421c in the active layer ACTc of the second transistor.
  • the first electrode region 421c in the active layer ACTc of the second transistor is coupled with the third conductive pattern 31 .
  • the third conductive pattern 31 and the first electrode region 421c in the active layer ACTc of the second transistor pass through the via hole on the film layer (for example, including the interlayer dielectric layer and the gate insulating layer) sandwiched therebetween.
  • 51b contacts.
  • the first electrode plate 43 is coupled with the third conductive pattern 31 .
  • the third conductive pattern 31 is in contact with the via hole 51a on the film layer (for example, including the interlayer dielectric layer and the gate insulating layer) sandwiched therebetween.
  • a portion of the gate line GL corresponding to the channel region 411b in the active layer ACTb of the first transistor may serve as the control electrode (ie, the gate electrode) 251b of the first transistor.
  • the channel regions included in the active layer ACTc of the second transistor are 411c1 , 411c2 and 411c3 respectively; the portion of the gate line GL corresponding to the channel regions 411c1 and 411c2 in the active layer ACTc of the second transistor may serve as The control electrodes (ie gates) 251c1 and 251c2 of the second transistor, that is, the second transistor has a double gate structure, which can avoid the generation of leakage current.
  • the third conductive layer 17 further includes at least one (eg, may be a plurality of) data lines DL.
  • the first electrode region in the active layer of the first transistor is coupled to the data line DL; for example, the data line DL and the first electrode region 421b in the active layer ACTb of the first transistor pass through a film sandwiched therebetween
  • the vias 51c on the layers are in contact with each other.
  • the third conductive layer 17 further includes at least one (eg, may be a plurality of) power supply voltage lines VDD.
  • the power supply voltage line VDD and the data line DL extend in the same direction, and the orthographic projection of each power supply voltage line VDD on the substrate 11 has no overlapping area with the orthographic projection of each data line DL on the substrate 11, that is, each power supply A gap exists in the width direction between the voltage line VDD and each data line DL.
  • the first electrode region in the active layer of the third transistor is coupled to the power supply voltage line; for example, the power supply voltage line VDD and the first electrode region 421d in the active layer of the third transistor pass through a film sandwiched therebetween
  • the vias 51d on the layers eg, including the interlayer dielectric layer and the gate insulating layer
  • the second electrode plate 44 in the capacitor C is coupled to the power supply voltage line VDD; for example, the power supply voltage line VDD and the second electrode plate 44 in the capacitor C pass through the film layer (for example, including the interlayer) sandwiched therebetween.
  • the via holes 51e on the dielectric layer) are in contact with each other.
  • the data line DL and the power supply voltage line VDD may both belong to the same pattern layer, for example, the above-mentioned third conductive layer 17 , that is, the two are arranged in the same layer.
  • the data line DL and the power supply voltage line VDD may also be arranged in different layers.
  • the data line DL belongs to the above-mentioned third conductive layer 17
  • the power supply voltage line VDD may belong to a conductive pattern on the side of the third conductive layer 17 away from the substrate 11 .
  • Floor the data line DL belongs to the above-mentioned third conductive layer 17 , and the power supply voltage line VDD may belong to a conductive pattern on the side of the third conductive layer 17 away from the substrate 11 .
  • Floor the data line DL belongs to the above-mentioned third conductive layer 17 .
  • the driving backplane 1 further includes a fourth conductive layer 20 and a third insulating layer disposed between the third conductive layer 17 and the fourth conductive layer 20 .
  • the fourth conductive layer 20 includes at least one (eg, a plurality of) auxiliary power supply voltage lines VDD', and the auxiliary power supply voltage lines VDD' are coupled to the power supply voltage lines VDD. It can be understood that, connecting the power supply voltage line VDD and the auxiliary power supply voltage line VDD' in parallel can reduce the resistance of each power supply voltage line VDD on the third conductive layer 17. Under the condition that the power supply voltage does not change, the power supply voltage line VDD can be reduced. The smaller the resistance is, the larger the current used to drive the light-emitting device L is, and accordingly, the better the light-emitting effect of the light-emitting device L is.
  • the arrangement of the plurality of auxiliary power supply voltage lines VDD' on the fourth conductive layer is not limited, and the extension direction of the plurality of power supply voltage lines VDD may be the same as the extension direction of the power supply voltage lines VDD on the third conductive layer 17. Consistent or inconsistent, and a part of the multiple auxiliary power supply voltage lines VDD' may be consistent with the extending direction of the power supply voltage line VDD, but inconsistent with the extending direction of the power supply voltage line VDD, for example, a part of the auxiliary power supply voltage line VDD' It extends in one direction (for example, along the X direction), and the other part extends in the second direction (for example, along the Y direction).
  • the power supply voltage lines VDD' are coupled to each other in a grid shape.
  • the auxiliary power supply voltage line VDD' and the method of coupling with the power supply voltage line VDD can refer to the above-mentioned coupling method of the first signal line 131 and the second signal line 141.
  • the power supply voltage line VDD is equivalent to the first signal line 131
  • the auxiliary power supply voltage line VDD' is equivalent to the second signal line 141, and the two are coupled.
  • the extension direction of the auxiliary power supply voltage line VDD' is consistent with the extension direction of the power supply voltage line VDD.
  • the orthographic projection of the auxiliary power supply voltage line VDD' on the substrate 11 and the orthographic projection of the power supply voltage line VDD on the third conductive layer 17 on the substrate 11 have a third overlapping region 112 .
  • the third insulating layer has at least one third via hole 191 (for example, there may be multiple), and the orthographic projection of each third via hole 191 on the substrate 11 at least partially overlaps with the third overlapping region 112 , and the fourth conductive hole 191 is conductive.
  • the layers are coupled to each power supply voltage line VDD on the third conductive layer 17 through the third via hole 191 to realize parallel connection.
  • the third conductive layer 17 further includes at least one fourth conductive pattern 32 (eg, may be one).
  • the fourth conductive pattern 32 is coupled to the second electrode region 422e in the active layer of the fourth transistor.
  • the fourth conductive pattern 32 is connected to the second electrode region 422e in the active layer of the fourth transistor through the via hole 51f on the film layer (for example, including the interlayer dielectric layer and the gate insulating layer) sandwiched therebetween. touch.
  • the fourth conductive pattern 32 is used for coupling with the light emitting device L.
  • the fourth conductive pattern 32 is coupled to one pole (anode or cathode) of the light emitting device L; the fourth transistor is coupled to the light emitting device L.
  • a passivation layer (PVX) is provided on the side of the third conductive layer 17 away from the substrate.
  • the material of the passivation layer can be an organic material including polyimide or the like; one pole (anode or cathode) of the light-emitting device
  • the fourth conductive pattern 32 is in contact with the via hole 61 provided on the passivation layer (the light emitting device L is not shown in the figure).
  • the plurality of transistors in the pixel circuit 210 includes a fifth transistor M5 and a sixth transistor M6 .
  • the portion in the active pattern layer 40 that overlaps with the orthographic projection of the reset signal line Reset in the first conductive layer 13 on the substrate 11 serves as the channel region (411f1 and 411f2) in the active layer ACTf of the fifth transistor.
  • the portion of the active pattern layer 40 that overlaps with the orthographic projection of the reset signal line Reset' in the first conductive layer 13 on the substrate 11 serves as a channel region in the active layer ACTg of the sixth transistor ( 411g).
  • the part of the reset signal line Reset corresponding to the channel regions ( 411f1 and 411f2 ) in the active layer of the fifth transistor may serve as the gate electrodes 251f1 and 251f2 of the fifth transistor, that is, the fifth transistor has a double gate structure, and may The generation of leakage current is avoided; the part of the reset signal line Reset' corresponding to the channel region (411g) in the active layer of the sixth transistor may serve as the gate electrode 251g of the sixth transistor.
  • the second electrode region 422f in the active layer ACTf of the fifth transistor is connected to the first electrode region 421c in the active layer ACTc of the second transistor, that is, the second electrode region in the active layer ACTf of the fifth transistor
  • the region 422f, coupled to the first conductive pattern 31, is also coupled to the first electrode plate 43; that is, the second electrode region 422f in the active layer ACTf of the fifth transistor is coupled to the control electrode 251a of the driving transistor.
  • the second electrode region 422g in the active layer ACTg of the sixth transistor is connected to the second electrode region 422e in the active layer ACTe of the fourth transistor, that is, the second electrode region 422g in the active layer ACTg of the sixth transistor is coupled to the fourth conductive pattern 32 .
  • the second electrode region 422g in the active layer ACTg of the sixth transistor is coupled to the light emitting device L.
  • the third conductive layer 17 further includes at least one fifth conductive pattern 33 (for example, there may be multiple ones), the fifth conductive pattern 33 is coupled to the initialization signal line Init, and the fifth conductive pattern 33 is also coupled to the sixth transistor. is coupled to the first pole region 421g in the active layer.
  • the fifth conductive pattern 33 is in contact with the initialization signal line Init through the via hole 51g on the film layer (for example, including the interlayer dielectric layer) sandwiched therebetween, and the fifth conductive pattern 33 is in contact with the active layer of the sixth transistor.
  • the first pole region 421g is connected through a via hole 51h on a film layer (for example, including an interlayer dielectric layer and a gate insulating layer) sandwiched therebetween.
  • the shapes and extending directions of the third conductive pattern 31 , the fourth conductive pattern 32 and the fifth conductive pattern 33 are not limited, as long as the electrical connection of the corresponding structure can be achieved through the corresponding via hole.
  • the reset signal lines Reset and Reset' may transmit the same signal; for example, one row of pixel circuits may be coupled to one reset signal line. That is, the fifth transistor and the sixth transistor are turned on at the same time, so that the driving transistor and the light emitting device are reset in the same period.
  • the reset signal lines Reset and Reset' may transmit different signals; for example, a row of pixel circuits may be coupled to two reset signal lines Reset and Reset'.
  • the reset signal line Reset coupled to the fifth transistor in one row of pixel circuits transmits the same signal as the gate line GL coupled to the previous row of pixel circuits in the row of pixel circuits;
  • the reset signal line Reset' coupled to the sixth transistor transmits the same signal as the gate line GL coupled to the pixel circuits of the row.
  • one reset signal line coupled to one row of pixel circuits is shared with the gate line GL coupled to the pixel circuit of the previous row, and another reset signal line coupled to one row of pixel circuits can be shared with the gate line GL coupled to the one row of pixel circuits .
  • the fifth transistor in response to the reset signal from the reset signal line coupled to the fifth transistor in one row of pixel circuits, the fifth transistor is turned on, and transmits the initialization signal from the initialization signal line Init to the control electrode of the driving transistor , reset the driving transistor; at the same time, the first transistor and the second transistor in the pixel circuit of the row above the pixel circuit respond to the gate driving signal from the gate line GL to which it is coupled, the first transistor and the second transistor Turn on, write the data signal, and write the threshold voltage of the drive transistor and the data signal to the gate of the drive transistor.
  • the sixth transistor in the pixel circuit of the row is turned on in response to the reset signal from the reset signal line coupled to the sixth transistor to reset the light-emitting device, and at the same time, the first transistor and the second transistor in the pixel circuit of the row are turned on.
  • the first transistor and the second transistor are turned on, the data signal is written, and the threshold voltage of the driving transistor and the data signal are written to the gate of the driving transistor .
  • the material of the active layer of each transistor in the active pattern layer includes amorphous silicon, polycrystalline silicon or organic semiconductor material.
  • Each structure in the first conductive layer 13 for example, including gate lines, light-emitting control lines, reset signal lines, etc.
  • each structure in the second conductive layer 14 for example, including second electrodes, initialization signal lines, etc.
  • Each structure in the conductive layer 17 may have a single-layer or multi-stacked layer structure, and the materials of the single-layer or multi-stacked layer structure include aluminum (Al), silver (Ag), magnesium (Mg) ), at least one of metals such as molybdenum (Mo), titanium (Ti), and copper (Cu).
  • the display panel may also be an LCD panel, and in this case, the driving backplane 1 may be an array substrate.
  • the display panel may further include an opposite substrate disposed opposite to the driving backplane 1, and a liquid crystal layer is disposed between the array substrate and the opposite substrate.
  • the gate line in the array substrate is used as the first signal line, and the second signal line forming a signal line pair with the gate line is set with reference to the above solution.
  • some embodiments of the present disclosure provide a method for manufacturing the above-mentioned driving backplane 1 , including:
  • Each first signal line 131 and one second signal line 141 form a signal line pair 15; in the same signal line pair 15, the first signal line 131 and the second signal line 141 extend in the same direction, and the first signal line 131 is lined
  • the orthographic projection on the bottom 11 and the orthographic projection of the second signal line 141 on the substrate 11 have a first overlapping area 111 , and the second signal line 141 is coupled with the first signal line 131 .
  • Some embodiments of the present disclosure provide a method for manufacturing the above-mentioned driving backplane 1 , referring to FIG. 15 , further comprising: forming a first conductive layer 13 , a first insulating layer 12 , and a second conductive layer arranged in sequence on the substrate 11 14.
  • the steps of forming the second insulating layer and the third conductive layer 17 include:
  • the first insulating layer 12 has at least one first via hole 121; the second insulating layer 16 has at least one second via hole 161; each first via hole 121 and one second via hole 161 form a via pair, and the same In the hole pair, the first via hole 121 communicates with the second via hole 161; the part exposed by the via hole pair in the first signal line is the first connection part; the second via hole in the second signal line is centered by the via hole pair
  • the part exposed by 161 is the second connection part, and the orthographic projection of the second connection part on the substrate 11 has a second overlapping area with the first overlapping area 111; the first conductive pattern is in contact with the second connection part through the second via hole 161 , and is in contact with the first connection part through the via pair.
  • the above-mentioned preparation method of the driving backplane 1 includes:
  • the steps of forming the first insulating layer 12, the second conductive layer 14 and the second insulating layer 16 include:
  • the materials of the first insulating film 50 and the second insulating film 51 can be selected from silicon nitride, silicon oxide, and the like.
  • the above preparation method, before forming the first conductive layer 13 on the substrate 11 may further include: forming the active pattern layer 40 on the substrate 11 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种驱动背板（1）及其制作方法、显示装置。背板（1）包括：衬底（11）；设置于衬底（11）上的第一导电层（13），第一导电层（13）包括至少一条第一信号线（131）；设置于第一导电层（13）远离衬底一侧的第一绝缘层（12）；设置于第一绝缘层（12）远离第一导电层（13）一侧的第二导电层（14），第二导电层（14）包括至少一条第二信号线（141）；其中，每条第一信号线（131）与一条第二信号线（141）组成一个信号线对；同一信号线对中，第一信号线（131）与第二信号线（141）延伸方向相同，第一信号线（131）在衬底上的正投影与第二信号线（141）在衬底上的正投影具有第一重叠区域，且第二信号线（141）与第一信号线（131）耦接。

Description

一种驱动背板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动背板及其制作方法、显示装置。
背景技术
显示装置具有轻、薄、省电、应用场景多样化等特点，具有广阔的应用前景。
显示装置的种类繁多，按显示媒质和工作原理进行划分，可分为液晶显示装置(LCD，Liquid Crystal Display)、无机电致发光显示装置(ELD，Electroluminescent Display)、有机电致发光显示装置(OLED，Organic Light Emitting Diode)、场发射显示装置(FED，Field Effection Display)等多种类型。每种类型的显示装置可以应用到各种各样的场景中，满足不同的图像显示需求。
发明内容
一方面，提供了一种驱动背板，驱动背板包括：衬底；设置于衬底上的第一导电层，设置于第一导电层远离衬底一侧的第一绝缘层，和设置于第一绝缘层远离第一导电层一侧的第二导电层。其中，第一导电层包括至少一条第一信号线；第二导电层包括至少一条第二信号线。每条第一信号线与一条第二信号线组成一个信号线对；同一信号线对中，第一信号线与第二信号线延伸方向相同，第一信号线在衬底上的正投影与第二信号线在衬底上的正投影具有第一重叠区域，且第二信号线与第一信号线耦接。
在一些实施例中，驱动背板还包括：设置于第二导电层远离衬底一侧的第二绝缘层，和设置于第二绝缘层远离衬底一侧的第三导电层。其中，第三导电层包括至少一个第一导电图案；每个第一导电图案贯穿第二绝缘层与第二信号线耦接，第一导电图案贯穿第二绝缘层和第一绝缘层与第一信号线耦接。
在一些实施例中，驱动背板还包括：设置在第一绝缘层上的至少一个第一过孔；设置在第二绝缘层上的至少一个第二过孔。其中，每个第一过孔和一个第二过孔组成一个过孔对，同一过孔对中，第一过孔与第二过孔连通。第一信号线中由过孔对露出的部分为第一连接部；第二信号线中由过孔对中的第二过孔露出的部分为第二连接部，第二连接部在衬底上的正投影与第一重叠区域具有第二重叠区域；第一导电图案通过第二过孔与第二连接部接触， 并通过过孔对与第一连接部接触。
在一些实施例中，同一过孔对中，第一过孔具有相对的第一开口和第二开口，相较于第二开口，第一开口远离衬底；第二过孔具有相对的第三开口和第四开口，相较于第四开口，第三开口远离衬底。第一开口在衬底上的正投影与第二连接部在衬底上的正投影的组合与第四开口在衬底上的正投影大致重合。
在一些实施例中，过孔对在衬底上的正投影包含于信号线对在衬底上的正投影的边界内。
在一些实施例中，同一信号线对中，第一信号线通过多个过孔对与第二信号线耦接，多个过孔对沿第一信号线的延伸方向排列。
在一些实施例中，第一导电图案在衬底上的正投影完全覆盖过孔对在衬底上的正投影。
在一些实施例中，第一导电图案在衬底上的正投影的边沿与过孔对在衬底上的正投影的边沿的之间的最小距离大于或等于第一信号线的宽度的1/6。
在一些实施例中，沿第一信号线的宽度方向，所述第一重叠区域的宽度与所述第一信号线的宽度的比值为1/3～1/2。
在一些实施例中，第二导电层还包括：第二导电图案。其中，与第二导电图案相邻的一个信号线对中，第一信号线相较于第二信号线更靠近第二导电图案。
在一些实施例中，第二导电层包括至少两个第二导电图案，至少两个第二导电图案包括：驱动背板包含的像素电路中电容器的一个极板和/或初始化信号线。
在一些实施例中，第一信号线与第二信号线的宽度相等。
在一些实施例中，驱动背板还包括与第一信号线的两端分别耦接的两个驱动电路。
在一些实施例中，至少一条第一信号线包括：栅线，发光控制信号线和复位信号线中的至少一者。
在一些实施例中，驱动背板还包括有源图案层，有源图案层设置于第一导电层靠近衬底的一侧。有源图案层包括至少一个半导体图案和多个导体化图案，其中，每个半导体图案将多个导体化图案中的两个导体化图案间隔开。
在一些实施例中，在驱动背板包括第三导电层的情况下，第三导电层还包括：电源电压线。其中，数据线和电源电压线的延伸方向相同，数据线在 衬底上的正投影与电源电压线在衬底上的正投影无重叠区域。
另一方面，提供了一种显示装置。显示装置包括：如上述任一实施例的驱动背板。
又一方面，提供了一种驱动背板的制作方法，包括：在衬底上形成第一导电层，在形成有第一导电层的衬底上，形成第一绝缘层和第二导电层。其中，第一导电层包括至少一条第一信号线；第二导电层位于第一绝缘层远离第一导电层的一侧，第二导电层包括至少一条第二信号线；每条第一信号线与一条第二信号线组成一个信号线对；同一信号线对中，第一信号线与第二信号线延伸方向相同，第一信号线在衬底上的正投影与第二信号线在衬底上的正投影具有第一重叠区域，且第二信号线与第一信号线耦接。
在一些实施例中，驱动背板的制作方法还包括：在第二导电层远离衬底的一侧形成第二绝缘层，在第二绝缘层远离衬底的一侧形成第三导电层。其中，第三导电层包括至少一个第一导电图案；第一绝缘层具有至少一个第一过孔；第二绝缘层具有至少一个第二过孔；每个第一过孔和一个第二过孔组成一个过孔对，同一过孔对中，第一过孔与第二过孔连通。第一信号线中由过孔对露出的部分为第一连接部；第二信号线中由过孔对中的第二过孔露出的部分为第二连接部，第二连接部在衬底上的正投影与第一重叠区域具有第二重叠区域；第一导电图案通过第二过孔与第二连接部接触，并通过过孔对与第一连接部接触。
在一些实施例中，形成第一绝缘层、第二导电层和第二绝缘层的步骤包括：在形成有第一导电层的衬底上，形成第一绝缘薄膜；在形成有第一绝缘薄膜的衬底上，形成第二导电层；在形成有第二导电层的衬底上，形成第二绝缘薄膜，并将第二绝缘薄膜和第一绝缘薄膜图案化，形成包含第二过孔的第二绝缘层和包含第一过孔的第一绝缘层。其中，第二导电层包括至少一条第二信号线。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开的一些实施例的靠近信号源的位置A的电压信号与远离信号源的位置B的电压信号波形图；
图2为根据本公开的一些实施例的显示面板结构图；
图3为根据本公开的一些实施例的7T1C像素电路结构图；
图4为根据本公开的一些实施例的包括GOA驱动电路的显示面板结构图；
图5为根据本公开的一些实施例的衬底结构图；
图6为根据本公开的一些实施例的驱动背板结构图；
图7为图6中的驱动背板沿A-A’方向的剖视图；
图8为图6中的驱动背板B区的放大结构图；
图9为根据本公开的一些实施例的过孔对结构图；
图10为根据本公开的一些实施例的第一导电层结构图；
图11为根据本公开的一些实施例的第二导电层结构图；
图12为根据本公开的一些实施例的有源层结构图；
图13为根据本公开的一些实施例的第三导电层和过孔结构图；
图14为根据本公开的一些实施例的第三导电层和第四导电层结构图；
图15为根据本公开的一些实施例的驱动背板制作流程图；
图16为根据本公开的一些实施例的驱动背板制作流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结 构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到……”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到……时”或“响应于检测到……”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“近似”或“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域 的实际形状，并且并非旨在限制示例性实施方式的范围。
显示装置包括多个发光颜色不同的子像素，大多采用驱动背板控制各个子像素的发光亮度，来实现相应的图像显示。以显示装置是AMOLED(Active Matrix Organic Light Emitting Diode，有源矩阵有机发光二极体)显示装置为例，随着显示技术的发展，现有的AMOLED显示装置已经不再局限于手机类等中小尺寸产品，应用范围逐渐向折叠显示装置、笔记本电脑(Notebook)、车载类显示装置等中大尺寸产品扩展。而对于这类中大尺寸显示装置，由于尺寸变大，一些信号线相应增长，此时信号线的电阻增大，在信号传输过程中，信号线中靠近信号源(即输出该信号的电路)位置处和远离信号源位置处的电压值不一致，导致在信号传输方向上出现颜色不均(例如发紫)的问题。参见图1，可以看出信号线中靠近信号源的位置A的电压信号与远离信号源的位置B的电压信号的电压值并不相等，且位置A电压信号差值的绝对值大于位置B电压信号差值的绝对值，即在电压信号从位置A传输到位置B的过程中，由于信号线面电阻的影响，出现了信号衰减，对显示效果造成不利影响。
为了解决这一问题，本公开的一些实施例提供显示装置。示例性地，该显示装置可以是：显示器，电视，广告牌，数码相框，具有显示功能的激光打印机，电话，手机，个人数字助理(Personal Digital Assistant，PDA)，数码相机，便携式摄录机，取景器，导航仪，车辆，大面积墙壁、家电、信息查询设备(如电子政务、银行、医院、电力等部门的业务查询设备等。
在本公开的一些实施例中，参见图2，显示装置包括显示面板100。显示面板具有显示区(active area，简称AA区)和周边区S。其中，周边区S位于显示区至少一侧。示例性地，周边区S可以围绕显示区一圈设置。
示例性地，显示面板可以是OLED(Organic Light Emitting Diode，有机发光二极管)面板、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)面板、LCD(Liquid Crystal Display，液晶显示器)面板、微LED(包括：miniLED或microLED)面板等。
示例性地，显示面板100可以包括多个子像素P，多个子像素P位于AA区。示例性地，多个子像素P可以呈阵列排布。例如，沿X方向排列成一排的子像素P称为同一像素，沿Y方向排列成一排的子像素P称为 同一列像素。
示例性地，多个子像素P包括第一颜色子像素P、第二颜色子像素P和第三颜色子像素P；例如，第一颜色、第二颜色和第三颜色为三基色；例如，第一颜色、第二颜色和第三颜色分别为红色、绿色和蓝色；即，多个子像素P包括红色子像素P、绿色子像素P和蓝色子像素P。
示例性地，显示装置还可以包括驱动芯片。例如，驱动芯片为驱动IC，例如，驱动IC包括源极驱动器。例如，驱动芯片被配置为向显示面板中的各个子像素P提供驱动信号；例如驱动信号包括数据信号。
示例性地，显示装置还可以包括：触摸板(也可称为触摸屏、触摸结构或触摸层)。该触摸板用于感应触摸位置，可以根据触摸板感应到触摸位置，控制显示面板上显示的图像，从而实现人机交互。
在本公开的一些实施例中，参见图2，显示面板100包括驱动背板1和待驱动件(例如，发光器件L)，待驱动件设置于驱动背板1上，由驱动背板1驱动工作。
以待驱动件为发光器件L为例，驱动背板1可以用于驱动发光器件L进行发光，包括多个像素电路210。可以理解的是，如图2所示，显示面板的至少一个子像素P(例如，每个子像素P)包括像素电路210和发光器件L。其中，像素电路210与发光器件L耦接。像素电路210被配置为驱动发光器件L发光。示例性地，多个像素电路呈阵列排布。
本公开的实施例对像素电路的具体结构不作限定，可以根据实际情况进行设计。示例性地，像素电路由薄膜晶体管(Thin Film Transistor，简称TFT)、电容器(Capacitance，简称C)等电子器件组成。例如，像素电路可以包括两个薄膜晶体管(一个开关晶体管和一个驱动晶体管)和一个电容器，构成2T1C结构；当然，像素电路还可以包括两个以上的薄膜晶体管(多个开关晶体管和一个驱动晶体管)和至少一个电容器，例如参考图3，像素电路210可以包括存储电容器Cst和七个晶体管(六个开关晶体管M1、M2、M3、M4、M5和M6以及一个驱动晶体管MD)，构成7T1C结构。
例如，如图3所示，以像素电路210为7T1C结构为例。驱动背板1除了像素电路还包括多条信号线，例如，栅线(Gate Line，GL)，数据线(Data Line，DL)，发光控制信号线EM，初始化信号线Init以及复位信号线Reset和Reset’等。其中，栅线GL可以用来传输栅极驱动信号；数据线DL被配置为待驱动件提供数据信号(数据电流或数据电压)，以驱动待驱动件工作； 驱动控制信号线(例如发光控制信号线EM)可以用来传输驱动控制信号(例如发光控制信号)；初始化信号线Init可以用来传输初始化信号；以及，复位信号线可以用来传输复位信号。
示例性地，同一行的各个像素电路可以与一条栅线GL、一条复位信号线Reset、一条复位信号线Reset’以及一条发光控制信号线EM耦接。其中，与同一行的各个像素电路耦接的复位信号线Reset和复位信号线Reset’，二者可以是两条信号线，分别传输不同的复位信号；二者也可以是同一条信号线。示例性地，同一列的像素电路可以与同一条数据线DL耦接。
示例性地，在像素电路中，一部分开关晶体管(例如，M5、M6)的控制极(栅极)用于接收复位信号。另一部分开关晶体管(例如，M1、M2)的控制极用于接收栅极驱动信号。又一部分开关晶体管(例如，M3、M4)的控制极用于接收驱动控制信号如发光控制信号。例如，晶体管M5和晶体管M6响应于复位信号导通，初始化信号通过晶体管M5和晶体管M6，分别传输至驱动晶体管MD的控制极以及发光器件L的阳极，达到对发光器件L的阳极以及驱动晶体管MD的控制极进行复位的目的。响应于栅极驱动信号，晶体管M1和晶体管M2导通，驱动晶体管MD的控制极(g)与漏极(d)耦接，该驱动晶体管MD成二极管导通状态。此时，数据信号通过该晶体管M1写入至驱动晶体管MD的源极(s)，并将由数据信号和驱动晶体管MD的阈值电压得到的补偿信号施加到驱动晶体管MD的控制极(g)。响应于发光控制信号，晶体管M3和晶体管M4导通，第一电源电压线VDD与第二电源电压端VSS之间的电流通路导通。基于驱动晶体管MD的控制极(g)的电压与第一电源电压信号(VDD提供的信号)之间的差产生的驱动电流通过上述电流通路传输至发光器件L，以驱动发光器件L进行发光。示例性地，发光器件L的一极(例如阳极)与像素电路耦接，发光器件L的另一极(例如阴极)与第二电源电压端VSS耦接；例如，该第二电源电压端VSS被配置为传输直流电压，例如直流低电压。
示例性地，发光器件L可以采用包括LED(发光二极管，Light Emitting Diode)、OLED(有机电致发光二极管，Organic Light Emitting Diode)或QLED等发光器件。发光器件L包括阴极和阳极，以及位于阴极和阳极之间的发光功能层。其中，发光功能层例如可以包括发光层E、位于发光层E和阳极之间的空穴传输层(Hole Transporting Layer，HTL)、位于发光层E和阴极之间的电子传输层(Election Transporting Layer，ETL)。当然，根据需要在一些实 施例中，还可以在空穴传输层HTL和阳极之间设置空穴注入层(Hole Injection Layer，HIL)，可以在电子传输层ETL和阴极之间设置电子注入层(Election Injection Layer，EIL)。
示例性地，阳极例如可由具有高功函数的透明导电材料形成，其电极材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等；阴极例如可由高导电性和低功函数的材料形成，其电极材料可以包括镁铝合金(MgAl)和锂铝合金(LiAl)等合金或者镁(Mg)、铝(Al)、锂(Li)和银(Ag)等金属单质。发光层的材料可以根据其发射光颜色的不同进行选择。例如，发光层的材料包括荧光发光材料或磷光发光材料。例如，在本公开至少一个实施例中，发光层可以采用掺杂体系，即在主体发光材料中混入掺杂材料来得到可用的发光材料。例如，主体发光材料可以采用金属化合物材料、蒽的衍生物、芳香族二胺类化合物、三苯胺化合物、芳香族三胺类化合物、联苯二胺衍生物和三芳胺聚合物等。
示例性地，参见图4，驱动背板1还可以包括：与栅线GL连接的GOA(Gate driver On Array)电路，用于向栅线GL提供栅极驱动信号，和/或用于向发光控制信号线EM提供发光控制信号。例如，GOA驱动电路可以包括发光驱动器22和扫描驱动器23中的至少一者。在显示面板有N行子像素的情况下，扫描驱动器23有N+1个信号输出端(即提供栅极驱动信号和复位信号的信号源)，与第一行子像素至第N行子像素中的像素电路210耦接的栅线GL(即N条栅线GL)N条栅线GL分别与扫描驱动器23的N个第一信号输出端一一对应地耦接；第1行子像素中的像素电路还与复位信号线RE0电连接，该复位信号线RE0与扫描驱动器23电连接，第1行子像素中的像素驱动电路在起始复位信号线RE0的控制下进行复位；第2行子像素至第N行子像素中的复位信号由上一行子像素耦接的栅线GL传输，即上一行子像素耦接的栅线GL复用为当前行子像素的复位信号线，或者上一行子像素的栅线GL和当前行子像素的复位信号线耦接。此外，第1行子像素至第N行子像素中的像素电路210耦接的发光控制信号线EM与扫描驱动器23的第1个至第N个第一信号输出端一一对应地耦接。类似的，发光驱动器22有N个第二信号输出端(即提供发光控制信号的信号源)，分别为Q 1，Q 2，……，Q N；与第一行子像素至与第N行子像素中的像素电路210 电连接的发光控制信号线EM(即N条发光控制信号线EM)，分别为EM(1)，EM(2)，……EM(N)；N条发光控制信号线EM分别与发光驱动器22的N个第二信号输出端耦接。GOA电路的设置不仅能降低信号线上的电压衰减程度，还能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使显示装置的边框更窄，实现更好的显示效果。
示例性地，驱动背板1可以采用双边驱动的方式，即驱动背板1包括两个沿行方向相对设置的GOA电路，例如图4中在显示区外的左右两侧分别设置一GOA电路。位于左侧的扫描驱动器23和位于右侧的扫描驱动器23，二者包含的第一信号输出端的数量相同；左右两侧次序相同的第一信号输出端输出的信号相同，并与同一条栅线耦接；例如，左侧第5个第一信号输出端和右侧第5个第一信号输出端输出的信号相同，且均与栅线GL(5)耦接。类似的，位于左侧的发光驱动器22和位于右侧的发光驱动器22，二者包含的第二信号输出端的数量相同；左右两侧次序相同的第二信号输出端输出的信号相同，并与同一条发光控制线耦接。这样一来，两个扫描驱动器23可以同步对多条栅线和多条复位信号线Reset逐行扫描，两个发光驱动器22可以同步对多条发光控制信号线逐行扫描，由于每条信号线(栅线或发光控制信号线)上的信号从该信号线两端分别输入，这样能够在一定程度上降低该信号线上的信号衰减。对于中大尺寸的显示装置而言，降低信号衰减的效果更为突出。
示例性地，驱动背板1也可以采用单边驱动的方式，即仅在驱动背板1的其中一侧设置一GOA电路，该GOA电路对多条栅线、多条复位信号线以及多条发光控制线中的至少一者逐行扫描。
下面，以驱动背板1包括上述的像素电路210为例，详细介绍驱动背板1的结构。
在本公开的一些实施例中，参见图7～图12，驱动背板1包括衬底11，设置在衬底11上的第一导电层13，设置在第一导电层13远离衬底11一侧的第一绝缘层12，以及设置在第一绝缘层12远离第一绝缘层一侧的第二导电层14。
衬底11被配置为承载驱动背板1的多个膜层，其可以为空白的衬底基板。例如，衬底基板可以是刚性衬底基板；该刚性衬底基板例如可以 为玻璃衬底基板或PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底基板等。又如，衬底基板可以为柔性衬底基板；该柔性衬底基板例如可以为PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)衬底基板、PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)衬底基板或PI(Polyimide，聚酰亚胺)衬底基板等。参见图5，衬底11还可以包括衬底基板和在衬底基板上形成的至少一个膜层，例如，屏障层(Barrier)、缓冲层(Buffer)等。示例性地，衬底11可以包括多个(例如两个)层叠设置的衬底单元，相邻两个衬底单元之间可以设置非晶硅层，用于增加相邻两个衬底单元之间的粘附力。每个衬底单元可以包括：衬底基板和设置在衬底基板上的屏障层。
第一导电层13、第二导电层14等均是图案层。图案层是指通过一次构图工艺形成的膜层。构图工艺是指能够形成至少一个具有一定形状的图案的工艺。例如，在衬底11上通过沉积、涂覆、溅射等多种成膜工艺中的任一种形成薄膜，然后将该薄膜图案化以形成包含至少一个图案的膜层，称之为图案层。图案化的步骤包括：涂覆光刻胶、曝光、显影、刻蚀和剥离光刻胶等。本实施例中，将属于同一图案层的多个图案的位置关系称为同层设置。
参见图6和图9，第一导电层13包括至少一条第一信号线131。例如，第一导电层13包括多条延伸方向相同的第一信号线131，相邻两条第一信号线131之间存在间隔。每条第一信号线131可以用于传输一种信号，驱动信号可以为栅极驱动信号、发光控制信号或复位信号等。第一导电层13的材料不做限制，可以选自金属、金属合金、金属氧化物导电材料、有机导电材料、碳纳米管和石墨烯中的至少一种等。例如，第一导电层13的材料可以为钼(Mo)。
示例性地，参见图4、图6和图9，第一导电层13可以包括至少两条第一信号线131，至少两条第一信号线131包括：栅线GL，发光控制信号线EM和复位信号线(Reset和Reset’)中的至少一种。示例性地，第一导电层13包括：多条栅线GL，多条发光控制信号线EM和多条复位信号线(Reset和Reset’)这三种第一信号线。此外，第一信号线131的全部或部分位于显示区。参考图4，在一些实现方式中，沿第一信号线131的延伸方向(X方向)，第一信号线131的两端可以超出AA区相对的两个边沿。在另一些实现方式中，沿第一信号线131的延伸方向(X方向)，第一信号线131的一端超出AA区的边沿，另一端与AA区的边沿齐平或在AA区之内。 在又一些实现方式中，沿第一信号线131的延伸方向(X方向)，第一信号线131的两端分别与AA区相对的两个边沿齐平。
参见图6和图10，第二导电层14包括至少一条第二信号线141。例如，第二导电层14包括多条延伸方向与第一信号线131延伸方向平行的第二信号线141，相邻两条第二信号线141之间存在间隔。例如，第二信号线141和第一信号线131均平行于X方向延伸。第二导电层14材料可以参考上述第一导电层13的描述，在此不加赘述。可以理解的是，第一导电层13与第二导电层14的材料可以相同，也可以不同。
示例性地，参见图6、图7和图8，每条第一信号线131与一条第二信号线141组成一个信号线对15。在同一信号线对15中，第一信号线131与第二信号线141的延伸方向平行。第二信号线141的全部或部分位于显示区内。在一些实现方式中，同一信号线对15中，沿第二信号线141的延伸方向(X方向)，第二信号线141的两端可以与第一信号线131的两端齐平，此时第二信号线141和第一信号线131长度相同。在另一些实现方式中，同一信号线对15中，沿第二信号线141的延伸方向(即X方向)，第二信号线141的两端中的至少一端位于第一信号线131的内侧，即第二信号线141的长度小于第一信号线131的长度；例如，第二信号线141的左端在第一信号线131的左端的右侧，第二信号线141的右端在第一信号线131的右端的左侧。在又一些实现方式中，第二信号线141可以包括沿其延伸方向间隔分布的多条信号子线。
在同一信号线对15中，第一信号线131在衬底上11的正投影与第二信号线141在衬底上11的正投影具有第一重叠区域111。第二信号线141在衬底上11的正投影可以被第一信号线131在衬底上11的正投影完全覆盖，也可以部分在第一信号线131在衬底上11的正投影以内。例如，参见图8，在显示区内，沿第二信号线141宽度方向(即Y方向)，第二信号线141在衬底上11的正投影相对的两个边沿中，其中一个边沿的全部或部分位于第一信号线131在衬底上11的正投影相对的两个边沿之间，另一个边沿位于第一信号线131在衬底上11的正投影相对的两个边沿之外，或与第一信号线131在衬底上11的正投影相对的两个边沿中的一个齐平。又如，在显示区内，沿第二信号线141宽度方向(即Y方向)，第二信号线141在衬底上11的正投影相对的两个边沿与第一信号线131在衬底上11的正投影相对的两个边沿分别齐平。可以理解的是，第一信号线131在衬底上11的正投影即为第一信号线131沿衬底11垂 线方向在衬底11上的投影。
此外，在同一信号线对15中，第一信号线131与第二信号线141耦接。第一信号线131与第二信号线141的耦接可以是直接连接，例如，第二信号线141贯穿第一绝缘层12与第一信号线131耦接；也可以是通过其他导电结构间接连接。
参见图8和图9，第一绝缘层12位于第一导电层13和第二导电层14之间，用于使第一信号线131和第二信号线141上对应于第一重叠区域111以外的部分电性绝缘。第一绝缘层12的材料可以选用氮化硅、氧化硅等。
在本公开的实施例中，一个信号线对中，将第一信号线131与第二信号线141耦接，相当于将第一信号线131与第二信号线141并联，可以理解的是，信号线对的面电阻相比于第一信号线131的面电阻减小。当信号线对用于传输驱动信号时，由于面电阻较小，使得信号线对构成的RC(电阻电容电路)带来的负载减少，在传输距离一定时，面电阻所导致的电压衰减程度降低，沿信号线对的延伸方向各像素发生颜色异常的概率降低，从而能够实现更好的显示效果。同时，在同一信号线对15中第一信号线131在衬底上11的正投影与第二信号线141在衬底上11的正投影具有第一重叠区域111，布线所占用的空间较小，能有效避免空间布线限制。
在本公开的一些实施例中，参见图7和图8，驱动背板1还可以包括：设置于第二导电层14远离衬底11一侧的第二绝缘层16，以及设置于第二绝缘层16远离衬底11一侧的第三导电层17。第三导电层17包括至少一个(例如，可以是多个)第一导电图案171，每个第一导电图案171贯穿第二绝缘层16与一条第二信号线141耦接，每个第一导电图案171贯穿第二绝缘层16和第一绝缘层12与一条第一信号线131耦接。通过第一导电图案171实现同一个信号线对中的第一信号线131和第二信号线141的耦接，以实现降低电阻、提高显示效果的目的。可以理解的是，第一导电图案171与一条第一信号线131耦接时在第二绝缘层16和第一绝缘层12上的贯穿位置，与第一导电图案171与一条第二信号线141耦接时在第二绝缘层16上的贯穿位置可以相同，也可以不同。无论贯穿的位置相同与否，在制备驱动背板时，可以在衬底上依次形成第一导电层13，第一绝缘薄膜(一整层绝缘材料)，第二导电层14，第二绝缘薄膜(一整层绝缘材料)，然后通过一次构图工艺，在上述贯穿位置 形成相应过孔，以便在形成第三导电层17后能够实现相应的电连接。由于两个绝缘层的过孔可以通过一次构图工艺形成，因此在实现电阻降低的同时，工艺过程更加简单，相应的，也就更加生产节省成本。在本公开的一些实施例中，参见图6，第一绝缘层12具有至少一个第一过孔121，第二绝缘层16具有至少一个第二过孔161；每个第一过孔121和一个第二过孔161组成一个过孔对18，同一过孔对18中，第一过孔121与第二过孔161连通。第一信号线161中由过孔对18露出的部分为第一连接部1311，第二信号线141中由过孔对18中的第二过孔161露出的部分为第二连接部1411。由于同一个过孔对18既要露出第一连接部1311，又要露出第二连接部1411，因此该过孔对18的位置应该在第一信号线161和第二信号线141重叠的位置处，即在衬底11上的正投影与第一重叠区域111具有第二重叠区域112。第一导电图案171通过至少一个过孔对18中的第二过孔161与第二连接部1411接触，并通过这些过孔对18中的每个过孔对18与第一连接部1311接触。从而实现了第一导电图案171通过同一个过孔对18就能既连接第一信号线161，又连接第二信号线141，能够减少过孔的数量，通过过孔连接的双方的尺寸就可以做小些，这样虽然本实施例中增加了第一导电图案171，但也不必因此增大一个子像素的尺寸。可以理解的是，第一过孔121与第二过孔161的形状可以为圆形、三角形、正方形等；第一过孔121与第二过孔161的形状可以相同，也可以不同；第一过孔121与第二过孔161可以在同一构图工艺中形成，也可以分两次构图工艺形成。
在本公开的一些实施例中，参见图7，在同一过孔对18中，第一过孔121具有相对的第一开口1211和第二开口1212，相较于第二开口1212，第一开口1211远离衬底11。第二过孔161具有相对的第三开口1611和第四开口1612，相较于第四开口1612，第三开口1611远离衬底11。第一开口1211在衬底11上的正投影与第二连接部1411在衬底11上的正投影的组合与第四开口1612在衬底11上的正投影大致重合。可以理解的是，要实现上述的过孔对18的设计，在制备驱动背板时，可以在衬底上依次形成第一导电层13，第一绝缘薄膜，第二导电层14，第二绝缘薄膜，然后通过一次构图工艺，在第一绝缘薄膜和第二绝缘薄膜上形成上述的过孔对18。由于一次构图工艺仅需要采用一张MASK(掩膜版)，还能够达到降低生产成本的效果。该过孔对18中，参见图8，第一开口1211在衬底11上的正投影与第二连接部1411在衬底11上的正 投影的组合与第四开口1612在衬底11上的正投影大致重合，其含义是：二者可以重合，也可以是因为构图工艺中的过刻等原因使得二者有微小的差异。第一导电图案171通过该过孔对18实现第一信号线131和第二信号线141的耦接，并达到降低电阻、提高显示效果的目的。
在本公开的一些实施例中，参见图8，上述的过孔对18在衬底11上的正投影包含于信号线对15在衬底11上的正投影的边界内，即过孔对18在衬底11上的正投影位于信号线对15在衬底11上的正投影的边界内，或者说信号线对15在衬底11上的正投影完全覆盖上述的过孔对18在衬底11上的正投影，两个正投影之间可留有间隙。其中，过孔对18在衬底11上的正投影是过孔对18的最大开口(例如是第三开口1611)在衬底11上的正投影。信号线对15在衬底11上的正投影是指该信号线对15中，第一信号线131在衬底11上的正投影和第二信号线141在衬底11上的正投影的组合。
可以理解的是，参见图9中的(a)，过孔对18的尺寸较大，其在衬底11上的正投影中的一部分位于信号线对15在衬底11上的正投影的边界以外，在形成过孔对18时，信号线对15边缘处的无机膜层会被一并刻蚀，形成倒角70(也可以称为Undercut)，该倒角70的存在使得信号线对15中例如第二信号线141的边缘处与其下方的第一绝缘层12之间存在段差，第二信号线141边缘处悬空，在后续的工艺过程中信号线边缘悬空区域可能发生断裂，导致信号线对15面电阻增大，并最终对显示效果产生不利影响。而当过孔对18的尺寸过小时，参见图9中的(b),过孔对18在衬底11上的正投影可能仅位于第一信号线131或第二信号线141在衬底11上的正投影内，导致第一导电图案171只能与其中一条信号线耦接，不能实现第一信号线131和第二信号线141的并联，无法实现降低电阻的效果。
在本公开的一些实施例中，参见图6和图13，同一信号线对15中，第一信号线131通过多个过孔对18与第二信号线141耦接，多个过孔对18沿第一信号线131的延伸方向排列。可以理解的是，由于存在多个用于实现电连接的过孔对18，即使某一第一导电图案171出现连接不良的现象，其他第一导电图案171仍通过相应的过孔对18实现第一信号线131和第二信号线141的耦接，从而提高显示装置的可靠性。
在本公开的一些实施例中，参见图8，第一导电图案171在衬底11上的正投影完全覆盖过孔对18在衬底11上的正投影。可以理解的是， 若第一导电图案171在衬底11上的正投影未完全覆盖过孔对18在衬底11上的正投影，第一导电图案171没有充满过孔对18，导致出现连接不良的几率增大，连接可靠性降低，因此本实施例中的方案可以避免出现上述问题。
在本公开的一些实施例中，参见图8，驱动背板1各个膜层都依赖于机械设备形成，受制于现有工艺技术水平，机械设备很难实现完全精准对位，只能实现将对位精度控制在预设范围内。对位精度是显示面板上需要对位的层与层的刻蚀图形的位置对准误差。示例性地，刻蚀形成的第一导电图案171在衬底11上的正投影具有第一几何中心，被第一导电图案171完全覆盖的过孔对18在衬底11上的正投影具有第二几何中心，在理想条件下，第一几何中心与第二几何中心完全重合，对位精度为0μm；而在非理想条件下，受制于工艺水平和工艺设备，第一几何中心与第二几何中心可能不重合，当第一几何中心与第二几何中心不重合时，第一几何中心与第二几何中心之间的直线距离的最大值即为对位精度。受到设备对位精度的影响，同时综合考虑需要对过孔对18进行完全覆盖，以避免出现覆盖不完全可能引起的连接不良的问题，因此，第一导电图案171在衬底11上的正投影的边沿与过孔对18在衬底11上的正投影的边沿的之间的最小距离d可以大于或等于设备的对位精度。例如，当设备对位精度为0.5μm时，则需要保证第一导电图案171在衬底11上的正投影的边沿与过孔对18在衬底11上的正投影的边沿的之间的最小距离d大于或等于0.5μm。可以理解的是，第一导电图案171在衬底11上的正投影的边沿与过孔对18在衬底11上的正投影的边沿的之间的最小距离d，会随着设备对位精度的改变相应的发生变化，只要最终实现对过孔对18的完全覆盖即可，并不局限于某一具体数值。可以理解的是，对位精度与工艺水平以及工艺设备有关，示例性地，当工艺水平提高、采用更先进的工艺设备时，工艺过程中操作位置的对位也就更精准，对位精度的数值也会更小。在本公开的一些实施例中，参见图8，为了实现更合理的空间布线，第一信号线131在衬底上11的正投影与第二信号线141在衬底上11的正投影具有第一重叠区域111，该第一重叠区域111的宽度与所述第一信号线的宽度的比值为1/3～1/2。例如，当第一信号线131的宽度为3μm时，第一重叠区域111的宽度可以为1μm。为了保证第一重叠区域111的宽度在预设范围内，消除设备的对位精度的影响，沿第一信号线131的宽度方向，第一重叠区域111的宽度h可以为第一 信号线131宽度的1/3±对位精度，例如，当第一信号线131宽度为3μm、对位精度为0.5μm时，第一重叠区域111的宽度可以为1±0.5μm，即第一重叠区域111的宽度h的取值范围为0.5μm～1.5μm，与所述第一信号线的宽度的比值在1/3～1/2之间。这里的第一信号线131的宽度可以理解为第一信号线131中与第一重叠区域111对应部分的平均宽度。又示例性地，在不考虑第一信号线131的宽度和对位精度的情况下，第一重叠区域111的宽度h的取值范围仍可以为0.5μm～1.5μm。
在本公开的一些实施例中，参见图8，同一信号线对15中的第一信号线131的宽度w1和第二信号线141的宽度w2相等，例如均为3μm，第一重叠区域111的宽度可以为1±0.5μm。耦接第一信号线131和第二信号线141的过孔对18在衬底11上的正投影可以为圆形，该圆形的直径可以为2μm，保证了过孔对18在衬底11上的正投影位于信号线对15在衬底11上的正投影的边界内；第一导电图案171在衬底11上的正投影可以为正方形，该正方形的边长可以为3μm，从而对过孔对18进行完全覆盖，保证连接效果。可以理解的是，上述数值可以根据工艺条件及设计需求进行改变，并不限定某一具体数值，只要能够实现相应的效果即可。
在本公开的一些实施例中，像素电路210还包括至少一个电容器C(例如，一个存储电容器C)，每个电容器C包括两个极板，第一极板43和第二极板44，其中，第二极板44位于第一极板43远离衬底11的一侧。示例性地，第一极板43与第一信号线131同层设置，二者均包含在第一导电层13中，第二极板44与第二信号线141同层设置，二者均包含在第二导电层14中。
在本公开的一些实施例中，参见图11，第二导电层14除了第二信号线141外，还包括至少两个第二导电图案142，至少两个第二导电图案142包括：像素电路210中电容器C的一个极板和/或初始化信号线Init。示例的，第二导电层14包括两种第二导电图案142，分别是像素电路210中电容器C的第二极板44和初始化信号线Init，其中，初始化信号线Init的延伸方向可以与栅线GL的延伸方向相同。
在本公开的一些实施例中，参见图6和图8，与第二导电图案142相邻的一个信号线对15中，第一信号线131相较于第二信号线141更靠近第二导电图案142。即相邻的信号线对15和第二导电图案142之间不 存在其他第二导电图案142或其他信号线对15。信号线对15中的第一信号线131具有沿其宽度方向相对的第一边沿1312和第二边沿1313，其中，相比于第二边沿1313在衬底11上的正投影，第一边沿1312在衬底11上的正投影更靠近第二导电图案142在衬底11上的正投影。信号线对15中的第二信号线141具有第三边沿1412和第四边沿1413，其中，相比于第四边沿1313在衬底11上的正投影，第三边沿1412在衬底11上的正投影更靠近第二导电图案142在衬底11上的正投影。第一信号线131相较于第二信号线141更靠近第二导电图案142，即一个信号线对15中，相比于第三边沿1412在衬底11上的正投影，第一边沿1312在衬底11上的正投影更靠近第二导电图案142在衬底11上的正投影。可以理解的是，当第二信号线141相较于第一信号线131更远离第二导电图案142时，在第二信号线141的宽度方向上，第二信号线141与第二导电图案142之间存在间隙，该间隙的存在能够保证同层设置的第二信号线141与第二导电图案142之间相互绝缘，不会因设备对位精度的存在导致第二信号线141与第二导电图案142相互连接发生短路，对设备对位精度的要求相对较低，在现有的工艺水平条件下更容易实现。
在本公开的一些实施例中，参见图12，驱动背板1还包括有源图案层40。有源图案层40设置于第一导电层13靠近衬底11的一侧。示例性地，有源图案层40与第一导电层13绝缘；例如，有源图案层40与第一导电层13之间设置有栅绝缘层GI。有源图案层40包括半导体图案41和导体化图案42。示例性地，在衬底11上形成半导体材料薄膜，对半导体材料薄膜中的一部分进行导体化，例如离子掺杂，得到导体化图案42，半导体材料薄膜中未进行导体化的部分即为半导体图案41，每个半导体图案41将多个导体化图案42中的两个导体化图案间隔开。
示例性地，像素电路包括多个晶体管，每个晶体管包括有源层，有源层包括沟道区、第一极区和第二极区，第一极区和第二极区分别位于沟道区的两侧；例如，第一极区和第二极区中的其中一者为源极区，另一者为漏极区。可以理解的是，半导体图案包括有源层中的沟道区，一导体化图案包括有源层中的第一极区或第二极区，相应的，导体化图案位于半导体图案的两侧。
在本公开的一些实施例中，参见图3、图6和图12，像素电路中的多个晶体管包括驱动晶体管MD。有源图案层40中的与第一极板43在衬底11上的正投影有重叠的部分，作为像素电路中驱动晶体管的有源层ACTa中的沟 道区411a。第一极板43中对应于驱动晶体管的有源层ACTa中的沟道区411a的部分充当驱动晶体管的控制极(即栅极)251a。
示例性地，参见图3、图6和图12，像素电路210中的多个晶体管包括第一晶体管M1和第二晶体管M2。其中，有源图案层40中的与栅线GL在衬底11上的正投影有重叠的部分，分别作为第一晶体管的有源层ACTb中的沟道区411b和第二晶体管的有源层ACTc中的沟道区411c1和411c2。其中，第一晶体管的有源层411b中的第二极区422b与驱动晶体管的有源层ACTa中的第一极区421a连接，第二晶体管的有源层ACTc中的第二极区422c与驱动晶体管的有源层ACTa中的第二极区422a连接。发光控制线EM与栅线GL间隔设置；发光控制线EM的延伸方向与栅线GL的延伸方向平行。像素电路中的多个晶体管还包括第三晶体管M3和第四晶体管M4。有源图案层40中的与发光控制线EM在衬底11上的正投影有重叠的部分，分别作为第三晶体管的有源层ACTd中的沟道区411d和第四晶体管的有源层ACTe中的沟道区411e。例如，发光控制线EM对应于第三晶体管的有源层中的沟道区(411d)的部分可以充当第三晶体管的控制极251d；发光控制线EM对应于第四晶体管的有源层中的沟道区(411e)的部分可以充当第六晶体管的控制极251e。第三晶体管的有源层ACTd中的第二极区422d与驱动晶体管的有源层ACTa中的第一极区421a和第一晶体管的有源层ACTb中的第二极区422b连接，且无间隙，例如，第三晶体管的有源层ACTd、驱动晶体管的有源层ACTa和第一晶体管的有源层ACTb连为一体结构。第四晶体管的有源层ACTe中的第一极区421e与驱动晶体管的有源层ACTa中的第二极区422a和第二晶体管的有源层ACTc中的第二极区422c连接，且无间隙，例如，第四晶体管的有源层ACTe、驱动晶体管的有源层ACTa和第二晶体管的有源层ACTc连为一体结构。
在本公开的一些实施例中，参见图6和图13，第三导电层17还包括至少一个第三导电图案31；例如，第三导电层17可以包括多个第三导电图案31，每个像素电路中包括一个第三导电图案31。其中，第三导电图案31可以将第一极板43和第二晶体管的有源层ACTc中的第一极区421c电连接。示例性地，第二晶体管的有源层ACTc中的第一极区421c与第三导电图案31耦接。例如，第三个导电图案31和第二晶体管的有源层ACTc中的第一极区421c通过两者之间夹设的膜层(例如包括层间介质层和栅绝缘层)上的过孔51b相接触。示例性地，第一极板43与第三导电图案31耦接。例如， 第三个导电图案31通过两者之间夹设的膜层(例如包括层间介质层和栅绝缘层)上的过孔51a相接触。
示例性地，栅线GL对应于第一晶体管的有源层ACTb中的沟道区411b的部分可以充当第一晶体管的控制极(即栅极)251b。示例性地，第二晶体管的有源层ACTc包括的沟道区分别为411c1、411c2和411c3；栅线GL对应于第二晶体管的有源层ACTc中的沟道区411c1和411c2的部分可以充当第二晶体管的控制极(即栅极)251c1和251c2，即，第二晶体管呈双栅结构，可以避免漏电流的产生。
在本公开的一些实施例中，参见图6和图13，第三导电层17还包括至少一条(例如，可以是多条)数据线DL。第一晶体管的有源层中的第一极区与数据线DL耦接；例如，数据线DL和第一晶体管的有源层ACTb中的第一极区421b通过两者之间夹设的膜层(例如包括层间介质层和栅绝缘层)上的过孔51c相接触。
在本公开的一些实施例中，参见图6和图13，第三导电层17还包括至少一条(例如，可以是多条)电源电压线VDD。电源电压线VDD和数据线DL的延伸方向相同，且每条电源电压线VDD在衬底11上的正投影与每条数据线DL在衬底11上的正投影无重叠区域，即每条电源电压线VDD和每条数据线DL之间沿宽度方向上存在间隙。第三晶体管的有源层中的第一极区与电源电压线耦接；例如，电源电压线VDD和第三晶体管的有源层中的第一极区421d通过两者之间夹设的膜层(例如包括层间介质层和栅绝缘层)上的过孔51d相接触。并且，电容器C中的第二极板44与电源电压线VDD耦接；例如，电源电压线VDD和电容器C中的第二极板44通过两者之间夹设的膜层(例如包括层间介质层)上的过孔51e相接触。可以理解的是，数据线DL与电源电压线VDD可以均属于同一图案层，例如上述第三导电层17，即二者同层设置。二者同层设置时，仅适用一张Mask通过一次构图工艺即可形成数据线DL与电源电压线VDD，能够简化制作工艺，节省制作成本。此外，数据线DL与电源电压线VDD也可以不同层设置，例如，数据线DL属于上述第三导电层17，电源电压线VDD可以属于第三导电层17远离衬底11一侧的一导电图案层。
参见图13和图14，驱动背板1还包括第四导电层20以及设置在第三导电层17和第四导电层20之间的第三绝缘层。第四导电层20包括至少一条(例如多条)辅助电源电压线VDD’，辅助电源电压线VDD’与电源电压线VDD耦接。可以理解的是，将电源电压线VDD与辅助电源电压线VDD’并联，能 够降低第三导电层17上每条电源电压线VDD的电阻，在电源电压不发生变化的条件下，电源电压线VDD的电阻越小，用于驱动发光器件L的电流就越大，相应的，发光器件L的发光效果也就越好。
示例性地，对第四导电层上的多条辅助电源电压线VDD’的设置方式不做限制，多条电源电压线VDD的延伸方向可以与第三导电层17上的电源电压线VDD延伸方向一致，也可以不一致，还可以多条辅助电源电压线VDD’中的一部分与电源电压线VDD延伸方向一致，与电源电压线VDD延伸方向不一致，例如，辅助电源电压线VDD’中的一部分沿第一方向(例如，沿X方向)延伸，另一部分沿第二方向(例如，沿Y方向)延伸，延伸方向相同的多条辅助电源电压线VDD’之间存在间隙，延伸方向不同的多条辅助电源电压线VDD’之间相互耦接，呈网格状。
辅助电源电压线VDD’和与电源电压线VDD耦接的方式可以参考上述的第一信号线131和第二信号线141耦接的方式，例如，电源电压线VDD相当于第一信号线131，辅助电源电压线VDD’相当于第二信号线141，二者进行耦接。又如，辅助电源电压线VDD’的延伸方向与电源电压线VDD延伸方向一致。辅助电源电压线VDD’在衬底11上的正投影与第三导电层17上的电源电压线VDD在衬底11上的正投影具有第三重叠区域112。第三绝缘层上具有至少一个第三过孔191(例如，可以是多个)，每个第三过孔191在衬底11上的正投影与第三重叠区域112至少部分重叠，第四导电层通过第三过孔191与第三导电层17上的每条电源电压线VDD耦接，实现并联。在本公开的一些实施例中，参见图6和图13，第三导电层17还包括至少一个第四导电图案32(例如，可以是一个)。该第四导电图案32与第四晶体管的有源层中的第二极区422e耦接。例如，第四导电图案32与第四晶体管的有源层中的第二极区422e通过两者之间夹设的膜层(例如包括层间介质层和栅绝缘层)上的过孔51f相接触。其中，该第四导电图案32用于与发光器件L耦接。例如，第四导电图案32与发光器件L的一极(阳极或阴极)耦接；第四晶体管与发光器件L耦接。例如，第三导电层17远离衬底的一侧设置有钝化层(PVX)，例如钝化层的材料可以采用包括聚酰亚胺等的有机材料；发光器件的一极(阳极或阴极)通过设置于钝化层上的过孔61与第四导电图案32接触(图中未示出发光器件L)。
在本公开的一些实施例中，参见图6和图12、图13，像素电路210中的多个晶体管包括第五晶体管M5和第六晶体管M6。有源图案层40中的与第一导电层13中的复位信号线Reset在衬底11上的正投影有重叠的部分，作为 第五晶体管的有源层ACTf中的沟道区(411f1和411f2)，有源图案层40中的与第一导电层13中的复位信号线Reset’在衬底11上的正投影有重叠的部分，作为第六晶体管的有源层ACTg中的沟道区(411g)。例如，复位信号线Reset对应于第五晶体管的有源层中的沟道区(411f1和411f2)的部分可以充当第五晶体管的控制极251f1和251f2，即，第五晶体管呈双栅结构，可以避免漏电流的产生；复位信号线Reset’对应于第六晶体管的有源层中的沟道区(411g)的部分可以充当第六晶体管的控制极251g。其中，第五晶体管的有源层ACTf中的第二极区422f与第二晶体管的有源层ACTc中的第一极区421c连接，即，第五晶体管的有源层ACTf中的第二极区422f，与第一导电图案31耦接，与第一极板43也耦接；也即，第五晶体管的有源层ACTf中的第二极区422f与驱动晶体管的控制极251a耦接。第六晶体管的有源层ACTg中的第二极区422g与第四晶体管的有源层ACTe中的第二极区422e连接，即，第六晶体管的有源层ACTg中的第二极区422g与第四导电图案32耦接。例如，第六晶体管的有源层ACTg中的第二极区422g与发光器件L耦接。
示例性地，第三导电层17还包括至少一个第五导电图案33(例如，可以是多个)，第五导电图案33与初始化信号线Init耦接，第五导电图案33还与第六晶体管的有源层中的第一极区421g耦接。第五导电图案33与初始化信号线Init通过两者之间夹设的膜层(例如包括层间介质层)上的过孔51g接触，第五导电图案33与第六晶体管的有源层中的第一极区421g通过两者之间夹设的膜层(例如包括层间介质层和栅绝缘层)上的过孔51h连接。可以理解的是，对第三导电图案31、第四导电图案32和第五导电图案33的形状以及延伸方向不做限制，只要能够通过相应过孔实现相应结构的电连接即可。
示例性地，复位信号线Reset和Reset’可以传输相同的信号；例如，一行像素电路可以耦接一条复位信号线。即，第五晶体管和第六晶体管同时导通，使得驱动晶体管和发光器件在同一时段实现复位。
又示例性地，复位信号线Reset和Reset’可以传输不同的信号；例如，一行像素电路可以耦接两条复位信号线Reset和Reset’。例如，对于一行像素电路，一行像素电路中的第五晶体管所耦接的复位信号线Reset与该一行像素电路的上一行像素电路所耦接的栅线GL传输相同的信号；一行像素电路中的第六晶体管所耦接的复位信号线Reset’与该一行像素电路所耦接的栅线GL传输相同的信号。此时，一行像素电路耦接的一条复位信号线与上一行像素电路耦接的栅线GL共用，一行像素电路耦接的另一条复位信号线可 以与该一行像素电路耦接的栅线GL共用。
在此情况下，一行像素电路中的第五晶体管响应于来自其所耦接的复位信号线的复位信号，第五晶体管导通，将来自初始化信号线Init的初始化信号传输至驱动晶体管的控制极，对驱动晶体管复位；同时，该一行像素电路的上一行像素电路中的第一晶体管和第二晶体管响应于来自其所耦接的栅线GL的栅极驱动信号，第一晶体管和第二晶体管导通，写入数据信号，并将驱动晶体管的阈值电压和数据信号写入至驱动晶体管的控制极。该一行像素电路中的第六晶体管响应于来自其所耦接的复位信号线的复位信号第六晶体管导通，对发光器件进行复位，同时，该一行像素电路中的第一晶体管和第二晶体管响应于来自其所耦接的栅线GL的栅极驱动信号，第一晶体管和第二晶体管导通，写入数据信号，并将驱动晶体管的阈值电压和数据信号写入至驱动晶体管的控制极。
示例性地，有源图案层中的各个晶体管的有源层的材料包括非晶硅、多晶硅或者有机半导体材料。第一导电层13中的各个结构(例如包括栅线、发光控制线、复位信号线等)、第二导电层14中的各个结构(例如包括第二电极、初始化信号线等)、以及第三导电层17中的各个结构(例如包括第一导电图案等)均可以具有单层或者多堆叠层结构，单层或者多堆叠层结构的材料包括铝(Al)、银(Ag)、镁(Mg)、钼(Mo)、钛(Ti)和铜(Cu)等金属中的至少一种。在另一些实施例中，该显示面板还可以是LCD面板，此时，驱动背板1可以是阵列基板。显示面板还可以包括与驱动背板1相对设置的对置基板，阵列基板和对置基板之间设置有液晶层。示例性地，阵列基板中的栅线作为第一信号线，参考上述方案设置与其构成信号线对的第二信号线。
另一方面，参见图15，本公开的一些实施例提供一种上述驱动背板1的制备方法，包括：
S101、在衬底11上形成第一导电层13，其中，第一导电层13包括至少一条第一信号线131。
S102、在形成有第一导电层13的衬底11上，形成第一绝缘层12和第二导电层14，其中，第二导电层14位于第一绝缘层12远离第一导电层13的一侧，第二导电层14包括至少一条第二信号线141；
每条第一信号线131与一条第二信号线141组成一个信号线对15；同一信号线对15中，第一信号线131与第二信号线141延伸方向相同，第一信号线131在衬底11上的正投影与第二信号线141在衬底11上的正投影具有第 一重叠区域111，且第二信号线141与第一信号线131耦接。
本公开的一些实施例提供一种上述驱动背板1的制备方法，参见图15，还包括，在衬底11上形成依次设置的第一导电层13、第一绝缘层12、第二导电层14、第二绝缘层和第三导电层17。其中，形成所述第二绝缘层和第三导电层17的步骤包括：
S103、在第二导电层14远离衬底11的一侧形成第二绝缘层16；
S104、在第二绝缘层16远离衬底11的一侧形成第三导电层17，第三导电层17包括至少一个第一导电图案171；
第一绝缘层12具有至少一个第一过孔121；第二绝缘层16具有至少一个第二过孔161；每个第一过孔121和一个第二过孔161组成一个过孔对，同一过孔对中，第一过孔121与第二过孔161连通；第一信号线中由过孔对露出的部分为第一连接部；第二信号线中由过孔对中的第二过孔161露出的部分为第二连接部，第二连接部在衬底11上的正投影与第一重叠区域111具有第二重叠区域；第一导电图案通过第二过孔161与第二连接部接触，并通过过孔对与第一连接部接触。
在本公开的一些实施例中，如图16所示，上述驱动背板1的制备方法，包括：
形成第一绝缘层12、第二导电层14和第二绝缘层16的步骤包括：
S201、在衬底11上形成第一导电薄膜，并将第一导电薄膜图案化形成第一导电层13，其中，第一导电层13包括至少一条第一信号线131。
S202、在形成有第一导电层13的衬底11上，形成第一绝缘薄膜50；
S203、在形成有第一绝缘薄膜50的衬底11上，形成第二导电薄膜，并将第二导电薄膜图案化形成第二导电层14，第二导电层14包括至少一条第二信号线141。
S204、在形成有第二导电层14的衬底11上，形成第二绝缘薄膜51。
其中，第一绝缘薄膜50和第二绝缘薄膜51的材料可以选用氮化硅、氧化硅等。
S205、将第二绝缘薄膜51和第一绝缘薄膜50图案化，形成包含第二过孔161的第二绝缘层16和包含第一过孔121的第一绝缘层12。
示例性地，上述制备方法，在衬底11上形成第一导电层13之前，还可以包括：在衬底11上形成有源图案层40。
S206、在形成有第二绝缘薄膜51的衬底11上，形成第三导电薄膜，并将第三导电薄膜图案化形成第三导电层17，第三导电层17包括至少一个第一 导电图案171。
由上述制备方法中制备得到各层的材料和形状、以及相互之间的位置关系均可以参考上述介绍驱动背板1的实施例，且能够产生相同的技术效果，在此不再赘述。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (20)

  1. 一种驱动背板，包括：
    衬底；
    设置于所述衬底上的第一导电层，所述第一导电层包括至少一条第一信号线；
    设置于所述第一导电层远离所述衬底一侧的第一绝缘层；
    设置于所述第一绝缘层远离所述第一导电层一侧的第二导电层，所述第二导电层包括至少一条第二信号线；
    其中，每条第一信号线与一条第二信号线组成一个信号线对；同一信号线对中，所述第一信号线与所述第二信号线延伸方向相同，所述第一信号线在所述衬底上的正投影与所述第二信号线在所述衬底上的正投影具有第一重叠区域，且所述第二信号线与所述第一信号线耦接。
  2. 根据权利要求1所述的驱动背板，还包括：
    设置于所述第二导电层远离所述衬底一侧的第二绝缘层；
    设置于所述第二绝缘层远离所述衬底一侧的第三导电层，所述第三导电层包括至少一个第一导电图案；
    其中，每个第一导电图案贯穿所述第二绝缘层与所述第二信号线耦接，所述第一导电图案贯穿所述第二绝缘层和所述第一绝缘层与所述第一信号线耦接。
  3. 根据权利要求2所述的驱动背板，还包括：
    所述第一绝缘层具有至少一个第一过孔；所述第二绝缘层具有至少一个第二过孔；每个第一过孔和一个第二过孔组成一个过孔对，同一过孔对中，所述第一过孔与所述第二过孔连通；
    所述第一信号线中由所述过孔对露出的部分为第一连接部；所述第二信号线中由所述过孔对中的第二过孔露出的部分为第二连接部，所述第二连接部在所述衬底上的正投影与所述第一重叠区域具有第二重叠区域；所述第一导电图案通过所述第二过孔与第二连接部接触，并通过所述过孔对与所述第一连接部接触。
  4. 根据权利要求3所述的驱动背板，其中，
    同一过孔对中，所述第一过孔具有相对的第一开口和第二开口，相较于 所述第二开口，所述第一开口远离所述衬底；所述第二过孔具有相对的第三开口和第四开口，相较于所述第四开口，所述第三开口远离所述衬底；
    所述第一开口在所述衬底上的正投影与所述第二连接部在所述衬底上的正投影的组合与所述第四开口在所述衬底上的正投影大致重合。
  5. 根据权利要求3或4所述的驱动背板，其中，
    所述过孔对在所述衬底上的正投影包含于所述信号线对在所述衬底上的正投影的边界内。
  6. 根据权利要求3～5任一项所述的驱动背板，其中，
    同一信号线对中，所述第一信号线通过多个所述过孔对与所述第二信号线耦接，多个所述过孔对沿所述第一信号线的延伸方向排列。
  7. 根据权利要求3～6任一项所述的驱动背板，其中，
    所述第一导电图案在所述衬底上的正投影完全覆盖所述过孔对在所述衬底上的正投影。
  8. 根据权利要求7所述的驱动背板，其中，
    所述第一导电图案在所述衬底上的正投影的边沿与所述过孔对在所述衬底上的正投影的边沿的之间的最小距离大于或等于所述第一信号线的宽度的1/6。
  9. 根据权利要求1～8任一项所述的驱动背板，其中，
    沿所述第一信号线的宽度方向，所述第一重叠区域的宽度与所述第一信号线的宽度的比值为1/3～1/2。
  10. 根据权利要求1～9任一项所述的驱动背板，所述第二导电层还包括：第二导电图案；
    与所述第二导电图案相邻的一个信号线对中，所述第一信号线相较于所述第二信号线更靠近所述第二导电图案。
  11. 根据权利要求10所述的驱动背板，其中，
    所述第二导电层包括至少两个所述第二导电图案，至少两个所述第二导电图案包括：所述驱动背板包含的像素电路中电容器的一个极板和/或初始化信号线。
  12. 根据权利要求1～11任一项所述的驱动背板，其中，所述第一信号线与所述第二信号线的宽度相等。
  13. 根据权利要求1～12任一项所述的驱动背板，还包括：
    与所述第一信号线的两端分别耦接的两个驱动电路。
  14. 根据权利要求1～13任一项所述的驱动背板，其中，
    至少一条所述第一信号线包括：栅线，发光控制信号线和复位信号线中的至少一者。
  15. 根据权利要求1～14任一项所述的驱动背板，还包括：
    有源图案层，所述有源图案层设置于所述第一导电层靠近衬底的一侧；
    所述有源图案层包括至少一个半导体图案和多个导体化图案，其中，每个半导体图案将所述多个导体化图案中的两个导体化图案间隔开。
  16. 根据权利要求2～15任一项所述的驱动背板，在所述驱动背板包括第三导电层的情况下，所述第三导电层还包括：
    数据线和电源电压线，其中，所述数据线和所述电源电压线的延伸方向相同，所述数据线在所述衬底上的正投影与所述电源电压线在所述衬底上的正投影无重叠区域。
  17. 一种显示装置，包括如权利要求1～16任一项所述的驱动背板。
  18. 一种驱动背板的制作方法，包括：
    在所述衬底上形成第一导电层，所述第一导电层包括至少一条第一信号线；
    在形成有所述第一导电层的衬底上，形成第一绝缘层和第二导电层，其中，所述第二导电层位于所述第一绝缘层远离所述第一导电层的一侧，所述第二导电层包括至少一条第二信号线；
    每条第一信号线与一条第二信号线组成一个信号线对；同一信号线对中，所述第一信号线与所述第二信号线延伸方向相同，所述第一信号线在所述衬底上的正投影与所述第二信号线在所述衬底上的正投影具有第一重叠区域，且所述第二信号线与所述第一信号线耦接。
  19. 根据权利要求18所述的驱动背板的制作方法，还包括：
    在所述第二导电层远离所述衬底的一侧形成第二绝缘层；
    在所述第二绝缘层远离所述衬底的一侧形成第三导电层，所述第三导电层包括至少一个第一导电图案；
    所述第一绝缘层具有至少一个第一过孔；所述第二绝缘层具有至少一个第二过孔；每个第一过孔和一个第二过孔组成一个过孔对，同一过孔对中，所述第一过孔与所述第二过孔连通；
    所述第一信号线中由所述过孔对露出的部分为第一连接部；所述第二信号线中由所述过孔对中的第二过孔露出的部分为第二连接部，所述第二连接部在所述衬底上的正投影与所述第一重叠区域具有第二重叠区域；所述第一导电图案通过所述第二过孔与第二连接部接触，并通过所述过孔对与所述第一连接部接触。
  20. 根据权利要求19所述的驱动背板的制作方法，形成所述第一绝缘层、所述第二导电层和所述第二绝缘层的步骤包括：
    在形成有所述第一导电层的衬底上，形成第一绝缘薄膜；
    在形成有所述第一绝缘薄膜的衬底上，形成第二导电层，所述第二导电层包括至少一条所述第二信号线；
    在形成有所述第二导电层的衬底上，形成第二绝缘薄膜；并将所述第二绝缘薄膜和所述第一绝缘薄膜图案化，形成包含所述第二过孔的第二绝缘层和包含所述第一过孔的第一绝缘层。
PCT/CN2020/137722 2020-12-18 2020-12-18 一种驱动背板及其制作方法、显示装置 WO2022126638A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/CN2020/137722 WO2022126638A1 (zh) 2020-12-18 2020-12-18 一种驱动背板及其制作方法、显示装置
CN202080003445.9A CN115176342A (zh) 2020-12-18 2020-12-18 一种驱动背板及其制作方法、显示装置
US17/621,176 US12057455B2 (en) 2020-12-18 2020-12-18 Driving backplane and method of manufacturing the same, and display apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/137722 WO2022126638A1 (zh) 2020-12-18 2020-12-18 一种驱动背板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
WO2022126638A1 true WO2022126638A1 (zh) 2022-06-23

Family

ID=82058894

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/137722 WO2022126638A1 (zh) 2020-12-18 2020-12-18 一种驱动背板及其制作方法、显示装置

Country Status (3)

Country Link
US (1) US12057455B2 (zh)
CN (1) CN115176342A (zh)
WO (1) WO2022126638A1 (zh)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104536610A (zh) * 2014-12-31 2015-04-22 上海天马有机发光显示技术有限公司 一种触控面板、触控显示装置及其制作方法
CN105575961A (zh) * 2016-03-18 2016-05-11 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN106468972A (zh) * 2016-08-31 2017-03-01 京东方科技集团股份有限公司 一种触控基板及其制造方法、触控装置
CN106816457A (zh) * 2016-12-28 2017-06-09 上海天马微电子有限公司 一种触控显示面板及其制作方法、触控显示装置
CN106935600A (zh) * 2017-05-17 2017-07-07 京东方科技集团股份有限公司 一种显示面板和显示装置
CN107026177A (zh) * 2017-03-31 2017-08-08 京东方科技集团股份有限公司 一种coa基板及其制备方法、显示装置
CN110095889A (zh) * 2018-01-30 2019-08-06 瀚宇彩晶股份有限公司 显示面板及其制作方法
CN110187797A (zh) * 2019-05-31 2019-08-30 京东方科技集团股份有限公司 触控显示面板
CN111491441A (zh) * 2020-04-23 2020-08-04 京东方科技集团股份有限公司 电路板结构和显示设备
CN111613648A (zh) * 2019-11-18 2020-09-01 友达光电股份有限公司 显示装置及其制造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104536610A (zh) * 2014-12-31 2015-04-22 上海天马有机发光显示技术有限公司 一种触控面板、触控显示装置及其制作方法
CN105575961A (zh) * 2016-03-18 2016-05-11 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN106468972A (zh) * 2016-08-31 2017-03-01 京东方科技集团股份有限公司 一种触控基板及其制造方法、触控装置
CN106816457A (zh) * 2016-12-28 2017-06-09 上海天马微电子有限公司 一种触控显示面板及其制作方法、触控显示装置
CN107026177A (zh) * 2017-03-31 2017-08-08 京东方科技集团股份有限公司 一种coa基板及其制备方法、显示装置
CN106935600A (zh) * 2017-05-17 2017-07-07 京东方科技集团股份有限公司 一种显示面板和显示装置
CN110095889A (zh) * 2018-01-30 2019-08-06 瀚宇彩晶股份有限公司 显示面板及其制作方法
CN110187797A (zh) * 2019-05-31 2019-08-30 京东方科技集团股份有限公司 触控显示面板
CN111613648A (zh) * 2019-11-18 2020-09-01 友达光电股份有限公司 显示装置及其制造方法
CN111491441A (zh) * 2020-04-23 2020-08-04 京东方科技集团股份有限公司 电路板结构和显示设备

Also Published As

Publication number Publication date
US12057455B2 (en) 2024-08-06
CN115176342A (zh) 2022-10-11
US20220399379A1 (en) 2022-12-15

Similar Documents

Publication Publication Date Title
CN112071882B (zh) 显示基板及其制备方法、显示装置
CN110047898B (zh) 显示基板及其制造方法、显示装置
US20240237432A9 (en) Display substrate, preparation method therefor, and display device
US10916613B1 (en) Array substrate and OLED display device
US20240212597A1 (en) Display Substrate, Preparation Method Thereof, and Display Apparatus
WO2021035545A1 (zh) 显示基板、显示面板及显示基板的制备方法
CN110165058A (zh) 阵列基板及其制备方法、修复方法、显示装置
CN208111487U (zh) 阵列基板及显示装置
CN111834292B (zh) 一种显示基板及其制作方法、显示面板及显示装置
US20220344439A1 (en) Anti-corrosion circuit, array substrate and electronic device
US20240081115A1 (en) Display substrate, manufacturing method thereof, and display device
US12133439B2 (en) Display panel and display device
WO2021207930A9 (zh) 显示基板及显示装置
US20240196689A1 (en) Display panel, display module, and display device
US12004376B2 (en) Display motherboard, preparation method thereof, display substrate and display device
WO2022126638A1 (zh) 一种驱动背板及其制作方法、显示装置
US20240188353A1 (en) Display Substrate and Display Apparatus
US12002817B2 (en) Display substrate, method for manufacturing same, and display device
CN114026693A (zh) 阵列基板及其制备方法、显示装置
WO2022252230A1 (zh) 显示基板和显示装置
CN113594212B (zh) 显示面板及其制备方法、显示装置
US20240276767A1 (en) Display Substrate, Preparing Method Therefor, and Display Apparatus
CN114823716B (zh) 一种驱动背板、显示面板及显示装置
WO2024113102A1 (zh) 显示基板和显示装置
WO2023230963A1 (zh) 显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20965652

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 02/10/2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20965652

Country of ref document: EP

Kind code of ref document: A1