WO2022095695A1

WO2022095695A1 - Mcm encapsulation structure and manufacturing method therefor

Info

Publication number: WO2022095695A1
Application number: PCT/CN2021/124734
Authority: WO
Inventors: 周辉星
Original assignee: 矽磐微电子(重庆)有限公司
Priority date: 2020-11-04
Filing date: 2021-10-19
Publication date: 2022-05-12
Also published as: CN114446918A

Abstract

Provided are an MCM encapsulation structure and a manufacturing method therefor. The encapsulation structure comprises: a first bare chip assembly or a bare chip, a wiring substrate, a plastic encapsulation layer, a first conductive trace, a second conductive trace, a conductive bump, a first dielectric layer and a second dielectric layer. The wiring substrate can transfer a wiring layer that needs to be formed on an active surface of the bare chip into the wiring substrate, the wiring substrate comprises a plurality of complex circuits, and the plurality of complex circuits are electrically connected to a bonding pad on the active surface of the bare chip, so as to be embedded into the encapsulation structure.

Description

MCM package structure and manufacturing method thereof

technical field

The present application relates to the technical field of chip packaging, and in particular, to an MCM packaging structure and a manufacturing method thereof.

Background technique

In the packaging process, bare chips with different functions are often packaged in a package structure to form a multi-chip module (MCM) with a specific function, which has the advantages of small size, high reliability, high performance and Multifunctionality and other advantages.

With the miniaturization and weight reduction of electronic devices, chip packages with compact structure and small volume are favored by more and more markets.

In MCM, the internal circuit structure of the chip is often complicated, and the wiring density in the re-wiring layer is high, and the wiring is difficult due to the small surface area of the chip. In addition, because the wiring is too dense, it is easy to lead to fine wiring and short circuit, which affects the yield of the product. At the same time, the service life of the chip is also low, especially when the multi-layer wiring layer needs to be formed, due to the complexity of the process. The process is difficult to control.

SUMMARY OF THE INVENTION

A first aspect of the present application provides an MCM package structure, including: a first die assembly, at least including: a first die and a second die, the first die includes a plurality of first pads, the first die A pad is located on the active surface of the first die, the second die includes a plurality of second pads, and the second pads are located on the active surface of the second die; the second die The active surface of the first die is covered with a second protective layer, and the second protective layer exposes the second pad; the active surface of the first die is facing away from the active surface of the second die; the wiring substrate, around the first die assembly; the wiring substrate is provided with a wiring line, the wiring line includes a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the wiring substrate, The backside electrical connection point is exposed on the backside of the wiring substrate; a plastic encapsulation layer covers the first die assembly and the wiring substrate, and the backside of the plastic encapsulation layer exposes the second protective layer, the first Two bonding pads and the back side of the wiring substrate, the front side of the plastic encapsulation layer exposes the active surface of the first die and the front side of the wiring substrate; the first conductive trace is located on the first bonding pad, the The front electrical connection point and the front surface of the plastic encapsulation layer are used to electrically connect the first die and the wiring circuit; the second conductive trace is located on the second pad and the back electrical connection point and on the back of the plastic encapsulation layer, for electrically connecting the second die and the wiring lines; conductive bumps, connected to the first conductive traces; a first dielectric layer, burying the first A conductive trace and the conductive bump are exposed outside the first dielectric layer; and a second dielectric layer embeds the second conductive trace.

A second aspect of the present application provides a method for fabricating an MCM package structure, including: providing a carrier board and multiple groups of packages carried on the carrier board, each group of the packages includes: a wiring substrate having a through opening, and a first die assembly located in the through opening; a wiring circuit is arranged in the wiring substrate, the wiring circuit includes a front electrical connection point and a back electrical connection point, and the front electrical connection point is exposed on the wiring substrate the front side of the wiring substrate, the back side electrical connection points are exposed on the back side of the wiring substrate; the first die assembly at least includes: a first die and a second die, the first die includes a number of first pads , the first pad is located on the active surface of the first die, the second die includes a plurality of second pads, and the second pads are located on the active surface of the second die; the The active surface of the second die is covered with a second protective layer; the active surface of the first die is facing away from the active surface of the second die; the front surface of the wiring substrate is opposite to the first die The active surface faces the carrier; a plastic encapsulation layer is formed on the surface of the carrier to embed each group of the packages; the plastic encapsulation layer is thinned until the second protective layer and the wiring substrate are exposed. backside; forming a second opening in the second protective layer to expose the second pad; on the second protective layer, the second pad, the backside electrical connection point and the plastic encapsulation layer A second conductive trace is formed on the backside of the device to electrically connect the second die in the group with the wiring circuit; a second dielectric layer is formed to embed the second conductive trace; the carrier is removed , exposing the active surface of the first die, the front surface of the wiring substrate and the front surface of the plastic packaging layer; forming a first pad on the first pad, the front electrical connection point and the front surface of the plastic packaging layer a conductive trace to electrically connect the first die and the wiring lines in the group; forming conductive bumps on the first conductive traces and burying the first conductive traces and the wiring lines A first dielectric layer of a conductive bump, the conductive bump is exposed outside the first dielectric layer; and a plurality of MCM package structures are formed by cutting, and each of the MCM package structures includes a group of the package components.

A third aspect of the present application provides an MCM package structure, comprising: a bare chip, the bare chip includes a plurality of pads, the bonding pads are located on an active surface of the bare chip; a wiring substrate disposed around the bare chip; The wiring substrate is provided with a wiring line, the wiring line includes a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the wiring substrate, and the back electrical connection point is exposed on the back side of the wiring substrate. the back side of the wiring substrate; a plastic encapsulation layer, covering the bare chip and the wiring substrate, the front side of the plastic encapsulation layer exposing the active surface of the bare chip and the electrical connection point of the front side; conductive traces, located on the solder The disk, the front electrical connection point and the front surface of the plastic encapsulation layer are used to electrically connect the bare chip and the wiring circuit; the conductive bump is connected to the back electrical connection point; the first dielectric layer, The conductive traces are embedded; the second dielectric layer is embedded with the conductive bumps, and the conductive bumps are exposed outside the second dielectric layer.

A fourth aspect of the present application provides a method for fabricating an MCM package structure, including: providing a carrier board and multiple groups of packages carried on the carrier board, each group of the packages includes: a wiring substrate having a through opening, and A bare chip located in the through opening; a wiring circuit is arranged in the wiring substrate, and the wiring circuit includes a front electrical connection point and a back electrical connection point, and the front electrical connection point is exposed on the front side of the wiring substrate, The backside electrical connection point is exposed on the backside of the wiring substrate; the bare chip includes a plurality of pads, and the pads are located on the active surface of the bare chip; the front surface of the wiring substrate is connected to the active surface of the bare chip facing the carrier board; forming a plastic encapsulation layer on the surface of the carrier board to embed each group of the packages; thinning the plastic encapsulation layer until the backside of the wiring substrate is exposed; removing the carrier board to expose the active surface of the bare chip, the front surface of the wiring substrate, and the front surface of the plastic packaging layer; conductive traces are formed on the pads, the front electrical connection points, and the front surface of the plastic packaging layer for electrical connection the die and the wiring lines in the group; forming a first dielectric layer that embeds the conductive traces; forming conductive bumps on the backside electrical connection points and forming a conductive bump that embeds the conductive bumps A second dielectric layer, the conductive bumps are exposed outside the second dielectric layer; and a plurality of MCM package structures are formed by cutting, and each of the MCM package structures includes a group of the package components.

The beneficial effects of this application are:

First, the wiring substrate can transfer the wiring layer that needs to be formed on the active surface of the die into the wiring substrate. The wiring substrate includes complex multiple circuits, which are embedded in the package by electrically connecting with the pads on the active surface of the die. In the structure, the performance of the entire MCM package structure can be improved. Second, the fine wiring in the rewiring layer is transferred to the wiring substrate, which reduces the probability of short circuits, increases product yield, and reduces the number of layers of the first conductive traces and/or the second conductive traces , reduce the complexity of the process. Third, by providing a preformed wiring substrate, the wiring substrate can be tested before packaging, avoiding the use of known poor wiring substrates. Fourth, the wiring substrate is a prefabricated substrate, and its fabrication process is performed independently of the packaging process, which can save the packaging time of the entire packaging process.

In addition, the active surface faces the same or opposite bare chip components, which can realize the effect of small size and compact structure of the MCM package. For the die components with the active surfaces facing away from each other, the wiring substrate can not only realize the electrical connection between the first die and the second die, but also realize the wiring on both sides of the front and back of the plastic encapsulation layer. The wiring on the top can improve the density of wiring and form an MCM package structure with more complex wiring and smaller volume.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will become apparent from the description, drawings and claims.

Description of drawings

1 is a schematic cross-sectional structure diagram of an MCM packaging structure according to a first embodiment of the present application;

Fig. 2 is the flow chart of a kind of manufacture method of the MCM packaging structure in Fig. 1;

3 to 9 are respectively schematic diagrams of intermediate structures corresponding to the process in FIG. 2;

10 is a flowchart of a method for manufacturing an MCM packaging structure according to a second embodiment of the present application;

FIG. 11 and FIG. 12 are schematic diagrams of intermediate structures corresponding to the flow in FIG. 10;

13 is a schematic cross-sectional structure diagram of the MCM package structure according to the third embodiment of the present application;

14 is a schematic cross-sectional structural diagram of the MCM package structure according to the fourth embodiment of the present application;

FIG. 15 is a schematic cross-sectional structural diagram of the MCM package structure according to the fifth embodiment of the present application.

Detailed ways

In order to make the above objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional structure diagram of an MCM package structure according to a first embodiment of the present application.

Referring to FIG. 1, the MCM package structure 1 includes:

The first die assembly 10 at least includes: a first die 11 and a second die 12 , wherein the first die 11 includes a plurality of first pads 111 , and the first pads 111 are located in the active area of the first die 11 . surface 11a, the second die 12 includes a plurality of second pads 121, and the second pads 121 are located on the active surface 12a of the second die 12; the active surface 12a of the second die 12 is covered with a second protective layer 120, the first The two protective layers 120 expose the second pad 121; the active surface 11a of the first die 11 and the active surface 12a of the second die 12 are facing away from each other;

The wiring substrate 13 is arranged around the first die assembly 10 ; the wiring substrate 13 is provided with a wiring circuit 130 , and the wiring circuit 130 includes a front electrical connection point 131 and a back electrical connection point 132 , and the front electrical connection point 131 is exposed on the wiring substrate 13 . The front side 13a, the back side electrical connection points 132 are exposed on the back side 13b of the wiring substrate 13;

The plastic encapsulation layer 14 covers the first die assembly 10 and the wiring substrate 13 , the back surface 14 b of the plastic encapsulation layer 14 exposes the second protective layer 120 , the second pad 121 and the back surface 13 b of the wiring substrate 13 , and the front surface 14 a of the plastic encapsulation layer 14 is exposed The active surface 11a of the first die 11 and the front surface 13a of the wiring substrate 13;

The first conductive trace 15 is located on the first pad 111, the front electrical connection point 131 and the front surface 14a of the plastic sealing layer 14, and is used for electrically connecting the first die 11 and the wiring circuit 130;

The second conductive traces 16 are located on the second pads 121 , the backside electrical connection points 132 and the backside 14b of the plastic encapsulation layer 14 , and are used to electrically connect the second die 12 and the wiring lines 130 ;

The conductive bump 17 is connected to the first conductive trace 15;

a first dielectric layer 18, burying the first conductive traces 15 and the conductive bumps 17, the conductive bumps 17 being exposed outside the first dielectric layer 18; and

The second dielectric layer 19 embeds the second conductive traces 16 .

The first die 11 and the second die 12 may be dies that need to be electrically interconnected, and their respective functions are not limited. In some embodiments, the first die 11 and the second die 12 may be, for example, a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die ( RADIO FREQUEENCE DIE) or the corresponding control chip.

Referring to FIG. 1 , the first die 11 includes an opposite active surface 11 a and a back surface 11 b. The first pad 111 is exposed to the active surface 11a. The first die 11 may contain a variety of devices formed on the semiconductor substrate, and electrical interconnect structures that are electrically connected to the respective devices. The first pads 111 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices. It should be noted that, in this application, "/" means "or".

The second die 12 includes opposing active surfaces 12a and back surfaces 12b. The second pad 121 is exposed to the active surface 12a. The second die 12 may contain various devices formed on the semiconductor substrate, as well as electrical interconnect structures that electrically connect the various devices. The second pads 121 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.

Continuing to refer to FIG. 1 , in this embodiment, the first die assembly 10 is a die stack structure, that is, the first die 11 and the second die 12 are arranged back-to-back. The back-to-back arrangement of the first die 11 and the second die 12 means that the back surface 11 b of the first die 11 and the back surface 12 b of the second die 12 are attached together.

In other embodiments, the first die assembly 10 may include one or more first dies 11 and may also include one or more second dies 12 . The first die 11 and the second die 12 may be arranged in a staggered position, or even arranged side by side. At this time, the front surface 14 a of the plastic encapsulation layer 14 also exposes the back surface 12 b of the second die 12 .

In this embodiment, the area of the first die 11 is larger than that of the second die 12 . In other embodiments, the area of the second die 12 may also be larger than that of the first die 11 .

In this embodiment, the active surface 11 a of the first die 11 is provided with a first protective layer 110 . In other embodiments, the first protective layer 110 may also be omitted from the active surface 11 a of the first die 11 .

The first protective layer 110 and/or the second protective layer 120 are insulating materials, such as organic polymer insulating materials, inorganic insulating materials or composite materials. The organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film or other organic materials with similar insulating properties. The inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride. The composite material is an inorganic-organic composite material, which can be an inorganic-organic polymer composite material, such as a SiO ₂ /resin polymer composite material.

The wiring substrate 13 includes wiring lines 130 and an insulating material layer filled between the wiring lines 130 . Compared with the scheme of making the rewiring layer on the plastic package of the first die 11 and the second die 12, the advantages of using the wiring substrate 13 in this solution are: first, the fine wiring in the rewiring layer is transferred to the wiring substrate 13, which reduces the probability of short circuit, increases product yield, reduces the number of layers of the first conductive traces 15 and/or the second conductive traces 16, and reduces the complexity of the process; second, provides pre-forming The wiring substrate 13 can be tested before packaging to avoid the use of known bad wiring substrates 13; thirdly, the wiring substrate 13 is a prefabricated substrate, and its manufacturing process is independent of the packaging process, which can save the entire packaging process. Packaging time.

In addition, the wiring layers that need to be formed on the

active surfaces

11a, 12a of the die are transferred into the wiring substrate 13, and the wiring substrate 13 includes complex multiple circuits that pass through the pads 111 on the

active surfaces

11a, 12a of the die , 121 are electrically connected and embedded in the package structure 1 , which can improve the performance of the entire package structure 1 .

The wiring substrate 13 may be a single piece provided around the first die assembly 10, or may be a plurality of wiring substrates. When there are multiple wiring substrates, each wiring substrate 13 can be electrically connected to the first die 11 through the first conductive traces 15 and/or can be electrically connected to the second die 12 through the second conductive traces 16 connect.

The wiring substrate 13 may include a front surface 13a and a back surface 13b which are opposed to each other. In this embodiment, the front surface 13 a of the wiring substrate 13 is flush with the first protective layer 110 , and the back surface 13 b of the wiring substrate 13 is flush with the second protective layer 120 . There may be a plurality of front electrical connection points 131 exposed on the front side 13a of the wiring substrate, and a plurality of rear electrical connection points 132 exposed on the back side 13b of the wiring substrate.

The material of the plastic sealing layer 14 can be, for example, epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyterephthalic acid One or more of glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc. The material of the plastic sealing layer 14 can also be various polymers or composite materials of resin and polymer.

The plastic sealing layer 14 includes a front side 14a and a back side 14b opposite to each other. In this embodiment, the front surface 14a of the plastic sealing layer 14 exposes the first protective layer 110 , the first pad 111 and the front surface 13 a of the wiring substrate 13 , and the back surface 14 b of the plastic sealing layer 14 exposes the second protective layer 120 , the second pad 121 and the The back surface 13 b of the wiring board 13 .

In the embodiment shown in FIG. 1 , the first conductive trace 15 includes several metal pattern blocks 15a, that is, the first conductive trace has a layer of metal pattern blocks. A partial number of metal pattern blocks 15a selectively electrically connect the front electrical connection point 131 and the first pad 111 to realize electrical connection between the wiring substrate 13 and the first die 11; a partial number of metal pattern blocks 15a selectively electrically connect the front side The electrical connection points 131 are drawn out through the conductive bumps 17 . In addition, a partial number of metal pattern blocks 15a may be selectively electrically connected to a plurality of front-side electrical connection points 131, so as to realize the circuit layout or electrical conduction of these front-side electrical connection points 131; and a partial number of metal pattern blocks 15a may also be selected The plurality of first pads 111 are electrically connected to realize circuit layout or electrical conduction of these first pads 111 .

The layout of the first conductive traces 15 may be determined according to a predetermined circuit layout.

In some embodiments, the number of layers of the first conductive traces 15 may further include two or more layers, that is, metal pattern blocks having two or more layers.

In the embodiment shown in FIG. 1 , the second conductive trace 16 includes a plurality of metal pattern blocks 16a, that is, the second conductive trace has a layer of metal pattern blocks. Part of the metal pattern blocks 16 a selectively electrically connect the back surface electrical connection points 132 and the second pads 121 , so as to realize the electrical connection between the wiring substrate 13 and the second die 12 . In addition, a partial number of metal pattern blocks 16a may be selectively electrically connected to a plurality of backside electrical connection points 132, so as to realize the circuit layout or electrical conduction of these backside electrical connection points 132; there may also be a partial number of metal pattern blocks 16a selected The plurality of second pads 121 are electrically connected to realize circuit layout or electrical conduction of these second pads 121 .

The layout of the second conductive traces 16 may be determined according to a predetermined circuit layout.

In some embodiments, the number of layers of the second conductive traces 16 may further include two or more layers, that is, metal pattern blocks having two or more layers.

Referring to FIG. 1 , in this embodiment, the conductive bumps 17 on the first conductive traces 15 serve as external connection terminals of the MCM package structure 1 .

In some embodiments, the conductive bumps 17 may also have an anti-oxidation layer.

The anti-oxidation layer may include: b1) a tin layer, or b2) a bottom-up stack of nickel layers and gold layers, or b3) a bottom-up stack of nickel layers, palladium layers, and gold layers. The material of the conductive bumps 17 can be copper, and the above-mentioned anti-oxidation layer can prevent the oxidation of copper, thereby preventing the deterioration of electrical connection performance caused by the oxidation of copper.

In some embodiments, the conductive bumps 17 may also have solder balls for flipping the MCM package structure 1 .

The materials of the first dielectric layer 18 and the second dielectric layer 19 can be, for example, organic high molecular polymer insulating materials, inorganic insulating materials or composite materials. The organic polymer insulating material is, for example, one or more of polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film or other organic materials with similar insulating properties. kind. The composite material is, for example, an inorganic-organic composite material, and can also be an inorganic-organic polymer composite material, such as a SiO ₂ /resin polymer composite material. The inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride. Compared with the inorganic insulating material, the tensile stress of the organic polymer insulating material and the composite material is smaller, which can prevent the surface of the MCM package structure 1 from warping.

In the MCM package structure 1 , on the one hand, the active surfaces face the opposite first die components 10 to achieve the effect of small size and compact structure of the MCM package structure 1 . On the other hand, the wiring substrate 13 not only realizes the electrical connection between the first die 11 and the second die 12, but also realizes the wiring on both sides of the front side 14a and the back side 14b of the plastic encapsulation layer 14. The wiring can improve the density of wiring, and form an MCM package structure 1 with more complex wiring and smaller volume.

An embodiment of the present application provides a manufacturing method of the MCM package structure 1 in FIG. 1 . FIG. 2 is a flow chart of the production method. 3 to 9 are schematic diagrams of intermediate structures corresponding to the process in FIG. 2 .

First, referring to step S1 in FIG. 2 , FIG. 3 and FIG. 4 , a carrier board 2 and a plurality of groups of packages 3 carried on the carrier board 2 are provided, each group of packages 3 includes: a wiring substrate 13 having a through opening 133 , and the first die assembly 10 located in the through opening 133; the wiring substrate 13 is provided with a wiring circuit 130, the wiring circuit 130 includes a front electrical connection point 131 and a back electrical connection point 132, and the front electrical connection point 131 is exposed on the wiring substrate The front side 13a of 13, the backside electrical connection points 132 are exposed on the backside 13b of the wiring substrate 13; the first die assembly 10 at least includes: a first die 11 and a second die 12, the first die 11 includes a number of first solder joints. The disk 111, the first pad 111 is located on the active surface 11a of the first die 11, the second die 12 includes a plurality of second pads 121, and the second pads 121 are located on the active surface 12a of the second die 12; The active surface 12a of the die 12 is covered with the second protective layer 120 ; the active surface 11a of the first die 11 and the active surface 12a of the second die 12 are facing away from each other; the front surface 13a of the wiring substrate 13 is opposite to the first die 11 The active surface 11a faces the carrier plate 2 . 3 is a top view of the carrier board and the multiple groups of packages; FIG. 4 is a cross-sectional view along the line AA in FIG. 3 .

The first die 11 and the second die 12 may be dies that need to be electrically interconnected, and their respective functions are not limited. In some embodiments, the first die 11 and the second die 12 may be, for example, a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO). FREQUEENCE DIE) or the corresponding control chip.

Referring to FIG. 4 , the first die 11 includes an opposite active surface 11 a and a back surface 11 b. The first die 11 may contain a variety of devices formed on the semiconductor substrate, and electrical interconnect structures that are electrically connected to the respective devices. The first pads 111 exposed to the active surface 11a of the first die 11 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.

The second die 12 includes opposing active surfaces 12a and back surfaces 12b. The second pad 121 is exposed to the active surface 12a. The second die 12 may also contain various devices formed on the semiconductor substrate, as well as electrical interconnect structures that electrically connect the various devices. The second pads 121 exposed to the active surface 12a of the second die 12 are connected to the electrical interconnection structure for inputting/outputting electrical signals of the respective devices.

Continuing to refer to FIG. 4 , in this embodiment, the first die assembly 10 is a die stack structure, that is, the first die 11 and the second die 12 are arranged back-to-back. In other embodiments, the first die assembly 10 may include one or more first dies 11 , and may also include one or more second dies 12 . The first bare chip 11 and the second bare chip 12 may be arranged in a staggered position, or even arranged side by side, and at this time, the front side of the plastic encapsulation layer also exposes the back side of the second bare chip.

The second protective layer 120 covers the second pads 121 to protect the second pads 121 when the plastic encapsulation layer 14 is thinned.

In this embodiment, the active surface 11 a of the first die 11 may also be provided with a first protective layer 110 , so as to play a role of stress buffering for the first pad 111 when the plastic sealing layer 14 is thinned. In some embodiments, the active surface 11 a of the first die 11 may also omit the first protective layer 110 .

Both the first die 11 and the second die 12 are formed by dicing wafers. Taking the first bare chip 11 as an example, the wafer includes a wafer active surface and a wafer back surface, and the wafer active surface exposes the first pads 111 and an insulating layer (not shown) protecting the first pads 111 . After the wafer is cut, a first die 11 is formed. Accordingly, the first die 11 includes an active surface 11a and a back surface 11b, and the insulating layer between the first pad 111 and the adjacent first pad 111 is exposed to the active surface 11a .

A first protective layer 110 is applied on the active surface 11 a of the first die 11 , and the application process of the first protective layer 110 may be as follows: before the wafer is cut into the first die 11 , the first protective layer is applied on the active surface of the wafer layer 110, cutting the wafer with the first protective layer 110 to form the first die 11 with the first protective layer 110; the application process of the first protective layer 110 can also be: cutting the wafer into the first die 11 After that, a first protective layer 110 is applied on the active surface 11 a of the first die 11 .

The first protective layer 110 and/or the second protective layer 120 are insulating materials, such as organic polymer insulating materials, or inorganic insulating materials. The organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties, etc. .

The organic high molecular polymer insulating material can be laminated on the first pad 111 and the insulating layer between the adjacent first pads 111 through a) lamination process/the second pad 121 and the adjacent second pad 121 On the insulating layer between, or b) firstly coated or printed on the insulating layer between the first pad 111 and the adjacent first pad 111 / the second pad 121 and the adjacent second pad 121 On the insulating layer between the first pads 111 and the insulating layer between the adjacent first pads 111, post-curing, or c) curing on the insulating layer between the first pads 111 and the adjacent first pads 111/the second pads 121 and the adjacent second pads 121 by an injection molding process on the insulating layer in between.

When the material of the first protective layer 110 and/or the second protective layer 120 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed between the first pad 111 and the adjacent first pads 111 through a deposition process. On the insulating layer/on the insulating layer between the second pads 121 and the adjacent second pads 121 .

The number of layers of the first protective layer 110 and/or the second protective layer 120 may include one or more layers.

The wafer may be thinned from the backside before dicing to reduce the thickness of the first die 11 and/or the second die 12 .

The wiring board 13 includes wiring lines 130 and an insulating material filled between the wiring lines 130 .

The wiring substrate 13 may be a single piece provided around the first die assembly 10, or may be a plurality of wiring substrates.

In this embodiment, as shown in FIG. 3 , the wiring substrates 13 of each group of packages 3 are separated. In some embodiments, the wiring substrates 13 of each group of packages 3 may also be connected together.

The carrier plate 2 is a rigid plate, which may include a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.

In some embodiments, the thickness of the wiring substrate 13 is smaller than the thickness of the die stack structure. When multiple groups of packages 3 are arranged on the surface of the carrier board 2, one solution may include:

a) The front surfaces 13a of the plurality of wiring substrates 13 face the carrier board 2, and the plurality of wiring substrates 13 are firstly arranged on the carrier board 2; A plurality of wiring substrates 13 are placed on the adhesive layer;

b) The first protective layer 110 on the plurality of first dies 11 faces the first carrier, and the plurality of first dies 11 are arranged on the first carrier, and the second dies 12 on the plurality of second dies 12 are arranged on the first carrier. The protective layer 120 faces the second carrier board, and the plurality of second dies 12 are arranged on the second carrier board. Specifically, a whole surface of the adhesive layer can be coated on the surfaces of the first carrier board and the second carrier board An adhesive layer is provided on the backside 11b of the plurality of first bare chips 11 and/or the backside 12b of the plurality of second bare chips 12, the first carrier plate and the second carrier plate are aligned, and the backside of the first bare chip 11 11b and the backside 12b of the second die 12 are bonded together to form a die stack structure; the first carrier is removed;

c) The stacked die structure faces the through opening 133 of the wiring substrate 13 , the second carrier is aligned with the carrier 2 , and the stacked die structure is fixed to the carrier 2 at the bottom of the through opening 133 ; the second carrier is removed.

Step a) and step b) are in no particular order, and may also be performed simultaneously. The first carrier board and the second carrier board are different from the carrier board 2 .

The adhesive layer on the surface of each carrier board can be made of an easily peelable material, so that the corresponding carrier board can be peeled off. For example, a thermal separation material that can be made to lose its viscosity by heating, a UV separation material that can be made to lose its viscosity by ultraviolet irradiation, or the like can be used.

In another solution, step a) is performed first; then step b) is performed, wherein the first protective layers 110 on the plurality of first bare chips 11 face the through openings 133 of the wiring substrate 13 , and the plurality of first bare chips 11 First, it is fixed on the carrier board 2 ; after that, the second carrier board on which a plurality of second dies 12 are arranged is aligned with the carrier board 2 , and the back surface 11 b of the first die 11 and the back surface 12 b of the second die 12 are glued together. connected together to form a die stack structure; the second carrier carrying the plurality of second dies 12 is removed.

In another solution, the first protective layers 110 on the plurality of first dies 11 face the carrier board 2 , and the plurality of first dies 11 are firstly arranged on the carrier board 2 ; The front side 13a faces the carrier board 2, the through openings 133 of each wiring substrate 13 are aligned with one first die 11, and the plurality of wiring boards 13 are arranged on the carrier board 2; after that, a plurality of second die are arranged The second carrier of 12 is aligned with the carrier 2, and the backside 11b of the first die 11 and the backside 12b of the second die 12 are bonded together to form a die stack structure; 12 of the second carrier board.

In some embodiments, the thickness of the wiring substrate 13 is greater than the thickness of the die stack structure. When multiple sets of packages 3 are disposed on the surface of the carrier board 2, a solution may include: firstly performing the above-mentioned steps a) and b), and then performing the step c), the through openings 133 of the wiring substrate 13 face the die stack structure , the second carrier board is combined with the carrier board 2 , and the wiring substrate 13 is fixed on the second carrier board; the carrier board 2 is removed.

A group of packages 3 is located in an area on the surface of the carrier board 2, which is convenient for subsequent cutting. Multiple groups of packages 3 are fixed on the surface of the carrier board 2 to manufacture multiple MCM package structures 1 at the same time, which is beneficial to mass production and reduces costs.

Next, referring to step S2 in FIG. 2 and as shown in FIG. 5 , a plastic encapsulation layer 14 is formed on the surface of the carrier board 2 to embed the packages 3 ; as shown in FIG. 6 , the plastic encapsulation layer 14 is thinned until the second layer is exposed. The protective layer 120 and the back surface 13 b of the wiring board 13 .

The material of the plastic sealing layer 14 can be, for example, epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyterephthalic acid One or more of glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, and the like. The material of the plastic sealing layer 14 can also be various polymers or composite materials of resin and polymer. Correspondingly, the encapsulation may be performed by filling a liquid molding compound between each of the first die assemblies 10 and each of the wiring substrates 13 , and then curing at a high temperature by a molding mold. In some embodiments, the plastic encapsulation layer 14 can also be formed by means of plastic material forming such as thermocompression forming and transfer forming.

The molding layer 14 may include opposite front surfaces 14a and back surfaces 14b.

Referring to FIG. 6 , the thinning of the plastic encapsulation layer 14 is performed from the back surface 14b, and mechanical grinding, such as grinding with a grinding wheel, may be used.

Specifically, when the plastic sealing layer 14 is thinned, when the thickness of the wiring substrate 13 is smaller than the thickness of the first die assembly 10, and the back surface 13b of the wiring substrate 13 is exposed, the second protective layer 120 has been partially removed; when the wiring substrate 13 is exposed When the thickness of 13 is greater than the thickness of the first die assembly 10, when the second protective layer 120 is exposed, the back surface 13b of the wiring substrate 13 has been removed by a part of the thickness.

During the process of forming the plastic encapsulation layer 14 and grinding the plastic encapsulation layer 14, the second protective layer 120 can prevent the electrical interconnection structures and devices in the second pad 121, the second die 12 and the first die 11 from being damaged; A protective layer 110 can perform stress buffering on the first pad 111 .

In this step, the plastic encapsulation bodies of each group of packages 3 are formed.

Next, referring to step S3 in FIG. 2 and as shown in FIG. 7 , a second opening 120 a is formed in the second protective layer 120 to expose the second pad 121 ; The second conductive traces 16 are formed on the backside electrical connection points 132 and the backside 14b of the plastic encapsulation layer 14 to electrically connect the second die 12 and the wiring lines 130 in the group; Electrical layer 19 .

In this embodiment, the number of layers of the second conductive traces 16 includes one layer. For each of the plurality of packages 3, forming the second conductive traces 16 includes the following steps S31-S38.

Step S31 : forming a photoresist layer on the second protective layer 120 of the second die 12 , the back surface 13 b of the wiring substrate 13 and the back surface 14 b of the plastic sealing layer 14 .

In step S31, in an optional solution, the formed photoresist layer may be, for example, a photosensitive film. The photosensitive film can be peeled off from the tape and attached to the second protective layer 120 of the second die 12 , the back surface 13 b of the wiring substrate 13 and the back surface 14 b of the plastic sealing layer 14 . In other alternatives, the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.

Step S32 : exposing and developing the photoresist layer to form a patterned photoresist layer.

The photoresist layer is patterned in step S32. In other alternatives, other easily removable sacrificial materials can also be used in place of the photoresist layer.

Step S33 : using the patterned photoresist layer as a mask, dry etching or wet etching the second protective layer 120 to form a plurality of second openings 120 a to expose partial regions of the second pads 121 . A second opening 120a may expose a partial area of a second pad 121 . In other embodiments, one second opening 120a may also expose partial regions of two or more second pads 121 .

The material of the second protective layer 120 may be a laser-reactive material, such as epoxy resin, etc., and the second opening 120a may be formed by denaturing it by laser irradiation. The material of the second protective layer 120 may be a photosensitive material, such as polyimide, etc., and the second opening 120a may be formed by first exposing and then developing. The material of the second protective layer 120 may also be a dry-etchable or wet-etchable material, such as silicon dioxide, silicon nitride, etc., and the second opening 120a may be formed by dry-etching or wet-etching.

Step S34: ashing to remove the remaining photoresist layer.

Step S35 : forming a photoresist layer on the second protective layer 120 of the second die 12 , the second pads 121 exposed by the second protective layer 120 , the back surface 13 b of the wiring substrate 13 and the back surface 14 b of the plastic sealing layer 14 .

For the formation method of the photoresist layer, reference may be made to the formation method of the photoresist layer in step S31.

Step S36 : exposing and developing the photoresist layer, retaining the photoresist layer in the first predetermined area, which is complementary to the area where the metal pattern blocks 16 a of the second conductive traces 16 to be formed are located.

Step S37 : filling a metal layer in a complementary region of the first predetermined region to form the metal pattern block 16 a of the second conductive trace 16 .

A partial number of the metal pattern blocks 16 a are positioned so as to electrically connect the back surface electrical connection points 132 and the second pads 121 to realize the electrical connection of the wiring substrate 13 and the second die 12 . A partial number of metal pattern blocks 16a are positioned so that a plurality of backside electrical connection points 132 can be electrically connected to achieve circuit layout or electrical continuity of these backside electrical connection points 132 . In addition, there may also be a partial number of metal pattern blocks 16a positioned so that a plurality of second pads 121 can be electrically connected to achieve circuit layout or electrical continuity of these second pads 121 .

Step S37 may be completed by an electroplating process. The process of electroplating copper or aluminum is relatively mature.

Specifically, before the photoresist layer is formed in step S35, the second protective layer 120 of the second die 12 and the second pad exposed by the second protective layer 120 may be formed by physical vapor deposition or chemical vapor deposition. 121 . A seed layer is formed on the back surface 13 b of the wiring substrate 13 and the back surface 14 b of the plastic sealing layer 14 . The seed layer can be used as a power supply layer for electroplating copper or aluminum.

Electroplating may include electrolytic plating or electroless plating. Electrolytic plating is to use the part to be plated as a cathode, and electrolyze the electrolyte to form a layer of metal on the part to be plated. Electroless plating is a method of reducing and precipitation of metal ions in a solution to form a metal layer on the part to be plated. In some embodiments, the metal pattern block 16a may also be formed by a method of sputtering first and then etching.

Step S38 : removing the photoresist layer in the first predetermined area by ashing.

After the ashing, the seed layer in the first predetermined region is removed by dry etching or wet etching.

The metal pattern blocks 16a of the second conductive traces 16 may be flattened on the upper surface by a polishing process, such as chemical mechanical polishing.

It should be noted that the metal pattern blocks 16a of the second conductive traces 16 in this step S3 are arranged according to design requirements, and the distribution of the second conductive traces 16 in different packages 3 may be the same or different.

In addition, in some embodiments, the number of layers of the second conductive traces 16 may also be two or more layers, that is, there are two or more metal pattern layers.

In the step of forming the second dielectric layer 19 , in order to prevent the plastic encapsulation layer 14 from being scratched during the process, the second dielectric layer 19 may also be formed on the back surface 14 b of the plastic encapsulation layer 14 .

The second dielectric layer 19 is an insulating material, such as an organic polymer insulating material, or an inorganic insulating material. The organic polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties, etc. .

The organic high molecular polymer insulating material can be laminated on the second conductive traces 16 and the second protective layer 120 not covering the second conductive traces 16, the back surface 13b of the wiring substrate 13 and the plastic sealing layer 14 through a) lamination process. On the back surface 14b, or b) firstly coated on the second conductive traces 16 and the second protective layer 120 not covering the second conductive traces 16, the back surface 13b of the wiring substrate 13 and the back surface 14b of the plastic sealing layer 14, and then cured , or c) cured on the second conductive traces 16 and the second protective layer 120 not covered with the second conductive traces 16 , the backside 13b of the wiring substrate 13 and the backside 14b of the plastic encapsulation layer 14 by an injection molding process.

When the material of the second dielectric layer 19 is an inorganic insulating material such as silicon dioxide or silicon nitride, the second protective layer 120 can be formed on the second conductive traces 16 by a deposition process without covering the second conductive traces 16 , on the backside 13b of the wiring substrate 13 and the backside 14b of the plastic encapsulation layer 14 .

Compared with the inorganic insulating material, the tensile stress of the organic high molecular polymer insulating material is smaller, which can prevent the plastic package from warping when the second dielectric layer 19 is formed in a large area.

The number of layers of the second dielectric layer 19 may be one or more layers.

After that, referring to step S4 in FIG. 2 and as shown in FIG. 8 , the carrier board 2 is removed to expose the active surface 11 a of the first die 11 , the front surface 13 a of the wiring substrate 13 and the front surface 14 a of the plastic encapsulation layer 14 ; 111. The front electrical connection points 131 and the first conductive traces 15 are formed on the front surface 14a of the plastic encapsulation layer 14 to electrically connect the first die 11 and the wiring lines 130 in the group.

Referring to FIG. 8 , after removing the carrier plate 2 , the first support plate 4 may be disposed on the second dielectric layer 19 .

The removal method of the carrier plate 2 may be, for example, a removal method such as laser lift-off and UV irradiation.

The first support plate 4 may be formed in the subsequent processes of forming the first conductive traces 15 , and/or forming the conductive bumps 17 , and/or forming the first dielectric layer 18 , and may play a supporting role.

The first support plate 4 is a hard plate, which may include a glass plate, a ceramic plate, a metal plate, and the like.

In this embodiment, since the active surface 11 a of the exposed first die 11 is provided with the first protective layer 110 , the first protective layer 110 is exposed after the carrier 2 is removed. Before fabricating the first conductive traces 15 , first openings 110 a are formed in the first protective layer 110 to expose the first pads 111 .

The material of the first protective layer 110 can be a laser-reactive material, such as epoxy resin, etc., and the first opening 110a can be formed by denaturing it by laser irradiation. The material of the first protective layer 110 may be a photosensitive material, such as polyimide, and the first opening 110a may be formed by exposing first and then developing. The material of the first protective layer 110 may also be a material capable of dry etching or wet etching, such as silicon dioxide, silicon nitride, etc., and the first opening 110a may be formed by dry etching or wet etching.

In some embodiments, in each group of packages 3 in step S1 , the first protective layer 110 of the first die assembly 10 may also have first openings 110 a exposing the first pads 111 .

The formation method of the metal pattern blocks 15a in the first conductive traces 15 may refer to the formation method of the metal pattern blocks 16a in the second conductive traces 16 . The layout of the first conductive traces 15 may be determined according to a predetermined layout.

In this embodiment, the number of layers of the first conductive traces 15 includes one layer.

A partial number of metal pattern blocks 15a selectively electrically connect the front electrical connection point 131 and the first pad 111 to realize electrical connection between the wiring substrate 13 and the first die 11; a partial number of metal pattern blocks 15a selectively electrically connect the front side Electrical connection points 131 , so as to lead these front electrical connection points 131 out through the conductive bumps 17 . In addition, a partial number of metal pattern blocks 15a may be selectively electrically connected to a plurality of front-side electrical connection points 131, so as to realize the circuit layout or electrical conduction of these front-side electrical connection points 131; and a partial number of metal pattern blocks 15a may also be selected The plurality of first pads 111 are electrically connected to realize circuit layout or electrical conduction of these first pads 111 .

In other embodiments, the first conductive traces 15 may include two or more layers of metal pattern blocks.

Next, referring to step S5 in FIG. 2 and as shown in FIG. 8 , conductive bumps 17 are formed on the first conductive traces 15 and a first dielectric layer 18 that embeds the first conductive traces 15 and the conductive bumps 17 is formed , the conductive bumps 17 are exposed outside the first dielectric layer 18 .

This step S5 may include steps S51-S55.

Step S51 : forming a photoresist layer on the metal pattern block 15 a , the insulating material layer exposed on the front surface 13 a of the wiring substrate 13 and the front surface 14 a of the plastic sealing layer 14 .

In step S51, in an optional solution, the formed photoresist layer may be, for example, a photosensitive film. The photosensitive film can be peeled off from the tape and attached to the metal pattern block 15a, the exposed insulating material layer on the front surface 13a of the wiring substrate 13, and the front surface 14a of the plastic sealing layer 14. In other alternatives, the photoresist layer can also be formed by first coating a liquid photoresist and then heating and curing.

Step S52 : exposing and developing the photoresist layer, and retaining the photoresist in the second predetermined area. The second predetermined area is complementary to the area where the conductive bumps 17 are to be formed.

The photoresist layer is patterned in step S52. In other alternatives, other easily removable sacrificial materials can also be used in place of the photoresist layer.

Step S53 : filling a metal layer in the complementary region of the second predetermined region to form the conductive bump 17 .

Step S53 may be completed by an electroplating process. The process of electroplating copper or aluminum is relatively mature. Before electroplating copper or aluminum, a seed layer (Seed Layer) can also be used as a power supply layer by physical vapor deposition or chemical vapor deposition.

Step S54 : removing the photoresist layer in the second predetermined region by ashing.

The upper surface of the conductive bumps 17 can be flattened by a polishing process, such as chemical mechanical polishing.

Step S55: Referring to FIG. 8, forming a first dielectric layer 18 on the conductive bumps 17, the metal pattern blocks 15a, the insulating material layer exposed on the front surface 13a of the wiring substrate 13, and the front surface 14a of the plastic sealing layer 14; thinning the first dielectric layer 18 until the conductive bumps 17 are exposed.

For the material and formation method of the first dielectric layer 18 , reference may be made to the material and formation method of the second dielectric layer 19 .

In the step of forming the first dielectric layer 18 , the first dielectric layer 18 may also be formed on the front surface 14 a of the plastic sealing layer 14 between the adjacent package components 3 in order to prevent the plastic sealing layer 14 from being scratched during the process.

When the first dielectric layer 18 wraps the conductive bumps 17, the first dielectric layer 18 is polished until the conductive bumps 17 are exposed.

The number of layers of the first dielectric layer 18 may include one or more layers.

After the conductive bumps 17 are fabricated, in option a), as shown in FIG. 8 , the conductive bumps 17 serve as external connections of the MCM package structure 1 .

In option b), after the conductive bumps 17 are exposed, an anti-oxidation layer is also formed on the conductive bumps 17 .

For example, the anti-oxidation layer may include: b1) a tin layer, or b2) a nickel layer and a gold layer stacked from bottom to top, or b3) a nickel layer, a palladium layer, and a gold layer stacked from bottom to top. The anti-oxidation layer can be formed by an electroplating process. The material of the conductive bumps 17 can be copper, and the above-mentioned anti-oxidation layer can prevent the oxidation of copper, thereby preventing the deterioration of electrical connection performance caused by the oxidation of copper.

In option c), after the conductive bumps 17 are exposed, solder balls are also formed on the conductive bumps 17 for flipping the MCM package structure 1 (see FIG. 1 ).

After the conductive bumps 17 are formed, as shown in FIG. 9 , the first support plate 4 is removed.

The removal method of the first support plate 4 may be, for example, a removal method such as laser lift-off and UV irradiation.

After that, referring to step S6 in FIG. 2 , as shown in FIG. 9 and FIG. 1 , a plurality of MCM package structures 1 are formed by cutting, and each MCM package structure 1 includes a set of packages 3 .

For the embodiment in which the wiring substrates 13 of each set of packages 3 are connected together, the wiring substrates 13 are cut apart in the cutting process of step S6.

In the MCM package structure 1 formed through the above steps, on the one hand, the first die components 10 whose active surfaces face opposite to each other realize the effect of small size and compact structure of the MCM package structure 1 . On the other hand, the wiring substrate 13 not only realizes the electrical connection between the first die 11 and the second die 12, but also realizes the wiring on both sides of the front side 14a and the back side 14b of the plastic encapsulation layer 14. The wiring can improve the density of wiring, and form an MCM package structure 1 with more complex wiring and smaller volume.

The advantages of using the wiring substrate 13 are: first, the fine wiring in the rewiring layer is transferred to the wiring substrate 13, which reduces the probability of short circuit, increases the product yield, and reduces the number of the first conductive traces 15 and 15. /or the number of layers of the second conductive traces 16 to reduce the complexity of the process; secondly, to provide a pre-formed wiring substrate 13, the wiring substrate 13 can be tested before packaging, avoiding the use of known bad wiring substrates 13; thirdly , the wiring substrate 13 is a prefabricated substrate, and its fabrication process is performed independently of the packaging process, which can save the packaging time of the entire packaging process.

In addition, the wiring layers that need to be formed on the

active surfaces

11a, 12a are transferred into the wiring substrate 13, and the wiring substrate 13 may include complex multi-circuits that are electrically connected to the pads 111, 121 on the

active surfaces

11a, 12a. Connected and embedded in the package structure 1 can improve the performance of the entire MCM package structure 1 .

The second embodiment of the present application provides another fabrication method of the MCM package structure 1 in FIG. 1 . FIG. 10 is a flowchart of a production method. FIG. 11 and FIG. 12 are schematic diagrams of intermediate structures corresponding to the flow in FIG. 10 .

Referring to FIGS. 10 to 12 , the manufacturing method of this embodiment is substantially the same as the manufacturing method of the embodiment shown in FIG. 2 , and the only difference is:

Step S2 ′, referring to FIG. 5 , forming a plastic encapsulation layer 14 on the surface of the carrier board 2 to embed the packages 3 of each group;

Step S3 ′, as shown in FIG. 11 , remove the carrier plate 2 to expose the active surface 11 a of the first die 11 , the front surface 13 a of the wiring substrate 13 and the front surface 14 a of the plastic encapsulation layer 14 ; the first pad 111 and the front surface are electrically connected The first conductive traces 15 are formed on the dots 131 and the front surface 14a of the plastic encapsulation layer 14 to electrically connect the first die 11 and the wiring lines 130 in the group;

Step S4 ′, continuing to refer to FIG. 11 , forming conductive bumps 17 on the first conductive traces 15 and forming a first dielectric layer 18 burying the first conductive traces 15 and the conductive bumps 17 , the conductive bumps 17 is exposed outside the first dielectric layer 18;

Step S5 ′, referring to FIG. 12 , the plastic sealing layer 14 is thinned until the second protective layer 120 and the back surface 13 b of the wiring substrate 13 are exposed; a second opening 120 a is formed in the second protective layer 120 to expose the second pads 121; second conductive traces 16 are formed on the second protective layer 120, the second pads 121, the backside electrical connection points 132 and the backside 14b of the plastic encapsulation layer 14 to electrically connect the second die 12 in the group with the wiring lines 130 ; forming the second dielectric layer 19 burying the second conductive traces 16 .

For step S2', refer to step S2 of the previous embodiment for forming a plastic encapsulation layer, for step S3', refer to step S4 of the previous embodiment, for step S4', refer to step S5 of the previous embodiment, and for step S5', refer to the step S5 of the previous embodiment. The thinning of the plastic sealing layer in step S2 and S3.

Specifically, in step S3 ′, referring to FIG. 11 and FIG. 12 , after removing the carrier plate 2 , a first support plate 4 can be provided on the back 14 b of the plastic sealing layer 14 ; after the step S4 ′, the first support plate is removed. 4. Disposing the second support plate 5 on the conductive bumps 17 and the first dielectric layer 18 ; and removing the second support plate 5 after step S5 ′.

In other words, the carrier board 2 is first removed to form the first conductive traces 15 , the conductive bumps 17 and the first dielectric layer 18 burying the first conductive traces 15 and the conductive bumps 17 ; The second support plate 5 is disposed on the

conductive bumps

18 and 17 , the plastic sealing layer 14 is thinned, and the second conductive traces 16 and the second dielectric layer 19 are formed.

In some embodiments, the thinning of the plastic encapsulation layer 14 may also be performed in step S2'.

FIG. 13 is a schematic cross-sectional structural diagram of the MCM package structure according to the third embodiment of the present application. Referring to FIG. 13 , the MCM package structure 6 in this embodiment is substantially the same as the MCM package structure 1 in the previous embodiment, and the only difference is that the first protective layer 110 is omitted, the active surface 11 a of the first die 11 , the wiring substrate The front side 13a of 13 and the front side 14a of the plastic encapsulation layer 14 are provided with a third dielectric layer 20; the third dielectric layer 20 has a third opening 20a exposing the first pad 111 and the front side electrical connection point 131; the first conductive trace 15 is located on the first pad 111 , the front electrical connection point 131 and the third dielectric layer 20 .

Correspondingly, with regard to the manufacturing method, the difference from the previous two embodiments is that: in step S4/S3 ′, the carrier plate 2 is removed to expose the active surface 11 a of the first die 11 , the front surface 13 a of the wiring substrate 13 and the plastic encapsulation layer 14 . After the front surface 14a of the exposed first die 11, the third dielectric layer 20 is formed on the exposed active surface 11a of the first die 11, the front surface 13a of the wiring substrate 13, and the front surface 14a of the plastic sealing layer 14; a third opening 20a, the third opening 20a exposes the first pad 111 and the front-side electrical connection point 131; then a first conductive trace is formed on the first pad 111, the front-side electrical connection point 131 and the third dielectric layer 20 15.

The material of the third dielectric layer 20 refers to the materials of the first dielectric layer 18 and the second dielectric layer 19 .

The material of the third dielectric layer 20 can be a laser-reactive material, such as epoxy resin, etc., and the third opening 20a can be formed by denaturing it by laser irradiation. The material of the third dielectric layer 20 may be a photosensitive material, such as polyimide, etc., and the third opening 20a may be formed by exposing first and then developing. The material of the third dielectric layer 20 can also be a material that can be dry-etched or wet-etched, such as silicon dioxide, silicon nitride, etc. The third opening 20a can be formed by dry-etching or wet-etching .

FIG. 14 is a schematic cross-sectional structural diagram of the MCM package structure according to the fourth embodiment of the present application. Referring to FIG. 14 , the MCM package structure 7 in this embodiment is substantially the same as the

MCM package structures

1 and 6 of the previous embodiment, the only difference being that the conductive bumps 17 are connected to the second conductive traces 16 ; correspondingly, the first The two dielectric layers 19 embed the second conductive traces 16 and the conductive bumps 17 , the conductive bumps 17 are exposed outside the second dielectric layer 19 , and the first dielectric layer 18 embeds the first conductive traces 15 .

Correspondingly, with regard to the manufacturing method, the difference from the foregoing three embodiments is: in step S3/S5 ′, after the second conductive traces 16 are formed, the conductive bumps 17 and the embedding are formed on the second conductive traces 16 . The second conductive traces 16 and the second dielectric layer 19 of the conductive bumps 17, the conductive bumps 17 are exposed outside the second dielectric layer 19; in step S5/S4', the buried first conductive traces 15 are formed of the first dielectric layer 18 .

FIG. 15 is a schematic cross-sectional structural diagram of the MCM package structure according to the fifth embodiment of the present application. Referring to FIG. 15 , the MCM package structure 8 in this embodiment is substantially the same as the

MCM package structures

1 , 6 , and 7 and the manufacturing method thereof in the previous embodiment, and the only difference is that the first die assembly 10 is replaced by a die, For example, the first die 11 is replaced. Correspondingly, the conductive bumps 17 are connected to the backside electrical connection points 132 . The conductive bumps 17 are exposed outside the second dielectric layer 19 , and the first dielectric layer 18 wraps the conductive traces 15 .

In other embodiments, the first die assembly 10 can also be replaced with a second die 12, or a second die assembly, and the second die assembly includes a plurality of first dies 11, or a plurality of second dies Die 12. In other words, in the second die assembly, the active surfaces of each die face the same direction.

Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be based on the scope defined by the claims.

Claims

An MCM package structure, comprising:

The first die assembly, including at least:

a first die, the first die including a number of first pads, the first pads being located on the active side of the first die, and

A second die, the second die includes a plurality of second pads, the second pads are located on the active surface of the second die; the active surface of the second die is covered with a second protective layer , the second protective layer exposes the second pad; the active surface of the first die is facing away from the active surface of the second die;

a wiring substrate, arranged around the first die assembly; the wiring substrate is provided with a wiring circuit, the wiring circuit includes a front electrical connection point and a back electrical connection point, and the front electrical connection point is exposed on the wiring substrate The front side of the wiring substrate, the back side electrical connection points are exposed on the back side of the wiring substrate;

a plastic encapsulation layer, covering the first die assembly and the wiring substrate, the backside of the plastic encapsulation layer exposes the second protective layer, the second pad and the backside of the wiring substrate, the plastic encapsulation layer The front surface of the first die is exposed to the active surface of the first die and the front surface of the wiring substrate;

a first conductive trace, located on the first pad, the front electrical connection point and the front surface of the plastic encapsulation layer, for electrically connecting the first die and the wiring circuit;

a second conductive trace, located on the second pad, the backside electrical connection point and the backside of the plastic encapsulation layer, for electrically connecting the second die and the wiring circuit;

a first conductive bump, connected to the first conductive trace;

a first dielectric layer, burying the first conductive traces and the first conductive bumps, the first conductive bumps being exposed outside the first dielectric layer; and

A second dielectric layer embeds the second conductive traces.
The MCM package structure of claim 1, wherein the first die assembly is a die stack structure.
The MCM package structure according to claim 1 or 2, wherein the first conductive bump connected to the first conductive trace is replaced by: a second conductive bump connected to the second conductive trace ; Correspondingly, the second dielectric layer embeds the second conductive traces and the second conductive bumps, the second conductive bumps are exposed outside the second dielectric layer, and the second conductive bumps are exposed outside the second dielectric layer. A dielectric layer buries the first conductive trace.
The MCM package structure according to claim 1, further comprising: a third dielectric layer located on the active surface of the first die, the front surface of the wiring substrate and the front surface of the plastic sealing layer; the third dielectric layer The electrical layer exposes the first pad and the front side electrical connection point; the first conductive trace is located on the first pad, the front side electrical connection point and the third dielectric layer.
The MCM package structure according to claim 1, further comprising: a first protective layer covering the active surface of the first die, the first protective layer exposing the first pad; The front surface exposes the first protective layer and the first pad.
The MCM package structure according to claim 1, wherein,

The material of the second protective layer is one of the following: organic high molecular polymer insulating material, inorganic insulating material or composite material; and/or

The material of the first dielectric layer is one of the following: organic high molecular polymer insulating material, inorganic insulating material or composite material; and/or

The material of the second dielectric layer is one of the following: organic high molecular polymer insulating material, inorganic insulating material or composite material.
A manufacturing method of an MCM package structure, comprising:

Provide a carrier board and multiple groups of packages carried on the carrier board, wherein each group of the packages includes:

A wiring substrate with a through opening, a wiring circuit is arranged in the wiring substrate, the wiring circuit includes a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the wiring substrate, and the back side is exposed. electrical connection points are exposed on the backside of the wiring substrate; and

A first die assembly located in the through opening, the first die assembly at least includes: a first die and a second die, the first die includes a plurality of first pads, the first die The pads are located on the active surface of the first die, the second die includes a plurality of second pads, and the second pads are located on the active surface of the second die; The active surface is covered with a second protective layer; the active surface of the first die is facing away from the active surface of the second die; the front surface of the wiring substrate is facing the active surface of the first die the carrier board;

forming a plastic encapsulation layer burying each group of the packages on the surface of the carrier board; thinning the plastic encapsulation layer until the second protective layer and the backside of the wiring substrate are exposed;

A second opening is formed in the second protective layer to expose the second pad; on the second protective layer, the second pad, the backside electrical connection point and the backside of the plastic encapsulation layer forming a second conductive trace thereon to electrically connect the second die and the wiring circuit in the group; forming a second dielectric layer burying the second conductive trace;

removing the carrier plate to expose the active surface of the first die, the front surface of the wiring substrate and the front surface of the plastic packaging layer; the first pad, the front surface electrical connection point and the plastic packaging layer A first conductive trace is formed on the front side of the group to electrically connect the first die and the wiring line in the group;

A first conductive bump is formed on the first conductive trace and a first dielectric layer burying the first conductive trace and the conductive bump is formed, the first conductive bump is exposed on the outside the first dielectric layer;

Cutting to form a plurality of MCM package structures, each of the MCM package structures including a group of the packages.
The method for fabricating an MCM package structure according to claim 7, wherein after the second conductive traces are formed, a second conductive bump is formed on the second conductive traces and the second conductive bumps are formed to bury the second conductive traces. a second dielectric layer of conductive traces and the second conductive bumps, the second conductive bumps being exposed outside the second dielectric layer; the first conductive traces are formed on the first conductive traces Conductive bumps and forming a first dielectric layer burying the first conductive traces and the first conductive bumps, where the first conductive bumps are exposed outside the first dielectric layer Replaced by: forming A first dielectric layer burying the first conductive trace.
The method for fabricating an MCM package structure according to claim 7, wherein, after removing the carrier, forming the first conductive trace, the first conductive bump, and embedding the first conductive trace and the After the first dielectric layer of the first conductive bumps; disposing a support plate on the first dielectric layer and the first conductive bumps, thinning the plastic encapsulation layer, and forming the first Two conductive traces and the second dielectric layer.
The method for manufacturing an MCM package structure according to claim 7, wherein after the carrier is removed, the exposed active surface of the first die, the front surface of the wiring substrate and the front surface of the plastic encapsulation layer are exposed. forming a third dielectric layer; forming a plurality of third openings in the third dielectric layer, the third openings expose the first pad and the front surface electrical connection point; in the first pad , the front surface electrical connection point and the first conductive trace are formed on the third dielectric layer.
The method for manufacturing an MCM package structure according to claim 7, wherein, in the first die assembly, an active surface of the first die is covered with a first protective layer; the first protective layer faces the a carrier board; the first protective layer is provided with a first opening exposing the first pad.
The method for fabricating an MCM package structure according to claim 7, wherein, in the first die assembly, an active surface of the first die is covered with a first protective layer, and the first protective layer faces the A carrier board, after the carrier board is removed and before the first conductive traces are formed, a first opening is formed in the first protective layer to expose the first pad.
The method for manufacturing an MCM package structure according to any one of claims 7 to 12, wherein the wiring substrates of the packages of each group are connected together, and are cut apart during cutting to form the plurality of MCM package structures .
An MCM package structure, comprising:

a bare chip, the bare chip includes a plurality of bonding pads, the bonding pads are located on the active surface of the bare chip;

a wiring substrate, arranged around the bare chip; the wiring substrate is provided with a wiring circuit, the wiring circuit includes a front electrical connection point and a back electrical connection point, and the front electrical connection point is exposed on the front surface of the wiring substrate, the backside electrical connection point is exposed on the backside of the wiring substrate;

a plastic encapsulation layer, covering the bare chip and the wiring substrate, and the front side of the plastic encapsulation layer exposes the active surface of the bare chip and the electrical connection point of the front side;

Conductive traces, located on the pads, the front electrical connection points and the front surface of the plastic encapsulation layer, are used to electrically connect the bare chip and the wiring lines;

a conductive bump, connected to the electrical connection point on the back surface;

a first dielectric layer burying the conductive traces;

A second dielectric layer embeds the conductive bumps, and the conductive bumps are exposed outside the second dielectric layer.
The MCM package structure of claim 14 , wherein the die is replaced with a second die assembly, the second die assembly comprising a plurality of dies, the active surfaces of the plurality of dies facing the same .
A manufacturing method of an MCM package structure, comprising:

Provide a carrier board and multiple groups of packages carried on the carrier board, wherein each group of the packages includes:

A wiring substrate with a through opening, a wiring circuit is arranged in the wiring substrate, the wiring circuit includes a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front side of the wiring substrate, and the back side is exposed. electrical connection points are exposed on the backside of the wiring substrate; and

A bare chip located in the through opening, the bare chip includes a plurality of pads, and the pads are located on the active surface of the bare chip; the front surface of the wiring substrate and the active surface of the bare chip face the carrier plate;

forming a plastic encapsulation layer burying each group of the packages on the surface of the carrier board; thinning the plastic encapsulation layer until the backside of the wiring substrate is exposed;

removing the carrier plate to expose the active surface of the die, the front surface of the wiring substrate and the front surface of the plastic packaging layer; forming on the pad, the front electrical connection point and the front surface of the plastic packaging layer conductive traces to electrically connect the die and the wiring lines in the group; forming a first dielectric layer burying the conductive traces;

forming conductive bumps on the backside electrical connection points and forming a second dielectric layer burying the conductive bumps, the conductive bumps being exposed outside the second dielectric layer;

Cutting to form a plurality of MCM package structures, each of the MCM package structures including a group of the packages.
The method for fabricating an MCM package structure according to claim 16, wherein the die is replaced with a second die assembly, the second die assembly includes a plurality of dies, and the active face the same.