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WO2022095328A1 - 驱动芯片、显示屏和显示装置 - Google Patents

驱动芯片、显示屏和显示装置 Download PDF

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Publication number
WO2022095328A1
WO2022095328A1 PCT/CN2021/083264 CN2021083264W WO2022095328A1 WO 2022095328 A1 WO2022095328 A1 WO 2022095328A1 CN 2021083264 W CN2021083264 W CN 2021083264W WO 2022095328 A1 WO2022095328 A1 WO 2022095328A1
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WO
WIPO (PCT)
Prior art keywords
signal
pixels
processing circuit
data
chip
Prior art date
Application number
PCT/CN2021/083264
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English (en)
French (fr)
Inventor
刘炳麟
黄彦辅
高振庸
Original Assignee
上海视涯技术有限公司
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Publication date
Application filed by 上海视涯技术有限公司 filed Critical 上海视涯技术有限公司
Priority to US17/793,113 priority Critical patent/US11663953B2/en
Publication of WO2022095328A1 publication Critical patent/WO2022095328A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel

Definitions

  • the embodiments of the present application relate to the field of display technology, for example, to a driver chip, a display screen, and a display device.
  • a silicon-based display is a combination of a display and a monocrystalline silicon integrated circuit. Its obvious feature is that the pixels in the display are formed on a silicon-based substrate through a CMOS process, so as to have the characteristics of lower cost and smaller volume.
  • a silicon-based display includes a display screen and a driver chip, and the driver chip can drive the pixels in the display screen to display.
  • the driver chip and the display screen are formed on the same silicon-based substrate.
  • the display effect of silicon-based displays has been continuously improved, so that the driver chip needs to be prepared by a high-level process, and each pixel in the display can be prepared by a low-level process. If the display and the driver chip are still formed When the same silicon-based substrate is used, the fabrication cost of the silicon-based display will undoubtedly increase. Therefore, how to reduce the manufacturing cost of the silicon-based display and improve the product yield of the silicon-based display on the premise of ensuring that the silicon-based display can have a high-quality display effect has become an urgent technical problem to be solved.
  • Embodiments of the present application provide a driving chip, a display screen and a display device, so as to reduce the manufacturing cost of the silicon-based display and improve the product yield of the silicon-based display.
  • an embodiment of the present application provides a driver chip for driving a silicon-based display screen, where the silicon-based display screen includes M rows and N columns of pixels, wherein M and N are both positive integers;
  • the driver chip includes: a bridge chip and a screen body chip; the bridge chip includes a first substrate and a first signal processing circuit disposed on one side of the first substrate; the first signal processing circuit includes a signal interface a module and a drive controller; the screen chip includes a second substrate and a second signal processing circuit disposed on one side of the second substrate; the second signal processing circuit includes a signal processor and a data processing circuit;
  • the signal interface module is used for receiving the video signal of each frame
  • the drive controller is electrically connected to the signal processor; the drive controller is used to control the video signals of P pixels in the video signals of one frame of pictures to be output to the first preset transmission speed at a time.
  • Signal processor wherein, P is a positive integer, and P ⁇ N;
  • the signal processor is electrically connected with the data processing circuit; the signal processor is used to convert the video signal of each pixel into a data driving signal, and output one frame of picture at a second preset transmission speed each time.
  • the data driving signals of the Q pixels are sent to the data processing circuit; wherein Q is a positive integer, and Q ⁇ N;
  • the data processing circuit is used for converting the data driving signal into a display driving signal, and outputting the data to each row of pixels in sequence, so as to control each of the pixels to display a picture.
  • an embodiment of the present application further provides a display screen, including the above-mentioned driver chip;
  • the second substrate of the panel chip includes a display area and a non-display area surrounding the display area; the pixels are arranged in the display area, and the second signal processing circuit is arranged in the non-display area.
  • an embodiment of the present application further provides a display device, including the above-mentioned display screen.
  • the driving chip includes a bridge chip and a screen body chip, and a first signal processing circuit with a relatively high transmission speed is provided on the first substrate of the bridge chip, and A second signal processing circuit with low transmission speed requirements is arranged on the second substrate of the screen chip, so that different substrates can be used to form the first signal processing circuit and the second signal processing circuit under different processes, so as to
  • the bridge chip can be prepared only by high-level process, while the screen chip can be prepared by low-level process, which is beneficial to reduce the manufacturing cost of the driver chip; at the same time, the video signal received by the signal interface module of the first signal processing circuit in the bridge chip can be processed by The drive controller of the first signal processing circuit outputs, and the drive controller can control the number of video signals output to the second signal processing circuit in the screen chip each time; in this way, if the first signal processing circuit in the bridge chip is connected The drive controller controls that each time the number of video signals output to the second signal processing circuit is small,
  • FIG. 1 is a schematic structural diagram of a driver chip for a silicon-based display screen in the related art
  • FIG. 2 is a schematic structural diagram of a driver chip provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another driver chip provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a bridge chip provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another driver chip provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a screen chip provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display screen provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the pixel 010 in the silicon-based display screen and the driving chip 020 for driving the silicon-based display screen are usually arranged on the same substrate 001, which makes the driving chip 020 and the silicon-based display screen Pixels 010 in need to be formed under the same process conditions.
  • the processing speed of the signal processing circuit in the driver chip 020 is continuously improved, so that the driver chip 020 needs to be prepared under higher demanding process conditions;
  • the manufacturing cost of the silicon-based display screen will undoubtedly increase, which is not conducive to the improvement of the production yield of the silicon-based display screen.
  • the driver chip 020 needs to be electrically connected to the pixel 010 in the silicon-based display screen through corresponding connection terminals and/or signal lines, In order to transmit the corresponding data driving signal to each pixel 010, each pixel 010 is driven to display. In this way, it is necessary to provide connection terminals corresponding to the number of pixels 010 in each row respectively on the substrate side where the driver chip is provided and the substrate side where the pixels of the silicon-based display screen are provided, and/or on the substrate where the driver chip is provided and the substrate side where the pixels of the silicon-based display screen are provided.
  • a signal line equivalent to the number of pixels 010 in each row is arranged between the substrates of the pixels of the silicon-based display screen; and when the number of pixels 010 in each row is large, more signal lines and/or connection terminals need to be arranged;
  • the yield of signal lines and connection terminals is constant, the more signal lines and/or connection terminals are provided, the less conducive it is to improve the production yield of silicon-based display screens, which will increase the manufacturing cost of silicon-based display screens and reduce silicon-based display screens. display effect.
  • the embodiments of the present application provide a driving chip, the driving chip is used for driving a silicon-based display screen, and the silicon-based display screen includes M rows and N columns of pixels; wherein, M and N are both positive integers;
  • the chip includes a bridge chip and a screen chip; the bridge chip includes a first substrate and a first signal processing circuit arranged on one side of the first substrate; the first signal processing circuit includes a signal interface module and a drive controller; the screen chip It includes a second substrate and a second signal processing circuit arranged on one side of the second substrate; the second signal processing circuit includes a signal processor and a data processing circuit; the signal interface module is used to receive video signals of each frame; drive The controller is electrically connected to the signal processor; the drive controller is used to control the video signal of P pixels in the video signal of one frame of pictures to be output to the signal processor at a first preset transmission speed each time; wherein, P is a positive integer, and P ⁇ N; the signal processor is electrically connected to the data processing
  • the first signal processing circuit disposed on the first substrate in the bridge chip can decode and transmit the received video signal, so the first signal processing circuit needs to have a high processing speed to be able to meet the high display
  • the required silicon-based display screen and the second signal processing circuit arranged on the second substrate in the screen chip can store and convert the signals output by the first signal processing circuit, etc., which does not require high processing speed. .
  • the first signal processing circuit and the second signal processing circuit are respectively arranged on the first substrate and the second substrate, so that different processes can be used to prepare the signal processing circuit formed on the first substrate.
  • the first signal processing circuit and the second signal processing circuit formed on the second substrate so that the first signal processing circuit with high requirements on production conditions can use high-level technology, and the second signal processing circuit with low requirements on production conditions can use A low-level process is enough, so that the production cost of the second signal processing circuit can be reduced, the production yield of the second signal processing circuit can be improved, and the cost of the driver chip can be reduced as a whole, and the production yield of the driver chip can be improved; on the other hand,
  • the driver chip is divided into a bridge chip and a screen chip.
  • the drive controller of the first signal processing circuit controls the output to the screen every time.
  • the number of video signals of the second signal processing circuit of the chip, and the drive controller controls the number of video signals output to the signal processor of the second signal processing circuit each time to be less than the number of pixels in each row, compared to different
  • the embodiment of the present application only uses the connection terminals and/or signal lines equivalent to the number of video signals output each time, so as to realize the bridge chip
  • the electrical connection with the screen body chip is beneficial to improve the production yield of the driver chip, reduce the production cost of the driver chip, thereby improve the production yield of the silicon-based display screen including the driver chip, and reduce the production yield of the driver chip.
  • the production cost of silicon-based displays is beneficial to improve the production yield of the driver chip, reduce the production cost of the driver chip, thereby improve the production yield of the silicon-based display screen including the driver chip, and reduce the production yield of the driver chip.
  • FIG. 2 is a schematic structural diagram of a driver chip provided by an embodiment of the present application.
  • the driver chip 100 can drive the silicon-based display screen to display a corresponding picture.
  • the silicon-based display screen may include M rows and N columns of pixels, that is, each row includes N pixels.
  • 230 presents lights of different colors and/or brightnesses according to corresponding display driving signals, and the combination of light displayed by each pixel 230 can constitute a picture to be displayed on the silicon-based display screen.
  • a plurality of data signal lines 34 are also set in the silicon-based display screen, and each pixel 230 in the same column will share one data signal line 34. Therefore, when the silicon-based display screen includes N columns of pixels 230, the silicon-based display screen can N data signal lines 34 are correspondingly arranged; at this time, the driving chip 100 needs to provide display driving signals to each pixel 230 by row.
  • the driver chip 100 includes a bridge chip 10 and a screen chip 20 .
  • the screen chip 20 is a chip provided with the pixels 230 of the silicon-based display screen and its peripheral circuits.
  • the bridge chip 10 includes a first substrate 110 and a first signal processing circuit 120 disposed on one side of the first substrate 110
  • the panel chip 20 includes a second substrate 210 and a first signal processing circuit 120 disposed on one side of the second substrate 210 .
  • Two signal processing circuits 220 namely the first signal processing circuit 120 of the bridge chip 10 and the second signal processing circuit 220 of the screen chip 20 are respectively formed on different substrates, so that the first signal processing circuit 120 of the bridge chip 10 and the The second signal processing circuit 220 of the panel chip 20 can be formed under different process conditions, so that a corresponding fabrication process can be selected according to the respective performance requirements of the first signal processing circuit 120 and the second signal processing circuit 220 .
  • the first signal processing circuit 120 includes at least a signal interface module 121 and a drive controller 122.
  • the signal interface module 121 can receive the video signal of each frame, and the video signal can drive each pixel 230 in the silicon-based display screen to display and emit light; when the signal When the interface module 121 receives a video signal of a frame, the video signal of the frame is usually a high-speed serial analog signal, and the signal interface module 121 will convert the received analog signal into a corresponding digital signal, and through the first After other modules of the signal processing circuit 120 perform high-speed processing such as decompression, the driving controller 122 of the first signal processing circuit 120 outputs the output to the second signal processing circuit 220 .
  • the drive controller 122 of the first signal processing circuit 120 can control the transmission speed of the video signal of each frame received by the signal interface module 121, that is, the video signal of each frame can be output to the second at the first preset transmission speed.
  • Signal processing circuit 220 Since the number of pixels 230 corresponding to each output video signal is small when the transmission speed is high, when the drive controller 122 outputs the video signal of each frame signal at the high first preset transmission speed, the drive control The controller 122 can output the video signals of P pixels 230 to the signal processor 221 of the second signal processing circuit 220 at a time; wherein, P is a positive integer, and P ⁇ N, that is, the video signals output by the drive controller 122 each time correspond to The number of pixels 230 in a silicon-based display will be less than the number of pixels 230 in each row of pixels in a silicon-based display.
  • the drive controller 122 outputs the video signal of each frame at a relatively fast speed, it is beneficial to improve the refresh rate of the silicon-based display screen. frequency and display brightness, etc.; at the same time, when the first signal processing circuit 120 has a high operation speed, it is necessary to use a high-level process with high production process conditions and high precision requirements to form the first signal processing circuit on the first substrate 110. 120 , so that the first signal processing circuit 120 formed on the side of the first substrate 110 can also make the bridge chip 10 have a higher yield under the premise of having a higher operation speed, so as to reduce the cost of the bridge chip 10 preparation cost.
  • the second signal processing circuit 220 includes a signal processor 221 and a data processing circuit 222.
  • the signal processor 221 is electrically connected to the drive controller 122 of the first signal processing circuit 120, and the signal processor 221 receives the video signal output by the drive controller 122.
  • the processor 221 may output the data driving signal at a lower second preset transmission speed; at this time, the first preset transmission speed may be greater than the second preset transmission speed, and P ⁇ Q.
  • the drive controller 122 controls each frame of video signal to output a video signal of 32 pixels at a frequency of 45MHz, and the signal processor 221 outputs a data drive signal of 64 pixels at a frequency of 22.5MHz
  • the signal processor 221 only divides the video signal of 32 pixels received each time into data driving signals of 64 pixels, that is, the video signal received by the signal processor 221 and the data driving signal output by the signal processor 221 are digital signals. Perform digital-to-analog conversion.
  • the data processing circuit 222 can perform digital-to-analog conversion on the received signal, so as to convert the data driving signal into a display capable of directly driving each pixel for display.
  • the driving signals are sequentially provided to the pixels in each row through the corresponding data signal lines 34, so that each pixel can display according to the display driving signal it receives.
  • the number of pixels 230 corresponding to the data driving signal output by the signal processor 221 each time may be twice the number of pixels 230 corresponding to the video signal output by the driving controller 122 each time.
  • the signal processor 221 nor the data processing circuit 222 of the second signal processing circuit 220 needs a high operation transmission speed, and the signal processor 221 only needs to divide the received video signal into a corresponding number of data driving signals, while the data
  • the processing circuit 222 only needs to convert the data driving signal into a display driving signal through digital-to-analog, so the second signal processing circuit 220 does not need a high transportation processing speed, and adopts a low-level process with lower production process conditions and precision requirements in the second lining.
  • the second signal processing circuit 220 may be formed on the bottom 210 , thereby reducing the fabrication cost of the screen chip 20 on the premise that the screen chip 20 has a high yield.
  • both the first substrate 110 and the second substrate 210 may be silicon-based substrates, and the high-level process of forming the first signal processing circuit 120 on the first substrate 110 and forming on the second substrate 210
  • the low-level processes of the second signal processing circuit 220 may all be CMOS processes, but the specific forming conditions thereof are different according to their respective performances. Under the premise that the yield of the bridge chip 10 and the screen chip 20 can be improved, and the cost of the bridge chip 10 and the screen chip 20 can be reduced, this embodiment of the present application does not specifically limit this.
  • the second signal processing circuit 220 in the screen chip 20 adopts a low-level process, which is equivalent to the process used by the pixels 230 in the silicon-based display screen, the second signal processing circuit 220 of the screen chip 20 adopts a low-level process.
  • the pixel 230 in the silicon-based display screen is simultaneously formed on the second substrate 210 under the same process conditions, which can simplify the process steps of the silicon-based display screen and reduce the cost of the silicon-based display screen.
  • the drive controller 122 of the first signal processing circuit 120 may be electrically connected to the signal processor 221 of the second signal processing circuit 220 through signal wires and/or connection terminals;
  • each signal line 31 can serially output a corresponding number of video signals, that is, the number of signal lines 31 used to electrically connect the drive controller 122 and the signal processor 221 should be the same as that of the drive controller 122.
  • the number of pixels 230 corresponding to each output video signal is equivalent; when the drive controller 122 outputs video signals of P pixels 230 each time at the first preset transmission speed, P signal lines for transmitting video signals need to be set 31.
  • the driving controller 122 of the first signal processing circuit 120 can control the number of pixels corresponding to the video signal output to the signal processing 221 of the second signal processing circuit 220 each time, when the driving controller 122 uses a higher first Transmission speed, when the number of pixels corresponding to each output video signal is small, the number of signal lines 31 for electrically connecting the drive controller 122 and the signal processor 221 between the bridge chip 10 and the screen chip 20 is relatively small.
  • the process for preparing the signal lines 31 will be relatively simple, and the pass rate of the signal lines 31 will be relatively high, which is beneficial to improve the output of the drive controller 122 to the signal processor 221 video signal accuracy, thereby improving the yield of the driver chip 100, reducing the cost and power consumption of the driver chip 100, thereby reducing the power consumption and cost of the silicon-based display screen, and improving the display effect of the silicon-based display screen.
  • the signal interface module 121 of the first signal processing circuit 120 is, for example, but not limited to, a PHY (physical layer chip) interface; on the premise that the signal interface module 121 can receive high-speed serial analog signals,
  • the embodiment of the present application does not specifically limit the type of the signal interface module.
  • FIG. 3 is a schematic structural diagram of another driving chip provided by an embodiment of the present application.
  • the driver chip 100 further includes a connector 301 for electrically connecting the bridge chip 10 and the screen chip 20 , and/or for electrically connecting the bridge chip 10 and the system motherboard (not shown in the figure) device 302.
  • the first signal processing circuit 120 of the bridge chip 10 can output the video signal to the second signal processing circuit 220 of the screen chip 20 through the connector 301; correspondingly, the first signal processing circuit 120 of the bridge chip 10 can output the video signal through the connector 302 receives video signals of each frame of pictures provided by the system mainboard.
  • the connector 301 for electrically connecting the bridge chip 10 and the screen chip 20 may be provided with corresponding connection terminals, signal lines, and the like.
  • the connector 301 can be provided with fewer connection terminals and signal lines; in this way, the connection of the connector 301 can be simplified.
  • the design is beneficial to improve the product yield of the connector 301 and reduce the manufacturing cost of the connector 301 .
  • the video signal of each frame generated by the system motherboard can be transmitted to the bridge chip 10 through the connector 302 and received by the signal interface module 121 of the bridge chip 10 .
  • the connectors (301, 302) may include, but are not limited to, printed circuit boards or flexible circuit boards.
  • FIG. 4 is a schematic structural diagram of a bridge chip provided by an embodiment of the present application.
  • the first signal processing circuit 120 of the bridge chip 10 further includes a digital signal decoder 123; the digital signal decoder 123 is electrically connected to the signal interface module 121; the digital signal decoder 123 can receive the signal interface module 121
  • the video signal of each frame of the picture is decoded, and the video signal of K pixels in the video signal of one frame of picture is output at a third preset transmission speed at a time; wherein, the third preset transmission speed is greater than the second preset transmission speed.
  • speed, and K ⁇ P, K is a positive integer.
  • the digital signal decoder 123 can decode the video signal of each frame received by the signal interface module 121 into an 8-bit RGB signal, or a digital signal in other formats (MIPI, HDMI, VGA, NTSC, SMPTE, etc.)
  • the decoded video signal is output at a third preset transmission speed greater than the second preset transmission speed and less than or equal to the first preset transmission speed, and outputs a video signal of K pixels each time; in this way, the digital signal decoder 123 A high decoding speed is required, so that when the first signal processing circuit 120 is fabricated by a high-level process, the requirements of the decoding pixels of the data decoder 123 can be met, and the bridge chip 10 can be ensured to have low power consumption.
  • the first signal processing circuit 120 further includes a signal correction module 124; the signal correction module 124 is electrically connected to the digital signal decoder 123 and the drive controller 122 respectively; the signal correction module 124 can Color correction is performed on the video signal of each pixel in the picture, and pixel compensation is performed on the video signal of each frame of picture, so as to improve the display effect of each frame of picture and ensure that the silicon-based display can accurately display the corresponding picture.
  • the correction module 124 may include a gamma correction unit 1241 , a saturation grayscale processing unit 1242 and a frame pixel compensation unit 1243 that are electrically connected in sequence.
  • the gamma correction unit 1241 can be used to perform gamma correction on the video signal decoded by the digital signal decoder 123, so that the displayed picture can have a higher contrast;
  • the bias adjustment of the video signal is performed to form the brightness signal finally input to each pixel unit, so that the displayed picture can have a higher display brightness and improve the display effect.
  • the silicon-based display screen includes not only the pixels used for normal display, but also the dummy pixels set at the frame position, it is necessary to use the frame pixel compensation unit 1243 to provide the video signal of the dummy pixels set at the frame position, so as to The finally outputted display driving signal can be in one-to-one correspondence with the pixels in the silicon-based display screen, thereby improving the display effect of the silicon-based display screen.
  • FIG. 5 is a schematic structural diagram of another driving chip provided by an embodiment of the present application.
  • the data processing circuit 222 includes a storage unit 2221, a digital-to-analog conversion unit 2222, and a data driver 2223; the signal processor 221 also receives the line synchronization signal and the data write control signal output by the drive controller 122, and according to the line Synchronization signal and data writing control signal, output the data drive signal and clock trigger signal of each pixel at the second preset transmission speed; the storage unit 2221 is respectively electrically connected with the signal processor 221 and the digital-to-analog conversion unit 2222; the storage unit 2221 includes A plurality of storage sub-units corresponding to one row of pixels 230; each storage sub-unit corresponds to the data driving signal of each pixel 230 in the same row output by the storage signal processor; the storage unit 2221 receives the data of each pixel 230 output by the signal processor 221 drive signal, and control the data drive signal of each pixel 230
  • the drive controller 122 of the first signal processing circuit 120 outputs the video signals of P pixels to the signal processor 221 of the second signal processing circuit 220, and also outputs the horizontal synchronization signal and the data writing control signal to the signal processor 221 of the second signal processing circuit 220.
  • the signal processor 221 enables the signal processor 221 to distinguish the video signals of each pixel 230 and each row of pixels according to the line synchronization signal and the data write control signal, and output the data driving signal of each row of pixels to the storage unit 2221 for storage.
  • the driving controller 122 only outputs the video signals of P pixels at a time, the video signals of each pixel can be distinguished by the line synchronization signal and the data writing control signal output by the driving controller, so that the bridge chip 10 and the screen chip 20 are connected.
  • the signal line 322 of the control signal that is, P ⁇ i ⁇ j+3 signal lines are set between the bridge chip 10 and the screen chip 20, so that the number of pixels corresponding to the video signal output by the drive controller 122 each time is less.
  • i is the number of sub-pixels contained in each pixel
  • j is the number of bytes of each video signal; for example, each pixel can include three sub-pixel pixels, that is, i is 3; each video signal can be 8bit , that is, j is 8, which is only an exemplary description.
  • the values of i and j are not specifically limited in the embodiments of the present application.
  • the signal processor 221 will output a corresponding clock trigger signal to the storage unit 2221, so that the storage unit 2221 can simultaneously output the data driving signals of a row of pixels to the digital-analog
  • the conversion unit 2222; the digital-to-analog conversion unit 2222 can convert the data driving signal into a display driving signal that can directly drive each pixel 230, and output it to each row of pixels 230 through the data driver 2223 at a preset driving timing, and drive each row of pixels 230 to emit light to display each frame.
  • FIG. 6 is a schematic structural diagram of a screen chip provided by an embodiment of the present application.
  • the storage unit 2221 includes a vertical shift register 2201 and a latch 2202;
  • the vertical shift register 2201 includes a plurality of vertical shift register units 22011 corresponding to each pixel 230 in the same row;
  • the processor 22021 includes a plurality of latch units 22021 corresponding to the pixels 230 in the same row.
  • the data driving signals output by the signal processor 221 can be sequentially stored in the vertical shift register units 22011 of the vertical shift register 2201, and when each vertical shift register unit 22011 stores the corresponding data driving signals, the signal processing The controller 221 outputs a corresponding clock trigger signal to the vertical shift register 2201, so that each vertical shift register unit 22011 in the vertical shift register 2201 simultaneously outputs a data driving signal to each latch unit 22021 of the latch 2202 for latching.
  • FIG. 6 is only an exemplary illustration of the embodiment of the present application.
  • the data driving signal output by the signal processor 221 in FIG. 6 is first stored in the vertical shift register 2201 and then output to the latch 2202;
  • the data driving signal output by the signal processor may also be stored in the latch first, and then output to the vertical shift register for storage, which is not specifically limited in this embodiment of the present application.
  • the digital-to-analog conversion unit 2222 includes a digital-to-analog converter 2203 and a gamma voltage generator 2204; the gamma voltage generator 2204 is electrically connected to the digital-to-analog converter 2203; the gamma voltage The generator 2204 can output the gamma voltage to the digital-to-analog converter 2203, so that the digital-to-analog converter 2203, according to the gamma voltage and the data driving signal, converts each data driving signal into a display driving signal in a one-to-one correspondence, and outputs it to the display driving signal.
  • the data driver 2223 that is electrically connected to it.
  • the second signal processing circuit 220 further includes a row driver 223 ; the signal processor 221 is also electrically connected to the row driver 223 ; the signal processor 221 also receives the column synchronization signal output by the drive controller 122 and the data write control signal, and output the first clock control signal to the row driver 223 according to the column synchronization signal and the data write control signal; the output end of the row driver 223 is electrically connected to the pixels 230 in each row, for example, the pixels located in the same row
  • the scanning signal lines 33 can be shared, and the row driver 223 can be electrically connected to each row of pixels through each scanning signal line; the row driver 223 can sequentially provide row driving signals to each row of pixels 230 according to the first clock control signal, so that each display driving signal Correspondingly, it is written into each row of pixels 230 .
  • the pixel mentioned in the embodiments of the present application may be a sub-pixel or a pixel unit including a plurality of different sub-pixels.
  • the embodiments of the present application may No specific limitation is made.
  • the second signal processing circuit 220 may further include multiple multiplexing circuits 240 and a plurality of clock signal lines 35; each multiplexing circuit 240 includes a plurality of switching units 241; the input terminals of each switching unit 241 of the same multiplexing circuit 240 and the same display driving signal output of the data processing circuit 222
  • the control terminals of each switch unit 241 of the same multiplexing circuit 240 are electrically connected to different clock signal lines 35 ; the output terminals of each switch unit 241 are electrically connected to each column of sub-pixels in a one-to-one correspondence.
  • each pixel 230 may include three sub-pixels 231 , 232 and 233 of different colors, and the colors of each sub-pixel ( 231 , 232 and 233 ) may include, but are not limited to, red, green and blue, for example.
  • each multiplexing circuit 240 may include three switch units 241, and each switch unit 241 may include a transistor; thus, when the transistor of the switch unit 241 is an NMOS, the clock electrically connected to the switch unit 241 When the signal transmitted by the signal line 35 is at a high level, the transistor of the switch unit 241 can be controlled to be turned on, so that the display drive signal output by the data processing circuit 222 can be transmitted to the sub-pixels of the corresponding column through the turned-on transistor; When the transistor of the unit 241 is a PMOS, when the signal transmitted by the clock signal line 35 electrically connected to the switch unit 241 is at a low level, the transistor of the switch unit 241 can be controlled to be turned on, so that the display drive signal output by the data processing circuit 222 can be It is transmitted to the sub-pixels of the corresponding column through the turned-on transistors.
  • the clock signal output end of the data processing circuit 222 is electrically connected to each clock signal line 35; the data processing circuit 222 can output a different second clock control signal to each clock signal line 35, so that each switch unit 241 is in each second clock signal line 35.
  • the two clock control signals are turned on or off under the control of the second clock control signal, and when the second clock control signal controls the switch unit 241 to be turned on, the display driving signals are controlled to be transmitted to each column of sub-pixels in a one-to-one correspondence.
  • An embodiment of the present application further provides a display screen, and the display screen includes the driver chip provided by the embodiment of the present application. Therefore, the display screen includes the technical features of the driver chip provided by the embodiment of the present application and has the driver chip provided by the embodiment of the present application. For the beneficial effects of the chip, reference may be made to the above description of the driver chip provided by the embodiment of the present application for the same, and details are not repeated here.
  • FIG. 7 is a schematic structural diagram of a display screen provided by an embodiment of the present application.
  • the display screen 200 includes the driver chip 100 provided by the embodiment of the present application, and the second substrate 210 of the screen body chip 20 of the driver chip 100 includes a display area 201 and a non-display area 202 surrounding the display area 201;
  • the pixels 230 of the display screen are arranged in the display area 201, and the second signal processing circuit 220 is arranged in the non-display area 202; in this way, the pixels of the display screen and the second signal processing circuit 220 can be arranged on the same substrate 210 to enable
  • the display screen includes, for example, a silicon-based display screen.
  • the embodiment of the present application also provides a display device, the display device includes the display screen provided by the embodiment of the present application, so the display device has the technical features and beneficial effects of the display screen provided by the embodiment of the present application, and for the same, please refer to the above-mentioned The description of the display screen provided by the embodiments of the present application will not be repeated here.
  • FIG. 8 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 300 may be, for example, an AR device, a VR device, or the like, which is not specifically limited in this embodiment of the present application.

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Abstract

一种驱动芯片（100）、显示屏（200）和显示装置（300），该驱动芯片（100）用于驱动硅基显示屏（200），该驱动芯片（100）由桥接芯片（10）和屏体芯片（20）组成。桥接芯片（10）中第一信号处理电路（120）的信号接口模块（121）接收各帧画面的视频信号，驱动控制器（122）以第一预设传输速度，控制每次输出一帧画面的视频信号中P个像素的视频信号至屏体芯片（20）的第二信号处理电路（220）；屏体芯片（20）中第二信号处理电路（220）的信号处理器（221）将各像素的视频信号转换为数据驱动信号，并以第二预设传输速度，每次输出一帧画面中Q个像素的数据驱动信号至数据处理电路（222），数据处理电路（222）用于将数据驱动信号转换为显示驱动信号，并依次输出至各行像素，控制各像素进行画面显示。

Description

驱动芯片、显示屏和显示装置
本申请要求申请日为2020年11月3日、申请号为202011206657.5的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如涉及一种驱动芯片、显示屏和显示装置。
背景技术
硅基显示器是将显示器与单晶硅集成电路结合，其明显的特征是显示器中的像素通过CMOS工艺在硅基衬底上形成，以具有较低的成本、较小的体积等特点。
通常硅基显示器包括显示屏和驱动芯片，驱动芯片能够驱动显示屏中的像素进行显示。传统工艺中，驱动芯片和显示屏在同一硅基衬底上形成。但是随着显示技术的发展，硅基显示器的显示效果不断提高，使得驱动芯片需要高阶工艺进行制备，而显示器中的各像素采用低阶工艺进行制备即可，若仍将显示器与驱动芯片形成于同一硅基衬底时，无疑会增加硅基显示器的制备成本。因此，如何在确保硅基显示器能够具有高质量的显示效果的前提下，降低硅基显示器的制备成本，提高硅基显示器的产品良率，成为当前亟待解决的技术问题。
发明内容
本申请实施例提供一种驱动芯片、显示屏和显示装置，以降低硅基显示器的制备成本，提高硅基显示器的产品良率。
第一方面，本申请实施例提供了一种驱动芯片，用于驱动硅基显示屏，所述硅基显示屏包括M行N列像素；其中，M和N均为正整数；
所述驱动芯片包括：桥接芯片和屏体芯片；所述桥接芯片包括第一衬底和 设置于所述第一衬底一侧的第一信号处理电路；所述第一信号处理电路包括信号接口模块和驱动控制器；所述屏体芯片包括第二衬底和设置于所述第二衬底一侧的第二信号处理电路；所述第二信号处理电路包括信号处理器和数据处理电路；
所述信号接口模块用于接收各帧画面的视频信号；
所述驱动控制器与所述信号处理器电连接；所述驱动控制器用于以第一预设传输速度，控制每次输出一帧画面的视频信号中P个所述像素的视频信号至所述信号处理器；其中，P为正整数，且P＜N；
所述信号处理器与所述数据处理电路电连接；所述信号处理器用于将各所述像素的视频信号转换为数据驱动信号，并以第二预设传输速度，每次输出一帧画面中Q个所述像素的数据驱动信号至所述数据处理电路；其中Q为正整数，且Q≤N；
所述数据处理电路用于将所述数据驱动信号转换为显示驱动信号，并依次输出至各行像素，控制各所述像素进行画面显示。
第二方面，本申请实施例还提供了一种显示屏，包括上述驱动芯片；
所述屏体芯片的第二衬底包括显示区和围绕所述显示区的非显示区；所述像素设置于所述显示区，所述第二信号处理电路设置于所述非显示区。
第三方面，本申请实施例还提供一种显示装置，包括上述显示屏。
本申请实施例提供的驱动芯片、显示屏和显示装置，该驱动芯片包括桥接芯片和屏体芯片，并在桥接芯片的第一衬底上设置具有较高传输速度的第一信号处理电路，以及在屏体芯片的第二衬底上设置传输速度要求低的第二信号处理电路，如此能够分别采用不同的衬底，在不同的工艺下形成第一信号处理电路和第二信号处理电路，以能够仅采用高阶工艺制备桥接芯片，而采用低阶工艺制备屏体芯片，从而有利于降低驱动芯片的制备成本；同时，桥接芯片中第 一信号处理电路的信号接口模块接收的视频信号能够由该第一信号处理电路的驱动控制器输出，且该驱动控制器能够控制每次输出至屏体芯片中第二信号处理电路的视频信号的数量；如此，若桥接芯片中第一信号处理电路的驱动控制器控制每次输出至第二信号处理电路的视频信号的数量较少时，则电连接桥接芯片和屏体芯片的信号线和/或连接端子较少，有利于降低因信号线和/或连接端子接触不良而造成桥接芯片无法向屏体芯片传输视频信号的风险，从而有利于提高信号传输的准确性，以及提高驱动芯片的生产良率。
附图说明
图1是相关技术中的一种硅基显示屏的驱动芯片的结构示意图；
图2是本申请实施例提供的一种驱动芯片的结构示意图；
图3是本申请实施例提供的又一种驱动芯片的结构示意图；
图4是本申请实施例提供的一种桥接芯片的结构示意图；
图5是本申请实施例提供的又一种驱动芯片的结构示意图；
图6是本申请实施例提供的一种屏体芯片的结构示意图；
图7是本申请实施例提供的一种显示屏的结构示意图；
图8是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
如图1所示，相关技术中通常将硅基显示屏中的像素010和用于驱动硅基显示屏的驱动芯片020均设置在同一衬底001上，这使得驱动芯片020与硅基显示屏中的像素010需要在相同的工艺条件下形成。随着对硅基显示屏的显示要求的提高，驱动芯片020中的信号处理电路的处理速度不断提高，使得驱动芯片020需要在较高要求的工艺条件下制备；如此，在将硅基显示屏中的像素010与驱动芯片020在同一工艺条件下制备时，无疑会增加硅基显示屏的制备成 本，不利于硅基显示屏的生产良率的提高。
但是，当分别采用不同的衬底制备驱动芯片020和硅基显示屏中的像素010时，驱动芯片020需要通过相应的连接端子和/或信号线与硅基显示屏中的像素010电连接，以将相应的数据驱动信号传输至各像素010，驱动各像素010进行显示。如此，需要在设置驱动芯片的衬底侧和设置硅基显示屏的像素的衬底侧分别设置与每行像素010的数量相当的连接端子，和/或在设置有驱动芯片的衬底与设置有硅基显示屏的像素的衬底之间设置与每行像素010的数量相当的信号线；而当每行像素010的数量较多时，需要设置较多的信号线和/或连接端子；在信号线和连接端子的成品率一定时，设置的信号线和/或连接端子越多，越不利于提高硅基显示屏的生产良率，从而会增加硅基显示屏的制备成本，降低硅基显示屏的显示效果。
为解决上述技术问题，本申请实施例提供一种驱动芯片，该驱动芯片用于驱动硅基显示屏，该硅基显示屏包括M行N列像素；其中，M和N均为正整数；驱动芯片包括桥接芯片和屏体芯片；桥接芯片包括第一衬底和设置于第一衬底一侧的第一信号处理电路；该第一信号处理电路包括信号接口模块和驱动控制器；屏体芯片包括第二衬底和设置于第二衬底一侧的第二信号处理电路；该第二信号处理电路包括信号处理器和数据处理电路；信号接口模块用于接收各帧画面的视频信号；驱动控制器与信号处理器电连接；驱动控制器用于以第一预设传输速度，控制每次输出一帧画面的视频信号中P个像素的视频信号至信号处理器；其中，P为正整数，且P＜N；信号处理器与数据处理电路电连接；信号处理器用于将各像素的视频信号转换为数据驱动信号，并以第二预设传输速度，每次输出一帧画面中Q个像素的数据驱动信号至所述数据处理电路；其中Q为正整数，且Q≤N；数据处理电路用于将数据驱动信号转换为显示驱动 信号，并依次输出至各行像素，控制各像素进行画面显示。
其中，设置在桥接芯片中第一衬底上的第一信号处理电路能够对所接收的视屏信号进行解码、传输等，因此第一信号处理电路需要有较高的处理速度，才能够满足高显示要求的硅基显示屏；而设置在屏体芯片中第二衬底上的第二信号处理电路能够对第一信号处理电路输出的信号进行存储和数模转换等，其无需较高的处理速度。
如此，采用上述技术方案，一方面，分别在第一衬底和第二衬底上设置第一信号处理电路和第二信号处理电路，以能够采用不同的工艺制备形成于第一衬底上的第一信号处理电路和形成于第二衬底上的第二信号处理电路，以能够使制备条件要求高的第一信号处理电路采用高阶工艺，而制备条件要求低的第二信号处理电路采用低阶工艺即可，从而能够降低第二信号处理电路的生产成本，提高第二信号处理电路的生产良率，进而能够整体降低驱动芯片的成本，提高驱动芯片的生产良率；另一方面，将驱动芯片分成桥接芯片和屏体芯片，通过桥接芯片中第一信号处理电路的信号接口模块接收每帧画面的视频信号后，由第一信号处理电路的驱动控制器控制每次输出至屏体芯片的第二信号处理电路的视频信号的数量，且驱动控制器控制每次输出至第二信号处理电路的信号处理器中的视频信号的数量小于每行像素的数量，相较于分别在不同衬底上制备驱动芯片的信号处理电路和硅基显示屏的像素的情况，本申请实施例仅采用与每次输出的视频信号的数量相当的连接端子和/或信号线，即可实现桥接芯片与屏体芯片的电连接，从而有利于提高驱动芯片的生产良率，降低驱动芯片的生产成本，进而能够提高包括该驱动芯片的硅基显示屏的生产良率，以及降低包括该驱动芯片的硅基显示屏的生产成本。
图2是本申请实施例提供的一种驱动芯片的结构示意图。如图2所示，驱 动芯片100能够驱动硅基显示屏显示相应的画面。该硅基显示屏中可以包括M行N列像素，即每一行包括N个像素；驱动芯片100通过向硅基显示屏中的各像素230提供显示驱动信号，以使硅基显示屏的各像素230根据相应的显示驱动信号呈现出不同颜色和/或亮度的光，各像素230所显示的光组合即可构成硅基显示屏所要显示的画面。通常硅基显示屏中还会设置多条数据信号线34，位于同一列的各像素230会共用一条数据信号线34，因此当硅基显示屏包括N列像素230时，硅基显示屏中可以对应设置N条数据信号线34；此时，驱动芯片100需要按行向各像素230提供显示驱动信号。
在本申请实施例中，驱动芯片100包括桥接芯片10和屏体芯片20。其中，屏体芯片20即为设置有硅基显示屏的像素230及其周边电路的芯片。桥接芯片10包括第一衬底110和设置在第一衬底110一侧的第一信号处理电路120，而屏体芯片20包括第二衬底210和设置在第二衬底210一侧的第二信号处理电路220，即桥接芯片10的第一信号处理电路120和屏体芯片20的第二信号处理电路220分别形成于不同的衬底上，使得桥接芯片10的第一信号处理电路120与屏体芯片20的第二信号处理电路220能够在不同的工艺条件下形成，由此可根据第一信号处理电路120和第二信号处理电路220各自性能需要选择相应的制备工艺。
第一信号处理电路120至少包括信号接口模块121和驱动控制器122，信号接口模块121能够接收各帧画面的视频信号，该视频信号能够驱动硅基显示屏中各像素230进行显示发光；当信号接口模块121接收到一帧画面的视频信号时，该帧画面的视频信号通常为高速串行的模拟信号，信号接口模块121会将所接收到的模拟信号转换为相应的数字信号，并经第一信号处理电路120的其它模块进行解压等高速处理过程后，由第一信号处理电路120的驱动控制器122 输出至第二信号处理电路220。第一信号处理电路120的驱动控制器122能够控制信号接口模块121所接收的各帧画面的视频信号的传输速度，即可以令各帧画面的视频信号以第一预设传输速度输出至第二信号处理电路220。由于传输速度较大时，每次输出的视频信号对应的像素230的数量较少，因此当驱动控制器122以较高的第一预设传输速度输出各帧信号的视频信号时，该驱动控制器122每次可输出P个像素230的视频信号至第二信号处理电路220的信号处理器221；其中，P为正整数，且P＜N，即驱动控制器122每次输出的视频信号对应的像素230的数量会小于硅基显示屏中每行像素中的像素230的数量。
如此，当信号接口模块121所接收的各帧视频信号为高速串行的模拟信号，驱动控制器122以较快的速度输出各帧画面的视频信号时，能够有利于提高硅基显示屏的刷新频率和显示亮度等；同时，当第一信号处理电路120具有较高的运算速度时，需要采用生产工艺条件以及精度要求较高的高阶工艺在第一衬底110上形成第一信号处理电路120，以使形成于第一衬底110一侧的第一信号处理电路120在具有较高的运算速度的前提下，还能够使桥接芯片10具有较高的成品率，以降低桥接芯片10的制备成本。
第二信号处理电路220包括信号处理器221和数据处理电路222，信号处理器221与第一信号处理电路120的驱动控制器122电连接，该信号处理器221接收驱动控制器122输出的视频信号，并将其所接收的视频信号转换为数据驱动信号后，以第二预设传输速度，每次输出Q个像素的数据驱动信号至与其电连接的数据处理电路222；其中，Q为正整数，且Q≤N，即信号处理器221每次输出的数据驱动信号所对应的像素230的数量可以小于每行像素中像素230的数量，也可以等于每行像素中像素230的数量，使得信号处理器221以较低的第二预设传输速度输出数据驱动信号即可；此时，第一预设传输速度可以大 于第二预设传输速度，且P＜Q。
示例性的，当驱动控制器122控制每帧视频信号以45MHz的频率每次输出32个像素的视频信号，而信号处理器221以22.5MHz的频率每次输出64个像素的数据驱动信号时，信号处理器221仅是将每次所接收的32个像素的视频信号划分为64个像素的数据驱动信号，即信号处理器221接收的视频信号和输出的数据驱动信号均为数字信号，并未进行数模转换。而当信号处理器221将数据驱动信号输出至数据处理电路222后，该数据处理电路222能够将所接收的信号进行数模转换，以将数据驱动信号转换为能够直接驱动各像素进行显示的显示驱动信号，并通过相应的数据信号线34依次提供至各行像素，使得各像素能够根据其所接收到的显示驱动信号进行显示。据此可知，信号处理器221每次输出的数据驱动信号对应的像素230的数量可以为驱动控制器122每次输出的视频信号对应的像素230的数量的两倍。
如此，第二信号处理电路220的信号处理器221和数据处理电路222均无需较高的运算传输速度，信号处理器221仅需将所接收的视频信号分为相应数量的数据驱动信号，而数据处理电路222将数据驱动信号经数模转换为显示驱动信号即可，因此第二信号处理电路220无需较高的运输处理速度，采用生产工艺条件及精度要求较低的低阶工艺在第二衬底210上形成第二信号处理电路220即可，从而在保证屏体芯片20具有较高的成品率的前提下，降低屏体芯片20的制备成本。
示例性的，第一衬底110和第二衬底210均可以为硅基衬底，在第一衬底110上形成第一信号处理电路120的高阶工艺和在第二衬底210上形成第二信号处理电路220的低阶工艺均可以为CMOS工艺，但是其具体的形成条件根据各自的性能具有差异。在能够提高桥接芯片10和屏体芯片20的成品率，以及降 低桥接芯片10和屏体芯片20的成本的前提下，本申请实施例对此不做具体限定。
另外，由于屏体芯片20中的第二信号处理电路220采用的是低阶工艺，这与硅基显示屏中的像素230所采用的工艺相当，因此屏体芯片20的第二信号处理电路220和硅基显示屏中的像素230在同种工艺条件下，同时形成于第二衬底210上，能够简化硅基显示屏的工艺步骤，降低硅基显示屏的成本。
此外，第一信号处理电路120的驱动控制器122可通过信号线和/或连接端子与第二信号处理电路220的信号处理器221电连接；示例性的，当驱动控制器122通过信号线31与信号处理器221电连接时，每条信号线31可串行输出相应数量的视频信号，即用于电连接驱动控制器122和信号处理器221的信号线31的数量应与驱动控制器122每次输出的视频信号对应的像素230的数量相当；当驱动控制器122以第一预设传输速度每次输出P个像素230的视频信号时，需要设置P条用于传输视频信号的信号线31。由于第一信号处理电路120的驱动控制器122能够控制每次输出至第二信号处理电路220的信号处理221中的视频信号对应的像素的数量，因此当驱动控制器122以较高的第一传输速度，每次输出的视频信号对应的像素的数量较少时，桥接芯片10与屏体芯片20之间设置的用于电连接驱动控制器122和信号处理器221的信号线31的数量较少；而在所设置的信号线31的数量较少时，制备该信号线31的工艺会相对简单，信号线31的合格率会相对较高，有利于提高驱动控制器122输出至信号处理器221的视频信号的准确性，从而能够提高驱动芯片100的成品率，降低驱动芯片100的成本和功耗，进而降低硅基显示屏的功耗和成本，提高硅基显示屏的显示效果。
其中，在本申请实施例中，第一信号处理电路120的信号接口模块121例 如为但不限于PHY(物理层芯片)接口；在信号接口模块121能够接收高速串行的模拟信号的前提下，本申请实施例对信号接口模块的类型不做具体限定。
可选的，图3是本申请实施例提供的又一种驱动芯片的结构示意图。如图3所示，驱动芯片100还包括用于电连接桥接芯片10与屏体芯片20的连接器301，和/或用于电连接桥接芯片10与系统主板(图中未示出)的连接器302。如此，桥接芯片10的第一信号处理电路120能够通过连接器301输出视频信号至屏体芯片20的第二信号处理电路220；相应的，桥接芯片10的第一信号处理电路120能够通过连接器302接收系统主板提供的各帧画面的视频信号。
其中，用于电连接桥接芯片10和屏体芯片20的连接器301中可设置有相应的连接端子和信号线等。当第一信号处理电路120的驱动控制器122控制每次输出的视频信号对应的像素数量较少时，连接器301可设置有较少的连接端子和信号线；如此，能够简化连接器301的设计，有利于提高连接器301的产品良率，降低连接器301的制备成本。相应的，由于系统主板产生的各帧画面的视频信号能够通过连接器302传输至桥接芯片10，并由桥接芯片10的信号接口模块121接收。示例性的，连接器(301、302)可以包括但不限于印刷电路板或柔性电路板。
可选的，图4是本申请实施例提供的一种桥接芯片的结构示意图。如图4所示，桥接芯片10的第一信号处理电路120还包括数字信号解码器123；该数字信号解码器123与信号接口模块121电连接；数字信号解码器123能够将信号接口模块121接收的各帧画面的视频信号进行解码，并以第三预设传输速度，每次输出一帧画面的视频信号中K个像素的视频信号；其中，第三预设传输速度大于第二预设传输速度，且K≤P，K为正整数。
其中，数字信号解码器123能够将信号接口模块121接收的各帧画面的视 频信号解码为8位的RGB信号，或者其它格式(MIPI、HDMI、VGA、NTSC、SMPTE等)的数字信号，并将解码后的视频信号以大于第二预设传输速度以及小于或等于第一预设传输速度的第三预设传输速度输出，且每次输出K个像素的视频信号；如此，数字信号解码器123需要具有较高的解码速度，使得在采用高阶工艺制备第一信号处理电路120时，能够满足数据解码器123的解码素的要求，同时能够确保桥接芯片10具有较低的功耗。
可选的，继续参考图4，第一信号处理电路120还包括信号修正模块124；该信号修正模块124分别与数字信号解码器123和驱动控制器122电连接；信号修正模块124能够对每帧画面中各像素的视频信号进行色彩修正，以及对每帧画面的视频信号进行像素补偿，从而能够提高每帧画面的显示效果，确保硅基显示器能够准确地显示相应的画面。
其中，修正模块124可以包括依次电连接的伽马校正单元1241、饱和度灰度处理单元1242以及边框像素补偿单元1243。如此，采用伽马校正单元1241能够对数字信号解码器123解码后的视频信号进行伽马校正，以能够使所显示的画面具有较高的对比度；采用饱和灰度处理单元1242对伽马校正后的视频信号进行偏置调整，以形成最后输入每个像素单元的亮度信号，从而能够使所显示的画面具有较高的显示亮度，提高显示效果。此外，由于硅基显示屏中不仅包括用于正常显示的像素，还包括设置在边框位置处的虚拟像素，因此需要采用边框像素补偿单元1243提供设置在边框位置处的虚拟像素的视频信号，以能够使最终输出至的显示驱动信号能够与硅基显示屏中的像素一一对应，提高硅基显示屏的显示效果。
可选的，图5是本申请实施例提供的又一种驱动芯片的结构示意图。如图5所示，数据处理电路222包括存储单元2221、数模转换单元2222和数据驱动器 2223；信号处理器221还接收驱动控制器122输出的行同步信号和数据写入控制信号，并根据行同步信号和数据写入控制信号，以第二预设传输速度输出各像素的数据驱动信号和时钟触发信号；存储单元2221分别与信号处理器221和数模转换单元2222电连接；存储单元2221包括与一行像素230对应的多个存储子单元；各存储子单元对应存储信号处理器输出的位于同一行的各像素230的数据驱动信号；存储单元2221接收信号处理器221输出的各像素230的数据驱动信号，并根据时钟触发信号控制位于同一行的各像素230的数据驱动信号输出至数模转换单元2222，以使数模转换单元2222将各像素的数据驱动信号转换为显示驱动信号，并输出至与其电连接的数据驱动器2223；其中，数据驱动信号为数字信号，显示驱动信号为模拟信号；数据驱动器2223的输出端与各列像素230对应电连接，例如数据驱动器2223可通过与同一列像素230电连接数据信号线34实现与各列像素230的电连接；此时，数据驱动器2223能够以预设驱动时序，依次输出各行像素230的显示驱动信号至各像素230，以驱动各像素230进行画面显示。
其中，第一信号处理电路120的驱动控制器122每次输出P个像素的视频信号至第二信号处理电路220的信号处理器221的同时，还会输出行同步信号和数据写入控制信号至信号处理器221，以使信号处理器221能够根据行同步信号和数据写入控制信号区分各个像素230及各行像素的视频信号，并将各行像素的数据驱动信号输出至存储单元2221中进行存储。虽然驱动控制器122每次仅输出P个像素的视频信号，但是可以由驱动控制器输出的行同步信号和数据写入控制信号区分各像素的视频信号，如此桥接芯片10和屏体芯片20之间需设置P条用于传输P个像素的视频信号的信号线31以及一条用于传输行同步信号的信号线321，一条用于传输列同步信号的信号线323和一条用于传输数据写 入控制信号的信号线322，即在桥接芯片10和屏体芯片20之间设置P×i×j+3条信号线，以在驱动控制器122每次输出的视频信号对应的像素的数量较少时，能够减少电连接桥接芯片10和屏体芯片20信号线，从而简化驱动芯片的设计，确保驱动芯片各模块之间信号传输的准确性，进而有利于降低功耗，提高显示效果。其中，i为每个像素所包含的子像素的个数，j为每个视频信号的字节数；例如每个像素可以包括三个子像素像素，即i为3；每个视频信号可以为8bit，即j为8，此仅为示例性的说明，在能够实现本申请实施例的核心申请点的前提下，本申请实施例对i和j的取值不做具体限定。
同时，当存储单元2221将一行像素的数据驱动信号存储完成后，信号处理器221会输出相应的时钟触发信号至存储单元2221，以使存储单元2221能够同时输出一行像素的数据驱动信号至数模转换单元2222；数模转换单元2222能够将数据驱动信号转换为能够直接驱动各像素230的显示驱动信号，并经数据驱动器2223以预设驱动时序，输出至各行像素230，驱动各行像素230进行发光，显示各帧画面。
可选的，图6是本申请实施例提供的一种屏体芯片的结构示意图。结合图5和图6所示，存储单元2221包括垂直移位寄存器2201和锁存器2202；垂直移位寄存器2201包括与同一行的各像素230对应的多个垂直移位寄存单元22011；锁存器22021包括与同一行的各像素230对应的多个锁存单元22021。如此，信号处理器221输出的数据驱动信号能够依次存储于垂直移位寄存器2201的垂直移位寄存单元22011中，并在各垂直移位寄存单元22011均存储有对应的数据驱动信号时，信号处理器221输出相应的时钟触发信号至垂直移位寄存器2201，以使垂直移位寄存器2201中各垂直移位寄存单元22011同时输出数据驱动信号至锁存器2202的各锁存单元22021进行锁存。
图6仅为本申请实施例示例性的说明，图6中信号处理器221输出的数据驱动信号会先存储于垂直移位寄存器2201中，再输出至锁存器2202；而在本申请实施例中信号处理器输出的数据驱动信号，还可以先存储于锁存器中，再输出至垂直移位寄存器进行存储，本申请实施例对此不做具体限定。
可选的，继续结合参考图5和图6，数模转换单元2222包括数模转换器2203和伽马电压产生器2204；伽马电压产生器2204与数模转换器2203电连接；伽马电压产生器2204能够输出伽马电压至数模转换器2203，以使数模转换器2203、根据伽马电压和数据驱动信号，将各数据驱动信号一一对应地转换为显示驱动信号，并输出至与其电连接的数据驱动器2223中。
可选的，继续参考图5所示，第二信号处理电路220还包括行驱动器223；信号处理器221还与行驱动器223电连接；信号处理器221还接收驱动控制器122输出的列同步信号和数据写入控制信号，并根据列同步信号和数据写入控制信号，输出第一时钟控制信号至行驱动器223；行驱动器223的输出端与各行像素230对应电连接，例如位于同一行的像素可共用扫描信号线33，行驱动器223可通过各条扫描信号线与各行像素电连接；该行驱动器223能够根据第一时钟控制信号依次向各行像素230提供行驱动信号，以使各显示驱动信号对应写入各行像素230中。
本申请实施例所提及的像素可以为一个子像素或者为包括多个不同样的子像素的一个像素单元，在能够实现本申请实施例的核心申请点的前提下，本申请实施例对此不做具体限定。
可选的，继续参考图6所示，当每个像素230包括多个不同颜色的子像素(231、232、233)时，第二信号处理电路220还可以包括多个多路选通电路240和多条时钟信号线35；每个多路选通电路240包括多个开关单元241；同一多 路选通电路240的各开关单元241的输入端与数据处理电路222的同一显示驱动信号输出端电连接；同一多路选通电路240的各开关单元241的控制端与不同的时钟信号线35电连接；各开关单元241的输出端与各列子像素一一对应电连接。
示例性的，每个像素230可以包括不同颜色的三个子像素231、232和233，各子像素(231、232和233)的颜色例如可以包括但不限于红色、绿色和蓝色。此时，每个多路选通电路240可以包括三个开关单元241，每个开关单元241可以包括一晶体管；如此，当开关单元241的晶体管为NMOS时，与该开关单元241电连接的时钟信号线35传输的信号为高电平时，能够控制该开关单元241的晶体管导通，使得数据处理电路222输出的显示驱动信号能够通过导通的晶体管传输至对应列的子像素中；而当开关单元241的晶体管为PMOS时，与该开关单元241电连接的时钟信号线35传输的信号为低电平时，能够控制该开关单元241的晶体管导通，使得数据处理电路222输出的显示驱动信号能够通过导通的晶体管传输至对应列的子像素中。
相应的，数据处理电路222的时钟信号输出端与各时钟信号线35电连接；数据处理电路222能够输出不同的第二时钟控制信号至各时钟信号线35，以使各开关单元241在各第二时钟控制信号的控制下导通或断开，并在第二时钟控制信号控制开关单元241导通时，控制显示驱动信号一一对应地传输至各列子像素。
本申请实施例还提供一种显示屏，该显示屏包括本申请实施例提供的的驱动芯片，因此该显示屏包括本申请实施例提供的驱动芯片的技术特征以及具备本申请实施例提供的驱动芯片的有益效果，相同之处可参照上述对本申请实施例提供的驱动芯片的描述，在此不再赘述
示例性的，图7是本申请实施例提供的一种显示屏的结构示意图。如图7所示，显示屏200包括本申请实施例提供的驱动芯片100，该驱动芯片100的屏体芯片20的第二衬底210包括显示区201和围绕显示区201的非显示区202；该显示屏的像素230设置于显示区201，第二信号处理电路220设置于非显示区202；如此，该显示屏的像素和第二信号处理电路220可以设置于同一衬底210上，以能够简化显示屏的制备工艺，降低显示屏的生产成本。其中，该显示屏例如包括硅基显示屏。
本申请实施例还提供一种显示装置，该显示装置包括本申请实施例提供的显示屏，因此该显示装置具备本申请实施例提供的显示屏的技术特征和有益效果，相同之处可参照上述对本申请实施例提供的显示屏的描述，在此不再赘述。
示例性的，图8是本申请实施例提供的一种显示装置的结构示意图。如图8所示，该显示装置300例如可以为AR设备、VR设备等，本申请实施例对此不做具体限定。

Claims (15)

  1. 一种驱动芯片，用于驱动硅基显示屏，所述硅基显示屏包括M行N列像素；其中，M和N均为正整数；
    所述驱动芯片包括：桥接芯片和屏体芯片；所述桥接芯片包括第一衬底和设置于所述第一衬底一侧的第一信号处理电路；所述第一信号处理电路包括信号接口模块和驱动控制器；所述屏体芯片包括第二衬底和设置于所述第二衬底一侧的第二信号处理电路；所述第二信号处理电路包括信号处理器和数据处理电路；
    所述信号接口模块用于接收各帧画面的视频信号；
    所述驱动控制器与所述信号处理器电连接；所述驱动控制器用于以第一预设传输速度，控制每次输出一帧画面的视频信号中P个所述像素的视频信号至所述信号处理器；其中，P为正整数，且P＜N；
    所述信号处理器与所述数据处理电路电连接；所述信号处理器用于将各所述像素的视频信号转换为数据驱动信号，并以第二预设传输速度，每次输出一帧画面中Q个所述像素的数据驱动信号至所述数据处理电路；其中Q为正整数，且Q≤N；
    所述数据处理电路用于将所述数据驱动信号转换为显示驱动信号，并依次输出至各行像素，控制各所述像素进行画面显示。
  2. 根据权利要求1所述的驱动芯片，其中，所述第一预设传输速度大于所述第二预设传输速度，且P＜Q。
  3. 根据权利要求1所述的驱动芯片，其中，所述第一信号处理电路还包括数字信号解码器；
    所述数字信号解码器与所述信号接口模块电连接；所述数字信号解码器用于对所述信号接口模块接收的各帧画面的视频信号进行解码，并以第三预设传 输速度，每次输出一帧画面的视频信号中K个所述像素的视频信号；其中，所述第三预设传输速度大于所述第二预设传输速度，且K≤P，K为正整数。
  4. 根据权利要求3所述的驱动芯片，其中，所述第一信号处理电路还包括信号修正模块；
    所述信号修正模块分别与所述数字信号解码器和所述驱动控制器电连接；所述信号修正模块用于对每帧画面中各所述像素的视频信号进行色彩修正，以及对每帧画面的视频信号进行像素补偿。
  5. 根据权利要求4所述的驱动芯片，其中，所述信号修正模块包括伽马校正单元、饱和度灰度处理单元和边框像素补偿单元；
    其中，所述伽马校正单元、所述饱和度灰度处理单元以及所述边框像素补偿单元依次电连接。
  6. 根据权利要求1所述的驱动芯片，其中，所述数据处理电路包括存储单元、数模转换单元和数据驱动器；
    所述信号处理器还用于接收所述驱动控制器输出的行同步信号和数据写入控制信号，并根据所述行同步信号和所述数据写入控制信号，以第二预设传输速度输出各所述像素的数据驱动信号和时钟触发信号；
    所述存储单元分别与所述信号处理器和所述数模转换单元电连接；所述存储单元包括与一行所述像素对应的多个存储子单元；各所述存储子单元对应存储所述信号处理器输出的位于同一行的各所述像素的数据驱动信号；所述存储单元用于接收所述信号处理器输出的各所述像素的数据驱动信号，并根据所述时钟触发信号控制位于同一行的各所述像素的数据驱动信号输出至所述数模转换单元；
    所述数模转换单元与所述数据驱动器电连接；所述数模转换单元用于将各 所述像素的数据驱动信号转换为显示驱动信号，并输出至所述数据驱动器；其中，所述数据驱动信号为数字信号，所述显示驱动信号为模拟信号；
    所述数据驱动器的输出端与各列所述像素对应电连接；所述数据驱动器用于以预设驱动时序，依次输出各行像素的显示驱动信号至各像素，以驱动各所述像素进行画面显示。
  7. 根据权利要求6所述的驱动芯片，其中，所述存储单元包括垂直移位寄存器和锁存器；
    所述垂直移位寄存器包括与同一行的各所述像素对应的多个垂直移位寄存单元；所述锁存器包括与同一行的各所述像素对应的多个锁存单元。
  8. 根据权利要求6所述的驱动芯片，其中，所述数模转换单元包括数模转换器和伽马电压产生器；
    所述伽马电压产生器与所述数模转换器电连接；所述伽马电压产生器用于输出伽马电压至所述数模转换器；
    所述数模转换器分别与所述存储单元和所述数据驱动器电连接；所述数模转换器用于根据所述伽马电压和所述数据驱动信号，将各所述数据驱动信号一一对应地转换为所述显示驱动信号。
  9. 根据权利要求1所述的驱动芯片，其中，所述第二信号处理电路还包括行驱动器；
    所述信号处理器还与所述行驱动器电连接；所述信号处理器还用于接收所述驱动控制器输出的列同步信号和数据写入控制信号，并根据所述列同步信号和所述数据写入控制信号，输出第一时钟控制信号至所述行驱动器；
    所述行驱动器的输出端与各行所述像素对应电连接；所述行驱动器用于根据所述第一时钟控制信号依次向各行所述像素提供行驱动信号，以使各所述显 示驱动信号对应写入各行所述像素中。
  10. 根据权利要求1所述的驱动芯片，其中，每个所述像素包括多个不同颜色的子像素；
    所述第二信号处理电路还包括多个多路选通电路和多条时钟信号线；每个所述多路选通电路包括多个开关单元；同一所述多路选通电路的各所述开关单元的输入端与所述数据处理电路的同一显示驱动信号输出端电连接；同一所述多路选通电路的各所述开关单元的控制端与不同的时钟信号线电连接；各所述开关单元的输出端与各列所述子像素一一对应电连接；
    所述数据处理电路的时钟信号输出端与各所述时钟信号线电连接；所述数据处理电路还用于输出不同的第二时钟控制信号至各所述时钟信号线，以使各所述开关单元在各所述第二时钟控制信号的控制下导通或断开，并在所述第二时钟控制信号控制所述开关单元导通时，控制所述显示驱动信号一一对应地传输至各列子像素。
  11. 根据权利要求1所述的驱动芯片，还包括：连接器；
    所述连接器用于电连接所述桥接芯片与所述屏体芯片；和/或，所述连接器用于电连接所述桥接芯片与系统主板。
  12. 根据权利要求11所述的驱动芯片，其中，所述连接器包括印刷电路板或柔性电路板。
  13. 根据权利要求1所述的驱动芯片，其中，所述第一衬底和所述第二衬底均为硅基衬底。
  14. 一种显示屏，包括：权利要求1～13任一项所述的驱动芯片；
    所述屏体芯片的第二衬底包括显示区和围绕所述显示区的非显示区；所述像素设置于所述显示区，所述第二信号处理电路设置于所述非显示区。
  15. 一种显示装置，包括：权利要求14所述的显示屏。
PCT/CN2021/083264 2020-11-03 2021-03-26 驱动芯片、显示屏和显示装置 WO2022095328A1 (zh)

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