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WO2022082737A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2022082737A1
WO2022082737A1 PCT/CN2020/123266 CN2020123266W WO2022082737A1 WO 2022082737 A1 WO2022082737 A1 WO 2022082737A1 CN 2020123266 W CN2020123266 W CN 2020123266W WO 2022082737 A1 WO2022082737 A1 WO 2022082737A1
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WO
WIPO (PCT)
Prior art keywords
substrate
conductive layer
layer
display
connection pads
Prior art date
Application number
PCT/CN2020/123266
Other languages
English (en)
French (fr)
Inventor
王金良
伍蓉
王洋
王文超
李梁梁
朴相镇
王宝强
方鑫
胡安国
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/123266 priority Critical patent/WO2022082737A1/zh
Priority to CN202080002433.4A priority patent/CN114667481B/zh
Priority to US17/310,374 priority patent/US20220317508A1/en
Publication of WO2022082737A1 publication Critical patent/WO2022082737A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133354—Arrangements for aligning or assembling substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element

Definitions

  • the invention belongs to the field of display, and in particular relates to a display substrate, a manufacturing method of the display substrate, and a display device.
  • the full-screen display substrate includes a display area and a bonding area, the display area has a plurality of gate lines, and the bonding area has a plurality of connection pads for connecting external signals.
  • the metal layer of the grid lines faces the display side of the display panel. Therefore, if external light is irradiated on the grid lines, it will be reflected by the grid lines, thereby causing reflection to affect the display quality of the display device formed by the display substrate.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate, which can prevent grid lines from reflecting light, and can avoid abnormal identification of connection pads.
  • an embodiment of the present disclosure provides a display substrate having a display area and a bonding area located on at least one side of the display area; wherein the display substrate includes:
  • the first conductive layer includes a plurality of grid lines
  • a light shielding layer disposed on the side of the first conductive layer close to the substrate, and the orthographic projection of the light shielding layer on the substrate at least covers the orthographic projection of the plurality of grid lines on the substrate;
  • connection pads are arranged on the substrate at intervals and located in the bonding area; wherein at least part of the connection pads and the orthographic projection of the light shielding layer on the substrate do not overlap.
  • the grid lines can be effectively prevented from reflecting light; and, since there is no light shielding layer provided under at least part of the connection pads, the light shielding layer is away from the substrate during the detection process.
  • the connection pads can be accurately identified.
  • the orthographic projections of the plurality of connection pads on the substrate do not overlap with the orthographic projections of the light shielding layer on the substrate.
  • the plurality of connection pads are disposed in the first conductive layer and are of the same material as the plurality of gate lines.
  • the plurality of connection pads include functional connection pads and redundant connection pads; wherein,
  • the orthographic projection of the redundant connection pad on the substrate does not overlap with the orthographic projection of the light shielding layer on the substrate;
  • the orthographic projection of the functional connection pad on the substrate at least partially overlaps the orthographic projection of the light shielding layer on the substrate.
  • the display substrate further includes: an auxiliary electrode and a common electrode disposed on a side of the first conductive layer away from the substrate, and the two are disposed in sequence along a direction away from the substrate and are electrically connected; the Orthographic projections of the auxiliary electrode and the common electrode on the substrate at least partially overlap;
  • the redundant connection pad includes a first conductive part and a second conductive part which are arranged on the side of the first conductive layer away from the substrate and are electrically connected, and the first conductive part and the common electrode are in the same layer
  • the second conductive part and the auxiliary electrode are arranged in the same layer and have the same material.
  • the functional connection pad and the plurality of gate lines are disposed in the same layer and have the same material.
  • the display substrate further has a frame sealing area disposed around the display area, and the bonding area is disposed on at least one side of the frame sealing area away from the display area; the display substrate further includes : a plurality of first marks disposed on the substrate and in the bonding area; wherein,
  • the first mark has no overlap with the orthographic projection of the light shielding layer on the substrate.
  • the plurality of first marks and the plurality of gate lines are disposed in the same layer and of the same material.
  • the display substrate further includes: an auxiliary electrode and a common electrode arranged on a side of the first conductive layer away from the substrate, and the two are arranged in sequence along a direction away from the substrate and are electrically connected; Orthographic projections of the auxiliary electrode and the common electrode on the substrate at least partially overlap;
  • the first mark includes a third conductive part and a fourth conductive part which are provided on the side of the first conductive layer away from the substrate and are electrically connected, the third conductive part is provided on the same layer as the common electrode and The materials are the same; the fourth conductive part and the auxiliary electrode are arranged in the same layer and have the same material.
  • the display substrate further includes a plurality of fan-out traces arranged on the substrate at intervals, and one of the fan-out traces is connected to one of the connection pads correspondingly, and the fan-out traces are connected by the bonding pads.
  • the fixed area extends to the display area; wherein, the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the plurality of fan-out traces on the substrate.
  • an embodiment of the present disclosure further provides a method for fabricating a display substrate, which has a display area and a bonding area located on at least one side of the display area, wherein the method includes the following steps:
  • the first conductive layer is patterned, a plurality of gate lines are formed on the portion of the first conductive layer located in the display area, and the first conductive layer is located in the bonding Parts of the area form a plurality of connection pads, including:
  • the first conductive layer and the portion of the first conductive layer disposed in the display area close to the first conductive layer is exposed and developed to form the plurality of gate lines and the plurality of connection pads.
  • embodiments of the present disclosure further provide a method for fabricating a display substrate, which has a display area and a bonding area located on at least one side of the display area; wherein the plurality of connection pads include functional connection pads and redundant connection pads.
  • the remaining connection pads; the manufacturing method includes the following steps:
  • a plurality of the redundant connection pads are formed on the side of the first conductive layer facing away from the substrate.
  • the redundant connection pad includes a first conductive portion and a second conductive portion that are disposed on a side of the first conductive layer away from the substrate and are electrically connected; the first conductive portion and the second conductive portion are electrically connected.
  • a plurality of the redundant connection pads are fabricated on the side of the layer away from the substrate, which specifically includes:
  • a second conductive layer is formed on the side of the first conductive layer facing away from the substrate;
  • a third conductive layer is formed on the side of the second conductive layer away from the substrate;
  • an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display substrate.
  • FIG. 1 is a schematic plan view of a structure of an embodiment of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2 is one of cross-sectional views of an embodiment of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 3 is a cross-sectional view taken along the direction A-B in FIG. 1 .
  • FIG. 4 is a cross-sectional view taken along the C-D direction in FIG. 1 .
  • FIG. 5 is a cross-sectional view taken along the direction E-F in FIG. 1 .
  • FIG. 6 is a cross-sectional view taken along the G-H direction in FIG. 1 .
  • FIG. 7 is a schematic plan view of an embodiment of an auxiliary electrode of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic plan structure diagram of an embodiment of a common electrode of a display substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the distribution of some connection pads in another embodiment of the display substrate provided by the embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view taken along the K-L direction in FIG. 9 .
  • FIG. 11 is a second cross-sectional view of an embodiment of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 12 is a flowchart of an embodiment of a method for fabricating a display substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram (side view) of a manufacturing process of an embodiment of a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram (plan view) of a manufacturing process of an embodiment of a method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • FIG. 15 is a flowchart of another embodiment of a method for fabricating a display substrate provided by an embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram (side view) of a manufacturing process of another embodiment of the manufacturing method of the display substrate provided by the embodiment of the present disclosure.
  • Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes.
  • the regions illustrated in the figures have schematic properties and the shapes of regions illustrated in the figures are illustrative of the specific shapes of regions of elements and are not intended to be limiting.
  • FIG. 1 shows a top view of an example of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate has a display area Q1 and a bonding area Q2 on at least one side of the display area Q1 .
  • the display area Q1 has a plurality of sub-pixels 100 arranged in an array, and the bonding area Q2 has a plurality of connection pads 3.
  • the connection pads 3 are used to receive the signals transmitted by the external driving integrated circuit and transmit them to the display area.
  • Subpixel 100 The display substrate further includes a plurality of gate lines 2 extending along the first direction, and a plurality of data lines 5 extending along the second direction, and the intersection of the gate lines 2 and the data lines 5 defines regions of the sub-pixels 100 .
  • the first direction and the second direction can be any direction, as long as the first direction and the second direction are not parallel.
  • the first direction is used as the row direction of the sub-pixels 100 arranged in the array.
  • the second direction is the column direction of the sub-pixels 100 arranged in the array as an example for description.
  • the display substrate may further include a frame sealing area Q3, the frame sealing area Q3 is arranged around the display area Q1, the bonding area Q2 is arranged on at least one side of the frame sealing area Q3 away from the display area Q1, and the frame sealing area is used for setting
  • the frame sealant is used to seal the display substrate and the color filter substrate when they are assembled.
  • a driver integrated circuit such as a gate driver integrated array (Gate on Array, GOA)
  • GOA gate driver integrated array
  • the GOA can be arranged along the extending direction of the gate line 2, and is arranged at both ends of the gate line 2.
  • the gate line 2 is connected to the GOA at both ends and receives the scanning signal transmitted by the GOA.
  • the display substrate may adopt GOAs arranged on one side, that is, GOAs are arranged only at one end of the gate lines 2, or GOAs may be arranged on both sides, that is, GOAs are arranged at both ends of the gate lines 2, which is not limited here.
  • the display substrate adopts the GOA arranged on both sides as an example for description.
  • the position of the bonding area Q2 of the display substrate is also different according to the different setting positions of the driving integrated circuits.
  • S-IC When the data lines 5 are driven, two sides of the display substrate opposite to both ends of the gate lines 2 and one side of the display substrate opposite to either end of the data lines 5 can be set as bonding regions Q2.
  • the display substrate adopts GOA to drive the gate line 2 only one side of the display substrate opposite to either end of the data line 5 is used as the bonding area Q2 .
  • the following description is given by taking the display substrate having one bonding area Q2 and the bonding area Q2 being disposed on the upper side of the display substrate as an example, but the embodiment of the present disclosure is not limited.
  • FIG. 2 is an example of a cross-sectional view of a display substrate provided in this embodiment.
  • the display substrate provided by an embodiment of the present disclosure includes a substrate 1 and a first conductive layer on the substrate 1 , The first conductive layer is located in the display area Q1, and the first conductive layer includes a plurality of gate lines 2, and the plurality of gate lines 2 are connected to the GOAs on both sides.
  • the display substrate also includes a light-shielding layer 4, which is arranged on the side of the first conductive layer close to the substrate 1.
  • the plurality of grid lines 2 will reflect the external light, thereby causing the display device composed of the display substrate. Therefore, setting the light shielding layer 4 on the side of the grid line 2 close to the substrate 1 can avoid the reflection phenomenon caused by the grid line 2, that is to say, the orthographic projection of the light shielding layer 4 on the substrate 1 covers at least a plurality of grid lines 2. Orthographic projection on substrate 1.
  • the display substrate further includes a plurality of connection pads 3, the plurality of connection pads 3 are arranged on the substrate 1 at intervals, and the plurality of connection pads 3 are located in the bonding area Q2, and the bonding
  • the area Q2 includes a plurality of sub-areas Q21 arranged side by side, and each sub-area Q21 corresponds to a connector, that is to say, the plurality of connection pads 3 are divided into multiple groups, and each sub-area Q21 is provided with a group of connection pads 3, connecting the Pad 3
  • the connection pad 3 is an exposed electrode. One end of a set of connection pads 3 is connected to each pin package in a connector, and the other end is connected to each data line 5 or GOA in the display area Q1.
  • An integrated driver circuit (eg, a source driver circuit) is connected to each pin of the connector, and transmits signals to the connection pads 3 through the connector.
  • the connector can be various types of connectors, such as a chip on film (Chip On Flex, COF) connector, or a chip on glass (Chip On Glass, COG) connector, etc., each set of connection pads 3.
  • ACF glue anisotropic conductive glue
  • connection pads 3 are usually arranged in the same layer and of the same material as the plurality of gate lines 2, that is to say, the connection pads 3 are arranged in the first conductive layer and are arranged in the same layer as the plurality of gate lines 2. 2 It is made of the same film layer, so usually a light-shielding layer 4 is formed on the substrate 1, and then a first conductive layer is formed on the side of the light-shielding layer 4 away from the substrate 1, and then the first conductive layer is patterned to form a plurality of grids Line 2 and a plurality of connection pads 3, so that there is also a light shielding layer 4 below the connection pads 3.
  • the camera detects the image of the connecting pads 3 through the side of the substrate 1 away from the connecting pads 3, so as to observe the pressure of the ACF glue.
  • the light shielding layer 4 is provided between the connection pad 3 and the substrate 1, the connection pad 3 cannot be observed.
  • the orthographic projection of at least part of the connection pads 3 on the substrate 1 does not overlap with the orthographic projection of the light shielding layer 4 on the substrate 1 .
  • the camera can observe the pressing quality of each connection pad 3 of the plurality of connection pads 3 from the side of the substrate 1 away from the connection pad 3; 4
  • the orthographic projection on the substrate 1 does not overlap, that is, there is no light shielding layer 4 under the part of the connection pad 3, then the camera can observe the part of the connection pad 3 without the light shielding layer 4 from the side of the substrate 1 away from the connection pad 3. Since a plurality of connection pads 3 are pressed in the same process, the difference in the quality of each connection pad 3 is small. Therefore, all connections can be judged by the quality of some connection pads 3. Bonding quality of pad 3.
  • the following takes the embodiment of observing the pressing quality of all the connection pads 3 as an example, referring to FIG. 1 to FIG. 6 , the orthographic projections of all the connection pads 3 on the substrate 1 are the same as the light-shielding layer 4 on the substrate 1 .
  • the orthographic projections on are non-overlapping.
  • the plurality of connection pads 3 are arranged in the first conductive layer, that is, the plurality of connection pads 3 and the plurality of gate lines 2 are arranged in the same layer and of the same material.
  • the difference is that the connection between the plurality of gate lines 2 and the substrate 1 is There is also a light shielding layer 4 in between, and the connection pads 3 are directly formed on the substrate 1 . Referring to FIG. 3 , FIG.
  • FIG. 3 is a cross-sectional view of FIG. 1 taken along the A-B direction at the gate line 2 in the display area Q1 .
  • a light shielding layer 4 is provided between the gate line 2 and the substrate 1 to prevent the gate line 2 from reflecting light.
  • FIG. 4 is a cross-sectional view taken along the C-D direction at the connection pad 3 in the bonding area Q2, the light shielding layer 4 is not provided between the connection pad 3 and the substrate 1, and the connection pad 3 is connected to the gate line. 2 is formed directly on the substrate 1 using the same material. As a result, the quality of pressing of each connection pad 3 can be directly observed from the side of the substrate 1 facing away from the connection pads 3 .
  • the display substrate further includes a gate insulating layer 01 disposed on the side of the first conductive layer (the layer where the connection pad 3 and the gate line 2 are located) away from the substrate 1; the gate insulating layer 01
  • An active layer 04 is provided on the side away from the substrate 1; the active layer 04 has a source electrode 05 and a drain electrode 06 on the side away from the substrate 1, the source electrode 05 and the drain electrode 06 are arranged in the same layer and have the same material, and the gate and the gate are insulated.
  • Layer 01, active layer 04, source electrode 05, and drain electrode 06 form a thin film transistor. Each film layer of the thin film transistor is only arranged in the display area Q1.
  • each sub-pixel 100 has a thin film transistor, and a gate line 2 is connected in the same row.
  • the thin film transistor of the sub-pixel 100, a data line 5 is connected to the thin film transistor of the sub-pixel 100 in the same column;
  • the source electrode 05 and the drain electrode 06 have a flat layer 03 on the side away from the substrate 1, and the flat layer 03 can be made of an organic film (ORG film), the flat layer 03 flattens the top layer of the thin film transistor to form a subsequent film layer;
  • the flat layer 03 is provided with a pixel electrode 07 on the side away from the substrate 1, and the pixel electrode 07 is connected to the drain through the via hole in the flat layer 03 06;
  • the side of the pixel electrode 07 away from the substrate 1 is provided with a protective layer 02 for protecting each film layer of the thin film transistor.
  • the protective layer 02 of the display substrate faces away from the substrate 1 , and is located in the display area Q1 with a common electrode 002 , the common electrode 002 is disposed opposite the pixel electrode 07 , and the common electrode 002 is on the substrate 1
  • the orthographic projection of the pixel electrode 07 and the orthographic projection of the pixel electrode 07 on the substrate 1 have an overlapping area, the common electrode 002 receives the common voltage, and the pixel electrode 07 receives the data voltage provided by the data line 5, so that an electric field is generated between the common electrode 002 and the data line 5,
  • the display substrate and the color filter substrate are assembled to form a display device, and the liquid crystal is poured between the display substrate and the color filter substrate, the electric field between the common electrode 002 and the data line 5 can change the deflection angle of the liquid crystal molecules in the liquid crystal, thereby enabling The transmittance of light is changed. Therefore, by controlling the voltage between the common electrode 002 and the pixel electrode 07,
  • FIG. 8 is a top view of the part where the common electrode 002 covers the sub-pixels in the 3 ⁇ 3 array.
  • the electrode, the common electrode 002 has a plurality of slits 021, and the electric field of the pixel electrode 07 can pass through the slits 021 to form an electric field with the common electrode 002.
  • a pixel opening P can be provided on the common electrode 002 corresponding to the area of the sub-pixel 100, so that the thin film transistor of the sub-pixel 100 is exposed.
  • the orthographic projection on the substrate 1 coincides with the orthographic projection of the thin film transistor (especially the gate electrode) on the substrate 1 .
  • Both the common electrode 002 and the pixel electrode 07 can be made of indium tin oxide (ITO), which increases the light transmittance of the sub-pixel 100, but the resistivity of ITO is relatively large, which will cause the common electrode 002 at each sub-pixel 100 on the display substrate to be formed.
  • ITO indium tin oxide
  • an auxiliary electrode 001 can be provided on the side of the common electrode 002 close to the substrate 1, and the auxiliary electrode 001 and the common electrode 002 are stacked.
  • auxiliary electrode 001 covers the 3 ⁇ 3 array of sub-pixels
  • the auxiliary electrode 001 is arranged around the pixel opening P on the corresponding common electrode 002
  • the auxiliary electrode 001 covers a plurality of gate lines 2 and a plurality of data lines 5, in order to reduce the resistance of the gate line 2 and the data line 5 and reduce the signal loss.
  • the auxiliary electrode 001 is only provided under a partial area of the common electrode 002 , and the common electrode 002 covers the auxiliary electrode 001 , that is, the common electrode 002 covers the top surface and the two sides of the auxiliary electrode 001 . Therefore, in the process of preparing the display substrate, a film of the auxiliary electrode 001 is formed on the side of the flat layer 02 away from the substrate 1, the auxiliary electrode 001 is patterned, and then the film of the common electrode 002 is formed, and then exposed to The common electrode 002 is patterned by developing and etching processes.
  • the common electrode 002 can cover the auxiliary electrode 001 .
  • the display panel provided by this public embodiment further includes a plurality of first marks 6 arranged in the frame area Q3, and the plurality of first marks 6 are arranged in the frame area Q3, for example , can be arranged at the four corners of the sealing frame area Q3, so that when the display substrate and the color filter substrate are assembled, the first marks 6 can be used for alignment.
  • the first mark 6 is usually arranged in the same layer and of the same material as the plurality of gate lines 2, that is to say, the first mark 6 is arranged in the first conductive layer, which is different from the plurality of gate lines 2.
  • the grid line 2 is made of the same film layer, so usually a light-shielding layer 4 is formed on the substrate 1, and then a first conductive layer is formed on the side of the light-shielding layer 4 away from the substrate 1, and then the first conductive layer is patterned to form A plurality of gate lines 2 , a plurality of first marks 6 , and a plurality of connection pads 3 , so that there is also a light shielding layer 4 under the first marks 6 .
  • the first mark 6 needs to be identified from the side of the substrate 1 away from the first mark 6, but since the light shielding layer 4 is provided between the first mark 6 and the substrate 1, the first mark 6 cannot be identified. .
  • the orthographic projection of the first mark 6 on the substrate 1 does not overlap with the orthographic projection of the light shielding layer 4 on the substrate 1 (as shown in FIG. 2 ), so that the camera
  • Each of the first marks 6 of the plurality of first marks 6 can be recognized from the side of the substrate 1 facing away from the first marks 6 .
  • the orthographic projection of the first mark 6 on the substrate 1 does not overlap with the orthographic projection of the light shielding layer 4 on the substrate 1 .
  • the plurality of first marks 6 are arranged in the first conductive layer, that is, the plurality of first marks 6 and the plurality of gate lines 2 are arranged in the same layer and of the same material. The difference is that the plurality of gate lines 2 and the substrate 1 are connected There is also a light shielding layer 4 in between, and the first marks 6 are directly formed on the substrate 1 , so that each first mark 6 can be accurately identified directly from the side of the substrate 1 away from the first mark 6 .
  • the display substrate provided in this embodiment further includes a plurality of second marks 7 , each sub-region Q21 includes a group of connection pads 3 , and a group of connection pads 3 is connected to a connector, Each group of connection pads 3 is connected with two second marks 7 .
  • the second marks 7 are respectively connected to the outer sides of the two outermost connection pads in each group of connection pads 3 , and are used to determine the connection between the connector and the connection. After bonding pad 3, the crimping state of the conductive gold ball in the ACF glue.
  • the structure of the second mark 7 is the same as that of the first mark 6 , and the orthographic projection of the second mark 6 on the substrate 1 does not overlap with the orthographic projection of the light shielding layer 4 on the substrate 1 , so that the second mark 7 can be directly away from the substrate 1
  • Each second marking 7 is precisely identified on one side.
  • the plurality of second marks 7 are arranged in the first conductive layer, that is, the plurality of second marks 7 are arranged in the same layer and of the same material as the plurality of grid lines 2 , the difference is that the plurality of grid lines 2 and the substrate 1 are connected There is also a light shielding layer 4 in between, and the second mark 7 is directly formed on the substrate 1 .
  • the display substrate provided in this embodiment further includes a plurality of fan-out (Fanout) traces 8 , the plurality of fan-out traces 8 are arranged on the substrate at intervals, and one fan-out trace 8 Correspondingly connected to a connection pad 3, one end of the fan-out trace 8 is connected to a connection pad 3 (as shown in Figure 2), and the other end extends from the bonding area Q2 to the display area Q1, and the GOA or data in the display area Q1. Line 5 is connected.
  • Fanout Fan-out
  • the film layer structure of the fan-out traces 8 is the same as that of the gate traces 2 , that is, the orthographic projection of the light shielding layer 4 on the substrate 1 covers the orthographic projections of the multiple fan-out traces 8 on the substrate 1 .
  • the fan-out wiring 8 and the gate line 2 are provided in the same layer and made of the same material, and a light shielding layer 4 is also provided between the fan-out wiring 8 and the substrate 1 .
  • the film layer structures of the first marks 6, the second marks 7, etc. are the same as the connection pads 3, and the first marks 6 and the second marks 7 are on the substrate
  • the orthographic projection on 1 and the orthographic projection of the light-shielding layer 4 on the substrate 1 do not overlap;
  • the film structure of the fan-out trace 8 is the same as that of the grid line 2, and the orthographic projection of the fan-out trace 8 on the substrate 1 is the same as that of the light-shielding layer 4.
  • the orthographic projections on substrate 1 overlap.
  • the first mark 6 may include any mark set in the sealing area Q3, for example, the first mark 6 may be at least one of a cutting mark, a grinding mark, a process mark, an overlap mark, and a total pitch mark.
  • the shapes of the marks such as the first mark 6 or the second mark 7 may include various shapes, such as a cross, a T-shape, a rectangle, a circle, a triangle and the like.
  • the first mark 6 is cross-shaped and the second mark 7 is T-shaped as an example, but the present invention is not limited.
  • the light-shielding layer 4 can be made of various materials.
  • the light-shielding layer 4 is made of molybdenum oxide, which is black and can effectively absorb and illuminate the gate lines 2 . light on.
  • the light shielding layer 4 can also be made of other types of materials, which are not limited here.
  • FIG. 9 is an exemplary distribution diagram of the connection pads connected by a connector
  • FIG. 10 It is a sectional view taken along the K-L direction of FIG. 9 .
  • the plurality of connection pads 3 in the bonding area Q2 include functional connection pads 31 and redundant connection pads 32, and the functional connection pads 31 and the redundant connection pads 32.
  • the pads 32 are all arranged on the substrate 1, and usually external signals are only input to the functional connection pads 31, that is to say, the pins of the connector are only connected to the functional connection pads 31, and the functional connection pads 31 are also connected to the display area Q1.
  • the data line 5 or the GOA is connected, or is connected through the fan-out trace 8, and the redundant connection pad 32 is an empty electrode, which is not connected to the pin of the connector and does not receive any electrical signal. Since the signals received by the plurality of functional connection pads 31 include positive signals and negative signals (eg, positive data voltage and negative data voltage input to the data line 5 ), in order to ensure that the functional connection pads 31 receiving positive and negative signals Therefore, at least one vacant redundant connection pad 32 is set between the functional connection pad 31 receiving the positive signal and the functional connection pad 31 receiving the negative signal to separate the function receiving the positive signal.
  • the redundant connection pad 32 is an empty electrode, which is not connected to the pin of the connector and does not receive any electrical signal. Since the signals received by the plurality of functional connection pads 31 include positive signals and negative signals (eg, positive data voltage and negative data voltage input to the data line 5 ), in order to ensure that the functional connection pads 31 receiving positive and negative signals Therefore, at least one vacant redundant connection pad 32 is set between the functional connection pad 31 receiving the positive signal and the functional connection pad
  • the orthographic projection of the redundant connection pads 32 on the substrate 1 does not overlap with the orthographic projection of the light shielding layer 4 on the substrate 1
  • the orthographic projection of the functional connection pads 31 on the substrate 1 does not overlap the light shielding layer 4
  • the orthographic projections on the substrate 1 are at least partially overlapped, that is, the light shielding layer 4 is only provided under the functional connection pads 31 in the bonding region Q2 , and no light shielding layer is provided under the redundant connection pads 32 .
  • the light-shielding layer 4 is disposed on the side of the functional connection pad 31 close to the substrate 1 , and the pattern of the light-shielding layer 4 can be consistent with the pattern of the functional connection pad 32 , that is, the positive direction of the functional connection pad 31 on the substrate 1
  • the projection and the orthographic projection of the light shielding layer 4 on the substrate 1 may completely overlap. Therefore, the pressing quality of each redundant connecting pad 32 can be observed on the side of the substrate 1 away from the connecting pad 3 . By observing the pressing quality of the redundant connecting pads 32 , the overall functional connecting pad can be judged. 31 and the bonding quality of the redundant connection pads 32.
  • FIG. 11 is a cross-sectional view of the display substrate corresponding to the embodiment of FIG. 9 .
  • the display substrate includes a base 1, a light shielding layer 4 disposed on the base 1, and a first conductive layer on the side of the light shielding layer 4 away from the base.
  • the part of the layer located in the bonding area Q1 includes a plurality of functional connection pads 31, and the orthographic projection of the light shielding layer 4 on the substrate 1 covers the orthographic projection of the plurality of gate lines 2 and the plurality of functional connection pads 31 on the substrate 1,
  • the light shielding layer 4 is arranged on the side of the gate line 2 close to the substrate 1 , which can prevent the gate 2 from reflecting light.
  • the display substrate also includes a gate insulating layer 01 disposed on the side of the first conductive layer (the layer where the functional connection pad 31 and the gate line 2 are located) away from the substrate 1; the gate insulating layer 01 is provided with an active layer 04 on the side away from the substrate 1 ;
  • the active layer 04 has a source electrode 05 and a drain electrode 06 on the side away from the substrate 1, the source electrode 05 and the drain electrode 06 are arranged in the same layer and have the same material, the gate electrode, the gate insulating layer 01, the active layer 04, the source electrode 05
  • the drain electrode 06 forms a thin film transistor, and each film layer of the thin film transistor is only arranged in the display area Q1.
  • the gate of the thin film transistor and the gate line 2 are formed in the same film layer, and the gate line 2 is connected to the gate.
  • the reference number 2 in FIG. 2 can be regarded as the position of the gate; in the display substrate, each sub-pixel 100 has a thin film transistor, a gate line 2 is connected to the thin film transistor of the sub-pixels 100 in the same row, and a data line 5.
  • Connect the thin film transistors of the sub-pixels 100 in the same column; the source 05 and the drain 06 have a flat layer 03 on the side away from the substrate 1.
  • the flat layer 03 can be an organic film (ORG film), and the flat layer 03 connects the top layer of the thin film transistor.
  • a pixel electrode 07 is provided on the side of the flat layer 03 facing away from the substrate 1, and the pixel electrode 07 is connected to the drain 06 through the via hole in the flat layer 03; the pixel electrode 07 is on the side facing away from the substrate 1
  • a protective layer 02 is provided for protecting each film layer of the thin film transistor.
  • the protective layer 02 of the display substrate faces away from the substrate 1 , and is located in the display area Q1 with a common electrode 002 , the common electrode 002 is disposed opposite the pixel electrode 07 , and the common electrode 002 is on the substrate 1
  • the orthographic projection of the pixel electrode 07 and the orthographic projection of the pixel electrode 07 on the substrate 1 have an overlapping area, the common electrode 002 receives the common voltage, and the pixel electrode 07 receives the data voltage provided by the data line 5, so that an electric field is generated between the common electrode 002 and the data line 5,
  • the display substrate and the color filter substrate are assembled to form a display device, and the liquid crystal is poured between the display substrate and the color filter substrate, the electric field between the common electrode 002 and the data line 5 can change the deflection angle of the liquid crystal molecules in the liquid crystal, thereby enabling The transmittance of light is changed. Therefore, by controlling the voltage between the common electrode 002 and the pixel electrode 07,
  • FIG. 8 is a top view of the part where the common electrode 002 covers the sub-pixels in the 3 ⁇ 3 array.
  • the electrode, the common electrode 002 has a plurality of slits 021, and the electric field of the pixel electrode 07 can pass through the slits 021 to form an electric field with the common electrode 002.
  • a pixel opening P can be provided on the common electrode 002 corresponding to the area of the sub-pixel 100, so that the thin film transistor of the sub-pixel 100 is exposed.
  • the orthographic projection on the substrate 1 coincides with the orthographic projection of the thin film transistor (especially the gate electrode) on the substrate 1 .
  • Both the common electrode 002 and the pixel electrode 07 can be made of indium tin oxide (ITO), which increases the light transmittance of the sub-pixel 100, but the resistivity of ITO is relatively large, which will cause the common electrode 002 at each sub-pixel 100 on the display substrate to be formed.
  • ITO indium tin oxide
  • an auxiliary electrode 001 can be set on the side of the common electrode 002 close to the substrate 1, and the auxiliary electrode 001 and the common electrode 002 are set on the first conductive layer away from the substrate 1.
  • FIG. 7 is a top view of the part where the auxiliary electrode 001 covers the 3 ⁇ 3 array of sub-pixels, the auxiliary electrode 001 is arranged around the pixel opening P on the corresponding common electrode 002, and the auxiliary electrode 001 covers a plurality of gate lines 2 and a plurality of data lines 5, in order to reduce the resistance of the gate line 2 and the data line 5 and reduce the signal loss.
  • the auxiliary electrode 001 is only provided under a partial area of the common electrode 002 , and the common electrode 002 covers the auxiliary electrode 001 , that is, the common electrode 002 covers the top surface and the two sides of the auxiliary electrode 001 . Therefore, in the process of preparing the display substrate, a film of the auxiliary electrode 001 is formed on the side of the flat layer 02 away from the substrate 1, the auxiliary electrode 001 is patterned, and then the film of the common electrode 002 is formed, and then exposed to , developing and etching processes to pattern the common electrode 002.
  • the common electrode 002 can cover the auxiliary electrode 001 .
  • the redundant connection pads 32 may be prepared by using an electrode layer on the same layer as the auxiliary electrode 001 and an electrode layer on the same layer as the common electrode 002 . It should be noted that, in FIG. 11 , in order to facilitate the illustration of the positional relationship of the film layers where the functional connection pads 31 and the redundant connection pads 32 are located, the functional connection pads 31 and the redundant connection pads 32 are simultaneously shown in the same cross-sectional view. There are redundant connection pads 32, but if it is cut from a functional connection pad 31, there is no redundant connection pad 32 above the functional connection pad 31.
  • each redundant connection pad 32 includes a first conductive portion 321 and a second conductive portion 322 disposed on the side of the first conductive layer away from the substrate 1 , and the first conductive portion 321 and the second conductive portion 322 are electrically
  • the first conductive part 321 located in the bonding area Q2 and the common electrode 002 located in the display area Q1 are arranged in the same layer and of the same material, that is, the first conductive part 321 and the common electrode 002 are prepared by the same film layer process;
  • the second conductive part 322 located in the bonding area Q2 and the auxiliary electrode 001 located in the display area Q1 are arranged in the same layer and made of the same material, that is, the second conductive part 322 and the auxiliary electrode 001 are prepared by the same film layer process, and are redundantly
  • the pressing quality of the redundant connecting pads 32 is determined, so as to judge the pressing quality of the entire connecting pads 3 (including the functional connecting pads 31 and the redundant connecting pads 32 ).
  • the redundant connection pads 32 can also be prepared by using other conductive film layers, which are not limited herein.
  • the functional connection pads 31 can be arranged in the first conductive layer, that is, the functional connection pads 31 and the plurality of gate lines 2 (also with the gates) are arranged in the same layer and made of material. The same, and there is a light shielding layer 4 under the functional connection pad 31 .
  • the functional connection pads 31 can also be prepared by using other conductive film layers, which are not limited herein.
  • the display substrate of the embodiment of the present disclosure further includes a plurality of first marks 6 arranged in the sealing area Q3 . 1, resulting in the problem that the first mark 6 cannot be recognized from the side of the substrate 1 away from the first mark 6.
  • the orthographic projections on the substrate 1 do not overlap (as shown in FIG. 2).
  • the first mark 6 can also be prepared by using other conductive film layers.
  • the first mark 6 includes a third conductive portion 62 and a fourth conductive portion 61 disposed on the side of the first conductive layer away from the substrate 1 , and the third conductive portion 62 and the fourth conductive portion 61 are electrically connected, and the third conductive portion 62 and the fourth conductive portion 61 are electrically connected.
  • the conductive portion 62 and the common electrode 002 are provided on the same layer and made of the same material, that is to say, the third conductive portion 62 and the common electrode 002 are prepared by the same film layer process, and the fourth conductive portion 61 and the auxiliary electrode 001 are provided on the same layer and made of the same material.
  • the fourth conductive portion 61 and the auxiliary electrode 001 are prepared by the same film layer process.
  • the light shielding layer 4 is not disposed under the third conductive portion 62 and the fourth conductive portion 61 of the first mark 6 , so that each first mark 6 can be accurately identified directly from the side of the substrate 1 away from the first mark 6 .
  • the display substrate provided in this embodiment further includes a plurality of second marks 7 , each sub-region Q21 includes a group of connection pads 3 , and a group of connection pads 3 is connected to a connector, Each group of connection pads 3 is connected to two second marks 7, specifically, the second marks 7 are respectively connected to the outermost two connection pads 3 (functional connection pads 31 or redundant connection pads 3) in each group of connection pads 3.
  • the outer side of the connection pad 32) is used to judge the crimping state of the conductive gold ball in the ACF glue after the connector and the connection pad 3 are bonded.
  • the structure of the second mark 7 is the same as that of the first mark 6 , and the orthographic projection of the second mark 6 on the substrate 1 does not overlap with the orthographic projection of the light shielding layer 4 on the substrate 1 , so that the second mark 7 can be directly away from the substrate 1
  • Each second marking 7 is precisely identified on one side.
  • the plurality of second marks 7 include a fifth conductive part and a sixth conductive part arranged in layers, and the fifth conductive part and the common electrode 002 are provided in the same layer and made of the same material, that is, the fifth conductive part and the common electrode 002 is prepared by the same film layer process, the sixth conductive part and the auxiliary electrode 001 are arranged in the same layer and made of the same material, that is to say, the sixth conductive part and the auxiliary electrode 001 are prepared by the same film layer process.
  • the display substrate provided in this embodiment further includes a plurality of fanout lines 8 , the plurality of fanout lines 8 are arranged on the substrate 1 at intervals, and one fanout line 8 8 is connected to a functional connection pad 31 correspondingly, one end of the fan-out trace 8 is connected to a functional connection pad 31 (as shown in FIG. 11 ), and the other end extends from the bonding area Q2 to the display area Q1, and is connected to the display area Q1.
  • GOA or data line 5 connection is shown in FIG. 11 .
  • the film layer structure of the fan-out traces 8 is the same as that of the gate traces 2 , that is, the orthographic projection of the light shielding layer 4 on the substrate 1 covers the orthographic projections of the multiple fan-out traces 8 on the substrate 1 .
  • the fan-out wiring 8 and the gate line 2 are provided in the same layer and made of the same material, and a light shielding layer 4 is also provided between the fan-out wiring 8 and the substrate 1 .
  • the film layer structures of the first marks 6 and the second marks 7 are the same as the redundant connection pads 32 , and the first marks 6 and the second marks 7
  • the orthographic projection on the substrate 1 does not overlap with the orthographic projection of the light-shielding layer 4 on the substrate 1;
  • the film layer structure of the fan-out trace 8 is the same as that of the gate wire 2 and the functional connection pad 31, and the fan-out trace 8 is on the substrate 1.
  • the orthographic projection on the substrate 1 overlaps with the orthographic projection of the light shielding layer 4 on the substrate 1 .
  • the first mark 6 may include any mark set in the sealing area Q3, for example, the first mark 6 may be at least one of a cutting mark, a grinding mark, a process mark, an overlap mark, and a total pitch mark.
  • the light-shielding layer 4 can be made of various materials.
  • the light-shielding layer 4 is made of molybdenum oxide, which is black and can effectively absorb and illuminate the gate lines 2 . light on.
  • the light shielding layer 4 can also be made of other types of materials, which are not limited here.
  • the material of the gate line 2 in the first conductive layer may be copper, molybdenum niobium, tin, aluminum and other materials. Taking copper as an example for the gate line 2 for illustration, the gate line 2 (also the first conductive layer)
  • the thickness of the film layer can be 1000-2000 Angstroms, and the film thickness of the light shielding layer 4 can be 400-500A.
  • the thin film transistor in this embodiment may be a top-gate thin film transistor or a bottom-gate thin film transistor, and the film layer where the gate of the thin film transistor is located (that is, the first conductive layer where the gate line 2 is located)
  • the structure of the same layer (for example, the functional connection pad 31 ) may be changed with the position of the gate.
  • the above descriptions are made by taking the thin film transistor as a bottom-gate thin film transistor as an example, but the present application is not limited.
  • an embodiment of the present disclosure further provides a method for manufacturing a display substrate.
  • the method for manufacturing a display substrate in this embodiment can be used to form the above-mentioned display substrate to form the display substrate shown in FIG. 2 .
  • the film layer structure of the display substrate shown in FIG. 2 has been described above, and will not be repeated here.
  • the structure of the display substrate formed by the manufacturing method of this embodiment is not limited to the display substrate shown in FIG. 2 .
  • the display substrate has a display area Q1, a bonding area Q2 located on at least one side of the display area Q1, and may also have a frame sealing area Q3 arranged around the display area Q1, and the bonding area Q2 is arranged on the sealing frame area Q3 away from the display area Q1. at least one side.
  • Figure 13 is a side view of the flow chart of each production step
  • Figure 14 is a plan view of the flow chart corresponding to each production step of Figure 13, the production method includes the following steps:
  • the light-shielding layer 4 adopts molybdenum oxide as an example for illustration.
  • molybdenum oxide is sputtered on the substrate 1 by a sputtering process to form a layer covering the substrate. 1 of the light-shielding layer 4.
  • the light shielding layer 4 is preliminarily patterned through a mask, specifically, exposure, development, and etching may be performed. The process removes the part of the light-shielding layer 4 covering the bonding area Q2 to form the light-shielding layer 4 of the display substrate as shown in FIG. identification of the connection pads 3.
  • the position of the substrate 1 corresponding to the frame sealing area Q3 may also have a plurality of first marks 6 to pattern the light shielding layer 4, including removing the light shielding layer 4 at the position where the first marks 6 are to be set in the frame sealing area Q3, i.e.
  • a plurality of hollow parts 63 are made, and each hollow part 63 is the position where the first mark 6 is subsequently formed, so as to ensure that there is no light-shielding layer 4 between the first mark 6 and the substrate 1,
  • the first marking 6 can thus be recognized from the side of the substrate 1 facing away from the first marking 6 . It should be noted that, since the encapsulation area Q3 has a part of the area where the fan-out traces 8 pass, the portion of the light shielding layer 4 located in the encapsulation area Q3 cannot be completely removed.
  • a layer of material of the first conductive layer D1 is sputtered by a sputtering process,
  • conductive materials such as copper, silver, molybdenum and niobium
  • the first conductive layer D1 covers the display area Q2
  • the connection pads 3 and the first marks 6 are also formed on the first conductive layer D1
  • the first conductive layer D1 also covers The sealing area Q3 and the bonding area Q2.
  • the first conductive layer D1 is disposed on the light shielding layer 4 without affecting the film formation quality of the first conductive layer D1 .
  • S14 may include:
  • the first conductive layer D1 is placed on the side of the first conductive layer D1 close to the substrate 1 through a mask made according to the pattern of the plurality of gate lines 2 and the plurality of connection pads 3, and only on the side of the first conductive layer D1.
  • the light shielding layer 4 in the display area Q1 is exposed, developed and etched to form a plurality of gate lines 2 located in the display area Q1 and a plurality of connection pads 3 located in the bonding area Q2, and a plurality of connection pads 3 connected to the connection pads 3 are formed.
  • the material of the first conductive layer D1 includes copper or molybdenum niobium
  • the material of the light shielding layer 4 includes The etching solution of molybdenum oxide, copper or molybdenum niobium can also act on molybdenum oxide, so the first conductive layer D1 and the light shielding layer 4 can be etched in the display area Q1 at the same time to form a plurality of patterns of grid lines 2 (as shown in Figure 14 ( d2) pattern), and can use the same mask to etch a plurality of connection pads 3 (as shown in Figure 14(d2)) and the connection pads connected to the part of the first conductive layer D1 in the bonding area Q2.
  • a plurality of first marks 6 are etched on the portion of the first conductive layer D1 located in the sealing frame region Q3 (as shown in FIG. 14(d2)).
  • a mask used only for etching the light shielding layer 4 can be omitted, and, compared to etching the light shielding layer 4 first, the first conductive layer is then etched.
  • the manufacturing method of D1 the manufacturing method provided by the embodiment of the present disclosure will not suffer from the problem of pattern dislocation caused by the drilling phenomenon when etching the light shielding layer 4 first, and the gate in the first conductive layer D1
  • the lines 2 can overlap the pattern of the light shielding layer 4 on the side of the grid lines 2 close to the substrate 1 as much as possible, thereby improving the fabrication accuracy.
  • the display substrate provided in this embodiment further includes a plurality of fan-out traces 8 and GOA circuits disposed in the sealing frame area Q2 at the edge of the display area Q1, and both the fan-out traces 8 and the GOA circuit have a light-shielding layer 4 under them, Therefore, in S14, patterning the first conductive layer D1 also includes using the above-mentioned mask to simultaneously perform the first conductive layer D1 and the light shielding layer 4 in the sealing area Q2 in the same process of etching the gate line 2. Etching to form a plurality of fan-out traces 8 and patterns of the GOA circuit.
  • the etching solution of copper or molybdenum-niobium can also act on the molybdenum oxide. At least one of components such as ammonium oxalate, hydrogen peroxide, and surfactant may be included. Of course, the copper etching solution may also include other components, which are not limited here.
  • the method for fabricating a display substrate further includes:
  • a gate insulating layer 01 is formed on the side of the first conductive layer D1 (the layer where the connection pad 3 and the gate line 2 are located) away from the substrate 1;
  • the film layer where the active layer 04 is located is formed on the side of the substrate 1, and the film layer is patterned to form the active layer 04; the film layer where the source electrode 05 and the drain electrode 06 are formed on the side of the active layer 04 away from the substrate 1,
  • the film layer is patterned to form a source electrode 05, a drain electrode 06 and a plurality of data lines 5.
  • the source electrode 05 and the drain electrode 06 are arranged in the same layer and have the same material;
  • Film flattening layer 03, the flattening layer 03 can use an organic film (ORG film), the flattening layer 03 flattens the top layer of the thin film transistor, so as to form the subsequent film layer; the flattening layer 03 is formed on the side away from the substrate 1.
  • ORG film organic film
  • the pixel electrode 07 is formed, The pixel electrode 07 is connected to the drain electrode 06 through the via hole in the flat layer 03; a protective layer 02 is formed on the side of the pixel electrode 07 away from the substrate 1 to protect each film layer of the thin film transistor; the protective layer 02 is away from the substrate 1 A film layer where the auxiliary electrode 001 is located is formed on one side, and the film layer is patterned to form an auxiliary electrode 001.
  • the auxiliary electrode 001 has a pixel opening P, and the auxiliary electrode 001 covers a plurality of gate lines 2 and data lines 5; The side of the electrode 001 facing away from the substrate 1 forms a film layer where the common electrode 002 is located, and the film layer is patterned to form the common electrode 002.
  • the common electrode 002 has a plurality of slits 021 and pixel openings P, and the slits 021 face the pixel electrode. 06.
  • the structure of the display substrate is not limited to this. For the convenience of description, the above description only takes the manufacturing process of the display substrate shown in FIG. 2 as an example.
  • an embodiment of the present disclosure further provides a method for manufacturing a display substrate.
  • the method for manufacturing a display substrate in this embodiment can be used to form the above-mentioned display substrate to form the display substrate shown in FIG. 11 .
  • the film layer structure of the display substrate shown in FIG. 11 has been described above, and will not be repeated here.
  • the structure of the display substrate formed by the manufacturing method of this embodiment is not limited to the display substrate shown in FIG. 11 .
  • the display substrate has a display area Q1, a bonding area Q2 located on at least one side of the display area Q1, and may also have a frame sealing area Q3 arranged around the display area Q1, and the bonding area Q2 is arranged on the sealing frame area Q3 away from the display area Q1. at least one side.
  • the bonding area has a plurality of connection pads 3, and the plurality of connection pads 3 include functional connection pads 31 and redundant connection pads 32. Usually, only external signals are input.
  • Functional connection pad that is to say, usually the pins of the connector are only connected to the functional connection pad 31, and the functional connection pad 31 is also connected to the data line 5 or GOA in the display area Q1, or through the fan-out trace 8 connection, while the redundant connection pad 32 is a vacant electrode that is not connected to the pins of the connector and does not receive any electrical signals.
  • Figure 16 is a side view of a flow chart of each fabrication step, the fabrication method comprising the following steps:
  • the light shielding layer 4 is made of molybdenum oxide as an example for illustration.
  • molybdenum oxide is sputtered on the substrate 1 through a sputtering process to form a light shielding layer 4 covering the substrate 1 .
  • the first conductive layer D1 as copper as an example, copper is sputtered on the side of the light shielding layer 4 away from the substrate 1 to form the first conductive layer D1 covering the substrate 1 .
  • the first conductive layer D1 and the light shielding layer 4 are patterned together through a mask made according to the pattern of the gate lines 2 and the functional connection pads 31 , after exposure, development, In the etching process, a plurality of gate lines are formed at the position of the display area Q1, and a plurality of functional connection pads 31 are formed at the position of the bonding area Q2.
  • the display substrate further includes a plurality of fan-out traces 8, GOA circuits, etc., which are arranged in the encapsulation area Q3.
  • the first conductive layer D1 and the light shielding layer 4 are patterned together, they are also formed in the encapsulation area Q3.
  • a number of fan-out traces 8 and GOA circuit graphics are created. That is to say, after S23, the orthographic projection of the light shielding layer 4 on the substrate 1 only covers the plurality of gate lines, the plurality of functional connection pads 31, the plurality of fan-out traces 8 and the GOA circuit pattern.
  • the manufacturing method of the layer D1 is not subject to the problem of pattern dislocation caused by the drilling phenomenon when the first conductive layer D1 is etched first, and the first conductive layer D1 is etched.
  • the gate line 2 , the multiple functional connection pads 31 , the multiple fan-out traces 8 and the GOA circuit pattern can overlap with the pattern of the light shielding layer 4 as much as possible, thereby improving the fabrication accuracy.
  • the method for fabricating the display substrate provided by the embodiment of the present disclosure further includes:
  • the gate insulating layer 01 is formed on the side of the first conductive layer D1 (the layer where the functional connection pad 31 and the gate line 2 are located) away from the substrate 1; the active layer 04 is formed on the side of the gate insulating layer 01 away from the substrate 1.
  • the film layer is patterned to form the active layer 04; the film layer where the source electrode 05 and the drain electrode 06 are formed on the side of the active layer 04 away from the substrate 1, and the film layer is patterned to form the source electrode 05 , the drain electrode 06 and a plurality of data lines 5, the source electrode 05 and the drain electrode 06 are arranged in the same layer and made of the same material; a flat layer 03 is formed on the side of the source electrode 05 and the drain electrode 06 away from the substrate 1, and the flat layer 03 can be made of organic film (ORG film), the flat layer 03 flattens the top layer of the thin film transistor to form subsequent film layers; the pixel electrode 07 is formed on the side of the flat layer 03 away from the substrate 1, and the pixel electrode 07 passes through the via hole in the flat layer 03 It is connected to the drain electrode 06; a protective layer 02 is formed on the side of the pixel electrode 07 away from the substrate 1 to protect each film layer of the thin film transistor.
  • the display substrate further includes: an auxiliary electrode 001 and a common electrode 002 arranged on the side of the first conductive layer D1 away from the substrate 1 , the auxiliary electrode 001 and the common electrode 002 are arranged in sequence along the direction away from the substrate 1 , and the auxiliary electrode 001 It is electrically connected to the common electrode 002 .
  • the auxiliary electrode 001 and the common electrode 002 are arranged on the side of the protective layer 02 away from the substrate 1
  • the auxiliary electrode 001 is arranged on the side of the common electrode 002 close to the substrate 1 .
  • the redundant connection pad 32 includes a first conductive portion 321 and a second conductive portion 322 disposed on the side of the first conductive layer D1 away from the substrate 1, and the first conductive portion 321 and the second conductive portion 322 are electrically connected.
  • a conductive portion 321 and the common electrode 002 are provided in the same layer and made of the same material, and the second conductive portion 322 and the auxiliary electrode 001 are provided in the same layer and are of the same material.
  • S24 may include, specifically:
  • a second conductive layer is formed on the side of the first conductive layer D1 away from the substrate 1, specifically, on the protective layer 02 (located on the side of the first conductive layer D1 away from the substrate 1) side)
  • the second conductive layer where the auxiliary electrode 001 is located is formed on the side away from the substrate 1 .
  • the display substrate further includes a plurality of first marks 6 arranged in the sealing area Q3, and a plurality of first marks 6 arranged in the bonding area Q2, connected to the functional connection pads 31 or redundantly connected
  • a plurality of second marks 7 (not shown in the figure) connected to the pads 32, wherein the first mark 6 includes a third conductive part 62 and a fourth conductive part 61, and the second mark 7 includes a fifth conductive part and a sixth conductive part Conductive part.
  • the second conductive layer is patterned according to the pattern of the auxiliary electrode 001, the pattern of the redundant connection pad 32, the pattern of the first mark 6, and the pattern of the second mark 7.
  • a pattern of the auxiliary electrode 001 is formed in the display area Q1 (as shown in FIG. 7 ), the auxiliary electrode 001 has a pixel opening P, and the auxiliary electrode 001 covers a plurality of gate lines 2 and data lines 5; redundant connections are formed in the bonding area Q2
  • the pattern of the second conductive portion 322 of the pad 32 and the pattern of the sixth conductive portion of the second mark 7; the pattern of the fourth conductive portion 61 of the first mark 6 is formed in the sealing area Q3.
  • a third conductive layer is formed on the side of the second conductive layer (the film layer where the auxiliary electrode 001 and the second conductive portion 322 are located) away from the substrate 1, and the third conductive layer is The film layer where the common electrode 001 is located.
  • the pattern of the common electrode 002 is patterned, and through exposure, development, and etching processes, a pattern of the common electrode 002 is formed in the display area Q1 (as shown in FIG.
  • the common electrode 002 has a pixel opening P and a plurality of slits 021, a plurality of slits 021 are facing the pixel electrode 06; the pattern of the first conductive part 321 of the redundant connection pad 32 and the pattern of the fifth conductive part of the second mark 7 are formed in the bonding area Q2; in the sealing area Q3 The pattern of the third conductive portion 62 of the first mark 6 is formed.
  • the auxiliary electrode 001 is only arranged under a partial area of the common electrode 002, and the common electrode 002 covers the auxiliary electrode 001, that is to say, the common electrode 002 covers the top surface and both sides of the auxiliary electrode 001, so that the In the process of preparing the display substrate, a film layer of the auxiliary electrode 001 is formed on the side of the flat layer 02 away from the substrate 1, the auxiliary electrode 001 is patterned, and then the film layer of the common electrode 002 is formed.
  • the common electrode 002 is patterned by the etching process.
  • the common electrode 002 Since the developer of the common electrode 002 is also corrosive to the auxiliary electrode 001, in order to prevent the developer from affecting the auxiliary electrode 001 when the common electrode 002 is developed, the common electrode 002 can be The auxiliary electrode 001 is covered.
  • the structure of the display substrate is not limited to this. For the convenience of description, the above description only takes the manufacturing process of the display substrate shown in FIG. 11 as an example.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.
  • the display device provided in this embodiment may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present invention.
  • the display device further includes a color filter substrate, the color filter substrate and the display substrate are arranged in a cell-to-cell arrangement, and liquid crystal is poured between the color filter substrate and the display substrate to form a liquid crystal display device.
  • the color filter substrate includes color filters, and the color filters may include various types of color filters, such as quantum dot color filters.

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Abstract

本发明提供一种显示基板及其制作方法、显示装置，属于显示技术领域。本发明提供的一种显示基板，具有显示区，和位于所述显示区至少一侧的邦定区。显示基板包括基底、第一导电层、遮光层和多个连接焊盘。其中，第一导电层设置在基底上、且位于显示区，第一导电层包括多条栅线；遮光层设置在第一导电层靠近基底的一侧，且遮光层在基底上的正投影至少覆盖多条栅线在基底上的正投影；多个连接焊盘间隔设置在基底上、且位于邦定区，其中，至少部分连接焊盘与遮光层在基底上的正投影无重叠。

Description

显示基板及其制作方法、显示装置 技术领域
本发明属于显示领域，具体涉及一种显示基板、显示基板的制作方法、显示装置。
背景技术
随着科技的进步，近年来，全面屏逐渐走进大家的视野。全面屏的显示基板包括显示区和邦定区，显示区具有多条栅线，邦定区具有多个连接焊盘，用于连接外部信号。栅线的金属层朝向显示面板的显示侧，因此若外部光线照射至栅线上会被栅线反射，从而造成反光影响显示基板形成的显示装置的显示质量。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板，其能够防止栅线反光，且能够避免连接焊盘识别异常。
第一方面，本公开实施例提供一种显示基板，具有显示区，和位于所述显示区至少一侧的邦定区；其中，所述显示基板包括：
基底；
第一导电层，设置在所述基底上、且位于所述显示区；所述第一导电层包括多条栅线；
遮光层，设置在所述第一导电层靠近所述基底的一侧，且所述遮光层在所述基底上的正投影至少覆盖所述多条栅线在所述基底上的正投影；
多个连接焊盘，间隔设置在所述基底上、且位于所述邦定区；其中，至少部分所述连接焊盘与所述遮光层在所述基底上的正投影无重叠。
本公开实施例提供的显示基板，由于在栅线下设置了遮光层，因此能够有效防止栅线反光；并且，由于至少部分连接焊盘下没有设置遮光层，因此在检测过程中从基底背离遮光层一侧检测连接焊盘的质量时，能够准确识别连接焊盘。
在一些示例中，所述多个连接焊盘在所述基底上的正投影均与所述遮光层在所述基底上的正投影无重叠。
在一些示例中，所述多个连接焊盘设置在所述第一导电层中，且与所述多条栅线材料相同。
在一些示例中，所述多个连接焊盘包括功能连接焊盘和冗余连接焊盘；其中，
所述冗余连接焊盘在所述基底上的正投影与所述遮光层在所述基底上的正投影无重叠；
所述功能连接焊盘在所述基底上的正投影与所述遮光层在所述基底上的正投影至少部分重叠。
在一些示例中，所述显示基板还包括：设置在所述第一导电层背离所述基底一侧的辅助电极和公共电极，二者沿背离所述基底方向依次设置、且电连接；所述辅助电极和所述公共电极在所述基底上的正投影至少部分重叠；
所述冗余连接焊盘包括设置在所述第一导电层背离所述基底一侧、且电连接的第一导电部和第二导电部，所述第一导电部与所述公共电极同层设置且材料相同，所述第二导电部与所述辅助电极同层设置且材料相同。
在一些示例中，所述功能连接焊盘与所述多条栅线同层设置且材料相同。
在一些示例中，所述显示基板还具有围绕所述显示区设置的封框区，所述邦定区设置在所述封框区背离所述显示区的至少一侧；所述显示基板还包括：多个第一标记，设置在所述基底上且设置在所述邦定区中；其中，
所述第一标记与所述遮光层在所述基底上的正投影无重叠。
在一些示例中，所述多个第一标记与所述多条栅线同层设置且材料相同。
在一些示例中，所述显示基板还包括：设置在所述第一导电层背离所述基底一侧的辅助电极和公共电极，且二者沿背离所述基底方向依次设置、且电连接；所述辅助电极和所述公共电极在所述基底上的正投影至少部分重叠；
所述第一标记包括设置在所述第一导电层背离所述基底一侧、且电连接的第三导电部和第四导电部，所述第三导电部与所述公共电极同层设置且材料相同；所述第四导电部与所述辅助电极同层设置且材料相同。
在一些示例中，所述显示基板还包括多条扇出走线，间隔设置在所述基底上，且一条所述扇出走线对应连接一个所述连接焊盘，所述扇出走线由所述邦定区延伸至所述显示区；其中，所述遮光层在所述基底上的正投影，覆盖多条所述扇出走线在所述基底上的正投影。
第二方面，本公开实施例还提供一种显示基板的制作方法，具有显示区，和位于所述显示区至少一侧的邦定区；其中，包括以下步骤：
在基底上制作遮光层；
去除所述遮光层位于所述邦定区的部分；
在所述遮光层背离所述基底一侧，制作第一导电层；
对所述第一导电层进行图案化，在所述第一导电层位于所述显示区的部分形成多条栅线，在所述第一导电层位于所述邦定区的部分形成多个连接焊盘。
在一些示例中，所述对所述第一导电层进行图案化，在所述第一导电层位于所述显示区的部分形成多条栅线，在所述第一导电层位于所述邦定区的部分形成多个连接焊盘，具体包括：
通过按照所述多条栅线和所述多个连接焊盘的图形制作的掩膜版，对所 述第一导电层，和设置在所述第一导电层位于所述显示区的部分靠近所述基底一侧的遮光层进行曝光、显影，形成所述多条栅线和所述多个连接焊盘。
第三方面，本公开实施例还提供一种显示基板的制作方法，具有显示区，和位于所述显示区至少一侧的邦定区；其中，多个连接焊盘包括功能连接焊盘和冗余连接焊盘；该制作方法包括以下步骤：
在基底上制作遮光层；
在所述遮光层上形成第一导电层；
对所述第一导电层和所述遮光层进行图案化，在所述第一导电层位于所述显示区的部分形成多条栅线，在所述第一导电层位于所述邦定区的部分形成多个功能连接焊盘；
在所述第一导电层背离所述基底一侧制作多个所述冗余连接焊盘。
在一些示例中，所述冗余连接焊盘包括设置在所述第一导电层背离所述基底一侧、且电连接的第一导电部和第二导电部；所述在所述第一导电层背离所述基底一侧制作多个所述冗余连接焊盘，具体包括：
在所述第一导电层背离所述基底一侧成膜第二导电层；
对所述第二导电层图案化，在所述第二导电层位于所述显示区的部分形成辅助电极，在所述第二导电层位于所述邦定区的部分形成所述冗余连接焊盘的第二导电部；
在所述第二导电层背离所述基底一侧成膜第三导电层；
对所述第三导电层图案化，在所述第三导电层位于所述显示区的部分形成公共电极，在所述第三导电层位于所述邦定区的部分形成所述冗余连接焊盘的第一导电部。
第四方面，本公开实施例还提供一种显示装置，其中，包括上述显示基板。
附图说明
图1为本公开实施例提供的显示基板的一种实施例的平面结构示意图。
图2为本公开实施例提供的显示基板的一种实施例的剖面图之一。
图3为沿图1中A-B方向剖切的剖面图。
图4为沿图1中C-D方向剖切的剖面图。
图5为沿图1中E-F方向剖切的剖面图。
图6为沿图1中G-H方向剖切的剖面图。
图7为本公开实施例提供的显示基板的辅助电极的一种实施例的平面结构示意图。
图8为本公开实施例提供的显示基板的公共电极的一种实施例的平面结构示意图。
图9为本公开实施例提供的显示基板的另一种实施例中部分连接焊盘的分布示意图。
图10为沿图9中K-L方向剖切的剖面图。
图11为本公开实施例提供的显示基板的一种实施例的剖面图之二。
图12为本公开实施例提供的显示基板的制作方法的一种实施例的流程图。
图13为本公开实施例提供的显示基板的制作方法的一种实施例的制作流程示意图(侧视图)。
图14为本公开实施例提供的显示基板的制作方法的一种实施例的制作流程示意图(平面图)。
图15为本公开实施例提供的显示基板的制作方法的另一种实施例的流程图。
图16为本公开实施例提供的显示基板的制作方法的另一种实施例的制作流程示意图(侧视图)。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅是本发明的部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
附图中各部件的形状和大小不反映真实比例，目的只是为了便于对本发明实施例的内容的理解。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是旨在限制性的。
如图1所示，图1示出本公开实施例提供的显示基板的一种示例的俯视图，该显示基板具有显示区Q1，和位于显示区Q1至少一侧的邦定(Bonding)区Q2。显示区Q1内具有多个阵列排布的子像素100，邦定区Q2内具有多个连接焊盘3，连接焊盘3用于接收外部驱动集成电路传输的信号，并传输 给显示区内的子像素100。显示基板还包括多条沿第一方向延伸的栅线2，和多条沿第二方向延伸的数据线5，栅线2与数据线5相交叉限定出子像素100的区域。其中，第一方向和第二方向可以为任意方向，只需第一方向和第二方向不平行即可，在以下实施例中，皆以第一方向为阵列排布的子像素100的行方向，第二方向为阵列排布的子像素100的列方向为例进行说明。
需要说明的是，显示基板还可以包括封框区Q3，封框区Q3围绕显示区Q1设置，邦定区Q2设置在封框区Q3背离显示区Q1的至少一侧，封框区用于设置封框胶，以在显示基板与彩膜基板对盒时将二者密封。并且，封框区还可以设置驱动集成电路，例如栅极驱动集成阵列(Gate on Array,GOA)。GOA可以设置沿栅线2的延伸方向，设置在栅线2的两端，栅线2与两端的GOA相连，接收GOA传输的扫描信号。显示基板可以采用单侧设置GOA，即仅在栅线2的一端设置GOA，也可以采用双侧设置GOA，即在栅线2的两端都设置GOA，在此不做限定。本公开实施例中以显示基板采用双侧设置GOA为例进行说明。
需要说明的是，根据驱动集成电路设置位置的不同，显示基板的邦定区Q2的位置也不同，例如，若显示基板采用栅极驱动芯片(G-IC)驱动栅线2，源极驱动芯片(S-IC)驱动数据线5，则可以将显示基板相对栅线2的两端的两侧，和显示基板相对数据线5的任一端的一侧设为邦定区Q2。而若显示基板采用GOA驱动栅线2，则只用将显示基板相对数据线5的任一端的一侧设为邦定区Q2。以下皆以显示基板具有一个邦定区Q2，且邦定区Q2设置在显示基板的上侧为例进行说明，但不对本公开实施例构成限制。
第一方面，参见图1、图2，图2为本实施例提供的显示基板的剖面图的一种示例，本公开实施例提供的显示基板包括基底1，以及基底1上第一导电层，第一导电层位于显示区Q1，第一导电层包括多条栅线2，多条栅线2连接两侧的GOA。显示基板还包括遮光层4，设置在第一导电层靠近基底 1一侧，由于外部光线照射到多条栅线2上多条栅线2会将外部光线反射，从而造成显示基板组成的显示装置的显示侧反光，因此在栅线2靠近基底1一侧设置遮光层4能够避免栅线2造成的反光现象，也就是说，遮光层4在基底1上的正投影至少覆盖多条栅线2在基底1上的正投影。
进一步地，继续参见图1、图2，显示基板还包括多个连接焊盘3，多个连接焊盘3间隔设置在基底1上，且多个连接焊盘3位于邦定区Q2，邦定区Q2包括多个并排设置的子区Q21，每个子区Q21对应一个连接器，也就是说，多个连接焊盘3分为多组，每个子区Q21中设置一组连接焊盘3，连接焊盘3连接焊盘3为裸露的电极，一组连接焊盘3的一端与一个连接器中的各引脚封装连接，另一端连接显示区Q1内的各条数据线5或GOA等，外部集成驱动电路(例如源极驱动电路)与连接器的各个引脚相连，通过连接器向连接焊盘3传输信号。该连接器可以为各种类型的连接器，例如采用覆晶薄膜(Chip On Flex，COF)的连接器，或采用玻璃上芯(Chip On Glass，COG)的连接器等，每组连接焊盘3与连接器采用各向异性导电胶(即ACF胶)压合，通过ACF胶中的导电金球电连接。以一种示例性的显示基板为例，连接焊盘3通常与多条栅线2同层设置且材料相同，也就是说，连接焊盘3设置在第一导电层中，与多条栅线2采用同一膜层制成，因此通常在基底1上成膜遮光层4，再在遮光层4背离基底1一侧成膜第一导电层，接着对第一导电层图案化，形成多条栅线2和多个连接焊盘3,从而连接焊盘3下方也具有遮光层4。而在显示基板的制作过程中，需要检测连接焊盘3的压合质量，具体的，摄像头通过基底1背离连接焊盘3的一侧检测连接焊盘3的图像，以观察ACF胶压合的粒子数，但由于连接焊盘3与基底1之间具有遮光层4，因此无法观察连接焊盘3。为了解决上述问题，在本公开里提供的显示基板中，至少部分连接焊盘3在基底1上的正投影，与遮光层4在基底1上的正投影无重叠。从而，若全部连接焊盘3在基底1上的正投影与遮光层4在基 底1上的正投影无重叠，也即多个连接焊盘3下均没有遮光层4(如图2所示)，则摄像头能够从基底1背离连接焊盘3一侧观察到多个连接焊盘3的每一个连接焊盘3的压合质量；若部分连接焊盘3在基底1上的正投影与遮光层4在基底1上的正投影无重叠，也即部分连接焊盘3下没有遮光层4，则摄像头能够从基底1背离连接焊盘3一侧观察到没有设置遮光层4的部分连接焊盘3的压合质量，由于多个连接焊盘3采用同样的工序压合，因此各个连接焊盘3的压合质量的差异较小，因此通过部分连接焊盘3的压合质量即可判断全部连接焊盘3的压合质量。
在一些示例中，以下以观察全部连接焊盘3的压合质量的实施例为例，参见图1-图6，所有连接焊盘3在基底1上的正投影均与遮光层4在基底1上的正投影无重叠。具体地，多个连接焊盘3设置在第一导电层中，即多个连接焊盘3与多条栅线2同层设置且材料相同，不同的是，多条栅线2与基底1之间还具有遮光层4，而连接焊盘3直接形成在基底1上。参见图3，图3为图1沿显示区Q1内的栅线2处的A-B方向剖切的剖面图，栅线2与基底1之间设置有遮光层4，以避免栅线2反光。参见图4，图4为沿邦定区Q2内的连接焊盘3处的C-D方向剖切的剖面图，连接焊盘3与基底1之间没有设置遮光层4，连接焊盘3与栅线2采用同一材料直接在基底1上形成。从而能够直接从基底1背离连接焊盘3一侧观察到每个连接焊盘3的压合质量。
在一些示例中，参见图1-图6，显示基板还包括设置在第一导电层(连接焊盘3和栅线2所在层)背离基底1一侧的栅极绝缘层01；栅极绝缘层01背离基底1一侧设置有源层04；有源层04背离基底1一侧具有源极05和漏极06，源极05和漏极06同层设置且材料相同，栅极、栅极绝缘层01、有源层04、源极05、漏极06组成一个薄膜晶体管，薄膜晶体管的各膜层仅设置在显示区Q1中，需要说明的是，薄膜晶体管的栅极与栅线2在同一膜层形 成，且栅线2连接栅极，图2中附图标记2可视作栅极所在位置；在显示基板中，每个子像素100都具有一薄膜晶体管，一条栅线2连接位于同一行的子像素100的薄膜晶体管，一条数据线5连接位于同一列的子像素100的薄膜晶体管；源极05和漏极06背离基底1一侧具有平坦层03，平坦层03可以采用有机膜(ORG膜)，平坦层03将薄膜晶体管的顶层平坦化，以便成膜后续膜层；平坦层03背离基底1一侧设置了像素电极07，像素电极07通过平坦层03中的过孔连接在漏极06上；像素电极07背离基底1一侧设置有保护层02，用于保护薄膜晶体管的各个膜层。
在一些示例中，参见图2，显示基板的保护层02背离基底1一侧，且位于显示区Q1内还具有公共电极002，公共电极002与像素电极07相对设置，公共电极002在基底1上的正投影与像素电极07在基底1上的正投影具有重叠区域，公共电极002接收公共电压，像素电极07接收数据线5提供的数据电压，从而公共电极002与数据线5之间产生电场，若显示基板与彩膜基板对盒形成显示装置，且在显示基板与彩膜基板之间灌注液晶，公共电极002与数据线5之间的电场能够改变液晶中的液晶分子的偏转角度，从而能够改变光线的透过率，因此，通过控制公共电极002与像素电极07之间的电压能够使显示装置发出所需灰阶的光。
在一些示例中，参见图2、图8，图8为公共电极002覆盖3×3阵列子像素的部分的俯视图，公共电极002与辅助电极001均设置在显示区Q1内，公共电极002为一面电极，公共电极002上具有多条狭缝021，像素电极07的电场能够透过狭缝021与公共电极002形成电场。为了子像素100的开口率，增加子像素100的亮度，可以在公共电极002上对应子像素100的区域设置像素开口P，使子像素100的薄膜晶体管裸露出来，也就是说，像素开口P在基底1上的正投影，与薄膜晶体管(尤其是栅极)在基底1上的正投影重合。公共电极002与像素电极07均可采用氧化铟锡(ITO)制成，增加 子像素100的透光率，但ITO的电阻率较大，会导致显示基板上各子像素100处的公共电极002上的公共电压的大小存在差异，因此，为了降低公共电极002的电阻，可以在公共电极002靠近基底1一侧设置辅助电极001，辅助电极001与公共电极002叠层设置，参见图7，图7为辅助电极001覆盖3×3阵列子像素的部分的俯视图，辅助电极001设置在对应公共电极002的上的像素开口P的周围，且辅助电极001覆盖多条栅线2和多条数据线5，以降低栅线2和数据线5的电阻，减少信号损失。
在一些示例中，参见图2，辅助电极001仅设置在公共电极002的部分区域下，公共电极002将辅助电极001包覆住，也就是说，公共电极002覆盖辅助电极001的顶面和两侧，从而在制备显示基板的过程中，在平坦层02背离基底1一侧成膜辅助电极001的膜层，对辅助电极001进行图案化，再成膜公共电极002的膜层，之后通过曝光、显影、刻蚀工艺对公共电极002进行图案化，由于公共电极002的显影液对辅助电极001也具有腐蚀性，因此为了防止在对公共电极002进行显影时，显影液影响辅助电极001，因此公共电极002可以将辅助电极001包覆住。
在一些示例中，参见图1-图6，本公共实施例提供的显示面板还包括设置在封框区Q3的多个第一标记6，多个第一标记6设置在封框区Q3，例如，可以设置在封框区Q3的四个角，从而在显示基板和彩膜基板对盒时，能够通过第一标记6进行对位。同理，以一种示例性的显示基板为例，第一标记6通常与多条栅线2同层设置且材料相同，也就是说，第一标记6设置在第一导电层中，与多条栅线2采用同一膜层制成，因此通常在基底1上成膜遮光层4，再在遮光层4背离基底1一侧成膜第一导电层，接着对第一导电层图案化，形成多条栅线2、多个第一标记6、多个连接焊盘3,从而第一标记6下方也具有遮光层4。而在显示基板的制作过程中，需要从基底1背离第一标记6一侧识别第一标记6，但由于第一标记6与基底1之间具有遮光层4， 因此无法识别到第一标记6。为了解决上述问题，在本公开里提供的显示基板中，第一标记6在基底1上的正投影，与遮光层4在基底1上的正投影无重叠(如图2所示)，从而摄像头能够从基底1背离第一标记6一侧识别到到多个第一标记6的每一个第一标记6。
在一些示例中，以能够识别全部第一标记6的为例，参见图1-图6，图5为图1中封框区Q3内第一标记6处沿E-F方向剖切的剖面图，所有第一标记6在基底1上的正投影均与遮光层4在基底1上的正投影无重叠。具体地，多个第一标记6设置在第一导电层中，即多个第一标记6与多条栅线2同层设置且材料相同，不同的是，多条栅线2与基底1之间还具有遮光层4，而第一标记6直接形成在基底1上，从而能够直接从基底1背离第一标记6一侧精准识别到每个第一标记6。
在一些示例中，参见图1，本实施例提供的显示基板还包括多个第二标记7，每个子区Q21中包括一组连接焊盘3，一组连接焊盘3与一个连接器相连，每组连接焊盘3与两个第二标记7连接，具体的，第二标记7分别连接在每组连接焊盘3中最外侧的两个连接焊盘的外侧，用于判断连接器与连接焊盘3邦定后，ACF胶里的导电金球的压接状态。第二标记7的结构与第一标记6相同，第二标记6在基底1上的正投影也与遮光层4在基底1上的正投影无重叠，从而能够直接从基底1背离第二标记7一侧精准识别到每个第二标记7。具体地，多个第二标记7设置在第一导电层中，即多个第二标记7与多条栅线2同层设置且材料相同，不同的是，多条栅线2与基底1之间还具有遮光层4，而第二标记7直接形成在基底1上。
在一些示例中，参见图1、图2，本实施例提供的显示基板还包括多条扇出(Fanout)走线8，多条扇出走线8间隔设置在基底上，且一条扇出走线8对应连接一个连接焊盘3，扇出走线8的一端连接一个连接焊盘3(如图2所示)，另一端由邦定区Q2延伸至显示区Q1，与显示区Q1内的GOA或 数据线5连接。其中，扇出走线8的膜层结构与栅线2相同，即遮光层4在基底1上的正投影，覆盖多条扇出走线8在基底1上的正投影。具体地，扇出走线8与栅线2同层设置且材料相同，扇出走线8与基底1之间还具有遮光层4。
综上所述，在本公开实施例提供的显示基板中，第一标记6、第二标记7等标记的膜层结构均与连接焊盘3相同，第一标记6、第二标记7在基底1上的正投影与遮光层4在基底1上的正投影无重叠；扇出走线8等的膜层结构均与栅线2相同，扇出走线8在基底1上的正投影与遮光层4在基底1上的正投影重叠。其中，第一标记6可以包括任意设置在封框区Q3内的标记，例如第一标记6可以为切割标记、研磨标记、工艺标记、重叠标记、总节距标记中的至少一个。
在一些示例中，第一标记6或第二标记7等标记的形状可以包括多种形状，例如十字形、T形、矩形、圆形、三角形等形状，在本公开实施例中，皆以第一标记6为十字形、第二标记7为T形为例进行说明，但不对本发明构成限制。
在一些示例中，在本公开实施例提供的显示基板中，遮光层4可以采用多种材料，例如，遮光层4采用氧化钼制备而成，氧化钼为黑色，能够有效吸收照射到栅线2上的光线。当然，遮光层4也可以采用其他种类的材料，在此不做限定。
在一些示例中，以下以观察部分连接焊盘3的压合质量的实施例为例，参见图9、图10，图9为一个连接器所连接的连接焊盘的示例性分布图，图10为沿图9的K-L方向剖切的剖面图。在本实施例提供的显示基板中，邦定区Q2中的多个连接焊盘3包括功能连接焊盘31和冗余连接焊盘(dummy leads)32，功能连接焊盘31和冗余连接焊盘32均设置在基底1上，通常外部信号仅输入功能连接焊盘31，也就是说，连接器的引脚仅连接功能连接焊 盘31，且功能连接焊盘31还会与显示区Q1内的数据线5或GOA连接，或通过扇出走线8连接，而冗余连接焊盘32为一个空置电极，不与连接器的引脚连接，也不接收任何电信号。由于多个功能连接焊盘31接收的信号有正信号和负信号(输入给数据线5的例如正数据电压和负数据电压)，因此，为了保证接收正、负信号的功能连接焊盘31之间的信号不发生串扰，因此在接收正信号的功能连接焊盘31与接收负信号的功能连接焊盘31之间设置至少一个空置的冗余连接焊盘32，用于分隔接收正信号的功能连接焊盘31和接收负信号的功能连接焊盘31，而冗余连接焊盘32本身不接收任何电信号，因此，冗余连接焊盘32可以与功能连接焊盘31形成在不同的膜层中，具有不同的层结构。具体地，参见图10，冗余连接焊盘32在基底1上的正投影与遮光层4在基底1上的正投影无重叠，功能连接焊盘31在基底1上的正投影与遮光层4在基底1上的正投影至少部分重叠，也即遮光层4在邦定区Q2中仅设置在功能连接焊盘31下，而冗余连接焊盘32下不设置遮光层。需要说明的是，遮光层4设置在功能连接焊盘31靠近基底1一侧，遮光层4的图案可以与功能连接焊盘32的图形一致，也即功能连接焊盘31在基底1上的正投影与遮光层4在基底1上的正投影可以完全重叠。从而，可以在基底1背离连接焊盘3一侧观察到每个冗余连接焊盘32的压合质量，通过观察冗余连接焊盘32的压合质量，即可判断整体的功能连接焊盘31和冗余连接焊盘32的压合质量。
在一些示例中，冗余连接焊盘32由于不接收任何电信号，因此可以不考虑其布线情况，因此冗余连接焊盘32可以采用显示基板中的任意导电膜层形成。以下以图11所示的示例性的显示基板为例，图11为对应图9的实施例的显示基板的剖面图，首先介绍显示基板的膜层结构。显示基板包括基底1，设置在基底1上的遮光层4，和遮光层4背离基底一侧的第一导电层，第一导电层位于显示区Q1的部分包括多条栅线2,第一导电层位于邦定区Q1 的部分包括多个功能连接焊盘31，遮光层4在基底1上的正投影，覆盖多条栅线2和多个功能连接焊盘31在基底1上的正投影，遮光层4设置在栅线2靠近基底1一侧，能够避免栅极2反光。显示基板还包括设置在第一导电层(功能连接焊盘31和栅线2所在层)背离基底1一侧的栅极绝缘层01；栅极绝缘层01背离基底1一侧设置有源层04；有源层04背离基底1一侧具有源极05和漏极06，源极05和漏极06同层设置且材料相同，栅极、栅极绝缘层01、有源层04、源极05、漏极06组成一个薄膜晶体管，薄膜晶体管的各膜层仅设置在显示区Q1中，需要说明的是，薄膜晶体管的栅极与栅线2在同一膜层形成，且栅线2连接栅极，图2中附图标记2可视作栅极所在位置；在显示基板中，每个子像素100都具有一薄膜晶体管，一条栅线2连接位于同一行的子像素100的薄膜晶体管，一条数据线5连接位于同一列的子像素100的薄膜晶体管；源极05和漏极06背离基底1一侧具有平坦层03，平坦层03可以采用有机膜(ORG膜)，平坦层03将薄膜晶体管的顶层平坦化，以便成膜后续膜层；平坦层03背离基底1一侧设置了像素电极07，像素电极07通过平坦层03中的过孔连接在漏极06上；像素电极07背离基底1一侧设置有保护层02，用于保护薄膜晶体管的各个膜层。
在一些示例中，参见图2，显示基板的保护层02背离基底1一侧，且位于显示区Q1内还具有公共电极002，公共电极002与像素电极07相对设置，公共电极002在基底1上的正投影与像素电极07在基底1上的正投影具有重叠区域，公共电极002接收公共电压，像素电极07接收数据线5提供的数据电压，从而公共电极002与数据线5之间产生电场，若显示基板与彩膜基板对盒形成显示装置，且在显示基板与彩膜基板之间灌注液晶，公共电极002与数据线5之间的电场能够改变液晶中的液晶分子的偏转角度，从而能够改变光线的透过率，因此，通过控制公共电极002与像素电极07之间的电压能够使显示装置发出所需灰阶的光。
在一些示例中，参见图2、图8，图8为公共电极002覆盖3×3阵列子像素的部分的俯视图，公共电极002与辅助电极001均设置在显示区Q1内，公共电极002为面电极，公共电极002上具有多条狭缝021，像素电极07的电场能够透过狭缝021与公共电极002形成电场。为了子像素100的开口率，增加子像素100的亮度，可以在公共电极002上对应子像素100的区域设置像素开口P，使子像素100的薄膜晶体管裸露出来，也就是说，像素开口P在基底1上的正投影，与薄膜晶体管(尤其是栅极)在基底1上的正投影重合。公共电极002与像素电极07均可采用氧化铟锡(ITO)制成，增加子像素100的透光率，但ITO的电阻率较大，会导致显示基板上各子像素100处的公共电极002上的公共电压的大小存在差异，因此，为了降低公共电极002的电阻，可以在公共电极002靠近基底1一侧设置辅助电极001，辅助电极001与公共电极002设置在第一导电层背离基底1一侧，且辅助电极001与公共电极002电连接，从而公共电极002的截面增大，电阻随之下降，参见图7，且辅助电极001与公共电极002沿背离基底1的方向依次设置，图7为辅助电极001覆盖3×3阵列子像素的部分的俯视图，辅助电极001设置在对应公共电极002的上的像素开口P的周围，且辅助电极001覆盖多条栅线2和多条数据线5，以降低栅线2和数据线5的电阻，减少信号损失。
在一些示例中，参见图2，辅助电极001仅设置在公共电极002的部分区域下，公共电极002将辅助电极001包覆住，也就是说，公共电极002覆盖辅助电极001的顶面和两侧，从而在制备显示基板的过程中，在平坦层02背离基底1一侧成膜辅助电极001的膜层，对辅助电极001进行图案化，再成膜公共电极002的膜层，之后通过曝光、显影、刻蚀工艺对公共电极002进行图案化，由于公共电极002的显影液对辅助电极001也具有腐蚀性，因此为了防止在对公共电极002进行显影时，显影液影响辅助电极001，因此公共电极002可以将辅助电极001包覆住。
在一些示例中，继续参见图11,可以采用辅助电极001同层的电极层，和公共电极002同层的电极层制备冗余连接焊盘32。需要说明的是，图11中为了便于示出功能连接焊盘31和冗余连接焊盘32各自所在的膜层的位置关系，因此在同一剖面图中同时示出了功能连接焊盘31和冗余连接焊盘32，但若从一个功能连接焊盘31处剖切，功能连接焊盘31的上方并不设置冗余连接焊盘32，若从一个冗余连接焊盘32处剖切，冗余连接焊盘32的下方并不设置功能连接焊盘31，也不具有遮光层4。具体地，每个冗余连接焊盘32包括设置在第一导电层背离所述基底1一侧第一导电部321和第二导电部322，且第一导电部321和第二导电部322电连接，位于邦定区Q2的第一导电部321与位于显示区Q1的公共电极002同层设置且材料相同，即第一导电部321与公共电极002采用同一膜层工序制备而成；相应地，位于邦定区Q2的第二导电部322与位于显示区Q1的辅助电极001同层设置且材料相同，即第二导电部322与辅助电极001采用同一膜层工序制备而成，冗余连接焊盘32的第一导电部321和第二导电部322下都不设置遮光层4，因此可以从基底1背离冗余连接焊盘32(也背离功能连接焊盘31)一侧观察多个冗余连接焊盘32的压合质量，从而判断整体的连接焊盘3(包括功能连接焊盘31和冗余连接焊盘32)的压合质量。当然，冗余连接焊盘32也可以采用其他导电膜层制备，在此不做限制。
在一些示例中，继续参加见图11，由于功能连接焊盘31要与显示区Q1内的数据线5或数据线的信号线，栅线2或栅线的信号线连接，因此需要使用像素电极07以下的膜层制备，具体地，功能连接焊盘31可以设置在第一导电层中，也就是说，功能连接焊盘31与多条栅线2(也与栅极)同层设置且材料相同，且功能连接焊盘31下具有遮光层4。当然，功能连接焊盘31也可以采用其他导电膜层制备，在此不做限制。
在一些示例中，继续参见图11，如上述，本公开实施例的显示基板还包 括设置在封框区Q3的多个第一标记6，为了解决由于遮光层4设置在第一标记6与基底1之间，导致无法从基底1背离第一标记6一侧识别到第一标记6的问题，在本公开里提供的显示基板中，第一标记6在基底1上的正投影，与遮光层4在基底1上的正投影无重叠(如图2所示)，具体地，除了第一标记6设置在第一导电层中的实施例，第一标记6还可以采用其他导电膜层制备，例如，第一标记6包括设置在第一导电层背离所述基底1一侧的第三导电部62和第四导电部61，且第三导电部62和第四导电部61电连接，第三导电部62与公共电极002同层设置且材料相同，也就是说，第三导电部62与公共电极002采用同一膜层工序制备而成，第四导电部61与辅助电极001同层设置且材料相同，也就是说，第四导电部61与辅助电极001采用同一膜层工序制备而成。且第一标记6的第三导电部62和第四导电部61下不设置遮光层4，从而能够直接从基底1背离第一标记6一侧精准识别到每个第一标记6。
在一些示例中，参见图1，本实施例提供的显示基板还包括多个第二标记7，每个子区Q21中包括一组连接焊盘3，一组连接焊盘3与一个连接器相连，每组连接焊盘3与两个第二标记7连接，具体的，第二标记7分别连接在每组连接焊盘3中最外侧的两个连接焊盘3(功能连接焊盘31或冗余连接焊盘32)的外侧，用于判断连接器与连接焊盘3邦定后，ACF胶里的导电金球的压接状态。第二标记7的结构与第一标记6相同，第二标记6在基底1上的正投影也与遮光层4在基底1上的正投影无重叠，从而能够直接从基底1背离第二标记7一侧精准识别到每个第二标记7。具体地，多个第二标记7包括叠层设置的第五导电部和第六导电部，第五导电部与公共电极002同层设置且材料相同，也就是说，第五导电部与公共电极002采用同一膜层工序制备而成，第六导电部与辅助电极001同层设置且材料相同，也就是说，第六导电部与辅助电极001采用同一膜层工序制备而成。
在一些示例中，参见图1、图11，本实施例提供的显示基板还包括多条扇出(Fanout)走线8，多条扇出走线8间隔设置在基底1上，且一条扇出走线8对应连接一个功能连接焊盘31，扇出走线8的一端连接一个功能连接焊盘31(如图11所示)，另一端由邦定区Q2延伸至显示区Q1，与显示区Q1内的GOA或数据线5连接。其中，扇出走线8的膜层结构与栅线2相同，即遮光层4在基底1上的正投影，覆盖多条扇出走线8在基底1上的正投影。具体地，扇出走线8与栅线2同层设置且材料相同，扇出走线8与基底1之间还具有遮光层4。
综上所述，在本公开实施例提供的显示基板中，第一标记6、第二标记7等标记的膜层结构均与冗余连接焊盘32相同，第一标记6、第二标记7在基底1上的正投影与遮光层4在基底1上的正投影无重叠；扇出走线8等的膜层结构均与栅线2和功能连接焊盘31相同，扇出走线8在基底1上的正投影与遮光层4在基底1上的正投影重叠。其中，第一标记6可以包括任意设置在封框区Q3内的标记，例如第一标记6可以为切割标记、研磨标记、工艺标记、重叠标记、总节距标记中的至少一个。
在一些示例中，在本公开实施例提供的显示基板中，遮光层4可以采用多种材料，例如，遮光层4采用氧化钼制备而成，氧化钼为黑色，能够有效吸收照射到栅线2上的光线。当然，遮光层4也可以采用其他种类的材料，在此不做限定。
在一些示例中，第一导电层中的栅线2的材料可以采用铜、钼铌、音、铝等材料，以栅线2采用铜为例进行说明，栅线2(也是第一导电层)的膜层厚度可以在1000～2000埃，而遮光层4的膜层厚度可以在400～500A。
需要说明的是，本实施例中薄膜晶体管可以为顶栅型薄膜晶体管，也可以为底栅型薄膜晶体管，与薄膜晶体管的栅极所在膜层(也即栅线2所在的第一导电层)同层的结构(例如功能连接焊盘31)随着栅极的位置变化即可。 以上均采用薄膜晶体管为底栅型薄膜晶体管为例进行说明，但并不对本申请构成限制。
第二方面，如图12所示，本公开实施例还提供一种显示基板的制作方法，本实施例中的显示基板的制作方法可用于形成上述显示基板，以形成图2所示的显示基板为例进行说明，上述已描述图2的显示基板的膜层结构，在此不做赘述，当然，本实施例的制作方法形成的显示基板的结构不限于图2所述的显示基板。显示基板具有显示区Q1，和位于显示区Q1至少一侧的邦定区Q2，还可以具有围绕显示区Q1设置的封框区Q3，邦定区Q2设置在封框区Q3背离显示区Q1的至少一侧。
参见图13、图14，图13为每一制作步骤的流程图的侧视图，图14为对应图13的每一制作步骤的流程图的平面图，该制作方法包括以下步骤：
S11、在基底1上制作遮光层4。
具体地，参见图13(a1)，图14(a1)，以遮光层4采用氧化钼为例进行说明，首先在基底1上通过溅射(sputter)工艺溅射氧化钼，形成一层覆盖基底1的遮光层4。
S12、去除遮光层4位于邦定区Q2的部分。
具体地，参见图13(a1)-(b1)，图14(a2)-(b2)，通过一道掩膜版，对遮光层4进行初步图案化，具体地，可以通过曝光、显影、刻蚀工艺去除遮光层4覆盖邦定区Q2的部分，形成例如图14(b2)所述的显示基板的遮光层4，使邦定区Q2无遮光层4，从而避免遮光层4影响邦定区Q2的连接焊盘3的识别。
可选地，基底1对应封框区Q3的位置还可以具有多个第一标记6对遮光层4进行图案化，包括在封框区Q3要设置第一标记6的位置去除遮光层4,即在遮光层4需要设置第一标记6的位置制作多个镂空部63，每个镂空部63 即后续形成第一标记6的位置，以保证第一标记6与基底1之间没有遮光层4，从而可以从基底1背离第一标记6一侧识别第一标记6。需要说明的是，由于封框区Q3具有部分扇出走线8经过的区域，因此不能完全去除遮光层4位于封框区Q3的部分。
S13、在遮光层4背离基底1一侧，制作第一导电层D1。
具体地，参见图13(b1)-(c1)，图14(b2)-(c2)，在遮光层3背离基底1一侧，通过溅射工艺溅射一层第一导电层D1的材料，例如铜、银、钼铌等导电材料，第一导电层D1覆盖显示区Q2，并且，由于连接焊盘3、第一标记6也形成在第一导电层D1，因此第一导电层D1也覆盖封框区Q3和邦定区Q2。并且，由于遮光层4较薄，因此遮光层4在靠近邦定区Q3的边缘的坡度较小，因此第一导电层D1设置在遮光层4上不会影响第一导电层D1的成膜质量。
S14、对第一导电层D1进行图案化，在第一导电层D1位于显示区Q1的部分形成多条栅线2，在第一导电层D1位于邦定区Q2的部分形成多个连接焊盘3。
具体地，参见图13(c1)-(d1)，图14(c2)-(d2)，S14可以包括：
通过按照多条栅线2和多个连接焊盘3的图形制作的掩膜版(mask)，对第一导电层D1，和设置在第一导电层D1靠近基底1一侧，且仅设置在显示区Q1中的遮光层4进行曝光、显影、刻蚀，形成多条位于显示区Q1的栅线2和多个位于邦定区Q2的连接焊盘3，与连接焊盘3连接的多个第二标记7，以及多个位于封框区Q3的第一标记6。也就是说，利用同一道mask(例如UV mask)，将第一导电层D1和遮光层4通过一道工序刻蚀，若第一导电层D1的材料包括铜或钼铌，遮光层4的材料包括氧化钼，铜或钼铌的刻蚀液也可以对氧化钼作用，因此可以同时在显示区Q1刻蚀第一导电层D1和遮光层4，形成多条栅线2的图形(如图14(d2)的图形)，并且可以用同一mask在 第一导电层D1位于邦定区Q2的部分刻蚀出多个连接焊盘3(如图14(d2)的图形)和与连接焊盘连接的第二标记7，在第一导电层D1位于封框区Q3的部分刻蚀出多个第一标记6(如图14(d2)的图形)。通过在同一道工序刻蚀第一导电层D1和遮光层4，能够省去一道仅用于刻蚀遮光层4的mask，并且，相较于先刻蚀遮光层4，再刻蚀第一导电层D1的制作方法，本公开实施例提供的制作方法不会受到先刻蚀遮光层4，在刻蚀第一导电层D1时由于钻刻现象造成的图形错位的问题，第一导电层D1中的栅线2能够尽可能地和栅线2靠近基底1一侧的遮光层4的图形相重合，从而提高了制作精度。
可选地，本实施例提供的显示基板还包括设置在显示区Q1的边缘的封框区Q2的多条扇出走线8和GOA电路，扇出走线8和GOA电路下都具有遮光层4，因此，S14中，对第一导电层D1进行图案化，还包括利用上述mask，在刻蚀栅线2的同一道工艺里，在封框区Q2对第一导电层D1和遮光层4同时进行刻蚀，形成多条扇出走线8和GOA电路的图形。
可选地，若第一导电层D1的材料包括铜或钼铌，遮光层4的材料包括氧化钼，铜或钼铌的刻蚀液也可以对氧化钼作用，具体地，铜的刻蚀液可以包括草酸铵、过氧化氢和表面活性剂等成分的至少一种，当然，铜的刻蚀液还可以包括其他成分，在此不做限制。
在一些示例中，参见图2，本公开实施例提供的显示基板的制作方法还包括：
在完成第一导电层D1的图案化后，在第一导电层D1(连接焊盘3和栅线2所在层)背离基底1一侧成膜栅极绝缘层01；在栅极绝缘层01背离基底1一侧成膜有源层04所在膜层，对该膜层进行图案化形成有源层04；在有源层04背离基底1一侧成膜源极05和漏极06所在膜层，对该膜层进行图案化形成源极05、漏极06和多条数据线5，源极05和漏极06同层设置且材料相同；在源极05和漏极06背离基底1一侧成膜平坦层03，平坦层03可 以采用有机膜(ORG膜)，平坦层03将薄膜晶体管的顶层平坦化，以便成膜后续膜层；在平坦层03背离基底1一侧成膜像素电极07，像素电极07通过平坦层03中的过孔连接在漏极06上；在像素电极07背离基底1一侧成膜保护层02，用于保护薄膜晶体管的各个膜层；在保护层02背离基底1一侧成膜辅助电极001所在膜层，并对该膜层进行图案化，形成辅助电极001，辅助电极001上具有像素开口P，辅助电极001覆盖多条栅线2和数据线5；在辅助电极001背离基底1一侧成膜公共电极002所在膜层，对该膜层进行图案化形成公共电极002，公共电极002上具有多条狭缝021和像素开口P，狭缝021正对像素电极06。当然，显示基板的结构不限于此，为了便于描述，以上仅以图2所示的显示基板的制作流程为例进行说明。
第三方面，如图15所示，本公开实施例还提供一种显示基板的制作方法，本实施例中的显示基板的制作方法可用于形成上述显示基板，以形成图11所示的显示基板为例进行说明，上述已描述图11的显示基板的膜层结构，在此不做赘述，当然，本实施例的制作方法形成的显示基板的结构不限于图11所述的显示基板。显示基板具有显示区Q1，和位于显示区Q1至少一侧的邦定区Q2，还可以具有围绕显示区Q1设置的封框区Q3，邦定区Q2设置在封框区Q3背离显示区Q1的至少一侧。在本实施例的制作方法形成的显示基板中，邦定区具有多个连接焊盘3，多个连接焊盘3包括功能连接焊盘31，和冗余连接焊盘32，通常外部信号仅输入功能连接焊盘，也就是说，通常连接器的引脚仅连接功能连接焊盘31，且功能连接焊盘31还会与显示区Q1内的数据线5或GOA连接，或通过扇出走线8连接，而冗余连接焊盘32为一个空置电极，不与连接器的引脚连接，也不接收任何电信号。
参见图16，图16为每一制作步骤的流程图的侧视图，该制作方法包括以下步骤：
S21、在基底1上制作遮光层4。
具体地，参见图16(a)，以遮光层4采用氧化钼为例进行说明，首先在基底1上通过溅射(sputter)工艺溅射氧化钼，形成一层覆盖基底1的遮光层4。
S22、在遮光层4背离基底1一侧形成第一导电层D1。
具体地，参见图16(a)，以第一导电层D1为铜为例，在遮光层4背离基底1一侧溅射铜，形成覆盖基底1的第一导电层D1。
S23、对第一导电层D1和遮光层4进行图案化，在第一导电层D1位于显示区Q1的部分形成多条栅线2，在第一导电层D1位于邦定区Q2的部分形成多个功能连接焊盘31。
具体地，参见图16(a)-(b)，通过按照栅线2和功能连接焊盘31的图案制作的mask，将第一导电层D1和遮光层4一起图案化，经过曝光、显影、刻蚀工艺，在显示区Q1位置形成多条栅线，在邦定区Q2位置形成多个功能连接焊盘31。
可选地，显示基板还包括设置在封框区Q3的多条扇出走线8、GOA电路等，S23中将第一导电层D1和遮光层4一起图案化时，还在封框区Q3形成了多条扇出走线8和GOA电路图形。也就是说，S23后，遮光层4在基底1上的正投影仅覆盖多条栅线、多个功能连接焊盘31、多条扇出走线8和GOA电路图形。
上述通过在同一道工序刻蚀第一导电层D1和遮光层4，能够省去一道仅用于刻蚀遮光层4的mask，并且，相较于先刻蚀遮光层4，再刻蚀第一导电层D1的制作方法，本公开实施例提供的制作方法不会受到先刻蚀遮光层4，在刻蚀第一导电层D1时由于钻刻现象造成的图形错位的问题，第一导电层D1中的栅线2、多个功能连接焊盘31、多条扇出走线8和GOA电路图形能够尽可能地和遮光层4的图形相重合，从而提高了制作精度。
进一步地，参见图16(b)-(d)，在S23之后，在S24之前，本公开实施例提供的显示基板的制作方法还包括：
在第一导电层D1(功能连接焊盘31和栅线2所在层)背离基底1一侧成膜栅极绝缘层01；在栅极绝缘层01背离基底1一侧成膜有源层04所在膜层，对该膜层进行图案化形成有源层04；在有源层04背离基底1一侧成膜源极05和漏极06所在膜层，对该膜层进行图案化形成源极05、漏极06和多条数据线5，源极05和漏极06同层设置且材料相同；在源极05和漏极06背离基底1一侧成膜平坦层03，平坦层03可以采用有机膜(ORG膜)，平坦层03将薄膜晶体管的顶层平坦化，以便成膜后续膜层；在平坦层03背离基底1一侧成膜像素电极07，像素电极07通过平坦层03中的过孔连接在漏极06上；在像素电极07背离基底1一侧成膜保护层02，用于保护薄膜晶体管的各个膜层。
S24、在第一导电层D1背离基底1一侧制作多个冗余连接焊盘32。
在一些示例中，显示基板还包括：设置在第一导电层D1背离基底1一侧的辅助电极001和公共电极002，辅助电极001和公共电极002沿背离基底1方向依次设置，且辅助电极001和公共电极002电连接，具体地，辅助电极001和公共电极002设置在保护层02背离基底1一侧，且辅助电极001设置在公共电极002靠近基底1一侧。冗余连接焊盘32包括设置在第一导电层D1背离所述基底1一侧的第一导电部321和第二导电部322，且第一导电部321和第二导电部322电连接，第一导电部321与公共电极002同层设置且材料相同，第二导电部322与辅助电极001同层设置且材料相同。
S24可以包括，具体包括：
241、在第一导电层D1背离基底一侧成膜第二导电层。
具体地，参见图16(d)-(e)，在第一导电层D1背离基底1一侧成膜第二导电层，具体地，在保护层02(位于第一导电层D1背离基底1一侧)背离 基底1一侧成膜辅助电极001所在的第二导电层。
S242、对第二导电层图案化，在第二导电层位于显示区Q1的部分形成辅助电极001，在第二导电层位于邦定区Q2的部分形成冗余连接焊盘32的第二导电部322。
具体地，参见图16(d)-(e)，显示基板还包括多个设置在封框区Q3的第一标记6，和设置在邦定区Q2、与功能连接焊盘31或冗余连接焊盘32连接的多个第二标记7(图中未示出)，其中，第一标记6包括第三导电部62和第四导电部61，第二标记7包括第五导电部和第六导电部。通过一道mask，按照辅助电极001的图形、冗余连接焊盘32的图形、第一标记6、第二标记7的图形，对第二导电层进行图案化，通过曝光、显影、刻蚀工艺，在显示区Q1形成辅助电极001的图形(如图7所示)，辅助电极001上具有像素开口P，辅助电极001覆盖多条栅线2和数据线5；在邦定区Q2形成冗余连接焊盘32的第二导电部322的图形、第二标记7的第六导电部图形；在封框区Q3形成第一标记6的第四导电部61的图形。
S243、在第二导电层背离基底一侧成膜第三导电层。
具体地，参见图16(e)-(f)，在第二导电层(辅助电极001、第二导电部322所在膜层)背离基底1一侧成膜第三导电层，第三导电层即公共电极001所在膜层。
S244、对第三导电层图案化，在第三导电层位于显示区的部分形成公共电极，在第三导电层位于邦定区的部分形成冗余连接焊盘的第一导电部。
具体地，参见图16(e)-(f)，通过与S242相同的一道mask，按照公共电极002的图形、冗余连接焊盘32的图形、第一标记6、第二标记7的图形，对第二导电层进行图案化，通过曝光、显影、刻蚀工艺，在显示区Q1形成公共电极002的图形(如图8所示)，公共电极002上具有像素开口P，以及多条狭缝021，多条狭缝021正对像素电极06；在邦定区Q2形成冗余连接 焊盘32的第一导电部321的图形、第二标记7的第五导电部图形；在封框区Q3形成第一标记6的第三导电部62的图形。
需要说明的是，辅助电极001仅设置在公共电极002的部分区域下，公共电极002将辅助电极001包覆住，也就是说，公共电极002覆盖辅助电极001的顶面和两侧，从而在制备显示基板的过程中，在平坦层02背离基底1一侧成膜辅助电极001的膜层，对辅助电极001进行图案化，再成膜公共电极002的膜层，之后通过曝光、显影、刻蚀工艺对公共电极002进行图案化，由于公共电极002的显影液对辅助电极001也具有腐蚀性，因此为了防止在对公共电极002进行显影时，显影液影响辅助电极001，因此公共电极002可以将辅助电极001包覆住。当然，显示基板的结构不限于此，为了便于描述，以上仅以图11所示的显示基板的制作流程为例进行说明。
第四方面，本公开实施例还提供一种显示装置，包括上述显示基板。需要说明的是，本实施例提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
可选地，显示装置还包括彩膜基板，彩膜基板与显示基板对盒设置，在彩膜基板与显示基板之间灌注液晶，形成液晶显示装置。所述彩膜基板包括彩色滤光片，所述彩色滤光片可以包括各类型的彩色滤光片，例如可以包括量子点彩色滤光片。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (15)

  1. 一种显示基板，具有显示区，和位于所述显示区至少一侧的邦定区；其中，所述显示基板包括：
    基底；
    第一导电层，设置在所述基底上、且位于所述显示区；所述第一导电层包括多条栅线；
    遮光层，设置在所述第一导电层靠近所述基底的一侧，且所述遮光层在所述基底上的正投影至少覆盖所述多条栅线在所述基底上的正投影；
    多个连接焊盘，间隔设置在所述基底上、且位于所述邦定区；其中，至少部分所述连接焊盘与所述遮光层在所述基底上的正投影无重叠。
  2. 根据权利要求1所述的显示基板，其中，所述多个连接焊盘在所述基底上的正投影均与所述遮光层在所述基底上的正投影无重叠。
  3. 根据权利要求2所述的显示基板，其中，所述多个连接焊盘设置在所述第一导电层中，且与所述多条栅线材料相同。
  4. 根据权利要求1所述的显示基板，其中，所述多个连接焊盘包括功能连接焊盘和冗余连接焊盘；其中，
    所述冗余连接焊盘在所述基底上的正投影与所述遮光层在所述基底上的正投影无重叠；
    所述功能连接焊盘在所述基底上的正投影与所述遮光层在所述基底上的正投影至少部分重叠。
  5. 根据权利要求4所述的显示基板，其中，所述显示基板还包括：设置在所述第一导电层背离所述基底一侧的辅助电极和公共电极，二者沿背离所 述基底方向依次设置、且电连接；所述辅助电极和所述公共电极在所述基底上的正投影至少部分重叠；
    所述冗余连接焊盘包括设置在所述第一导电层背离所述基底一侧、且电连接的第一导电部和第二导电部，所述第一导电部与所述公共电极同层设置且材料相同，所述第二导电部与所述辅助电极同层设置且材料相同。
  6. 根据权利要求5所述的显示基板，其中，所述功能连接焊盘与所述多条栅线同层设置且材料相同。
  7. 根据权利要求1所述的显示基板，其中，所述显示基板还具有围绕所述显示区设置的封框区，所述邦定区设置在所述封框区背离所述显示区的至少一侧；所述显示基板还包括：多个第一标记，设置在所述基底上且设置在所述邦定区中；其中，
    所述第一标记与所述遮光层在所述基底上的正投影无重叠。
  8. 根据权利要求7所述的显示基板，其中，所述多个第一标记与所述多条栅线同层设置且材料相同。
  9. 根据权利要求7所述的显示基板，其中，所述显示基板还包括：设置在所述第一导电层背离所述基底一侧的辅助电极和公共电极，且二者沿背离所述基底方向依次设置、且电连接；所述辅助电极和所述公共电极在所述基底上的正投影至少部分重叠；
    所述第一标记包括设置在所述第一导电层背离所述基底一侧、且电连接的第三导电部和第四导电部，所述第三导电部与所述公共电极同层设置且材料相同；所述第四导电部与所述辅助电极同层设置且材料相同。
  10. 根据权利要求1-9任一项所述的显示基板，其中，所述显示基板还包 括多条扇出走线，间隔设置在所述基底上，且一条所述扇出走线对应连接一个所述连接焊盘，所述扇出走线由所述邦定区延伸至所述显示区；其中，所述遮光层在所述基底上的正投影，覆盖多条所述扇出走线在所述基底上的正投影。
  11. 一种显示基板的制作方法，具有显示区，和位于所述显示区至少一侧的邦定区；其中，包括以下步骤：
    在基底上制作遮光层；
    去除所述遮光层位于所述邦定区的部分；
    在所述遮光层背离所述基底一侧，制作第一导电层；
    对所述第一导电层进行图案化，在所述第一导电层位于所述显示区的部分形成多条栅线，在所述第一导电层位于所述邦定区的部分形成多个连接焊盘。
  12. 根据权利要求11所述的制作方法，其中，所述对所述第一导电层进行图案化，在所述第一导电层位于所述显示区的部分形成多条栅线，在所述第一导电层位于所述邦定区的部分形成多个连接焊盘，具体包括：
    通过按照所述多条栅线和所述多个连接焊盘的图形制作的掩膜版，对所述第一导电层，和设置在所述第一导电层位于所述显示区的部分靠近所述基底一侧的遮光层进行曝光、显影，形成所述多条栅线和所述多个连接焊盘。
  13. 一种显示基板的制作方法，具有显示区，和位于所述显示区至少一侧的邦定区；其中，多个连接焊盘包括功能连接焊盘和冗余连接焊盘；该制作方法包括以下步骤：
    在基底上制作遮光层；
    在所述遮光层上形成第一导电层；
    对所述第一导电层和所述遮光层进行图案化，在所述第一导电层位于所 述显示区的部分形成多条栅线，在所述第一导电层位于所述邦定区的部分形成多个功能连接焊盘；
    在所述第一导电层背离所述基底一侧制作多个所述冗余连接焊盘。
  14. 根据权利要求13所述的制作方法，其中，所述冗余连接焊盘包括设置在所述第一导电层背离所述基底一侧、且电连接的第一导电部和第二导电部；所述在所述第一导电层背离所述基底一侧制作多个所述冗余连接焊盘，具体包括：
    在所述第一导电层背离所述基底一侧成膜第二导电层；
    对所述第二导电层图案化，在所述第二导电层位于所述显示区的部分形成辅助电极，在所述第二导电层位于所述邦定区的部分形成所述冗余连接焊盘的第二导电部；
    在所述第二导电层背离所述基底一侧成膜第三导电层；
    对所述第三导电层图案化，在所述第三导电层位于所述显示区的部分形成公共电极，在所述第三导电层位于所述邦定区的部分形成所述冗余连接焊盘的第一导电部。
  15. 一种显示装置，其中，包括权利要求1-10任一项所述的显示基板。
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