Nothing Special   »   [go: up one dir, main page]

WO2022067460A1 - 显示面板及其像素电路的驱动方法、显示装置 - Google Patents

显示面板及其像素电路的驱动方法、显示装置 Download PDF

Info

Publication number
WO2022067460A1
WO2022067460A1 PCT/CN2020/118657 CN2020118657W WO2022067460A1 WO 2022067460 A1 WO2022067460 A1 WO 2022067460A1 CN 2020118657 W CN2020118657 W CN 2020118657W WO 2022067460 A1 WO2022067460 A1 WO 2022067460A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
node
power supply
signal
initial power
Prior art date
Application number
PCT/CN2020/118657
Other languages
English (en)
French (fr)
Inventor
邱远游
程羽雕
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002169.4A priority Critical patent/CN114667560B/zh
Priority to US17/441,716 priority patent/US11798456B2/en
Priority to PCT/CN2020/118657 priority patent/WO2022067460A1/zh
Priority to CN202080002277.1A priority patent/CN114730540A/zh
Priority to US17/426,681 priority patent/US11978380B2/en
Priority to PCT/CN2020/120484 priority patent/WO2022067877A1/zh
Publication of WO2022067460A1 publication Critical patent/WO2022067460A1/zh
Priority to US18/221,960 priority patent/US20230360581A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto

Definitions

  • the present application relates to the field of display technology, and in particular, to a method for driving a display panel and a pixel circuit thereof, and a display device.
  • a display panel of the display device is provided with a light permeable display area, so that an optical device (eg, a camera) is arranged below the light permeable display area.
  • an optical device eg, a camera
  • each pixel circuit can be connected to one light-emitting element through a conductive line.
  • the present application provides a method for driving a display panel and a pixel circuit thereof, and a display device.
  • the technical solutions are as follows:
  • a base substrate has a display area and a non-display area located on at least one side of the display area, the display area includes a first display area and a second display with a higher resolution than the first display area area, the non-display area includes a pixel circuit area;
  • the at least one first pixel circuit is further connected to the gate signal terminal, the light emission control signal terminal, the DC signal terminal, the data signal terminal, the pull-down control terminal and the reset signal terminal respectively; the at least one first pixel circuit Including: drive sub-circuit and reset sub-circuit;
  • the driving sub-circuit is respectively connected with the gate signal terminal, the data signal terminal, the light-emitting control signal terminal, the DC signal terminal, the pull-down control terminal, the first initial power supply terminal and the target node connection, the driving sub-circuit is configured to respond to the gate driving signal provided by the gate signal terminal, the data signal provided by the data signal terminal, the lighting control signal provided by the lighting control signal terminal, the direct current The DC signal provided by the signal terminal, the pull-down control signal provided by the pull-down power terminal, and the first initial power signal, output a drive signal to the target node;
  • the reset sub-circuit is respectively connected to the reset signal terminal, the second initial power supply terminal and the target node, and the reset sub-circuit is configured to respond to the reset signal provided by the reset signal terminal to the target node.
  • the node outputs the second initial power signal;
  • the first light-emitting element is connected to the target node through the conductive line.
  • the at least one first pixel circuit further includes: a compensation subcircuit
  • the compensation sub-circuit is respectively connected with the regulated power supply terminal and the target node, and the compensation sub-circuit is used for compensating the potential of the target node according to the regulated signal provided by the regulated power supply terminal.
  • the compensation sub-circuit includes: a compensation capacitor
  • the gate of the reset transistor is connected to the reset signal terminal, the first pole of the reset transistor is connected to the second initial power supply terminal, and the second pole of the reset transistor is connected to the target node.
  • the data writing unit is respectively connected with the gate signal terminal, the data signal terminal and the first node, and the data writing unit is used for controlling the data signal terminal and the first node in response to the gate driving signal. the on-off state of the first node;
  • the pull-down unit is respectively connected to the pull-down control terminal, the first initial power terminal and the second node, and the pull-down unit is used for controlling the first initial power terminal and the second node in response to the pull-down control signal The on-off state of the second node;
  • the compensation unit is respectively connected to the gate signal terminal, the third node and the second node, and the compensation unit is configured to adjust the voltage of the third node according to the potential of the third node in response to the gate driving signal the potential of the second node;
  • the storage unit is respectively connected to the DC signal terminal and the second node, and the storage unit is configured to control the potential of the second node according to the DC signal;
  • the driving unit is respectively connected to the second node, the first node and the third node, and the driving unit is configured to send the voltage to the second node and the potential of the first node according to the potential of the second node and the potential of the first node.
  • the third node outputs the driving signal.
  • the gate of the data writing transistor is connected to the gate signal terminal, the first pole of the data writing transistor is connected to the data signal terminal, and the second pole of the data writing transistor is connected to the first pole. a node connection;
  • the gate of the compensation transistor is connected to the gate signal terminal, the first electrode of the compensation transistor is connected to the third node, and the second electrode of the compensation transistor is connected to the second node;
  • the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are both connected to the light-emitting control signal terminal, and the first pole of the first light-emitting control transistor is connected to the DC signal terminal,
  • the second electrode of the first light-emitting control transistor is connected to the first node;
  • the first electrode of the second light-emitting control transistor is connected to the third node, and the second electrode of the second light-emitting control transistor is connected to the third node.
  • the target node is connected;
  • the gate of the drive transistor is connected to the second node, the first electrode of the drive transistor is connected to the first node, and the second electrode of the drive transistor is connected to the third node.
  • At least one second pixel circuit in the plurality of second pixel circuits is connected with at least one second light-emitting element in the plurality of second light-emitting elements, and the at least one second pixel circuit is connected with the at least one second light-emitting element in the plurality of second light-emitting elements
  • the orthographic projections of a second light-emitting element on the base substrate at least partially overlap.
  • the pixel circuit area and the second display area are sequentially arranged along the extending direction of the data lines in the display panel.
  • the display panel further includes: a photosensitive sensor, and the photosensitive sensor is located in the first display area.
  • a method for driving a pixel circuit where the pixel circuit is the first pixel circuit in the display panel according to the above aspect; the method includes:
  • the first pixel circuit outputs the second initial power supply signal provided by the second initial power supply terminal to the connected first light-emitting element
  • the first pixel circuit In the light-emitting stage, the first pixel circuit outputs a drive signal to the connected first light-emitting element in response to the first initial power supply signal provided by the first initial power supply terminal;
  • the method further includes: in the reset stage and the light-emitting stage, providing the second initial power supply signal to the second initial power supply terminal, where the second initial power supply signal is a DC signal;
  • the second initial power supply signal is provided to the second initial power supply terminal, and the second initial power supply signal is an AC signal.
  • the driving circuit is connected to at least one first pixel circuit among the plurality of first pixel circuits, and the driving circuit is used for driving the at least one first pixel circuit to work.
  • the driving circuit is further configured to control the potential of the second initial power supply signal provided by the second initial power supply signal terminal connected to the at least one first pixel circuit based on the picture currently displayed on the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a first pixel circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another first pixel circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another first pixel circuit provided by an embodiment of the present application.
  • FIG. 8 is a simulation diagram of the time required to turn on the first light-emitting element provided by the embodiment of the present application.
  • FIG. 9 is a simulation diagram of the time required for turning on of another first light-emitting element provided by the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • 17 is a working timing diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the transistors used in all the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present application are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present application, the source electrode is referred to as the first electrode and the drain electrode is referred to as the second electrode; or, the drain electrode is referred to as the first electrode and the source electrode is referred to as the second electrode. According to the form in the drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain.
  • the switch transistor used in the embodiments of the present application may include any one of a P-type switch transistor and an N-type switch transistor, wherein the P-type switch transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level , the N-type switching transistor is turned on when the gate is high and turned off when the gate is low.
  • the light-emitting element has a light emission delay phenomenon.
  • the delay phenomenon is more obvious.
  • the lengths of the conductive lines connected between different light-emitting elements and the pixel circuits are different, and the longer the length of the conductive lines, the greater the parasitic capacitance, the light-emitting time of different light-emitting elements is also different. In this way, when the light-emitting delay time is relatively long, the display panel will have a flicker phenomenon, and the risk of screen flicker of the display panel is relatively high.
  • the embodiments of the present application provide a new display panel, in which the voltage difference between the two ends of the light-emitting elements in the light-transmitting display area can quickly reach the turn-on voltage in the light-emitting stage, that is, there is no light-emitting delay phenomenon. Furthermore, the risk of screen splashing of the display panel is small.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel includes: a base substrate 01 .
  • the base substrate 01 has a display area A1 and a non-display area located on at least one side of the display area A1 (as shown on the upper side), the non-display area may include a pixel circuit area A2, and the display area A1 may include a first display area A11 and second display area A12,
  • the area of the second display area A12 may be much larger than the area of the first display area A11, so the resolution of the second display area A12 may be greater than the resolution of the first display area A11. Since the resolution of the second display area A12 is higher than that of the first display area A11, a larger part of a display picture can be displayed in the second display area A12, so the second display area A12 can also Called the main display area.
  • the first display area A11 may be a transparent display area capable of transmitting light, that is, the area where the first display area A11 is located can transmit light.
  • the second display area A12 may be an opaque display area.
  • the first display area A11 may be a transparent display area
  • the second display area A12 may be a non-transparent display area.
  • the display panel may further include: a plurality of first light emitting elements 10 located in the first display area A11 , and a plurality of first pixel circuits 20 located in the pixel circuit area A2 .
  • the plurality of first pixel circuits 20 may provide signals for the plurality of first light emitting elements 10 to drive the plurality of first light emitting elements 10 to emit light.
  • the first pixel circuit 20 and the first light-emitting element 10 are not in the same area, at least one of the first pixel circuits 20 of the plurality of first pixel circuits 20 can communicate with the plurality of first light-emitting elements through at least one conductive line L1. At least one of the first light emitting elements 10 in 10 is connected. And the at least one first pixel circuit 20 may also be connected to the first initial power supply terminal Vinit1 and the second initial power supply terminal Vinit2 respectively.
  • the first initial power supply terminal Vinit1 may be configured to provide a first initial power supply signal
  • the second initial power supply terminal Vinit2 may be configured to provide a second initial power supply signal to reset one end (eg, the anode) of the first light-emitting element 10 .
  • the first pixel circuit 20 can output a driving signal to one end (eg, the anode) of the first light-emitting element 10 in response to the first initial power supply signal and other signals (eg, gate driving signal and data signal) to drive the first light-emitting element 10 A light-emitting element 10 emits light.
  • the other end (eg, the cathode) of each first light-emitting element 10 may also be connected to the power supply terminal VSS.
  • the first pixel circuit connected to the two initial power supply terminals may also be referred to as a dual Vinit pixel circuit.
  • FIG. 2 shows a schematic diagram of a pixel structure by taking the connection of a first pixel circuit 20 and a first light-emitting element 10 as an example.
  • the potential of the second initial power supply signal may be greater than the potential of the first initial power supply signal, and may be lower than the turn-on voltage of the first light-emitting element 10 .
  • the process of driving the first light-emitting element 10 to emit light is: firstly control the second initial power supply
  • the terminal Vinit2 outputs the second initial power signal to the anode of the first light-emitting element 10, so that the initial potential of the anode of the first light-emitting element 10 can be the potential of the second initial power signal (this process can be called a reset phase).
  • the driving signal is output in response to the first initial power supply signal provided by the first initial power supply terminal Vinit1 and other signals.
  • the potential of the anode of the first light emitting element 10 can be continuously increased from the potential of the second initial power supply signal.
  • the potential of the anode of the first light-emitting element 10 rises to a potential where the voltage difference from the cathode reaches the turn-on voltage, that is, the potential required for turn-on, the first light-emitting element 10 can emit light (this process can be called a light-emitting stage).
  • the potential of the second initial power supply signal to be lower than the turn-on voltage of the first light-emitting element 10
  • the phenomenon of erroneous lighting occurs due to bright voltage.
  • the electrical connection relationship between the plurality of first pixel circuits 20 and the plurality of first light emitting elements 10 may be in one-to-one correspondence. That is, each first pixel circuit 20 can be connected to one first light-emitting element 10 through a conductive line L1, and the first light-emitting elements 10 connected to each first pixel circuit 20 are different.
  • This embodiment of the present application does not limit the connection relationship.
  • the first pixel circuit Since the first pixel circuit is connected to two initial power supply terminals, and the potential of the signal provided by the second initial power supply terminal for resetting the first light-emitting element is greater than that of the signal provided by the other initial power supply signal terminal, Therefore, before emitting light, the potential of one end of the first light emitting element is higher than that when the second initial power supply end is not provided, so that the voltage difference across the first light emitting element can quickly reach the turn-on voltage during light emission. In this way, the problem of light-emitting delay caused by the influence of parasitic capacitance on the conductive line is solved, and the risk of screen splashing is reduced.
  • the second initial power terminal Vinit2 described in this embodiment of the present application may be a DC power terminal.
  • the second initial power supply terminal Vinit2 can be controlled to provide the second initial power supply signal in each stage (including the reset stage and the reset stage).
  • the potential of the second initial power supply signal provided by the second initial power supply terminal Vinit2 described in the embodiment of the present application may also be dynamically adjusted based on the current display screen.
  • the driving circuit that controls the operation of the pixel circuit may detect the picture currently displayed on the display panel, and flexibly adjust the second initial power supply signal according to the detection result. In this way, a better display effect can be further ensured.
  • the reset sub-circuit 202 may be connected to the reset signal terminal RST1, the second initial power terminal Vinit2 and the target node N01, respectively. And the reset sub-circuit 202 can output the second initial power signal to the target node N01 in response to the reset signal provided by the reset signal terminal RST1.
  • the compensation sub-circuit 203 can be connected to the regulated power supply terminal VGL and the target node N01 respectively, and the compensation sub-circuit 203 can be used for compensating the potential of the target node N01 according to the regulated signal provided by the regulated power supply terminal VGL.
  • the regulated power supply terminal VGL can be a ground terminal.
  • FIG. 5 is a schematic structural diagram of still another first pixel circuit provided by an embodiment of the present application.
  • the driving sub-circuit 201 may include: a data writing unit 2011 , a pull-down unit 2012 , a compensation unit 2013 , a storage unit 2014 , a lighting control unit 2015 and a driving unit 2016 .
  • the data writing unit 2011 can be connected to the gate signal terminal G1, the data signal terminal D1 and the first node N1 respectively, and the data writing unit 2011 can be used to control the data signal terminal D1 and the first node N1 in response to the gate driving signal The on-off state of node N1.
  • the data writing unit 2011 can control the first node N1 to conduct with the data signal terminal D1 when the potential of the gate driving signal is the first potential. At this time, the data signal terminal D1 can pass through the data writing transistor T1 to the first node. A node N1 outputs a data signal. The data writing unit 2011 can control the first node N1 to be disconnected from the data signal terminal D1 when the potential of the gate driving signal provided by the gate signal terminal G1 is the second potential.
  • the first potential may be an effective potential
  • the second potential may be an inactive potential
  • the first potential may be a low potential relative to the second potential.
  • the pull-down unit 2012 can control the second node N2 to conduct with the first initial power terminal Vinit1 when the potential of the pull-down control signal provided by the pull-down control terminal RST2 is the first potential.
  • the first initial power terminal Vinit1 can pass through
  • the pull-down transistor T2 outputs the first initial power supply signal at the second potential to the second node, so as to achieve noise reduction on the second node N2.
  • the pull-down unit 2012 can control the second node N2 to be disconnected from the first initial power supply terminal Vinit1 when the potential of the pull-down control signal provided by the pull-down control terminal RST2 is the second potential.
  • the compensation unit 2013 may be connected to the gate signal terminal G1, the third node N3 and the second node N2 respectively, and the compensation unit 2013 may be used to adjust the potential of the second node N2 according to the potential of the third node N3 in response to the gate driving signal .
  • the storage unit 2014 may be connected to the DC signal terminal VDD and the second node N2 respectively, and the storage unit 2014 may be used to control the potential of the second node N2 according to the DC signal.
  • the lighting control unit 2015 can be respectively connected to the lighting control signal terminal EM, the DC signal terminal VDD, the first node N1, the third node N3 and the target node N01, and the lighting control unit 2015 can be used to control the DC signal terminal in response to the lighting control signal
  • the on-off state of VDD and the first node N1, and the on-off state of the third node N3 and the target node N01 are controlled.
  • the lighting control unit 2015 may control the first node N1 to conduct with the DC signal terminal VDD when the potential of the lighting control signal is the first potential.
  • the DC signal terminal VDD may be connected to the first node N1 through the lighting control transistor T4. Output DC power signal.
  • the third node N3 can be controlled to be turned on with the target node N01.
  • the lighting control unit 2015 can control the first node N1 to be disconnected from the DC signal terminal VDD, and the third node N3 to be disconnected from the target node N01 when the potential of the lighting control signal is the second potential.
  • the driving unit 2016 can be connected to the second node N2, the first node N1 and the third node N3 respectively, and the driving unit 2016 can be used to output driving to the third node N3 according to the potential of the second node N2 and the potential of the first node N1 Signal.
  • FIG. 6 is a schematic structural diagram of still another first pixel circuit provided by an embodiment of the present application.
  • the compensation sub-circuit 203 may include: a compensation capacitor C1.
  • One end of the compensation capacitor C1 can be connected to the target node N01 , and the other end of the compensation capacitor can be connected to the regulated power supply terminal VGL.
  • the compensation capacitor C1 By setting the compensation capacitor C1, effective compensation for the parasitic capacitance on the transparent conductive line L1 can be achieved, and on the other hand, the time for the voltage difference across the first light-emitting element 10 to reach the turn-on voltage can be accelerated.
  • the capacitance value of the compensation capacitor C1 can be set to be smaller than the parasitic capacitance on the conductive line L1, so that a certain deviation range of the compensation value can be reserved.
  • the data writing unit 2011 may include: a data writing transistor T1; the pull-down unit 2012 may include: a pull-down transistor T2; the compensation unit 2013 may include: a compensation transistor T3; The unit 2014 may include: a first light emission control transistor T4 and a second light emission control transistor T5; the storage unit 2015 may include: a storage capacitor C0; and the driving unit 2016 may include: a driving transistor T6.
  • the reset subcircuit 202 may include a reset transistor T7.
  • the gate of the data writing transistor T1 may be connected to the gate signal terminal G1, the first pole may be connected to the data signal terminal D1, and the second pole may be connected to the first node N1.
  • the gates of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are both connected to the light-emitting control signal terminal EM, the first electrode of the first light-emitting control transistor T4 is connected to the DC signal terminal VDD, and the first light-emitting control transistor T4 is connected to the DC signal terminal VDD.
  • the diode is connected to the first node N1
  • the first electrode of the second light-emitting control transistor T5 is connected to the third node N3
  • the second electrode of the second light-emitting control transistor T5 is connected to the target node N01.
  • One end of the storage capacitor C0 may be connected to the second node N1, and the other end may be connected to the DC signal terminal VDD.
  • the gate of the reset transistor T7 may be connected to the reset signal terminal RST1, the first pole of the reset transistor T7 may be connected to the second initial power supply terminal Vinit2, and the second pole of the reset transistor T7 may be connected to the target node N01.
  • connection line between the target node N01 and the anode of the first light-emitting element 10 is the conductive line L1 .
  • the loading on the conductive line L1 includes a parasitic capacitance Cap and a parasitic resistance R1 in parallel.
  • the charge in the driving signal generally flows to the parasitic capacitance Cap first, thereby making the potential of the node N02 continuously increase. Therefore, it can be further determined that the larger the capacitance of the parasitic capacitance Cap is, the slower the potential rise rate of the node N02 is.
  • FIG. 6 only schematically shows a first pixel circuit, and the embodiment of the present application does not limit the specific structure of the first pixel circuit. That is, the first pixel circuit may be the 7T2C shown in FIG. 6 (ie, 7 transistors and 2 capacitors), or may be other structures, such as 4T2C.
  • the capacitance c of the parasitic capacitance Cap on the conductive line L1 is 1.5 picofarads (pF)
  • the resistance r of the parasitic resistance R1 is 300 kiloohms (k ⁇ )
  • the first The potential v1 of an initial power supply signal and the potential v2 of the power supply signal provided by VSS are both -3 volts (V) as an example:
  • 9 shows a simulation diagram of the time required for the first light-emitting element 10 to turn on when the potential v3 of the second initial power supply signal is -3V and the loading on the conductive line L1 is 50% and 100% respectively.
  • the horizontal axis represents time, in milliseconds (ms); the vertical axis represents current, in pA (pA). The current at turn-on is 300pA.
  • the potential of the second initial power supply signal is -1.5V compared to -3V, no matter how large the loading on the conductive line L1 is, the time required for the first light-emitting element 10 to turn on is shorter. . That is, the higher the potential of the second initial power supply signal, the faster the first light-emitting element 10 is turned on.
  • the potential of the second initial power supply signal is -3V compared to -1.5V, and the turn-on time of the first light-emitting element 10 under 50% loading and 100% loading is quite different.
  • the parasitic capacitance on the conductive line L1 that is, the effect of loading on the conductive line L1 can be effectively improved. Turn on delay issue.
  • FIG. 10 shows that when the potential v3 of the second initial power supply signal is -1.5V, and the loading on the conductive line L1 is 50% and 100%, respectively, the anode potential of the first light-emitting element 10 reaches the required potential for lighting.
  • Simulation diagram. 11 shows a simulation diagram of the potential of the anode of the first light-emitting element 10 reaching the required potential for lighting when the potential v3 of the second initial power supply signal is -3V and the loading on the conductive line L1 is 50% and 100% respectively .
  • the horizontal axis represents time, the unit is ms; the vertical axis represents the anode potential of the first light-emitting element 10, the unit is V, and it can be seen that the required potential for lighting is -1V.
  • the potential of the second initial power supply signal is -1.5V compared to -3V, no matter how much the loading on the conductive line L1 is, the anode potential of the first light-emitting element 10 rises to (also called The smaller the slope of the potential 1V required to climb to), the shorter the time. That is, the greater the potential of the second initial power supply signal, the faster the anode potential of the first light-emitting element 10 can reach the potential required for turning on.
  • the potential can quickly reach the required potential for turning on, correspondingly, the voltage difference between the two ends of the first light-emitting element 10 can quickly reach the turning-on voltage, and the turn-on time of the first light-emitting element 10 can be shortened, thereby effectively improving the Turn-on delay problem.
  • the potentials of the second initial power supply signal are -1.5V and -3V.
  • One sub-pixel eg, the red sub-pixel
  • the simulation results can refer to Tables 1 to 3 below.
  • Table 1 shows the light-emitting current when the first light-emitting element 10 emits light and the current difference percentage delta when the loading on the conductive line L1 is 50% loading and 100% loading, respectively.
  • Table 2 shows the light-emitting current when the first light-emitting element 10 emits light, and the current difference percentage delta between the two when the loading on the conductive line L1 is 50% loading and 100% loading, respectively.
  • Table 3 shows the light-emitting current when the first light-emitting element 10 emits light and the current difference percentage delta when the loading on the conductive line L1 is 50% loading and 100% loading, respectively.
  • the brightness difference of the first light-emitting element 10 can be made smaller under different loads, that is, the uniformity of grayscale brightness can also be ensured.
  • FIG. 12 shows a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • the display panel may further include: a plurality of second light emitting elements 30 located in the second display area A12, and a plurality of second pixel circuits 40 located in the second display area A12.
  • At least one second pixel circuit 40 of the plurality of second pixel circuits 40 can be connected to at least one second light emitting element 30 of the plurality of second light emitting elements 30, and the at least one second pixel circuit 40 is in the
  • the orthographic projection on the base substrate 01 may at least partially overlap with the orthographic projection of the connected at least one second light-emitting element 30 on the base substrate 01 .
  • the electrical connection relationship between the plurality of second pixel circuits 40 and the plurality of second light emitting elements 30 in the display panel may also be in one-to-one correspondence. That is, each second pixel circuit 40 can be connected to one second light emitting element 30 , and the second light emitting elements 30 connected to each second pixel circuit 40 are different.
  • the plurality of driving signal lines are not located in the first display area A11, but are only located in the second display area A12.
  • the driving signal lines eg, Gate, EM1, and Data
  • the driving signal lines may at least partially overlap with the conductive line L1, or completely overlap.
  • the driving signal line in the same layer as the conductive line L1 does not overlap with the conductive line L1.
  • the orthographic projection of the conductive line L1 on the base substrate 01 may not overlap with the orthographic projection of the via area connecting different layers on the base substrate 01 .
  • the second display area A12 includes a plurality of second light-emitting elements 30 and a plurality of second pixel circuits 40, while the first display area A11 only includes a plurality of first light-emitting elements 10, and does not include a plurality of first light-emitting elements 10.
  • pixel circuit 20 .
  • the plurality of first pixel circuits 20 are arranged in other areas except the first display area A11.
  • a plurality of first pixel circuits 20 may be disposed in the pixel circuit area A3.
  • a plurality of first pixel circuits 20 may be disposed in the second display area A12.
  • the plurality of first pixel circuits 20 may be partially disposed in the pixel circuit area A3 and partially disposed in the second display area A12.
  • the conductive lines L1 may extend from the first display area A11 to the second display area A12 first, and then It further extends from the second display area A12 to the pixel circuit area A13.
  • the conductive line L1 may extend directly from the first display area A11 to the pixel circuit area A3 without passing through the second display area A12.
  • the pixel circuit area A2 and the second display area A12 can be sequentially arranged along the extending direction of the data lines in the display panel (ie, the second direction X2). That is, the pixel circuit area A2 may be located in the area between the second display area A12 and the frame.
  • the distance between the first pixel circuit 20 and the first light-emitting element 10 can be made smaller. Accordingly, it is not only convenient for wiring, but also can make the length of the set conductive line L1 shorter, and further, the conductive line L1 The parasitic capacitance on it will be correspondingly smaller, which further solves the problem of turn-on delay.
  • the structures of the second pixel circuit 40 and the first pixel circuit 20 described in the embodiments of the present application may be the same, that is, they may both be the dual Vinit structure shown in FIG. The display effect can be better.
  • the second pixel circuit 40 may also have a single Vinit structure, that is, the second pixel circuit 40 is only connected to one initial power supply terminal.
  • the first pixel circuit 20 and the second pixel circuit 40 can share the first initial power supply terminal Vinit1, and The second initial power terminal Vinit2 is shared.
  • the first pixel circuit 20 and the second pixel circuit 40 can also be connected to different initial power terminals (including the first initial power terminal Vinit1 and the second initial power terminal Vinit2 ), so that the driving circuit can flexibly control the pixels in different display areas The potential of the initial power supply signal provided by the initial power supply terminal connected to the circuit.
  • the conductive lines L1 described in the above embodiments may be transparent conductive lines.
  • the conductive line L1 may be made of transparent materials such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO). Assuming that the conductive line L1 is made of ITO material, the conductive line L1 may also be called an ITO trace.
  • the display panel may further include: a photosensitive sensor 50 , and the photosensitive sensor 50 may be located in the first display area A11 .
  • the photosensitive sensor does not need to occupy additional positions in the non-display area, which is beneficial to the narrow frame design of the display panel.
  • the display panel may also be referred to as a display panel with an under-screen camera.
  • the light-emitting elements (including the first light-emitting element 10 and the second light-emitting element 30 ) described in the embodiments of the present application may both be electroluminescence (electroluminescence, EL) devices.
  • electroluminescence electroluminescence, EL
  • an embodiment of the present application provides a display panel, the display panel includes a first light-emitting element located in a first display area, and is connected to the first light-emitting element through a conductive wire for driving the first light-emitting element The first pixel circuit where the element emits light.
  • the first pixel circuit Since the first pixel circuit is connected to two initial power supply terminals, and the potential of the signal provided by the second initial power supply terminal for resetting the first light-emitting element is greater than that of the signal provided by the other initial power supply signal terminal, Therefore, before emitting light, the potential of one end of the first light emitting element is higher than that when the second initial power supply terminal is not provided, so that the voltage difference across the first light emitting element can quickly reach the turn-on voltage during light emission. In this way, the problem of light-emitting delay caused by the influence of parasitic capacitance on the conductive line is solved, and the risk of screen splashing is reduced.
  • Step 1601 in the reset stage, the first pixel circuit outputs the second initial power supply signal provided by the second initial power supply terminal to the connected first light-emitting element.
  • the second initial power supply terminal Vinit2 may be an AC power supply terminal, or may also be a DC power supply terminal.
  • the method described in the embodiment of the present application may also include:
  • the potential of the light-emitting control signal provided by the light-emitting control signal terminal EM is the first potential, and at this time, the light-emitting control transistors T4 and T5 are both turned on.
  • the DC signal terminal VDD outputs a DC power signal to the first node N1 through the light-emitting control transistor T4, and the driving transistor T6 outputs a driving current to the third node N3 according to the potential of the first node N1 and the potential of the second node N2. Then, the driving current is output to the target node N01 through the light-emitting control transistor T5.
  • the first light-emitting element 10 emits light when the potential of the target node N01 reaches the potential required for turn-on.
  • the embodiments of the present application provide a driving method for a pixel circuit, since the first pixel circuit is connected to two initial power supply terminals, and the second initial power supply terminal for resetting the first light-emitting element provides
  • the potential of the initial power supply signal is larger than that of the signal provided by the other initial power signal terminal, so that before emitting light, the potential of one end of the first light-emitting element is higher than the potential when the second initial power supply terminal is not set, and then Therefore, when emitting light, the voltage difference across the first light-emitting element can quickly reach the turn-on voltage. In this way, the problem of light-emitting delay caused by the influence of parasitic capacitance on the conductive line is solved, and the risk of screen splashing is reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示面板及其像素电路的驱动方法、显示装置，属于显示技术领域。该显示面板包括位于第一显示区（A11）的第一发光元件（10），以及通过导电线（L1）与该第一发光元件（10）连接且用于驱动该第一发光元件（10）发光的第一像素电路（20）。该第一像素电路（20）与两个初始电源端（Vinit1，Vinit2）连接，且用于对第一发光元件（10）进行复位的第二初始电源端（Vinit2）提供的信号的电位较另一初始电源信号端（Vinit1）提供的信号的电位更大，因此使得在发光之前，第一发光元件（10）一端的电位相对于未设置第二初始电源端（Vinit2）时的电位更高，进而使得在发光时，第一发光元件（10）两端的压差能够快速达到启亮电压。该显示面板解决了因导电线（L1）上寄生电容的影响导致发光延时的问题，降低了闪屏风险。

Description

显示面板及其像素电路的驱动方法、显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及其像素电路的驱动方法、显示装置。
背景技术
目前，为了提高显示装置的屏占比，显示装置的显示面板上均会设置有可透光显示区，以便在该可透光显示区的下方设置光学器件(如，摄像头)。
相关技术中，为了保证可透光显示区的透光率，可透光显示区内一般仅设置多个发光元件，驱动该多个发光元件发光的多个像素电路一般均位于除该可透光显示区外的其他区域，如专门用于设置像素电路的像素电路区。每个像素电路可以通过一条导电线与一个发光元件连接。
但是，受导电线上寄生电容的影响，位于可透光显示区内的发光元件的启亮时间会出现一定程度的延迟，如此，导致显示面板易出现闪屏风险。
发明内容
本申请提供了一种显示面板及其像素电路的驱动方法、显示装置，所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，所述衬底基板具有显示区和位于所述显示区至少一侧的非显示区，所述显示区包括第一显示区和分辨率高于所述第一显示区的第二显示区，所述非显示区包括像素电路区；
位于所述第一显示区的多个第一发光元件；
位于所述像素电路区的多个第一像素电路，所述多个第一像素电路与所述多个第一发光元件在所述衬底基板上的正投影不重叠；
所述多个第一像素电路中的至少一个第一像素电路通过至少一条导电线与所述多个第一发光元件中的至少一个第一发光元件连接，且所述至少一个第一 像素电路分别与第一初始电源端和第二初始电源端连接，所述第一初始电源端被配置为提供第一初始电源信号，所述第二初始电源端被配置为提供第二初始电源信号以对所述第一发光元件复位，且，所述第二初始电源信号的电位大于所述第一初始电源信号的电位，且小于所述第一发光元件的启亮电压。
可选的，所述第二初始电源端为交流电源端。
可选的，所述第二初始电源端为直流电源端。
可选的，所述至少一个第一像素电路还分别与栅极信号端、发光控制信号端、直流信号端、数据信号端、下拉控制端和复位信号端连接；所述至少一个第一像素电路包括：驱动子电路和复位子电路；
其中，所述驱动子电路分别与所述栅极信号端、所述数据信号端、所述发光控制信号端、所述直流信号端、所述下拉控制端、所述第一初始电源端和目标节点连接，所述驱动子电路用于响应于所述栅极信号端提供的栅极驱动信号、所述数据信号端提供的数据信号、所述发光控制信号端提供的发光控制信号、所述直流信号端提供的直流信号、所述下拉电源端提供的下拉控制信号和所述第一初始电源信号，向所述目标节点输出驱动信号；
所述复位子电路分别与所述复位信号端、所述第二初始电源端和所述目标节点连接，所述复位子电路用于响应于所述复位信号端提供的复位信号，向所述目标节点输出所述第二初始电源信号；
所述第一发光元件通过所述导电线与所述目标节点连接。
可选的，所述至少一个第一像素电路还包括：补偿子电路；
所述补偿子电路分别与稳压电源端和所述目标节点连接，所述补偿子电路用于根据所述稳压电源端提供的稳压信号，补偿所述目标节点的电位。
可选的，所述补偿子电路包括：补偿电容；
所述补偿电容的一端与所述目标节点连接，所述补偿电容的另一端与所述稳压电源端连接。
可选的，所述复位子电路包括：复位晶体管；
所述复位晶体管的栅极与所述复位信号端连接，所述复位晶体管的第一极与所述第二初始电源端连接，所述复位晶体管的第二极与所述目标节点连接。
可选的，所述驱动子电路包括：数据写入单元、下拉单元、补偿单元、存储单元、发光控制单元以及驱动单元；
所述数据写入单元分别与所述栅极信号端、所述数据信号端和第一节点连接，所述数据写入单元用于响应于所述栅极驱动信号，控制所述数据信号端和所述第一节点的通断状态；
所述下拉单元分别与所述下拉控制端、所述第一初始电源端和第二节点连接，所述下拉单元用于响应于所述下拉控制信号，控制所述第一初始电源端和所述第二节点的通断状态；
所述补偿单元分别与所述栅极信号端、第三节点和所述第二节点连接，所述补偿单元用于响应于所述栅极驱动信号，根据所述第三节点的电位调整所述第二节点的电位；
所述存储单元分别与所述直流信号端和所述第二节点连接，所述存储单元用于根据所述直流信号，控制所述第二节点的电位；
所述发光控制单元分别与所述发光控制信号端、所述直流信号端、所述第一节点、所述第三节点和所述目标节点连接，所述发光控制单元用于响应于所述发光控制信号，控制所述直流信号端和所述第一节点的通断状态，以及控制所述第三节点和所述目标节点的通断状态；
所述驱动单元分别与所述第二节点、所述第一节点和所述第三节点连接，所述驱动单元用于根据所述第二节点的电位和所述第一节点的电位，向所述第三节点输出所述驱动信号。
可选的，所述数据写入单元包括：数据写入晶体管；所述下拉单元包括：下拉晶体管；所述补偿单元包括：补偿晶体管；所述存储单元包括：存储电容；所述发光控制单元包括：第一发光控制晶体管和第二发光控制晶体管；所述驱动单元包括：驱动晶体管；
所述数据写入晶体管的栅极与所述栅极信号端连接，所述数据写入晶体管的第一极与所述数据信号端连接，所述数据写入晶体管的第二极与所述第一节点连接；
所述下拉晶体管的栅极与所述下拉控制端连接，所述下拉晶体管的第一极与所述第一初始电源端连接，所述下拉晶体管的第二极与所述第二节点连接；
所述补偿晶体管的栅极与所述栅极信号端连接，所述补偿晶体管的第一极与所述第三节点连接，所述补偿晶体管的第二极与所述第二节点连接；
所述存储电容的一端与所述第二节点连接，另一端与所述直流信号端连接；
所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极均与所述发光控制信号端连接，所述第一发光控制晶体管的第一极与所述直流信号端连接，所述第一发光控制晶体管的第二极与所述第一节点连接；所述第二发光控制晶体管的第一极与所述第三节点连接，所述第二发光控制晶体管的第二极与所述目标节点连接；
所述驱动晶体管的栅极与所述第二节点连接，所述驱动晶体管的第一极与所述第一节点连接，所述驱动晶体管的第二极与所述第三节点连接。
可选的，所述显示面板还具有第二显示区；所述显示面板还包括：
位于所述第二显示区的多个第二发光元件；
位于所述第二显示区的多个第二像素电路；
其中，所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件连接，且所述至少一个第二像素电路与所述至少一个第二发光元件在所述衬底基板上的正投影至少部分重叠。
可选的，所述至少一个第一像素电路和所述至少一个第二像素电路共用所述第一初始电源端。
可选的，所述至少一个第一像素电路和所述至少一个第二像素电路共用所述第二初始电源端。
可选的，所述像素电路区和所述第二显示区沿所述显示面板中的数据线的延伸方向依次排布。
可选的，所述导电线为透明导电线，且所述透明导电线由氧化铟锡材料制成。
可选的，所述显示面板还包括：感光传感器，所述感光传感器位于所述第一显示区内。
另一方面，提供了一种像素电路的驱动方法，所述像素电路为如上述方面所述的显示面板中的第一像素电路；所述方法包括：
在复位阶段，所述第一像素电路向所连接的第一发光元件输出第二初始电源端提供的第二初始电源信号；
在发光阶段，所述第一像素电路响应于第一初始电源端提供的第一初始电源信号，向所连接的所述第一发光元件输出驱动信号；
其中，所述第二初始电源信号的电位大于所述第一初始电源信号的电位， 且小于所述第一发光元件的启亮电压。
可选的，所述方法还包括：在所述复位阶段和所述发光阶段，向所述第二初始电源端提供所述第二初始电源信号，所述第二初始电源信号为直流信号；
或者，在所述复位阶段，向所述第二初始电源端提供所述第二初始电源信号，所述第二初始电源信号为交流信号。
又一方面，提供了一种显示装置，所述显示装置包括：驱动电路以及如上述方面所述的显示面板，所述显示面板包括多个第一像素电路；
所述驱动电路与所述多个第一像素电路中的至少一个第一像素电路连接，所述驱动电路用于驱动所述至少一个第一像素电路工作。
可选的，所述驱动电路还用于基于所述显示面板当前所显示画面，控制所述至少一个第一像素电路所连接的第二初始电源信号端提供的第二初始电源信号的电位。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示面板的结构示意图；
图2是本申请实施例提供的另一种显示面板的结构示意图；
图3是本申请实施例提供的一种第一像素电路的结构示意图；
图4是本申请实施例提供的另一种第一像素电路的结构示意图；
图5是本申请实施例提供的又一种第一像素电路的结构示意图；
图6是本申请实施例提供的再一种第一像素电路的结构示意图；
图7是本申请实施例提供的一种驱动信号的流向示意图；
图8是本申请实施例提供的一种第一发光元件的启亮所需时间仿真图；
图9是本申请实施例提供的另一种第一发光元件的启亮所需时间仿真图；
图10是本申请实施例提供的又一种第一发光元件的启亮所需时间仿真图；
图11是本申请实施例提供的再一种第一发光元件的启亮所需时间仿真图；
图12是本申请实施例提供的又一种显示面板的结构示意图；
图13是本申请实施例提供的再一种显示面板的结构示意图；
图14是本申请实施例提供的再一种显示面板的结构示意图；
图15是本申请实施例提供的再一种显示面板的结构示意图；
图16是本申请实施例提供的一种像素电路的驱动方法流程图；
图17是本申请实施例提供的一种像素电路的工作时序图；
图18是本申请实施例提供的另一种像素电路的工作时序图；
图19是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
本申请所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本申请的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，将其中源极称为第一极，漏极称为第二极；或，将其中漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本申请实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。
具有可透光显示区的显示面板中，位于该可透光显示区的发光元件的一端(如，阳极)通过导电线(例如，透明导电线)与像素电路连接，另一端(如，阴极)与一电源端(如，提供低电平信号的VSS端)连接。当像素电路向发光元件输出的驱动信号与发光元件所连接的电源端提供的电源信号之间的压差，即发光元件的阴极和阳极两端之间的压差达到启亮电压时，发光元件即可发光。
但是，因导电线上寄生电容的存在，导致发光元件两端的压差需要较长时间才能达到启亮时间，进而导致在一帧扫描时间内，发光元件总会延时数毫秒后才会发光，即，发光元件存在发光延迟现象。尤其是对于低灰阶画面而言，因驱动信号的电位本身较小，故延迟现象更为明显。此外，由于不同发光元件 和像素电路之间所连接的导电线长度不同，且由于导电线的长度越长，寄生电容越大，因此不同发光元件的发光时间也不相同。如此，在发光延迟的时间较长时，显示面板就会出现闪屏现象，显示面板的闪屏风险较大。
本申请实施例提供了一种新的显示面板，该显示面板中位于可透光显示区的发光元件两端的压差能够在发光阶段快速达到启亮电压，即不存在发光延迟现象。进而，该显示面板的闪屏风险较小。
图1是本申请实施例提供的一种显示面板的结构示意图。如图1所示，该显示面板包括：衬底基板01。该衬底基板01具有显示区A1和位于该显示区A1至少一侧(如图示上侧)的非显示区，该非显示区可以包括像素电路区A2，且该显示区A1可以包括第一显示区A11和第二显示区A12，
其中，该第二显示区A12的面积可以远大于第一显示区A11的面积，如此，第二显示区A12的分辨率即可以大于第一显示区A11的分辨率。由于第二显示区A12的分辨率较第一显示区A11的分辨率更高，因此一副显示画面的较大部分可以显示于该第二显示区A12内，故该第二显示区A12也可以称为主显示区。并且，该第一显示区A11可以为能够透光的可透光显示区，即该第一显示区A11所在区域能够透光。如此，即可以将显示装置所需配置的一些感光元件(例如，摄像头，指纹识别器件等)设置在该第一显示区A11内，以为显示面板的窄边框设计奠定基础。该第二显示区A12为可以为不可透光显示区。例如，该第一显示区A11可以为透明显示区，该第二显示区A12可以为非透明显示区。
继续参考图1，显示面板还可以包括：位于第一显示区A11的多个第一发光元件10，以及位于像素电路区A2的多个第一像素电路20。多个第一像素电路20可以为多个第一发光元件10提供信号，以驱动多个第一发光元件10发光。
在一些实施例中，由于多个第一像素电路20和多个第一发光元件10位于不同区域，因此该多个第一像素电路20在衬底基板01上的正投影，与多个第一发光元件10在衬底基板01上的正投影不重叠，即该多个第一像素电路20与多个第一发光元件10在垂直于显示面板方向上没有任何重叠面积。如此，可以确保第一显示区A11的开口率，使得第一显示区A11的透光效果较好。
且因第一像素电路20与第一发光元件10不在同一个区域，故多个第一像素电路20中的至少一个第一像素电路20可以通过至少一条导电线L1，与多个 第一发光元件10中的至少一个第一发光元件10连接。且该至少一个第一像素电路20还可以分别与第一初始电源端Vinit1和第二初始电源端Vinit2连接。该第一初始电源端Vinit1可以被配置为提供第一初始电源信号，第二初始电源端Vinit2可以被配置为提供第二初始电源信号以对第一发光元件10的一端(如，阳极)进行复位。且，第一像素电路20可以响应于第一初始电源信号以及其他信号(如，栅极驱动信号和数据信号)向第一发光元件10的一端(如，阳极)输出驱动信号，以驱动该第一发光元件10发光。此外，每个第一发光元件10的另一端(如，阴极)还可以与电源端VSS连接。与两个初始电源端连接的第一像素电路也可以称为双Vinit像素电路。示例的，图2以一个第一像素电路20与一个第一发光元件10连接为例，示出了一种像素结构示意图。
在本申请实施例中，第二初始电源信号的电位可以大于第一初始电源信号的电位，且可以小于第一发光元件10的启亮电压。假设如图2所示，第一发光元件10与第一像素电路20所连接的一端为第一发光元件10的阳极，则驱动第一发光元件10发光的过程即为：先控制第二初始电源端Vinit2向第一发光元件10的阳极输出第二初始电源信号，如此，第一发光元件10的阳极的起始电位即可以为第二初始电源信号的电位(该过程可以称为复位阶段)。然后，再响应于第一初始电源端Vinit1提供的第一初始电源信号，以及其他信号输出驱动信号，此时，第一发光元件10的阳极的电位可以自第二初始电源信号的电位不断上升。当第一发光元件10的阳极的电位上升至与阴极压差达到启亮电压的电位，即启亮所需电位时，第一发光元件10可以发光(该过程可以称为发光阶段)。
基于控制第一发光元件10发光的原理可知，通过设置第二初始电源信号的电位较第一初始电源信号的电位更大，可以使得在复位阶段，第一发光元件10与第二像素电路20所连接的一端的起始电位较不设置第二初始电源信号端的像素电路中的起始电位大，进而可以使得在发光阶段，该端电位能够快速上升至启亮所需电位，解决了因透明导电线上寄生电容的影响导致出现发光延迟的问题。并且，通过设置第二初始电源信号的电位小于第一发光元件10的启亮电压，可以有效避免在驱动信号来临之前，即在复位阶段，第一发光元件10两端之间的压差达到启亮电压而误发光的现象发生。
可选的，在一些实施例中，多个第一像素电路20与多个第一发光元件10的电连接关系可以一一对应。即每个第一像素电路20均可以通过一条导电线L 1与一个第一发光元件10连接，且各个第一像素电路20所连接的第一发光元件10不同。本申请实施例对连接关系不做限定。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括位于第一显示区的第一发光元件，以及通过导电线与该第一发光元件连接且用于驱动该第一发光元件发光的第一像素电路。由于该第一像素电路与两个初始电源端连接，且用于对第一发光元件进行复位的第二初始电源端提供的信号的电位较另一初始电源信号端提供的信号的电位更大，因此使得在发光之前，第一发光元件一端的电位相对于未设置第二初始电源端时的电位更高，进而使得在发光时，第一发光元件两端的压差能够快速达到启亮电压。如此，解决了因导电线上寄生电容的影响导致发光延时的问题，降低了闪屏风险。
在一些实施例中，第一初始电源信号的电压值范围在约-5～-1V之间。在一些实施例中，第二初始电源信号的电压值减去VSS端提供的信号的电压值小于OLED启亮电压。在一些实施例中，第一发光元件的启亮电压在约1.2V～1.8V之间。在一些实施例中，VSS端提供的信号的电压值在约-5～-2.5V之间。在一些实施例中，第二初始电源信号的电压值在约-0.7～-3.8V之间。此处的约是指不严格限定界限，允许工艺和测量误差范围内上下浮动的数值。
作为一种可选的实现方式，本申请实施例记载的第二初始电源端Vinit2可以为交流电源端。如此，可以仅在复位阶段，控制第二初始电源端Vinit2提供第二初始电源信号，而在其他阶段(如，发光阶段)不提供第二初始电源信号。如，可以在其他阶段，控制第二初始电源信号的电位与第一发光元件10的另一端所连接的电源端(如，VSS)提供的电源信号的电位相同。
通过设置第二初始电源端Vinit2为交流电源端，可以避免在非发光阶段，因第一像素电路20中的晶体管(如，驱动晶体管)漏电，而导致第一发光元件10两端压差达到启亮时间而误发光的现象发生。即避免了显示异常现象发生。
此外，若第二初始电源端Vinit2为交流电源端，则可以设置第一初始电源端Vinit1与第二初始电源端Vinit2共用，并控制共用的初始电源端在不同阶段，灵活输出不同电位的初始电源信号即可。如此，还简化了布线，节省了成本。
作为另一种可选的实现方式，本申请实施例记载的第二初始电源端Vinit2可以直流电源端。如此，可以在各个阶段(包括复位阶段和复位阶段)，均控制第二初始电源端Vinit2提供第二初始电源信号。
需要说明的是，本申请实施例记载的第二初始电源端Vinit2提供的第二初始电源信号的电位还可以基于当前显示画面动态调整。可选的，可以由控制像素电路工作的驱动电路检测显示面板当前所显示画面，并根据检测结果灵活调整第二初始电源信号。如此，可以进一步确保显示效果较好。
例如，若显示面板当前显示画面为低灰阶画面，则驱动电路可以确定第一像素电路20输出的驱动信号的电位较小，相应的，为使得第一发光元件10与第一像素电路20所连接的一端的电位能够快速达到启亮所需电位，驱动电路可以控制第二初始电源信号的电位相对于未设置第二初始电源端时较大。相反的，若当前显示画面为高灰阶画面，则驱动电路可以确定第一像素电路20输出的驱动信号的电位较大，相应的，驱动电路可以控制第二初始电源信号的电位相对于于未设置第二初始电源端时较大，且相对于显示低灰阶画面时的电位较小。其中，低灰阶画面的灰阶值小于高灰阶画面的灰阶值。
图3是本申请实施例提供的一种第一像素电路的结构示意图。如图3所示，每个第一像素电路20还可以分别与栅极信号端G1、发光控制信号端EM、直流信号端VDD、数据信号端D1、复位信号端RST1和下拉控制端RST2连接。与第一发光元件10连接的第一像素电路20可以包括：驱动子电路201和复位子电路202。
其中，驱动子电路201可以分别与栅极信号端G1、数据信号端D1、发光控制信号端EM、直流信号端VDD、下拉控制端RST2、第一初始电源端Vinit1和目标节点N01连接。且该驱动子电路201可以响应于栅极信号端G1提供的栅极驱动信号、数据信号端D1提供的数据信号、发光控制信号端EM提供的发光控制信号、直流信号端VDD提供的直流信号、下拉控制端RST2提供的下拉控制信号和第一初始电源信号，向目标节点N01输出驱动信号。
复位子电路202可以分别与复位信号端RST1、第二初始电源端Vinit2和目标节点N01连接。且该复位子电路202可以响应于复位信号端RST1提供的复位信号，向目标节点N01输出第二初始电源信号。
第一发光元件10可以通过导电线L1与目标节点N01连接。
可选的，再结合图4所示的另一种第一像素电路，本申请实施例记载的第一发光元件10连接的第一像素电路20还可以包括：补偿子电路203。
其中，该补偿子电路203可以分别与稳压电源端VGL和目标节点N01连接， 补偿子电路203可以用于根据稳压电源端VGL提供的稳压信号，补偿目标节点N01的电位。例如，该稳压电源端VGL可以为地端。
可选的，图5是本申请实施例提供的又一种第一像素电路的结构示意图。如图5所示，驱动子电路201可以包括：数据写入单元2011、下拉单元2012、补偿单元2013、存储单元2014、发光控制单元2015以及驱动单元2016。
其中，数据写入单元2011可以分别与栅极信号端G1、数据信号端D1和第一节点N1连接，数据写入单元2011可以用于响应于栅极驱动信号，控制数据信号端D1和第一节点N1的通断状态。
例如，数据写入单元2011可以在栅极驱动信号的电位为第一电位时，控制第一节点N1与数据信号端D1导通，此时，数据信号端D1可以通过数据写入晶体管T1向第一节点N1输出数据信号。数据写入单元2011可以在栅极信号端G1提供的栅极驱动信号的电位为第二电位时，控制第一节点N1与数据信号端D1断开连接。可选的，第一电位可以为有效电位，第二电位可以为无效电位，且第一电位相对于第二电位可以为低电位。
下拉单元2012可以分别与下拉控制端RST2、第一初始电源端Vinit1和第二节点N2连接，下拉单元2012可以用于响应于下拉控制信号，控制第一初始电源端Vinit1和第二节点N2的通断状态。
例如，下拉单元2012可以在下拉控制端RST2提供的下拉控制信号的电位为第一电位时，控制第二节点N2与第一初始电源端Vinit1导通，此时，第一初始电源端Vinit1可以通过下拉晶体管T2向第二节点输出处于第二电位的第一初始电源信号，以实现对第二节点N2的降噪。下拉单元2012可以在下拉控制端RST2提供的下拉控制信号的电位为第二电位时，控制第二节点N2与第一初始电源端Vinit1断开连接。
补偿单元2013可以分别与栅极信号端G1、第三节点N3和第二节点N2连接，补偿单元2013可以用于响应于栅极驱动信号，根据第三节点N3的电位调整第二节点N2的电位。
存储单元2014可以分别与直流信号端VDD和第二节点N2连接，存储单元2014可以用于根据直流信号，控制第二节点N2的电位。
发光控制单元2015可以分别与发光控制信号端EM、直流信号端VDD、第一节点N1、第三节点N3和目标节点N01连接，发光控制单元2015可以用于响 应于发光控制信号，控制直流信号端VDD和第一节点N1的通断状态，以及控制第三节点N3和目标节点N01的通断状态。
例如，发光控制单元2015可以在发光控制信号的电位为第一电位时，控制第一节点N1与直流信号端VDD导通，此时，直流信号端VDD可以通过发光控制晶体管T4向第一节点N1输出直流电源信号。且，可以控制第三节点N3与目标节点N01导通。发光控制单元2015可以在发光控制信号的电位为第二电位时，控制第一节点N1与直流信号端VDD断开连接，且控制第三节点N3与目标节点N01断开连接。
驱动单元2016可以分别与第二节点N2、第一节点N1和第三节点N3连接，驱动单元2016可以用于根据第二节点N2的电位和第一节点N1的电位，向第三节点N3输出驱动信号。
例如，驱动单元2016可以根据第二节点N2的电位和第一节点N1的电位，向第三节点N3输出驱动电流。相应的，在发光控制单元2015控制第三节点N3与目标节点N01导通时，驱动电流可以经发光控制单元2015被输出至目标节点N01。
图6是本申请实施例提供的再一种第一像素电路的结构示意图。如图6所示，补偿子电路203可以包括：补偿电容C1。该补偿电容C1的一端可以与目标节点N01连接，该补偿电容的另一端可以与稳压电源端VGL连接。
通过设置该补偿电容C1，可以实现对透明导电线L1上的寄生电容的有效补偿，从另一方面加快第一发光元件10两端压差达到启亮电压的时间。可选的，补偿电容C1的容值相对于导电线L1上的寄生电容可以设置的较小，由此可以保留一定的补偿值偏差范围。
再继续参考图6所示第一像素电路，其中，数据写入单元2011可以包括：数据写入晶体管T1；下拉单元2012可以包括：下拉晶体管T2；补偿单元2013可以包括：补偿晶体管T3；发光控制单元2014可以包括：第一发光控制晶体管T4和第二发光控制晶体管T5；存储单元2015可以包括：存储电容C0；驱动单元2016可以包括：驱动晶体管T6。复位子电路202可以包括：复位晶体管T7。
其中，数据写入晶体管T1的栅极可以与栅极信号端G1连接，第一极可以与数据信号端D1连接，第二极可以与第一节点N1连接。
下拉晶体管T2的栅极可以与下拉控制端RST2连接，第一极可以与第一初 始电源端Vinit1连接，第二极可以与第二节点N2连接。
补偿晶体管T3的栅极可以与栅极信号端G1连接，第一极可以与第三节点N3连接，第二极可以与第二节点N2连接。
第一发光控制晶体管T4和第二发光控制晶体管T5的栅极均与发光控制信号端EM连接，第一发光控制晶体管T4的第一极与直流信号端VDD连接，第一发光控制晶体管T4的第二极与第一节点N1连接，第二发光控制晶体管T5的第一极与第三节点N3连接，第二发光控制晶体管T5的第二极与目标节点N01连接。
存储电容C0的一端可以与第二节点N1连接，另一端可以与直流信号端VDD连接。
驱动晶体管T6的栅极可以与第二节点N2连接，驱动晶体管T6的第一极可以与第一节点N1连接，驱动晶体管T6的第二极可以与第三节点N3连接。
复位晶体管T7的栅极可以与复位信号端RST1连接，复位晶体管T7的第一极可以与第二初始电源端Vinit2连接，复位晶体管T7的第二极可以与目标节点N01连接。
此外，参考图6可以看出，目标节点N01至第一发光元件10的阳极(即，图5示出的节点N02)之间的连接线即为导电线L1。该导电线L1上的负载(loading)包括并联的寄生电容Cap和寄生电阻R1。再结合图7所示驱动电流流向示意图可知，驱动信号中的电荷一般会先流向寄生电容Cap，由此使得节点N02的电位不断升高。故可以进一步确定，寄生电容Cap的容值越大，节点N02的电位上升速率越慢。即，第一发光元件10的阳极电位达到启亮所需电位的时间越长。需要说明的是，图6仅是示意性示出一种第一像素电路，本申请实施例并不对第一像素电路的具体结构进行限定。即第一像素电路可以为图6所示的7T2C(即，7个晶体管和2个电容)，或者，也可以为其他结构，如4T2C。
示例的，以图6所示第一像素电路20，导电线L1上的寄生电容Cap的容值c为1.5皮法(pF)，寄生电阻R1的阻值r为300千欧(kΩ)，第一初始电源信号的电位v1和VSS提供的电源信号的电位v2均为-3伏特(V)为例：
图8示出了第二初始电源信号端Vinit2提供的第二初始电源信号的电位v3为-1.5V，且透明导电线L1上的loading分别为50％(即，c＝0.75pF，r＝150kΩ)和100％(即，c＝1.5pF，r＝300kΩ)时，第一发光元件10启亮所需时间的仿真 图。图9示出了第二初始电源信号的电位v3为-3V，且导电线L1上的loading分别为50％和100％时，第一发光元件10启亮所需时间的仿真图。图8和图9中，横轴均表示时间，单位为毫秒(ms)；纵轴均表示电流，单位为皮安(pA)，且参考图8和图9可以看出，第一发光元件10启亮时的电流为300pA。
对比图8和图9可以看出，第二初始电源信号的电位为-1.5V相对于为-3V，无论导电线L1上的loading多大，第一发光元件10的启亮所需时间均较短。即，第二初始电源信号的电位越大，第一发光元件10启亮越快。此外还可以看出，第二初始电源信号的电位为-3V相对于为-1.5V，50％loading与100％loading下第一发光元件10的启亮时间差异较大。故由此可以确定，本申请实施例通过设置第二初始电源信号的电位大于第一初始电源信号的电位，可以有效改善因导电线L1上的寄生电容，即导电线L1上的loading影响，造成启亮延迟的问题。
图10示出了第二初始电源信号的电位v3为-1.5V时，且导电线L1上的loading分别为50％和100％时，第一发光元件10的阳极电位达到启亮所需电位的仿真图。图11示出了第二初始电源信号的电位v3为-3V，且导电线L1上的loading分别为50％和100％时，第一发光元件10的阳极电位达到启亮所需电位的仿真图。且图10和图11中，横轴均表示时间，单位为ms；纵轴均表示第一发光元件10的阳极电位，单位为V，且可以看出启亮所需电位均为-1V。
对比图10和图11可以看出，第二初始电源信号的电位为-1.5V相对于为-3V，无论导电线L1上的loading多大，第一发光元件10的阳极电位上升至(也可以称为爬升至)启亮所需电位1V的坡度越小，时间越短。即，第二初始电源信号的电位越大，第一发光元件10的阳极电位越能够较快的达到启亮所需电位。且还可以看出，第二初始电源信号的电位为-3V相对于为-1.5V，50％loading与100％loading下第一发光元件10的阳极电位达到启亮所需电位的时间差异越大。故，由此可以确定，本申请实施例通过设置第二初始电源信号的电位大于第一初始电源信号的电位，即设置第二初始电源信号的电位较大，可以使得第一发光元件10一端的电位能够快速达到启亮所需电位，相应的，即可以使得第一发光元件10两端之间的压差能够快速达到启亮电压，缩短第一发光元件10的启亮时间，从而有效改善了启亮延迟问题。
为了进一步体现本申请实施例的有益效果，针对高灰阶画面、低灰阶画面以及黑态画面，以第二初始电源信号的电位为-1.5V和-3V，对第一发光元件10 中的一个子像素(如，红色子像素)进行了仿真。其中，仿真结果可以参考下述表1至表3。表1示出的为显示高灰阶画面，且导电线L1上的loading分别为50％loading和100％loading时，第一发光元件10发光时的发光电流，以及两者的电流差异百分比delta。表2示出的为显示低灰阶画面，且导电线L1上的loading分别为50％loading和100％loading时，第一发光元件10发光时的发光电流，以及两者的电流差异百分比delta。表3示出的为显示黑态画面，且导电线L1上的loading分别为50％loading和100％loading时，第一发光元件10发光时的发光电流，以及两者的电流差异百分比delta。
表1
Figure PCTCN2020118657-appb-000001
表2
Figure PCTCN2020118657-appb-000002
表3
Figure PCTCN2020118657-appb-000003
参考上述表1可以看出，在显示高灰阶画面时，在不同loading下，任一第二初始电源信号对应的第一发光元件10的发光电流差异均较小，如表1示出的均小于2％，满足伽马(gamma)标准。如此可以确定，本申请实施例提高第二初始电源信号的电位，不会对高灰阶画面的显示造成任何影响，即显示高灰阶 画面时，第一发光元件10的发光电流也可以满足发光电流标准。
参考上述表2可以看出，在显示低灰阶画面时，在不同loading下，较大电位(如，-1.5V)的第二初始电源信号对应的第一发光元件10的发光电流差异较小，如表1示出的为13.54％，较小电位(如，-3V)的第二初始电源信号对应的第一发光元件10的发光电流差异较大，如表1示出的为72.19％。由此可以确定，对于低灰阶画面，通过提高第二初始电源信号的电位，可以使得在不同负载下，第一发光元件10的亮度差异较小，即还可以确保灰阶亮度均一性较好。
参考上述表3可以看出，在显示黑态画面(可以理解为不显示画面)时，在不同loading下，任一第二初始电源信号对应的第一发光元件10的发光电流差异均较小，如此可以确定，本申请实施例提高第二初始电源信号的电位，不会对黑态画面的显示造成任何影响，此外，在提高第二初始电源信号的电位为-1.5V后，不同负载下，第一发光元件10的发光电流也可以均小于1pA，满足黑态电流标准(specific)。由此也可以确定，提高第二初始电源信号的电位为-1.5V，在复位阶段，第一发光元件10两端压差也无法达到启亮电压，不会误发光。
基于以上仿真表可以确定，通过提高第二初始电源信号的电位，不会影响任一类型的显示画面(包括高灰阶画面、低灰阶画面和黑态画面)的正常显示，且可以确保低灰阶画面的亮度均一性较好，以及改善启亮延迟问题。
由于第二显示区A12为非透明显示区，因此驱动该第二显示区A12内的发光元件的像素电路可以位于该第二显示区A12内，且两者之间无需通过导电线连接。例如，图12示出了本申请实施例提供的再一种显示面板的结构示意图。如图12所示，该显示面板还可以包括：位于第二显示区A12的多个第二发光元件30，以及位于第二显示区A12的多个第二像素电路40。
其中，该多个第二像素电路40中的至少一个第二像素电路40，可以与多个第二发光元件30中的至少一个第二发光元件30连接，且该至少一个第二像素电路40在衬底基板01上的正投影，与所连接的至少一个第二发光元件30在衬底基板01上的正投影至少部分可以重叠。
或者，显示面板中的多个第二像素电路40与多个第二发光元件30在电连接关系上也可以一一对应。即每个第二像素电路40均可以与一个第二发光元件30连接，且各个第二像素电路40所连接的第二发光元件30不同。
还需要说明的是，为正常驱动显示面板工作，如图13所示，显示面板还会 包括沿第一方向延伸的多条驱动信号线，如沿第一方向X1延伸的多条栅线Gate和多条发光控制线EMl，以及沿第二方向X2延伸的多条数据线Data，第一方向X1与第二方向X2可以垂直。
其中，结合图6所示第一像素电路，栅线Gate可以与栅极信号端G1连接，并为栅极信号端G1输出栅极驱动信号。数据线Data可以与数据信号端D1连接，并为数据信号端D1输出数据信号。发光控制线EMl可以与发光控制信号端EM连接，并为发光控制信号端EM输出发光控制信号。
并且，为了保证第一显示区A11的透光率，该多条驱动信号线均不会位于第一显示区A11内，而仅位于第二显示区A12内。此外，与导电线L1不同层的驱动信号线(如，Gate、EMl和Data)可以与导电线L1至少部分重叠，或，完全重叠。与导电线L1同层的驱动信号线与导电线L1不重叠。且，为避免导电线L1对其他驱动信号的影响，导电线L1在衬底基板01上的正投影，与连接不同层的过孔区域在衬底基板01上的正投影可以不重叠。
图14是以图12和图13所示显示面板为例，示出的一种包括第一显示区A11、像素电路区A2和第二显示区A12的简图。其中，P1是指一个第二像素电路40以及与其连接的一个第二发光元件30，D_1和D_2是指第一像素电路20，P2是指第一发光元件10。并且，结合图1和图6可以看出，目标节点N01可以位于像素电路区A2，节点N02可以位于第一显示区A11。
可选的，第二显示区A12中包括多个第二发光元件30和多个第二像素电路40，而第一显示区A11中仅包括多个第一发光元件10，不包括多个第一像素电路20。相应的，多个第一像素电路20设置在除第一显示区A11之外的其他区域中。如，多个第一像素电路20可以设置于像素电路区A3。或者，多个第一像素电路20可以设置于第二显示区A12中。或者，多个第一像素电路20可以部分设置于像素电路区A3中，部分设置于第二显示区A12中。
需要说明的是，结合图13所示显示面板，若多个第二像素电路20设置于像素电路区A3中，则导电线L1可以自第一显示区A11先延伸至第二显示区A12，再进一步自第二显示区A12延伸至像素电路区A13。或者，导电线L1可以直接从第一显示区A11延伸至像素电路区A3，而不经过第二显示区A12。
再结合图12至图14所示的显示面板还可以看出，像素电路区A2和第二显示区A12可以沿显示面板中的数据线的延伸方向(即，第二方向X2)依次排布。 即像素电路区A2可以位于第二显示区A12与边框之间的区域。如此设置，可以使得第一像素电路20与第一发光元件10之间的距离可以较小，相应的，不仅便于走线，还可以使得设置的导电线L1的长度较短，进而，导电线L1上的寄生电容即会相应的较小，进一步解决了启亮延时的问题。
可选的，本申请实施例记载的第二像素电路40与第一像素电路20的结构可以相同，即可以均为图6所示的双Vinit结构，如此，还可以确保第二显示区A12的显示效果能够较好。或者，第二像素电路40也可以为单Vinit结构，即第二像素电路40仅连接一个初始电源端。
可选的，为了简化走线，节省成本，在第二像素电路40与第一像素电路20的结构相同时，第一像素电路20和第二像素电路40可以共用第一初始电源端Vinit1，且共用第二初始电源端Vinit2。或者，第一像素电路20和第二像素电路40也可以连接不同的初始电源端(包括第一初始电源端Vinit1和第二初始电源端Vinit2)，进而驱动电路可以灵活控制不同显示区内的像素电路所连接的初始电源端提供的初始电源信号的电位。
可选的，为了进一步确保第一显示区A11内的透光率，上述实施例记载的导电线L1可以为透明导电线。如，该导电线L1可以由氧化铟锡(indium tin oxide，ITO)或铟镓锌氧化物(indium gallium zinc oxide，IGZO)等透明材料制成。假设该导电线L1由ITO材料制成，则该导电线L1也可以称为ITO走线。
可选的，参考图15示的再一种显示面板，该显示面板还可以包括：感光传感器50，且该感光传感器50可以位于第一显示区A11内。如此，感光传感器即无需额外占用非显示区的位置，有利于显示面板的窄边框设计。若该感光传感器为摄像头组件，则该显示面板也可以称为具有屏下摄像头的显示面板。
可选的，本申请实施例记载的发光元件(包括第一发光元件10和第二发光元件30)可以均为电致发光(electroluminescence，EL)器件。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括位于第一显示区的第一发光元件，以及通过导电线与该第一发光元件连接且用于驱动该第一发光元件发光的第一像素电路。由于该第一像素电路与两个初始电源端连接，且用于对第一发光元件进行复位的第二初始电源端提供的信号的电位较另一初始电源信号端提供的信号的电位更大，因此使得在发光之前，第一发光元件一端的电位相对于未设置第二初始电源端时的电位更高，进而使得在发光时， 第一发光元件两端的压差能够快速达到启亮电压。如此，解决了因导电线上寄生电容的影响导致发光延时的问题，降低了闪屏风险。
图16是本申请实施例提供的一种像素电路的驱动方法流程图，该像素电路可以为上述附图中示出的显示面板中的第一像素电路20。如图16所示，该方法可以包括：
步骤1601、在复位阶段，第一像素电路向所连接的第一发光元件输出第二初始电源端提供的第二初始电源信号。
步骤1602、在发光阶段，第一像素电路响应于第一初始电源端提供的第一初始电源信号，向所连接的第一发光元件输出驱动信号。
其中，第二初始电源信号的电位大于第一初始电源信号的电位，且小于第一发光元件的启亮电压。
综上所述，本申请实施例提供了一种像素电路的驱动方法，由于该第一像素电路与两个初始电源端连接，且用于对第一发光元件进行复位的第二初始电源端提供的初始电源信号的电位较另一初始电源信号端提供的信号的电位更大，因此使得在发光之前，第一发光元件一端的电位相对于未设置第二初始电源端时的电位更高，进而使得在发光时，第一发光元件两端的压差能够快速达到启亮电压。如此，解决了因导电线上寄生电容的影响导致发光延时的问题，降低了闪屏风险。
可选的，如上述装置侧记载，第二初始电源端Vinit2可以为交流电源端，或者也可以为直流电源端。相应的，本申请实施例记载的方法还可以包括：
在复位阶段和发光阶段，向第二初始电源端提供第二初始电源信号，第二初始电源信号为直流信号；或者，在复位阶段，向第二初始电源端提供第二初始电源信号，第二初始电源信号为交流信号。
以图6所示第一像素电路20，第一电位相对于第二电位为低电位为例，图17示出了第二初始电源端Vinit2为直流电源端时的第一像素电路工作时序图。图18示出了第二初始电源端Vinit2为交流电源端时的第一像素电路工作时序图。结合图17和图18可以看出，整个第一像素电路工作共包括三个阶段“下拉阶段t1，复位阶段t2和发光阶段t3”。
其中，在下拉阶段t1，下拉控制端RST2提供的下拉控制信号的电位均为第 一电位，此时，下拉晶体管T2可以开启。第一初始电源端Vinit1可以通过下拉晶体管T2向第二节点N2输出处于第二电位的第一初始电源信号，从而实现对第二节点N2的下拉重置。
在复位阶段t2，复位信号端RST1提供的复位信号的电位，以及栅极信号端G1提供的栅极驱动信号的电位为第一电位，此时，数据写入晶体管T1和复位晶体管T7可以开启。第二初始电源端Vinit2可以通过复位晶体管T7向目标节点N01输出处于第二电位的第二初始电源信号，从而实现对目标节点N01的复位。数据信号端D1可以通过数据写入晶体管T1向第一节点N1输出数据信号，从而实现对第一节点N1的充电。
在发光阶段t3，发光控制信号端EM提供的发光控制信号的电位为第一电位，此时，发光控制晶体管T4和T5均开启。直流信号端VDD通过发光控制晶体管T4向第一节点N1输出直流电源信号，驱动晶体管T6根据第一节点N1的电位和第二节点N2的电位，向第三节点N3输出驱动电流。然后，该驱动电流再经发光控制晶体管T5输出至目标节点N01。在目标节点N01的电位达到启亮所需电位时，第一发光元件10发光。
图17和图18的区别在于：图17中，第二初始电源端Vinit2提供的第二初始电源信号的电位持续为所需的第二电位(如，-1.5V)。图18中，仅复位阶段t2，第二初始电源端Vinit2提供的第二初始电源信号的电位持续为所需的第二电位，而在下拉阶段t1和发光阶段t3，第二初始电源信号的电位可以与VSS端提供的电源信号的电位一致。
综上所述，本申请实施例提供了一种像素电路的驱动方法，由于该第一像素电路与两个初始电源端连接，且用于对第一发光元件进行复位的第二初始电源端提供的初始电源信号的电位较另一初始电源信号端提供的信号的电位更大，因此使得在发光之前，第一发光元件一端的电位相对于未设置第二初始电源端时的电位更高，进而使得在发光时，第一发光元件两端的压差能够快速达到启亮电压。如此，解决了因导电线上寄生电容的影响导致发光延时的问题，降低了闪屏风险。
可选的，图19是本申请实施例提供的一种显示装置的结构示意图。如图19所示，该显示装置可以包括：驱动电路100以及如图1、图2、图11至图15任 一所示的显示面板200，该显示面板200包括多个第一像素电路。
其中，驱动电路100可以与显示面板200中的至少一个第一像素电路连接，且驱动电路100可以用于驱动该至少一个第一像素电路工作。此外，驱动电路100也可以与至少一个第二像素电路连接，并驱动至少一个第二像素电路工作。例如，驱动电路100可以通过图13所示的各条驱动信号线连接至显示面板200中的像素电路。
可选的，驱动电路100还可以用于基于显示面板200当前所显示画面，控制第一像素电路20所连接的第二初始电源信号端提供的第二初始电源信号的电位。即，第二初始电源信号的电位可动态调整，如此，提高了驱动灵活性。
可选的，该显示装置可以为：有机发光二极管(organic light-emitting diode，OLED)显示装置、液晶显示(liquid crystal display，LCD)装置、手机、电视机和显示器等任何具有显示功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    衬底基板，所述衬底基板具有显示区和位于所述显示区至少一侧的非显示区，所述显示区包括第一显示区和分辨率高于所述第一显示区的第二显示区，所述非显示区包括像素电路区；
    位于所述第一显示区的多个第一发光元件；
    位于所述像素电路区的多个第一像素电路，所述多个第一像素电路与所述多个第一发光元件在所述衬底基板上的正投影不重叠；
    所述多个第一像素电路中的至少一个第一像素电路通过至少一条导电线与所述多个第一发光元件中的至少一个第一发光元件连接，且所述至少一个第一像素电路分别与第一初始电源端和第二初始电源端连接，所述第一初始电源端被配置为提供第一初始电源信号，所述第二初始电源端被配置为提供第二初始电源信号以对所述第一发光元件复位，且，所述第二初始电源信号的电位大于所述第一初始电源信号的电位，且小于所述第一发光元件的启亮电压。
  2. 根据权利要求1所述的显示面板，其中，所述第二初始电源端为交流电源端。
  3. 根据权利要求1所述的显示面板，其中，所述第二初始电源端为直流电源端。
  4. 根据权利要求1至3任一所述的显示面板，其中，所述至少一个第一像素电路还分别与栅极信号端、发光控制信号端、直流信号端、数据信号端、下拉控制端和复位信号端连接；所述至少一个第一像素电路包括：驱动子电路和复位子电路；
    其中，所述驱动子电路分别与所述栅极信号端、所述数据信号端、所述发光控制信号端、所述直流信号端、所述下拉控制端、所述第一初始电源端和目标节点连接，所述驱动子电路用于响应于所述栅极信号端提供的栅极驱动信号、所述数据信号端提供的数据信号、所述发光控制信号端提供的发光控制信号、 所述直流信号端提供的直流信号、所述下拉电源端提供的下拉控制信号和所述第一初始电源信号，向所述目标节点输出驱动信号；
    所述复位子电路分别与所述复位信号端、所述第二初始电源端和所述目标节点连接，所述复位子电路用于响应于所述复位信号端提供的复位信号，向所述目标节点输出所述第二初始电源信号；
    所述第一发光元件通过所述导电线与所述目标节点连接。
  5. 根据权利要求4所述的显示面板，其中，所述至少一个第一像素电路还包括：补偿子电路；
    所述补偿子电路分别与稳压电源端和所述目标节点连接，所述补偿子电路用于根据所述稳压电源端提供的稳压信号，补偿所述目标节点的电位。
  6. 根据权利要求5所述的显示面板，其中，所述补偿子电路包括：补偿电容；
    所述补偿电容的一端与所述目标节点连接，所述补偿电容的另一端与所述稳压电源端连接。
  7. 根据权利要求4所述的显示面板，其中，所述复位子电路包括：复位晶体管；
    所述复位晶体管的栅极与所述复位信号端连接，所述复位晶体管的第一极与所述第二初始电源端连接，所述复位晶体管的第二极与所述目标节点连接。
  8. 根据权利要求4所述的显示面板，其中，所述驱动子电路包括：数据写入单元、下拉单元、补偿单元、存储单元、发光控制单元以及驱动单元；
    所述数据写入单元分别与所述栅极信号端、所述数据信号端和第一节点连接，所述数据写入单元用于响应于所述栅极驱动信号，控制所述数据信号端和所述第一节点的通断状态；
    所述下拉单元分别与所述下拉控制端、所述第一初始电源端和第二节点连接，所述下拉单元用于响应于所述下拉控制信号，控制所述第一初始电源端和所述第二节点的通断状态；
    所述补偿单元分别与所述栅极信号端、第三节点和所述第二节点连接，所述补偿单元用于响应于所述栅极驱动信号，根据所述第三节点的电位调整所述第二节点的电位；
    所述存储单元分别与所述直流信号端和所述第二节点连接，所述存储单元用于根据所述直流信号，控制所述第二节点的电位；
    所述发光控制单元分别与所述发光控制信号端、所述直流信号端、所述第一节点、所述第三节点和所述目标节点连接，所述发光控制单元用于响应于所述发光控制信号，控制所述直流信号端和所述第一节点的通断状态，以及控制所述第三节点和所述目标节点的通断状态；
    所述驱动单元分别与所述第二节点、所述第一节点和所述第三节点连接，所述驱动单元用于根据所述第二节点的电位和所述第一节点的电位，向所述第三节点输出所述驱动信号。
  9. 根据权利要求8所述的显示面板，其中，所述数据写入单元包括：数据写入晶体管；所述下拉单元包括：下拉晶体管；所述补偿单元包括：补偿晶体管；所述存储单元包括：存储电容；所述发光控制单元包括：第一发光控制晶体管和第二发光控制晶体管；所述驱动单元包括：驱动晶体管；
    所述数据写入晶体管的栅极与所述栅极信号端连接，所述数据写入晶体管的第一极与所述数据信号端连接，所述数据写入晶体管的第二极与所述第一节点连接；
    所述下拉晶体管的栅极与所述下拉控制端连接，所述下拉晶体管的第一极与所述第一初始电源端连接，所述下拉晶体管的第二极与所述第二节点连接；
    所述补偿晶体管的栅极与所述栅极信号端连接，所述补偿晶体管的第一极与所述第三节点连接，所述补偿晶体管的第二极与所述第二节点连接；
    所述存储电容的一端与所述第二节点连接，另一端与所述直流信号端连接；
    所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极均与所述发光控制信号端连接，所述第一发光控制晶体管的第一极与所述直流信号端连接，所述第一发光控制晶体管的第二极与所述第一节点连接；所述第二发光控制晶体管的第一极与所述第三节点连接，所述第二发光控制晶体管的第二极与所述目标节点连接；
    所述驱动晶体管的栅极与所述第二节点连接，所述驱动晶体管的第一极与所述第一节点连接，所述驱动晶体管的第二极与所述第三节点连接。
  10. 根据权利要求1至9任一所述的显示面板，其中，所述显示面板还包括：
    位于所述第二显示区的多个第二发光元件；
    位于所述第二显示区的多个第二像素电路；
    其中，所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件连接，且所述至少一个第二像素电路与所述至少一个第二发光元件在所述衬底基板上的正投影至少部分重叠。
  11. 根据权利要求10所述的显示面板，其中，所述至少一个第一像素电路和所述至少一个第二像素电路共用所述第一初始电源端。
  12. 根据权利要求11所述的显示面板，其中，所述至少一个第一像素电路和所述至少一个第二像素电路共用所述第二初始电源端。
  13. 根据权利要求1至12任一所述的显示面板，其中，所述像素电路区和所述第二显示区沿所述显示面板中的数据线的延伸方向依次排布。
  14. 根据权利要求1至13任一所述的显示面板，其中，所述导电线为透明导电线，且所述透明导电线由氧化铟锡材料制成。
  15. 根据权利要求1至14任一所述的显示面板，其中，所述显示面板还包括：感光传感器，所述感光传感器位于所述第一显示区内。
  16. 根据权利要求9所述的显示面板，其中，所述至少一个第一像素电路还包括：补偿子电路；所述补偿子电路分别与稳压电源端和所述目标节点连接，所述补偿子电路用于根据所述稳压电源端提供的稳压信号，补偿所述目标节点的电位；所述补偿子电路包括：补偿电容；所述补偿电容的一端与所述目标节 点连接，所述补偿电容的另一端与所述稳压电源端连接；所述复位子电路包括：复位晶体管；所述复位晶体管的栅极与所述复位信号端连接，所述复位晶体管的第一极与所述第二初始电源端连接，所述复位晶体管的第二极与所述目标节点连接；
    所述显示面板还包括：位于所述第二显示区的多个第二发光元件；位于所述第二显示区的多个第二像素电路；其中，所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件连接，且所述至少一个第二像素电路与所述至少一个第二发光元件在所述衬底基板上的正投影至少部分重叠；所述至少一个第一像素电路和所述至少一个第二像素电路共用所述第一初始电源端，且共用所述第二初始电源端；
    所述像素电路区和所述第二显示区沿所述显示面板中的数据线的延伸方向依次排布；所述导电线为透明导电线，且所述透明导电线由氧化铟锡材料制成；所述显示面板还包括：感光传感器，所述感光传感器位于所述第一显示区内。
  17. 一种像素电路的驱动方法，其中，所述像素电路为如权利要求1至16任一所述的显示面板中的第一像素电路；所述方法包括：
    在复位阶段，所述第一像素电路向所连接的第一发光元件输出第二初始电源端提供的第二初始电源信号；
    在发光阶段，所述第一像素电路响应于第一初始电源端提供的第一初始电源信号，向所连接的所述第一发光元件输出驱动信号；
    其中，所述第二初始电源信号的电位大于所述第一初始电源信号的电位，且小于所述第一发光元件的启亮电压。
  18. 根据权利要求17所述的方法，其中，所述方法还包括：
    在所述复位阶段和所述发光阶段，向所述第二初始电源端提供所述第二初始电源信号，所述第二初始电源信号为直流信号；
    或者，在所述复位阶段，向所述第二初始电源端提供所述第二初始电源信号，所述第二初始电源信号为交流信号。
  19. 一种显示装置，其中，所述显示装置包括：驱动电路以及如权利要求1 至16任一所述的显示面板，所述显示面板包括多个第一像素电路；
    所述驱动电路与所述多个第一像素电路中的至少一个第一像素电路连接，所述驱动电路用于驱动所述至少一个第一像素电路工作。
  20. 根据权利要求19所述的显示装置，其中，所述驱动电路还用于基于所述显示面板当前所显示画面，控制所述至少第一像素电路所连接的第二初始电源信号端提供的第二初始电源信号的电位。
PCT/CN2020/118657 2020-09-29 2020-09-29 显示面板及其像素电路的驱动方法、显示装置 WO2022067460A1 (zh)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN202080002169.4A CN114667560B (zh) 2020-09-29 2020-09-29 显示面板及其像素电路的驱动方法、显示装置
US17/441,716 US11798456B2 (en) 2020-09-29 2020-09-29 Display panel, method for driving pixel circuit of display panel, and display device
PCT/CN2020/118657 WO2022067460A1 (zh) 2020-09-29 2020-09-29 显示面板及其像素电路的驱动方法、显示装置
CN202080002277.1A CN114730540A (zh) 2020-09-29 2020-10-12 像素驱动电路、其驱动方法、显示基板及显示装置
US17/426,681 US11978380B2 (en) 2020-09-29 2020-10-12 Pixel driving circuit, driving method thereof, display substrate and display device
PCT/CN2020/120484 WO2022067877A1 (zh) 2020-09-29 2020-10-12 像素驱动电路、其驱动方法、显示基板及显示装置
US18/221,960 US20230360581A1 (en) 2020-09-29 2023-07-14 Display panel, method for driving pixel circuit of display panel, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/118657 WO2022067460A1 (zh) 2020-09-29 2020-09-29 显示面板及其像素电路的驱动方法、显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/441,716 A-371-Of-International US11798456B2 (en) 2020-09-29 2020-09-29 Display panel, method for driving pixel circuit of display panel, and display device
US18/221,960 Continuation US20230360581A1 (en) 2020-09-29 2023-07-14 Display panel, method for driving pixel circuit of display panel, and display device

Publications (1)

Publication Number Publication Date
WO2022067460A1 true WO2022067460A1 (zh) 2022-04-07

Family

ID=80949246

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/CN2020/118657 WO2022067460A1 (zh) 2020-09-29 2020-09-29 显示面板及其像素电路的驱动方法、显示装置
PCT/CN2020/120484 WO2022067877A1 (zh) 2020-09-29 2020-10-12 像素驱动电路、其驱动方法、显示基板及显示装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/120484 WO2022067877A1 (zh) 2020-09-29 2020-10-12 像素驱动电路、其驱动方法、显示基板及显示装置

Country Status (3)

Country Link
US (3) US11798456B2 (zh)
CN (2) CN114667560B (zh)
WO (2) WO2022067460A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117012152B (zh) * 2023-08-31 2024-05-17 惠科股份有限公司 像素驱动电路及显示装置

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100079361A1 (en) * 2008-09-29 2010-04-01 Samsung Electronics Co., Ltd. Display device and driving method thereof
US20120038605A1 (en) * 2010-08-11 2012-02-16 Samsung Mobile Display Co., Ltd. Pixel and Organic Light Emitting Display Device Using the Same
CN103778883A (zh) * 2012-10-25 2014-05-07 群康科技(深圳)有限公司 主动式矩阵有机发光二极管的像素驱动电路及其方法
CN104409047A (zh) * 2014-12-18 2015-03-11 合肥鑫晟光电科技有限公司 像素驱动电路、像素驱动方法和显示装置
CN104751784A (zh) * 2013-12-30 2015-07-01 乐金显示有限公司 有机发光显示器件及其驱动方法
KR20160070642A (ko) * 2014-12-10 2016-06-20 엘지디스플레이 주식회사 Oled 표시 장치
CN106157880A (zh) * 2015-04-23 2016-11-23 上海和辉光电有限公司 Oled像素补偿电路
CN106531074A (zh) * 2017-01-10 2017-03-22 上海天马有机发光显示技术有限公司 有机发光像素驱动电路、驱动方法以及有机发光显示面板
CN109215582A (zh) * 2018-09-28 2019-01-15 昆山国显光电有限公司 显示面板、像素电路的驱动方法及显示装置
CN110047432A (zh) * 2019-05-30 2019-07-23 京东方科技集团股份有限公司 一种像素电路、其驱动方法、显示面板及显示装置
CN110858471A (zh) * 2018-08-23 2020-03-03 三星显示有限公司 像素电路
CN111179855A (zh) * 2020-03-18 2020-05-19 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN111326560A (zh) * 2020-01-23 2020-06-23 京东方科技集团股份有限公司 显示基板和显示装置
CN111402814A (zh) * 2020-03-26 2020-07-10 昆山国显光电有限公司 显示面板、显示面板的驱动方法和显示装置
CN111508377A (zh) * 2020-05-29 2020-08-07 京东方科技集团股份有限公司 一种显示面板及显示装置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9922595B2 (en) * 2014-05-05 2018-03-20 Commonwealth Scientific And Industrial Research Organisation Pixel structure for OLED display panel
US10297781B2 (en) * 2016-06-30 2019-05-21 Lg Display Co., Ltd. Organic light emitting display device and driving method of the same
TWI612508B (zh) 2016-07-22 2018-01-21 友達光電股份有限公司 顯示裝置及其資料驅動器
KR102544322B1 (ko) 2016-09-26 2023-06-19 삼성디스플레이 주식회사 발광 표시 장치
CN106991964A (zh) 2017-04-14 2017-07-28 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN112767871B (zh) 2017-10-27 2023-06-23 武汉天马微电子有限公司 一种显示面板和电子设备
CN107564470B (zh) 2017-10-31 2019-09-24 京东方科技集团股份有限公司 一种有机发光显示面板的亮度调节方法及相关装置
CN108492782A (zh) * 2018-03-30 2018-09-04 武汉华星光电半导体显示技术有限公司 一种像素驱动电路及显示装置
CN108806578B (zh) 2018-06-08 2021-04-13 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN110619813B (zh) * 2018-06-20 2021-05-14 京东方科技集团股份有限公司 显示基板、其驱动方法、显示装置及高精度金属掩模版
US11238792B2 (en) * 2018-07-10 2022-02-01 Seeya Optronics Co., Ltd. Pixel circuit and display device
KR102561172B1 (ko) 2018-11-22 2023-07-31 삼성전자주식회사 디스플레이 내에 카메라 모듈이 포함된 전자 장치 및 상기 카메라 모듈 주변의 이미지를 보정하는 방법
WO2020113550A1 (en) 2018-12-07 2020-06-11 Lingdong Technology (Beijing) Co.Ltd Brushless direct-current motor using single wire to transmit information of positions of a plurality of magnets
CN110767157B (zh) 2019-01-31 2020-11-06 昆山国显光电有限公司 显示装置及其显示面板、oled阵列基板
KR20200117137A (ko) * 2019-04-03 2020-10-14 삼성전자주식회사 디스플레이를 포함하는 전자 장치
CN110767720B (zh) * 2019-06-05 2020-09-08 昆山国显光电有限公司 显示基板、显示面板及显示装置
CN111028757B (zh) 2019-12-25 2022-07-22 武汉天马微电子有限公司 显示装置及其驱动方法
CN111063719B (zh) 2019-12-30 2022-08-12 武汉天马微电子有限公司 显示面板及显示装置
KR20210120165A (ko) 2020-03-25 2021-10-07 삼성디스플레이 주식회사 표시 장치
KR102663276B1 (ko) * 2020-04-22 2024-05-08 삼성디스플레이 주식회사 표시 장치 및 이의 검사 방법
KR20220001034A (ko) * 2020-06-26 2022-01-05 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
KR20220002790A (ko) * 2020-06-30 2022-01-07 삼성디스플레이 주식회사 화소 및 유기 발광 표시 장치
KR20220027365A (ko) * 2020-08-26 2022-03-08 삼성디스플레이 주식회사 표시장치
KR20220059697A (ko) * 2020-11-03 2022-05-10 엘지디스플레이 주식회사 표시패널과 이를 이용한 표시장치

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100079361A1 (en) * 2008-09-29 2010-04-01 Samsung Electronics Co., Ltd. Display device and driving method thereof
US20120038605A1 (en) * 2010-08-11 2012-02-16 Samsung Mobile Display Co., Ltd. Pixel and Organic Light Emitting Display Device Using the Same
CN103778883A (zh) * 2012-10-25 2014-05-07 群康科技(深圳)有限公司 主动式矩阵有机发光二极管的像素驱动电路及其方法
CN104751784A (zh) * 2013-12-30 2015-07-01 乐金显示有限公司 有机发光显示器件及其驱动方法
KR20160070642A (ko) * 2014-12-10 2016-06-20 엘지디스플레이 주식회사 Oled 표시 장치
CN104409047A (zh) * 2014-12-18 2015-03-11 合肥鑫晟光电科技有限公司 像素驱动电路、像素驱动方法和显示装置
CN106157880A (zh) * 2015-04-23 2016-11-23 上海和辉光电有限公司 Oled像素补偿电路
CN106531074A (zh) * 2017-01-10 2017-03-22 上海天马有机发光显示技术有限公司 有机发光像素驱动电路、驱动方法以及有机发光显示面板
CN110858471A (zh) * 2018-08-23 2020-03-03 三星显示有限公司 像素电路
CN109215582A (zh) * 2018-09-28 2019-01-15 昆山国显光电有限公司 显示面板、像素电路的驱动方法及显示装置
CN110047432A (zh) * 2019-05-30 2019-07-23 京东方科技集团股份有限公司 一种像素电路、其驱动方法、显示面板及显示装置
CN111326560A (zh) * 2020-01-23 2020-06-23 京东方科技集团股份有限公司 显示基板和显示装置
CN111179855A (zh) * 2020-03-18 2020-05-19 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN111402814A (zh) * 2020-03-26 2020-07-10 昆山国显光电有限公司 显示面板、显示面板的驱动方法和显示装置
CN111508377A (zh) * 2020-05-29 2020-08-07 京东方科技集团股份有限公司 一种显示面板及显示装置

Also Published As

Publication number Publication date
CN114667560B (zh) 2024-07-09
US11798456B2 (en) 2023-10-24
WO2022067877A1 (zh) 2022-04-07
US11978380B2 (en) 2024-05-07
US20220309990A1 (en) 2022-09-29
US20230360581A1 (en) 2023-11-09
CN114667560A (zh) 2022-06-24
US20220319421A1 (en) 2022-10-06
CN114730540A (zh) 2022-07-08

Similar Documents

Publication Publication Date Title
US11881164B2 (en) Pixel circuit and driving method thereof, and display panel
US10902781B2 (en) Pixel circuit, driving method, organic light emitting display panel, and display device
US10181283B2 (en) Electronic circuit and driving method, display panel, and display apparatus
CN107358917B (zh) 一种像素电路、其驱动方法、显示面板及显示装置
CN104933993B (zh) 像素驱动电路及其驱动方法、显示装置
US10643535B2 (en) Driving method for preventing image sticking of display panel upon shutdown, and display device
US20200126478A1 (en) Pixel circuit and driving method thereof, display device
JP7159182B2 (ja) 画素回路及びその駆動方法、表示パネル
CN112908258B (zh) 像素驱动电路、驱动方法、显示面板与显示装置
US9595227B2 (en) Pixel circuit and driving method thereof, organic light emitting display panel and display apparatus
CN106910468A (zh) 显示面板、显示装置及像素电路的驱动方法
CN110176213A (zh) 像素电路及其驱动方法、显示面板
US11328668B2 (en) Pixel circuit and driving method thereof, and display panel
CN104240639A (zh) 一种像素电路、有机电致发光显示面板及显示装置
CN105161051A (zh) 像素电路及其驱动方法、阵列基板、显示面板及显示装置
CN107945743A (zh) 一种像素电路、其驱动方法及显示装置
TWI417843B (zh) 對偶畫素單元及對偶驅動電路
CN106960656B (zh) 一种有机发光显示面板及其显示方法
US10622424B2 (en) Pixel circuit and driving method thereof, display panel
US11501713B2 (en) Pixel circuit, driving method thereof and display device
US20180096654A1 (en) Pixel circuit, display panel and display device
CN108511497B (zh) 像素驱动电路的布线结构、显示面板和显示装置
CN107170409A (zh) 一种像素电路及显示面板
CN112581908A (zh) 像素驱动电路、驱动方法、显示面板与显示装置
US20190333446A1 (en) Pixel driving circuit and driving method thereof display panel and display apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20955488

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 12.07.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20955488

Country of ref document: EP

Kind code of ref document: A1