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WO2022047863A1 - 显示面板及拼接显示面板 - Google Patents

显示面板及拼接显示面板 Download PDF

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Publication number
WO2022047863A1
WO2022047863A1 PCT/CN2020/117725 CN2020117725W WO2022047863A1 WO 2022047863 A1 WO2022047863 A1 WO 2022047863A1 CN 2020117725 W CN2020117725 W CN 2020117725W WO 2022047863 A1 WO2022047863 A1 WO 2022047863A1
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WO
WIPO (PCT)
Prior art keywords
display panel
goa
signal
area
line
Prior art date
Application number
PCT/CN2020/117725
Other languages
English (en)
French (fr)
Inventor
王添鸿
钟云肖
金一坤
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US15/734,614 priority Critical patent/US11403991B2/en
Publication of WO2022047863A1 publication Critical patent/WO2022047863A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the invention relates to the field of display technology, in particular to a display panel with an ultra-narrow frame and a splicing display panel.
  • both sides of the entire chip-on-film area 12 have connecting lines connected to the GOA signal bus 11 , and the GOA signal bus 11 and the data lines of the GOA circuit area 13 have large area
  • the cross setting will cause the delay (RC Loading) on the GOA signal bus 11.
  • There is a non-negligible difference between the near end A and the far end B of the access point of the GOA signal bus 11 (refer to Figure 2 for the specific waveform difference). Therefore, As a result, the waveform delay of the GOA signal received by the GOA circuits in different regions varies greatly, which in turn makes the pixels in the display area poorly charged.
  • One object of the present invention is to provide a display panel, which is used to reduce the difference between the near end and the far end of the access point of the GOA signal bus.
  • the present invention provides a display panel including a main display area and a non-display area; the non-display area includes a wide area and three narrow areas, the one wide area and the three narrow areas surround the main display area, The width of the frame of the wide area is larger than the width of the frame of the narrow area; in the non-display area, the display panel further includes: a GOA circuit disposed in the wide area and close to the main display area; a GOA signal bus , which is arranged in parallel with the GOA circuit in the wide area, and is connected to the GOA circuit; the chip-on-film area is arranged in the wide area in parallel with the GOA signal bus, and the GOA signal bus is arranged in the GOA between the circuit and the chip-on-film area; wherein the chip-on-film area includes a plurality of thin-film chips arranged in an array, each thin-film chip has at least one output terminal, and the GOA signal bus has a corresponding output terminal for each thin-film At least one input end of the chip,
  • the output end includes a first output end and a second output end, the first output end and the second output end are respectively arranged on both sides of the thin film chip, and the input end includes a corresponding the first output end and the first input end and the second input end of the second output end; the first output end and the second output end are respectively connected to the first input through the metal wires terminal and the second input terminal.
  • the metal trace includes a plurality of first signal lines arranged in parallel;
  • the GOA signal bus includes a plurality of second signal lines arranged in parallel, and the second signal lines are parallel to the first signal lines;
  • the first signal lines are connected to the corresponding second signal lines through connecting lines, and the connecting lines are perpendicular to the second signal lines.
  • the display panel includes: a substrate; a first metal layer disposed on the substrate, and the first signal line and the second signal line are formed on the first metal
  • the first insulating layer is arranged on the substrate and covers the first metal layer; the second metal layer is arranged on the first insulating layer, and the connection line is formed in the second metal layer.
  • first via hole and a second via hole are formed on the first insulating layer, the first via hole corresponds to the first signal line, and the second via hole corresponds to the second signal line, so One end of the connection line is connected to the first signal line through a first via hole, and the other end of the connection line is connected to the second signal line through the second via hole.
  • the first signal line includes a clock signal line, a voltage line and a restart line.
  • clock signal line and the voltage line are connected to the GOA signal bus; the restart line is connected to the GOA circuit.
  • the wiring of the GOA circuit is formed in the first metal layer; a third via hole is further opened on the first insulating layer, and the third via hole corresponds to the wiring of the GOA circuit; One end of the connection line is connected to the first signal line through the first via hole, and the other end of the connection line is connected to the wiring of the GOA circuit through the third via hole.
  • Another object of the present invention is to provide a spliced display panel, comprising: a main display panel, the main display panel being the display panel; and at least one pair of display panels spliced in a narrow area of the main display panel.
  • the splicing distance between the main display panel and the sub-display panel is less than 1 mm.
  • the beneficial effects of the present invention are: by outputting the chip-on-film area from the traditional two sides, and outputting the signal from each thin-film chip, so as to reduce the signal difference of the GOA bus line, so that each level of GOA The difference of the GOA signal received by a single channel is reduced as much as possible, thereby reducing the difference of the output signal of the GOA circuit and reducing the influence on the charging of the pixels in the display area.
  • FIG. 1 is a plan view of a prior art display panel.
  • FIG. 2 is a waveform diagram of the GOA signal bus A at B in the prior art.
  • FIG. 3 is a schematic plan view of a display panel provided by the present invention.
  • FIG. 4 is a schematic diagram of the specific wiring of the connection (marked E) in FIG. 3 .
  • connection hole 5 and 4 are cross-sectional views of the connection hole.
  • FIG. 6 is a waveform diagram of detecting the GOA signal bus E in the present invention.
  • FIG. 7 is a schematic plan view of a spliced display panel provided by the present invention.
  • Main display area 110 wide area 120; narrow area 130;
  • GOA circuit 101 GOA signal bus 102; chip-on-film area 103;
  • Thin film chip 104 output end 105; first output end 1051;
  • Input terminal 106 first signal line 1031; second signal line 1021;
  • Metal trace 21 GOA circuit trace 1011; third via 1012;
  • a display panel 100 includes a main display area 110 and a non-display area.
  • the non-display area includes a wide area 120 and three narrow areas 130.
  • the wide area 120 and the three narrow areas 130 surround the main display area 110.
  • the width of the frame of the wide area 120 is larger than that of the narrow area. Border width of zone 130.
  • the display panel 100 is a product with three narrows and one wide, wherein the wide area 120 is used for setting control circuits, and the three narrow areas 130 are used for panel splicing.
  • the display panel 100 further includes: a GOA circuit 101 , a GOA signal bus 102 and a chip-on-film area 103 .
  • the GOA circuit 101 is disposed in the wide area 120 and close to the main display area 110 .
  • the GOA signal bus 102 is arranged in parallel with the GOA circuit 101 in the wide area 120 and is connected to the GOA circuit 101 .
  • the chip-on-film area 103 and the GOA signal bus 102 are disposed in parallel with the wide area 120 , and the GOA signal bus 102 is disposed between the GOA circuit 101 and the chip-on-film area 103 .
  • the chip-on-film area 103 includes a plurality of thin film chips 104 arranged in an array, each thin film chip 104 has at least one output terminal 105 , and the GOA signal bus 102 has at least one input terminal 106 corresponding to each thin film chip 104 , the output end 105 and the input end 106 are connected by a metal wire 21 .
  • the chip-on-film area 103 is output from the traditional two sides, and the signal is output from each thin-film chip, so as to reduce the signal difference of the GOA bus line, so that each level of GOA can receive a single channel.
  • the difference of the obtained GOA signal is reduced as much as possible, thereby reducing the difference of the output signal of the GOA circuit 101 and reducing the influence on the charging of the pixels in the display area.
  • the output end 105 includes a first output end 1051 and a second output end 1052, the first output end 1051 and the second output end 1052 are respectively disposed on two sides of the thin film chip, and the input end 106 includes The first input end 1061 and the second input end 1062 correspond to the first output end 1051 and the second output end 1052 .
  • the first output terminal 1051 and the second output terminal 1052 are respectively connected to the first input terminal 1061 and the second input terminal 1062 through the metal traces 21 .
  • the metal trace 21 includes a plurality of first signal lines 1031 arranged in parallel.
  • the GOA signal bus 102 includes a plurality of second signal lines 1021 arranged in parallel, and the second signal lines 1021 are parallel to the first signal lines 1031 .
  • the first signal lines 1031 are connected to the corresponding second signal lines 1021 through connecting lines 22 , and the connecting lines 22 are perpendicular to the second signal lines 1021 .
  • the layered structure diagram of the non-display area shown in FIG. 5 is a cross-sectional view of the position of the connection holes (the first via hole 1032 , the second via hole 1022 and the third via hole 1012 ) in FIG. 3 .
  • the display panel 100 includes: a substrate 201 , a first metal layer 202 , a first insulating layer 203 and a second metal layer 204 .
  • the first metal layer 202 is disposed on the substrate 201 , and the first signal line 1031 and the second signal line 1021 are formed in the first metal layer 202 .
  • the first insulating layer 203 is disposed on the substrate 201 and covers the first metal layer 202 .
  • the second metal layer 204 is disposed on the first insulating layer 203, and the connection line 22 is formed in the second metal layer.
  • a first via hole 1032 and a second via hole 1022 are defined on the first insulating layer 203 , the first via hole 1032 corresponds to the first signal line 1031 , and the second via hole 1022 corresponds to the second signal line Line 1021 , one end of the connection line 22 is connected to the first signal line 1031 through the first via hole 1032 , and the other end of the connection line 22 is connected to the second signal line 1021 through the second via hole 1022 .
  • the first signal line 1031 includes a clock signal line, a voltage line 108 and a restart line 107 .
  • the clock signal line and the voltage line 108 are connected to the GOA signal bus 102 .
  • the restart line 107 is connected to the GOA circuit 101 .
  • the traces of the GOA circuit 101 are formed in the first metal layer 202 .
  • a third via hole 1012 is further formed on the first insulating layer 203 , and the third via hole 1012 corresponds to the wiring of the GOA circuit 101 .
  • connection line 22 One end of the connection line 22 is connected to the first signal line 1031 through the first via hole 1032 , and the other end of the connection line 22 is connected to the trace 1011 of the GOA circuit through the third via hole 1012 .
  • the present invention detects the waveform of the GOA signal bus 102 . It can be seen that the waveform C of the present invention is almost the same as the original signal of the dotted line, while the prior art waveform D has a certain difference from the original signal.
  • the Falling Time ⁇ of prior art waveforms 5.85us is ⁇ 0.05us, which greatly reduces the waveform difference between the far and near ends of the signal source on the GOA signal trace.
  • the present invention further provides a spliced display panel 300 , including: a main display panel 301 and at least one secondary display panel 302 .
  • the main display panel 301 is the aforementioned display panel 100 .
  • the secondary display panel 302 is spliced to the narrow area 130 of the primary display panel.
  • the splicing distance between the main display panel 301 and the sub-display panel 302 is less than 1 mm.
  • the chip-on-film area 103 is output from the traditional two sides, and the signal output is performed by each thin-film chip 104, so as to reduce the signal difference of the GOA bus line, so that each level of GOA receives a single channel.
  • the difference of the obtained GOA signal is reduced as much as possible, thereby reducing the difference of the output signal of the GOA circuit 101 and reducing the influence on the charging of the pixels in the display area.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明提供一种显示面板及拼接显示面板，所述显示面板包括：GOA电路、GOA信号总线以及覆晶薄膜区。本发明通过将所述覆晶薄膜区由传统的两侧输出，更为由每个薄膜芯片进行信号的输出，以达到降低GOA总线走线的信号差异。

Description

显示面板及拼接显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种超窄边框的显示面板及拼接显示面板。
 背景技术
因应市场的需求，大尺寸和高解析度的显示器及超窄边框（UNB：Ultra NarrowBorder）成为市场的趋势，而近年来广受市场关注的拼接屏更是对极致窄边宽技术的显示产品提出了需求，拼接缝极致缩减，相邻拼接面板之间的距离需求小于1mm已经成为未来的趋势。而GOA电路设在面板的单侧（GOA in Source）三窄一宽的产品由于其可用于三边拼接，且相较现有产品有着不可忽视的价格优势，近几年引起了业界的广泛关注。
 技术问题
如图1所示，现有的GOA in source的技术中，整个覆晶薄膜区域12的两侧具有连接GOA信号总线11的连接线，GOA信号总线11与GOA电路区域13的数据线大面积的交叉设置会造成GOA信号总线11上的延迟（RC Loading），GOA信号总线11的接入点近端A和远端B存在着不可忽视的差异（具体的波形差异参照图2所示），因而导致不同区域的GOA电路接收到的GOA信号波形延迟差异较大，进而使得显示区像素充电不佳。
因此，有必要提供一种超窄边框的显示面板，以改善现有技术中存在的问题。
 技术解决方案
本发明一目的提供一种显示面板，用以减小GOA信号总线的接入点近端和远端的差异问题。
本发明提供一种显示面板，包括主显示区以及非显示区；所述非显示区包括一条宽区以及三条窄区，所述一条宽区以及所述三条窄区将所述主显示区包围，所述宽区的边框宽度大于所述窄区的边框宽度；在所述非显示区，所述显示面板还包括：GOA电路，设置于所述宽区且靠近所述主显示区；GOA信号总线，与所述GOA电路平行设置于所述宽区，且连接所述GOA电路；覆晶薄膜区，与所述GOA信号总线平行设置于所述宽区，所述GOA信号总线设置于所述GOA电路与所述覆晶薄膜区之间；其中，所述覆晶薄膜区包括阵列设置的多个薄膜芯片，每个薄膜芯片具有至少一输出端，所述GOA信号总线具有对应所述每个薄膜芯片的至少一输入端，所述输出端与所述输入端通过一金属走线连接。
进一步地，所述输出端包括第一输出端以及第二输出端，所述第一输出端以及所述第二输出端分别设于所述薄膜芯片的两侧，所述输入端包括对应所述第一输出端以及所述第二输出端的第一输入端以及所述第二输入端；所述第一输出端以及所述第二输出端分别通过所述金属走线分别连接所述第一输入端以及所述第二输入端。
进一步地，所述金属走线包括多条平行设置的第一信号线；所述GOA信号总线包括多条平行设置的第二信号线，所述第二信号线平行于所述第一信号线；所述第一信号线通过连接线连接相应的所述第二信号线，所述连接线垂直所述第二信号线。
进一步地，在所述非显示区，所述显示面板包括：基板；第一金属层，设于所述基板上，所述第一信号线以及所述第二信号线形成于所述第一金属层中；第一绝缘层，设于所述基板上且覆盖所述第一金属层；第二金属层，设于所述第一绝缘层上，所述连接线形成于第二金属层中。
进一步地，所述第一绝缘层上开设第一过孔以及第二过孔，所述第一过孔对应所述第一信号线，所述第二过孔对应所述第二信号线，所述连接线的一端通过第一过孔连接所述第一信号线，所述连接线的另一端通过所述第二过孔连接所述第二信号线。
进一步地，所述第一信号线包括时钟信号线、电压线以及重启线。
进一步地，所述时钟信号线以及电压线连接所述GOA信号总线；所述重启线连接所述GOA电路。
进一步地，所述GOA电路的走线形成于所述第一金属层中；所述第一绝缘层上还开设第三过孔，所述第三过孔对应所述GOA电路的走线；所述连接线的一端通过所述第一过孔连接所述第一信号线，所述连接线的另一端通过所述第三过孔连接所述GOA电路的走线。
本发明另一目的提供一种拼接显示面板，包括：主显示面板，所述主显示面板为所述的显示面板；至少一副显示面板，拼接于所述主显示面板的窄区。
进一步地，所述主显示面板与所述副显示面板的拼接距离小于1mm。
 有益效果
本发明的有益效果是：通过将所述覆晶薄膜区由传统的两侧输出，更为由每个薄膜芯片进行信号的输出，以达到降低GOA总线走线的信号差异，使得每一级GOA单路接受到的GOA信号差异尽可能减小，从而降低GOA电路输出信号差异，减小对显示区像素充电影响。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术显示面板的平面图。
图2为现有技术中GOA信号总线A处于B处的波形图。
图3为本发明提供的显示面板的平面示意图。
[根据细则91更正 17.11.2020]　
图4为图3中连接处（标记E）的具体走线示意图。
图5图4为连接孔处的剖面图。
图6为本发明检测GOA信号总线E处的波形图。
图7为本发明还提供拼接显示面板的平面示意图。
显示面板100；
主显示区110；宽区120；窄区130；
GOA电路101；GOA信号总线102；覆晶薄膜区103；
薄膜芯片104；输出端105；第一输出端1051；
第二输出端1052；第一输入端1061；第二输入端1062；
输入端106；第一信号线1031；第二信号线1021；
第一过孔1032；第二过孔1022；基板201；
第一金属层202；第一绝缘层203；第二金属层204；
金属走线21；GOA电路的走线1011；第三过孔1012；
电压线108；重启线107；连接线22。
 本发明的实施方式
以下是各实施例的说明是参考附加的图式，用以例示本发明可以用实施的特定实施例。本发明所提到的方向用语，例如上、下、前、后、左、右、内、外、侧等，仅是参考附图式的方向。本发明提到的元件名称，例如第一、第二等，仅是区分不同的元部件，可以更好的表达。在图中，结构相似的单元以相同标号表示。
本文将参照附图来详细描述本发明的实施例。本发明可以表现为许多不同形式，本发明不应仅被解释为本文阐述的具体实施例。本发明提供实施例是为了解释本发明的实际应用，从而使本领域其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改方案。
如图3所示，一种显示面板100，包括主显示区110以及非显示区。
所述非显示区包括一条宽区120以及三条窄区130，所述一条宽区120以及所述三条窄区130将所述主显示区110包围，所述宽区120的边框宽度大于所述窄区130的边框宽度。
所述显示面板100即为三窄一宽的产品，其中，所述宽区120用以设置控制电路，而所述三条窄区130用以进行面板拼接。
在所述非显示区，所述显示面板100还包括：GOA电路101、GOA信号总线102以及覆晶薄膜区103。
所述GOA电路101设置于所述宽区120且靠近所述主显示区110。
所述GOA信号总线102与所述GOA电路101平行设置于所述宽区120，且连接所述GOA电路101。
所述覆晶薄膜区103与所述GOA信号总线102平行设置于所述宽区120，所述GOA信号总线102设置于所述GOA电路101与所述覆晶薄膜区103之间。
所述覆晶薄膜区103包括阵列设置的多个薄膜芯片104，每个薄膜芯片104具有至少一输出端105，所述GOA信号总线102具有对应所述每个薄膜芯片104的至少一输入端106，所述输出端105与所述输入端106通过一金属走线21连接。
本发明通过将所述覆晶薄膜区103由传统的两侧输出，更为由每个薄膜芯片的进行信号的输出，以达到降低GOA总线走线的信号差异，使得每一级GOA单路接受到的GOA信号差异尽可能减小，从而降低GOA电路101输出信号差异，减小对显示区像素充电影响。
所述输出端105包括第一输出端1051以及第二输出端1052，所述第一输出端1051以及所述第二输出端1052分别设于所述薄膜芯片的两侧，所述输入端106包括对应所述第一输出端1051以及所述第二输出端1052的第一输入端1061以及所述第二输入端1062。
所述第一输出端1051以及所述第二输出端1052分别通过所述金属走线21分别连接所述第一输入端1061以及所述第二输入端1062。
如图4以及图5所示，在所述输入端106的连接区域，所述金属走线21包括多条平行设置的第一信号线1031。
所述GOA信号总线102包括多条平行设置的第二信号线1021，所述第二信号线1021平行于所述第一信号线1031。
所述第一信号线1031通过连接线22连接相应的所述第二信号线1021，所述连接线22垂直所述第二信号线1021。
如图5所示的非显示区的层状结构图，具体是在图3中连接孔（第一过孔1032、第二过孔1022以及第三过孔1012）位置的剖面图，在所述非显示区，所述显示面板100包括：基板201、第一金属层202、第一绝缘层203以及第二金属层204。
所述第一金属层202设于所述基板201上，所述第一信号线1031以及所述第二信号线1021形成于所述第一金属层202中。
所述第一绝缘层203设于所述基板201上且覆盖所述第一金属层202。
所述第二金属层204设于所述第一绝缘层203上，所述连接线22形成于第二金属层中。
所述第一绝缘层203上开设第一过孔1032以及第二过孔1022，所述第一过孔1032对应所述第一信号线1031，所述第二过孔1022对应所述第二信号线1021，所述连接线22的一端通过第一过孔1032连接所述第一信号线1031，所述连接线22的另一端通过所述第二过孔1022连接所述第二信号线1021。
所述第一信号线1031包括时钟信号线、电压线108以及重启线107。所述时钟信号线以及电压线108连接所述GOA信号总线102。
所述重启线107连接所述GOA电路101。
所述GOA电路101的走线形成于所述第一金属层202中。
所述第一绝缘层203上还开设第三过孔1012，所述第三过孔1012对应所述GOA电路101的走线。
所述连接线22的一端通过所述第一过孔1032连接所述第一信号线1031，所述连接线22的另一端通过所述第三过孔1012连接所述GOA电路的走线1011。
如图6所示，本发明检测GOA信号总线102的波形图，可以看出本发明的波形C与虚线的原始信号相差无几，而现有技术波形D与原始信号具有一定差异。
现有技术波形的下降时间（Falling Time）≈ 5.85us，本发明的Falling Time ≈ 0.05us，极大程度上减小了GOA信号走线上信号源远近端的波形差异。
如图7所示，本发明还提供一种拼接显示面板300，包括：主显示面板301以及至少一副显示面板302。
所述主显示面板301为所述的显示面板100。
所述副显示面板302拼接于所述主显示面板的窄区130。所述主显示面板301与所述副显示面板302的拼接距离小于1mm。
本发明通过将所述覆晶薄膜区103由传统的两侧输出，更为由每个薄膜芯片104进行信号的输出，以达到降低GOA总线走线的信号差异，使得每一级GOA单路接受到的GOA信号差异尽可能减小，从而降低GOA电路101输出信号差异，减小对显示区像素充电影响。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
本发明的技术范围不仅仅局限于所述说明中的内容，本领域技术人员可以在不脱离本发明技术思想的前提下，对所述实施例进行多种变形和修改，而这些变形和修改均应当属于本发明的范围内。

Claims (10)

  1. 一种显示面板，其中，包括主显示区以及非显示区；
    所述非显示区包括一条宽区以及三条窄区，所述宽区以及所述窄区将所述主显示区包围，所述宽区的边框宽度大于所述窄区的边框宽度；
    在所述非显示区，所述显示面板还包括：
    GOA电路，设置于所述宽区且靠近所述主显示区；
    GOA信号总线，与所述GOA电路平行设置于所述宽区，且连接所述GOA电路；
    覆晶薄膜区，与所述GOA信号总线平行设置于所述宽区，所述GOA信号总线设置于所述GOA电路与所述覆晶薄膜区之间；
    其中，所述覆晶薄膜区包括阵列设置的多个薄膜芯片，每个薄膜芯片具有至少一输出端，所述GOA信号总线具有对应所述每个薄膜芯片的至少一输入端，所述输出端与所述输入端通过一金属走线连接。
  2. 如权利要求1所述的显示面板，其中，
    所述输出端包括第一输出端以及第二输出端，所述第一输出端以及所述第二输出端分别设于所述薄膜芯片的两侧，所述输入端包括对应所述第一输出端以及所述第二输出端的第一输入端以及所述第二输入端；
    所述第一输出端以及所述第二输出端分别通过所述金属走线分别连接所述第一输入端以及所述第二输入端。
  3. 如权利要求1所述的显示面板，其中，
    所述金属走线包括多条平行设置的第一信号线；
    所述GOA信号总线包括多条平行设置的第二信号线，所述第二信号线平行于所述第一信号线；
    所述第一信号线通过连接线连接相应的所述第二信号线，所述连接线垂直所述第二信号线。
  4. 如权利要求3所述的显示面板，其中，在所述非显示区，所述显示面板包括：
    基板；
    第一金属层，设于所述基板上，所述第一信号线以及所述第二信号线形成于所述第一金属层中；
    第一绝缘层，设于所述基板上且覆盖所述第一金属层；
    第二金属层，设于所述第一绝缘层上，所述连接线形成于所述第二金属层中。
  5. 如权利要求4所述的显示面板，其中，
    所述第一绝缘层上开设第一过孔以及第二过孔，所述第一过孔对应所述第一信号线，所述第二过孔对应所述第二信号线，所述连接线的一端通过第一过孔连接所述第一信号线，所述连接线的另一端通过所述第二过孔连接所述第二信号线。
  6. 如权利要求3所述的显示面板，其中，
    所述第一信号线包括时钟信号线、电压线以及重启线。
  7. 如权利要求6所述的显示面板，其中，
    所述时钟信号线以及所述电压线连接所述GOA信号总线；
    所述重启线连接所述GOA电路。
  8. 如权利要求5所述的显示面板，其中，
    所述GOA电路的走线形成于所述第一金属层中；
    所述第一绝缘层上还开设第三过孔，所述第三过孔对应所述GOA电路的走线；
    所述连接线的一端通过所述第一过孔连接所述第一信号线，所述连接线的另一端通过所述第三过孔连接所述GOA电路的走线。
  9. 一种拼接显示面板，其中，包括：
    主显示面板，所述主显示面板为权利要求1所述的显示面板；
    至少一副显示面板，拼接于所述主显示面板的窄区。
  10. 权利要求9所述的拼接显示面板，其特征在于，
    所述主显示面板与所述副显示面板的拼接距离小于1mm。
PCT/CN2020/117725 2020-09-03 2020-09-25 显示面板及拼接显示面板 WO2022047863A1 (zh)

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