WO2021232255A1

WO2021232255A1 - True random number generator and electronic device

Info

Publication number: WO2021232255A1
Application number: PCT/CN2020/091112
Authority: WO
Inventors: 杨江
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2020-05-19
Filing date: 2020-05-19
Publication date: 2021-11-25

Abstract

A true random number generator and an electronic device. The true random number generator comprises a first up-sampling circuit (101), a first down-sampling circuit (102), a second up-sampling circuit (103) and a second down-sampling circuit (104), wherein the first up-sampling circuit (101) outputs a first up-sampling signal, the first down-sampling circuit (102) outputs a first down-sampling signal, the second up-sampling circuit (103) outputs a second up-sampling signal, and the second down-sampling circuit (104) outputs a second down-sampling signal; and a post-processing circuit (105) used to perform an exclusive-OR operation on one of the first up-sampling signal and the first down-sampling signal and one of the second up-sampling signal and the second down-sampling signal to generate and output a true random number signal, wherein the two signals that have been subjected to the exclusive-OR operation are signals respectively sampled according to different high-frequency clock signals, and have relatively high independence of each other, thus improving the randomness of an obtained true random number signal, such that an output sequence of the true random number signal can satisfy the random number characteristic of independent and uniform distribution.

Description

True random number generator and electronic equipment

Technical field

The embodiments of the present application relate to the field of information security technology, and in particular, to a true random number generator and electronic equipment.

Background technique

With the widespread use of network technology, mobile payment has been widely popularized. Electronic devices are increasingly used to store, process, and transmit data containing key information such as mobile payment information. Therefore, the importance of information security is also increasing. improve. In order to prevent the information from being stolen during the transfer process, it is generally necessary to encrypt the information with a security key before the information is transferred.

As an indispensable part of the cryptographic system, the True Random Number Generator (TRNG) is generally used to generate high-quality random number sequences required in the cryptographic system, for example, to generate security keys.

Summary of the invention

In view of this, the embodiments of the present invention provide a true random number generator and an electronic device to overcome the defects in the prior art.

The first aspect of the embodiments of the present application provides a true random number generator, which includes a first up-sampling circuit, a first down-sampling circuit, a second up-sampling circuit, and a second down-sampling circuit;

The first up-sampling circuit receives the first high-frequency clock signal output by the first high-frequency oscillator and the low-frequency clock signal output by the low-frequency oscillator, and the first up-sampling circuit is used to increase the first high-frequency clock signal according to the low-frequency clock signal Edge sampling, output the first up-sampling signal;

The first down-sampling circuit receives the first high-frequency clock signal and the low-frequency clock signal, and the first down-sampling circuit is configured to sample the falling edge of the first high-frequency clock signal according to the low-frequency clock signal, and output the first down-sampling signal;

The second up-sampling circuit receives the second high-frequency clock signal and the low-frequency clock signal output by the second high-frequency oscillator. The second up-sampling circuit is used to sample the rising edge of the second high-frequency clock signal according to the low-frequency clock signal, and output the first 2. Up-sampled signal;

The second down-sampling circuit receives the second high-frequency clock signal and the low-frequency clock signal, and the second down-sampling circuit is used to sample the falling edge of the second high-frequency clock signal according to the low-frequency clock signal, and output the second down-sampling signal;

The post-processing circuit receives the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal, and the post-processing circuit is used for processing one of the first up-sampling signal and the first down-sampling signal, Perform an exclusive OR operation with one of the second up-sampled signal and the second down-sampled signal to generate and output a true random number signal.

In the true random number generator provided by the embodiment of the present application, the first high-frequency oscillator, the second high-frequency oscillator, and the low-frequency oscillator are different oscillators, so the first high-frequency clock signal and the second high-frequency clock The signal and the low-frequency clock signal are uncorrelated clock signals. The first high-frequency clock signal and the second high-frequency clock signal are sampled at the rising edge and the falling edge of the first high-frequency clock signal through the low-frequency clock signal, respectively, and the first up-sampled signal, The first down-sampled signal, the second up-sampled signal, and the second down-sampled signal are not correlated with each other. After that, one of the first up-sampled signal and the first down-sampled signal is XORed with one of the second up-sampled signal and the second down-sampled signal through a post-processing circuit, and the two XOR operations are performed The signals are not correlated with each other, the sampling mode can be set to the same or can be set to different, and the two signals are obtained by sampling according to different high-frequency clock signals, so the two signals that are subjected to the exclusive OR operation are mutually exclusive The independence is high, which improves the randomness of the true random number signal obtained through the XOR operation, and at the same time, the output sequence of the true random number signal can meet the independent and uniformly distributed random number characteristics through the XOR operation.

Description of the drawings

Hereinafter, some specific embodiments of the embodiments of the present application will be described in detail in an exemplary but not restrictive manner with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the attached picture:

FIG. 1 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the application;

2 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the application;

3 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the application;

4 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the application;

FIG. 5 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the application;

6 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the application;

FIG. 7 is a schematic structural diagram of an electronic device containing a true random number generator provided by an embodiment of the application.

Detailed ways

The specific implementation of the embodiments of the present invention will be further described below in conjunction with the accompanying drawings of the embodiments of the present invention.

In related technologies, random number generators are mainly divided into two types: pseudo random number generators and true random number generators. The random sequence calculated by a deterministic algorithm is called a pseudo-random number. If the attacker has sufficient computing power, the generation rule of the pseudo-random number can be predicted, and it is generally used in occasions with low security requirements. The true random number is generated by physical methods, and the natural randomness of the real world is selected. Because it has the advantages of unpredictable and unreproducible from the outside world, it can better protect the transmission of information and is widely used in the field of information security.

The core of a true random number generator must be an essentially random physical process, which is selected from natural randomness. There are many ways to realize a true random number generator, such as discrete-time chaos method, direct noise amplification method, oscillation sampling method, metastable sampling method, etc. Among them, the oscillation sampling method is the most widely used due to its simple implementation method and good data randomness. However, the random number signal generated by the true random number generator implemented according to the oscillation sampling method is not very random, and the output sequence of the random number signal cannot meet the characteristics of independent and uniformly distributed random numbers. , Noise direct amplification method, oscillating sampling method, metastable sampling method, etc. The real random number signal generated by the real random number generator has a high cracking rate, thereby increasing the probability of data leakage during transmission and harming users Experience.

In view of this, the embodiments of the present application provide a true random number generator and electronic equipment to overcome the low randomness of random number signals in the prior art, and the output sequence of random number signals satisfies independent and uniformly distributed random number characteristics. Technical defects.

The specific implementation of the embodiments of the present application will be further described below in conjunction with the drawings of the embodiments of the present application.

Example one

FIG. 1 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the present application. As shown in FIG. 1, the true random number generator provided by the first embodiment of the present application includes: a first up-sampling circuit 101 , The first down-sampling circuit 102, the second up-sampling circuit 103, and the second down-sampling circuit 104.

The first up-sampling circuit 101 receives the first high-frequency clock signal output by the first high-frequency oscillator 201 and the low-frequency clock signal output by the low-frequency oscillator 203. The clock signal is sampled on the rising edge, and the first up-sampling signal is output.

The first down-sampling circuit 102 receives the first high-frequency clock signal and the low-frequency clock signal, and the first down-sampling circuit 102 is configured to sample the first high-frequency clock signal on the falling edge according to the low-frequency clock signal, and output the first down-sampling signal.

The second up-sampling circuit 103 receives the second high-frequency clock signal and the low-frequency clock signal output by the second high-frequency oscillator 202, and the second up-sampling circuit 103 is used to sample the rising edge of the second high-frequency clock signal according to the low-frequency clock signal , Output the second up-sampling signal;

The second down-sampling circuit 104 receives the second high-frequency clock signal and the low-frequency clock signal, and the second down-sampling circuit 104 is configured to sample the falling edge of the second high-frequency clock signal according to the low-frequency clock signal, and output the second down-sampling signal.

The post-processing circuit 105 receives the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal. The post-processing circuit 105 is used to perform an exclusive OR operation on one of the first up-sampled signal and the first down-sampled signal with one of the second up-sampled signal and the second down-sampled signal to generate a true random number signal And output.

Exemplarily, as shown in FIG. 1, the first input terminal 1011 of the first up-sampling circuit 101 is connected to the output terminal 2011 of the first high-frequency oscillator 201, and the first input terminal 1011 of the first up-sampling circuit 101 receives The first high-frequency clock signal output by the first high-frequency oscillator 201; the second input terminal 1012 of the first up-sampling circuit 101 and the output terminal 2031 of the low-frequency oscillator 203 are conducted, and the second input of the first up-sampling circuit 101 The terminal 1012 receives the low-frequency clock signal output by the low-frequency oscillator 203. The output terminal 1013 of the first up-sampling circuit 101 is connected to the first input terminal 1051 of the post-processing circuit 105. The first input terminal 1051 of the post-processing circuit 105 receives the first up-sampling signal output from the output terminal 1013 of the first up-sampling circuit 101.

The first input terminal 1021 of the first down-sampling circuit 102 is connected to the output terminal 2011 of the first high-frequency oscillator 201, and the first input terminal 1021 of the first down-sampling circuit 102 receives the first output from the first high-frequency oscillator 201 A high-frequency clock signal, the second input terminal 1022 of the first down-sampling circuit 102 and the output terminal 2031 of the low-frequency oscillator 203 are conducted, and the second input terminal 1022 of the first down-sampling circuit 102 receives the low-frequency output from the low-frequency oscillator 203 For the clock signal, the output terminal 1023 of the first down-sampling circuit 102 and the second input terminal 1052 of the post-processing circuit 105 are connected. The second input terminal 1052 of the post-processing circuit 105 receives the first down-sampling signal output from the output terminal 1023 of the first down-sampling circuit 102.

The first input terminal 1031 of the second up-sampling circuit 103 is connected to the output terminal 2021 of the second high-frequency oscillator 202, and the first input terminal 1031 of the second up-sampling circuit 103 receives the first output from the second high-frequency oscillator 202. Two high-frequency clock signals, the second input terminal 1032 of the second up-sampling circuit 103 and the output terminal 2031 of the low-frequency oscillator 203 are conducted, and the second input terminal 1032 of the second up-sampling circuit 103 receives the low-frequency output of the low-frequency oscillator 203 For the clock signal, the output terminal 1033 of the second up-sampling circuit 103 and the third input terminal 1053 of the post-processing circuit 105 are connected. The third input terminal 1053 of the post-processing circuit 105 receives the second up-sampling signal output from the output terminal 1033 of the second up-sampling circuit 103.

The first input terminal 1041 of the second down-sampling circuit 104 is connected to the output terminal 2021 of the second high-frequency oscillator 202, and the first input terminal 1041 of the second down-sampling circuit 104 receives the first output from the second high-frequency oscillator 202. Two high-frequency clock signals, the second input terminal 1042 of the second down-sampling circuit 104 and the output terminal 2031 of the low-frequency oscillator 203 are conducted, and the second input terminal 1042 of the second down-sampling circuit 104 receives the low-frequency output from the low-frequency oscillator 203 For the clock signal, the output terminal 1043 of the second down-sampling circuit 104 and the fourth input terminal 1054 of the post-processing circuit 105 are connected. The fourth input terminal 1054 of the post-processing circuit 105 receives the second down-sampling signal output from the output terminal 1043 of the second down-sampling circuit 104.

The output terminal 1055 of the post-processing circuit 105 outputs a true random number signal.

Specifically, phase jitter (jitter) is a random phenomenon caused by thermal noise in an oscillator, and phase jitter is essentially a kind of noise, which is a random variable conforming to a Gaussian distribution. Since the phase jitter of the first high-frequency oscillator, the second high-frequency oscillator, and the low-frequency oscillator are random, the low-frequency clock signal generated by the low-frequency oscillator is compared with the first high-frequency clock signal generated by the first high-frequency oscillator. The second high-frequency clock signal generated by the second high-frequency oscillator performs rising edge sampling and falling edge sampling respectively. The output sequence is random. A true random number signal is generated by XORing one of the first up-sampling signal and the first down-sampling signal with one of the second up-sampling signal and the second down-sampling signal The output sequence is random.

The first up-sampling signal is generated by the first up-sampling circuit 101 for sampling the rising edge of the first high-frequency clock signal according to the low-frequency clock signal. The frequency of the first up-sampling signal is the same as that of the low-frequency clock signal. The sampling signal is generated by the first down-sampling circuit 103 for sampling the falling edge of the first high-frequency clock signal according to the low-frequency clock signal, and the frequency of the first down-sampling signal is the same as the frequency of the low-frequency clock signal. Based on the same principle, the frequencies of the second up-sampling signal and the second down-sampling signal are the same as the frequency of the low-frequency clock signal. The frequency and low-frequency clock signal of the true random number signal generated by XORing one of the first up-sampling signal and the first down-sampling signal with one of the second up-sampling signal and the second down-sampling signal The frequency is the same.

Exemplarily, the frequency of the low-frequency clock signal is 32K Hz, the frequencies of the first high-frequency clock signal and the second high-frequency clock signal are greater than or equal to 80 MHz and less than or equal to 100 MHz, and the frequency of the true random number signal is 32K Hz.

In the post-processing circuit, the XOR operation is based on the two-bit data to generate one bit of data, so it can reduce the correlation between the first digit and the next digit in the output sequence of the true random number signal, so that the true The two digits in the output sequence of the random number signal are independent of each other.

In addition, in the post-processing circuit, the output sequence of the true random number signal obtained by the exclusive OR operation can also meet the uniformly distributed random number characteristics. Exemplarily, the post-processing circuit performs an exclusive-OR operation on the first up-sampled signal and the second down-sampled signal as an example. The output sequence of any one of the first up-sampled signal and the second down-sampled signal appears in the output sequence The probabilities of "0" and "1" are 0.5C and 0.5C, respectively, where C<1, and C is a parameter used to measure the independence between the first up-sampled signal and the second down-sampled signal. The value of C is Smaller, the better the independence between the first up-sampling signal and the second down-sampling signal, the more irrelevant the first up-sampling signal and the second down-sampling signal. A true random number signal is generated by XORing the first up-sampled signal and the second down-sampled signal. The probability of "0" in the true random number signal is P(0)=(0.5+C) ² +(0.5 -C) ² =0.5+2C ² , the probability of "1" appearing in a true random number signal is P(1)=(0.5+C)*(0.5-C)+(0.5-C)*(0.5+C) =0.5-2C ² , compared with 0.5C, P(0) and P(1) are closer to 0.5, so the output sequence "0" and "1" of the true random number signal generated after the exclusive OR operation are evenly distributed .

Among them, the first high-frequency oscillator that outputs the first high-frequency clock signal, the second high-frequency oscillator that outputs the second high-frequency clock signal, and the low-frequency oscillator that outputs the low-frequency clock signal are different oscillators, which can be regarded as different oscillators. A timing instrument that physically exists as different entities. The first high-frequency clock signal, the second high-frequency clock signal, and the low-frequency clock signal are not related to each other, that is, the first high-frequency clock signal, the second high-frequency clock signal, and the low-frequency clock The signals will not have any connection with each other, and it is impossible to obtain another clock signal based on one of the clock signals. The first up-sampling signal and the first down-sampling signal are obtained by sampling the first high-frequency clock signal according to the low-frequency clock signal, and the second up-sampling signal and the second down-sampling signal are obtained by sampling the second high-frequency clock signal according to the low-frequency clock signal. The signal is sampled, so the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal are not correlated with each other. The post-processing circuit performs an exclusive OR operation on one of the first up-sampled signal and the first down-sampled signal and one of the second up-sampled signal and the second down-sampled signal, and the two signals are subjected to the exclusive OR operation The mutual non-correlation and sampling mode can be set to be the same or different, and they are signals obtained by sampling respectively according to different high-frequency clock signals. Among them, compared with two signals obtained by sampling based on the same high-frequency clock signal, the signals obtained by sampling based on different high-frequency clock signals are more mutually independent. Therefore, the randomness of the true random number signal generated by the post-processing circuit through the exclusive OR operation is relatively high.

In the true random number generator provided by the embodiment of the present application, the first high-frequency oscillator, the second high-frequency oscillator, and the low-frequency oscillator are different oscillators, so the first high-frequency clock signal and the second high-frequency clock The signal and the low-frequency clock signal are clock signals that are not related to each other. The first high-frequency clock signal and the second high-frequency clock signal are respectively sampled on the rising edge and the falling edge through the low-frequency clock signal, and the first up-sampled signal, The first down-sampled signal, the second up-sampled signal, and the second down-sampled signal are not correlated with each other. After that, one of the first up-sampled signal and the first down-sampled signal is XORed with one of the second up-sampled signal and the second down-sampled signal through a post-processing circuit, and the two XOR operations are performed The signals are not correlated with each other, the sampling mode can be set to the same or can be set to different, and the two signals are obtained by sampling according to different high-frequency clock signals, so the two signals that are subjected to the exclusive OR operation are mutually exclusive The independence is high, which improves the randomness of the true random number signal obtained through the XOR operation, and at the same time, the output sequence of the true random number signal can meet the independent and uniformly distributed random number characteristics through the XOR operation.

Optionally, FIG. 2 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the application. As shown in FIG. 2, in an embodiment of the application, the true random number generator further includes a first Three up-sampling circuit 108 and third down-sampling circuit 109.

The third up-sampling circuit 108 receives the third high-frequency clock signal output by the third high-frequency oscillator 204 and the low-frequency clock signal output by the low-frequency oscillator 203. The clock signal is sampled on the rising edge, and the third up-sampling signal is output.

The third down-sampling circuit 109 receives the third high-frequency clock signal and the low-frequency clock signal, and the third down-sampling circuit 109 is configured to sample the third high-frequency clock signal on the falling edge according to the low-frequency clock signal, and output the third down-sampling signal.

The post-processing circuit 105 receives the third up-sampling signal and the third down-sampling signal. The post-processing circuit 105 is used to sample the first up-sampling signal, one of the first down-sampling signals, the second up-sampling signal, and the second down-sampling signal. Select any two signals from one of the signals and one of the third up-sampled signal and the third down-sampled signal to perform an exclusive OR operation to generate and output a true random number signal.

Exemplarily, as shown in FIG. 2, the first input terminal 1081 of the third up-sampling circuit 108 and the output terminal 2041 of the third high-frequency oscillator 204 are turned on, and the first input terminal 1081 of the third up-sampling circuit 108 receives The first high-frequency clock signal output by the third high-frequency oscillator 204; the second input terminal 1082 of the third up-sampling circuit 108 and the output terminal 2031 of the low-frequency oscillator 203 are conducted, and the second input of the third up-sampling circuit 108 The terminal 1082 receives the low-frequency clock signal output by the low-frequency oscillator 203. The output terminal 1083 of the third up-sampling circuit 108 is connected to the fifth input terminal 1056 of the post-processing circuit 105. The fifth input terminal 1056 of the post-processing circuit 105 receives the third up-sampling signal output from the output terminal 1083 of the third up-sampling circuit 108.

The first input terminal 1091 of the third down-sampling circuit 109 is connected to the output terminal 2041 of the third high-frequency oscillator 204, and the first input terminal 1091 of the third down-sampling circuit 109 receives the first output from the third high-frequency oscillator 204 A high-frequency clock signal, the second input terminal 1092 of the third down-sampling circuit 109 and the output terminal 2031 of the low-frequency oscillator 203 are conducted, and the second input terminal 1092 of the third down-sampling circuit 109 receives the low-frequency output from the low-frequency oscillator 203 For the clock signal, the output terminal 1093 of the third down-sampling circuit 109 is connected to the sixth input terminal 1057 of the post-processing circuit 105. The sixth input terminal 1057 of the post-processing circuit 105 receives the first down-sampling signal output from the output terminal 1093 of the third down-sampling circuit 109.

In the true random number generator provided by the embodiment of the present application, the first high-frequency oscillator, the second high-frequency oscillator, the third high-frequency oscillator, and the low-frequency oscillator are different oscillators, and the first high-frequency clock signal , The second high-frequency clock signal, the third high-frequency clock signal, and the low-frequency clock signal are uncorrelated clock signals. The first, second, and third high-frequency clock signals are The signal is sampled at the rising edge and the falling edge, and the obtained first up-sampling signal, first down-sampling signal, second up-sampling signal, second down-sampling signal, third up-sampling signal, and third down-sampling signal are obtained. They are not related to each other. Then through the post-processing circuit from the first up-sampled signal, one of the first down-sampled signals, the second up-sampled signal, one of the second down-sampled signals, and the third up-sampled signal and the third down-sampled signal Select any two signals from one of the signals for XOR operation. The two signals for XOR operation are not related to each other. The sampling method can be set to the same or different, and is based on different high frequency The two signals obtained by sampling the clock signal, therefore, the independence of the two signals subjected to the exclusive OR operation is relatively high, which improves the randomness of the true random number signal obtained through the exclusive OR operation. The output sequence of the true random number signal can meet the characteristics of independent and uniformly distributed random numbers.

Optionally, in an embodiment of the present application, FIG. 3 is a schematic circuit structure diagram of a true random number generator provided in an embodiment of the present application. As shown in FIG. 3, the post-processing circuit 105 includes a first switch 301, the second switch 302 and the exclusive OR gate 303, the first input terminal 3011 of the first switch 301 receives the first up-sampling signal, the second input terminal 3012 of the first switch 302 receives the first down-sampling signal, the first switch 301 It is used to output a first switching signal, and the first switching signal is a first up-sampling signal or a first down-sampling signal. The first input terminal 3021 of the second switch 302 receives the second up-sampling signal, the second input terminal 3022 of the second switch 302 receives the second down-sampling signal, the second switch 302 is used to output the second switching signal, the second switching signal It is the second up-sampled signal or the second down-sampled signal. The first input terminal 3031 of the XOR gate 303 receives the first switch signal, the second input terminal 3032 of the XOR gate 303 receives the second switch signal, and the XOR gate 303 is used to XOR the first switch signal and the second switch signal. Or operation to generate and output a true random number signal.

Exemplarily, as shown in FIG. 3, the first input terminal 3011 of the first switch 301 is connected to the output terminal 1013 of the first up-sampling circuit 101 through the first input terminal 1051 of the post-processing circuit 105, and the first switch 301 The first input terminal 3011 receives the first up-sampling signal. The second input terminal 3012 of the first switch 301 is connected to the output terminal 1023 of the first down-sampling circuit 102 through the second input terminal 1052 of the post-processing circuit 105, and the second input terminal 3012 of the first switch 301 receives the first down-sampling Signal.

The first input terminal 3021 of the second switch 302 is connected to the output terminal 1033 of the second up-sampling circuit 103 through the third input terminal 1053 of the post-processing circuit 105, and the first input terminal 3021 of the second switch 302 receives the second up-sampling Signal. The second input terminal 3022 of the second switch 302 is connected to the output terminal 1043 of the second down-sampling circuit 104 through the fourth input terminal 1054 of the post-processing circuit 105, and the second input terminal 3022 of the second switch 302 receives the second down-sampling Signal.

The first input terminal 3031 of the exclusive OR gate 303 is connected to the output terminal 3013 of the first switch 301, the second input terminal 3032 of the exclusive OR gate 303 is connected to the output terminal 3033 of the second switch 302, and the exclusive OR gate 303 passes through the output The terminal 3033 outputs a true random number signal.

Exemplarily, the first switch 301 and the second switch 302 are single-pole double-throw switches. The first switch unit 301 is configured such that when the first input terminal 3011 of the first switch unit 301 and the output terminal 3033 of the first switch unit 301 are connected, the first switch signal output by the output terminal 3013 of the first switch unit 301 is the first switch signal. An up-sampling signal. At this time, the signal input to the first input terminal 3031 of the exclusive OR gate 303 is the first up-sampling signal.

The first switch unit 301 is configured such that when the second input terminal 3012 of the first switch unit 301 is connected to the output terminal 3033 of the first switch unit 301, the first switch signal output by the output terminal 3013 of the first switch unit 301 is the first switch signal. The down-sampled signal, at this time, the signal input to the first input terminal 3031 of the exclusive OR gate 303 is the first down-sampled signal.

The second switch unit 302 is configured such that when the first input terminal 3021 of the second switch unit 302 and the output terminal 3023 of the second switch unit 302 are connected, the second switch signal output by the output terminal 3023 of the second switch unit 302 is the first switch signal. The second up-sampling signal. At this time, the signal input to the second input terminal 3032 of the exclusive OR gate 303 is the second up-sampling signal.

The second switch unit 302 is configured such that when the second input terminal 3022 of the second switch unit 302 and the output terminal 3023 of the second switch unit 302 are connected, the second switch signal output by the output terminal 3023 of the second switch unit 302 is the first switch signal. The second down-sampled signal. At this time, the signal input to the second input terminal 3032 of the exclusive OR gate 303 is the second down-sampled signal.

In the true random number generator provided by the embodiment of the present application, the post-processing circuit includes a first switch, a second switch, and an exclusive OR gate. The first switch and the second switch can be configured in different conduction states to make the input exclusive The sampling method of the two signals of the OR gate can be the same (both signals are up-sampled signals or both are down-sampled signals) or different (one signal is an up-sampled signal, and the other signal is a down-sampled signal), which is convenient Select the sampling method of the two signals to be XORed.

Optionally, in an embodiment of the present application, FIG. 4 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the present application. As shown in FIG. 4, the control terminal 3014 of the first switch 301 Receiving the first control signal, the first switch 301 outputs a first up-sampling signal in response to the first control signal. Or, the control terminal 3014 of the first switch 301 receives the second control signal, and the first switch 301 outputs the first down-sampling signal in response to the second control signal.

Exemplarily, as shown in FIG. 4, the control terminal 3014 of the first switch 301 receives the first control signal, and the first switch 301 connects the first input terminal 3011 of the first switch 301 to the first switch 301 in response to the first control signal. The output terminal 3013 of the first switch 301 is turned on, and the output terminal 3013 of the first switch 301 outputs the first up-sampling signal.

Or, the control terminal 3014 of the first switch 301 receives the second control signal, and the first switch 301 conducts the second input terminal 3012 of the first switch 301 and the output terminal 3013 of the first switch 301 in response to the second control signal, and The output terminal 3013 of a switch 301 outputs the first down-sampling signal.

Wherein, the control circuit in the true random number generator can output the first control signal or the second control signal; or, the control chip in the electronic device where the true random number generator is located can output the first control signal or the second control signal. Exemplarily, the control chip in the electronic device where the true random number generator is located can randomly output the first control signal or the second control signal, or can output the first control signal and the second control signal cyclically according to a preset period.

In the true random number generator provided by the embodiment of the application, the control terminal of the first switch receives the first control signal, and the first switch outputs the first up-sampling signal in response to the first control signal; or the control terminal of the first switch receives the first control signal. Two control signals, the first switch outputs the first down-sampling signal in response to the second control signal, so that the first switch can configure itself into different conduction states according to the received different control signals, which is convenient for the output of the first switch The sampling method of the signal is controlled.

Optionally, in an embodiment of the present application, as shown in FIG. 4, the control terminal 3024 of the second switch 302 receives the third control signal, and the second switch 302 outputs the second up-sampling signal in response to the third control signal. Or, the control terminal 3024 of the second switch 302 receives the fourth control signal, and the second switch 302 outputs the second down-sampling signal in response to the fourth control signal.

Exemplarily, as shown in FIG. 4, the control terminal 3024 of the second switch 302 receives the third control signal, and the second switch 302 connects the first input terminal 3021 of the second switch 302 to the second switch 302 in response to the third control signal. The output terminal 3023 of the second switch 302 is turned on, and the output terminal 3023 of the second switch 302 outputs the first up-sampling signal.

Or, the control terminal 3024 of the second switch 302 receives the fourth control signal, and the second switch 302 conducts the second input terminal 3022 of the second switch 302 and the output terminal 3023 of the second switch 302 in response to the fourth control signal, and The output terminal 3023 of the second switch 302 outputs the first down-sampling signal.

Wherein, the control circuit in the true random number generator can output the third control signal or the fourth control signal; or, the control chip in the electronic device where the true random number generator is located can output the third control signal or the fourth control signal. Exemplarily, the control chip in the electronic device where the true random number generator is located can randomly output the third control signal or the fourth control signal, and can also output the third control signal and the fourth control signal cyclically according to a preset period.

In the true random number generator provided by the embodiment of the application, the control terminal of the second switch receives the third control signal, and the second switch outputs the second up-sampling signal in response to the third control signal; or the control terminal of the second switch receives the first Four control signals, the second switch outputs a second down-sampling signal in response to the fourth control signal. The second switch can configure itself into different conduction states according to the different control signals received, which facilitates control of the sampling mode of the signal output by the second switch.

Optionally, in an embodiment of the present application, the period value of the first high-frequency clock signal and the period value of the second high-frequency clock signal are the period value of the high-frequency clock, and the standard deviation value of the phase jitter of the low-frequency clock signal The ratio to the high-frequency clock period value is greater than or equal to 100 and less than or equal to 1000.

Specifically, when the first high-frequency clock signal and the second high-frequency clock signal are respectively subjected to rising edge sampling or falling edge sampling according to the low-frequency clock signal, the low-frequency oscillator that generates the low-frequency clock signal generates the first high-frequency clock signal The phase jitter of the first high-frequency oscillator and the second high-frequency oscillator that generate the second high-frequency clock signal are random, and the phase jitter of the first high-frequency oscillator and the second high-frequency oscillator are relative to the phase jitter of the low-frequency oscillator. The phase jitter of the frequency oscillator can be ignored, so the randomness of the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal mainly depends on the standard deviation of the phase jitter of the low-frequency oscillator. (That is, the root mean square value) relative to the period value of the first high-frequency oscillator and the second high-frequency oscillator. The period value of the first high-frequency clock signal and the second high-frequency clock signal is the high-frequency clock period value, when the ratio of the standard deviation value of the phase jitter of the low-frequency clock signal to the high-frequency clock period value is greater than or equal to 100 and less than or When it is equal to 1000, the output sequences of the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal are relatively random.

Example two

On the basis of the first embodiment, in the true random number generator provided in the second embodiment of the present application, as shown in FIG. 5, FIG. 5 is a schematic circuit structure diagram of a true random number generator provided in an embodiment of the present application The true random number generator also includes a differential circuit 106. The input terminal 1061 of the differential circuit 106 receives a true random number signal, the first output terminal 1062 of the differential circuit 106 outputs a true random number signal, and the second output terminal 1063 of the differential circuit 106 outputs Differential output signal, the differential output signal and the true random number signal form a pair of differential signals.

Exemplarily, as shown in FIG. 5, the input terminal 1061 of the differential circuit 106 and the output terminal 1055 of the post-processing circuit 105 are connected.

In the true random number generator provided by the embodiment of the present application, the differential circuit 106 receives a true random number signal, and outputs a true random number signal and a differential output signal forming a pair of differential signals with the true random number signal to enhance the signal transmission process The anti-interference ability of the true random number signal and the differential output signal can be verified according to the true random number signal and the differential output signal to avoid errors caused by malicious attacks or tampering of the signal wiring.

Optionally, in an embodiment of the present application, as shown in FIG. 6, FIG. 6 is a schematic circuit structure diagram of a true random number generator provided by an embodiment of the present application, and the differential circuit 106 includes an inverter 107 , The input terminal 1071 of the inverter 107 receives a true random number signal, and the output terminal 1072 of the inverter 107 outputs a differential output signal.

Exemplarily, the input terminal 1071 of the inverter 107 is connected to the output terminal 1055 of the post-processing circuit 105 through the input terminal 1061 of the differential circuit 106, so that the input terminal 1071 of the inverter 107 inputs a true random number signal. The output terminal 1072 of 107 is connected to the second output terminal 1063 of the differential circuit 106, and the output terminal 1061 of the differential circuit 106 is connected to the first output terminal 1062 of the differential circuit 106. The inverter 107 is used to reverse the true random number signal input from the input terminal 1071 of the inverter 107, so that the differential output signal output from the output terminal of the inverter 107 has the opposite phase and the same frequency as the true random number signal. The output signal and the true random number signal form a pair of differential signals.

In the true random number generator provided by the embodiment of the present application, the differential circuit 106 includes an inverter 107. The input terminal 1071 of the inverter 107 receives a true random number signal, and the inverter 107 reverses the true random number signal to make The differential output signal output by the output terminal 1072 of the inverter 107 is opposite to the true random number signal and has the same frequency, and the differential output signal and the true random number signal form a pair of differential signals.

Example three

FIG. 7 is a schematic structural diagram of an electronic device provided by an embodiment of the application. As shown in FIG. 7, the electronic device 300 provided by the second embodiment of the present application includes a low-frequency oscillator 203, a first high-frequency oscillator 201, The second high-frequency oscillator 202 and any of the true random number generators 301 provided in the first embodiment of the present application, the first high-frequency oscillator 201 is used to output the first high-frequency clock signal, and the second high-frequency oscillator 202 Used to output the second high frequency clock signal.

Exemplarily, as shown in FIG. 7, the first input terminal 3011 of the true random number generator 301 is connected to the output terminal 2011 of the first high-frequency oscillator 201, and the first input terminal 1011 of the first up-sampling circuit 101 passes through The first input terminal 3011 of the true random number generator 301 is connected to the output terminal 2011 of the first high-frequency oscillator 201, and receives the first high-frequency clock signal output by the first high-frequency oscillator 201. The first input terminal 1021 of the first down-sampling circuit 102 is connected to the output terminal 2011 of the first high-frequency oscillator 201 through the first input terminal 3011 of the true random number generator 301, and receives the output of the first high-frequency oscillator 201 The first high-frequency clock signal.

The second input terminal 3012 of the true random number generator 301 is connected to the output terminal 2021 of the second high-frequency oscillator 202, and the first input terminal 1031 of the second up-sampling circuit 103 passes through the second input of the true random number generator 301 The terminal 3012 is connected to the output terminal 2021 of the second high-frequency oscillator 202 to receive the second high-frequency clock signal output by the second high-frequency oscillator 202. The first input terminal 1041 of the second down-sampling circuit 104 is connected to the output terminal 2021 of the second high-frequency oscillator 202 through the second input terminal 3012 of the true random number generator 301, and receives the output of the second high-frequency oscillator 202. The second high frequency clock signal.

The third input terminal 3013 of the true random number generator 301 is connected to the output terminal 2031 of the low frequency oscillator 203, the second input terminal 1012 of the first up-sampling circuit 101, the second input terminal 1022 of the first down-sampling circuit 102 The second input terminal 1032 of the second up-sampling circuit 103 and the second input terminal 1042 of the second down-sampling circuit 104 are both conducted through the third input terminal 3013 of the true random number generator 301 and the output terminal 2031 of the low frequency oscillator 203 , Receiving the low-frequency clock signal output by the low-frequency oscillator 203.

The electronic device provided by the embodiment of the present application includes a low frequency oscillator 203, a first high frequency oscillator 201, a second high frequency oscillator 202, and a true random number generator 301. The first high frequency oscillator 201 is used to output the first The high-frequency clock signal, and the second high-frequency oscillator 202 is used to output the second high-frequency clock signal. The two signals for the exclusive OR operation in the true random number generator 301 are not correlated with each other, the sampling mode can be set to the same or different, and the two signals are obtained by sampling according to different high-frequency clock signals. The two signals undergoing exclusive OR operation are highly independent of each other, which improves the randomness of the true random number signal obtained through the exclusive OR operation, and enables the output sequence of the true random number signal to meet independent and uniformly distributed randomness Number characteristics.

Optionally, in an embodiment of the present application, the types of the first high-frequency oscillator 201 and the second high-frequency oscillator 202 include a crystal oscillator, a phase-locked loop, and a voltage-controlled oscillator.

In the electronic device provided by the embodiment of the present application, the oscillator types of the first high-frequency oscillator 201 and the second high-frequency oscillator 202 include crystal oscillators, phase-locked loops, and voltage-controlled oscillators. Compared with oscillators, crystal oscillators, phase-locked loops, and voltage-controlled oscillators have lower phase jitter. According to the low-frequency clock signal, the first high-frequency clock signal and the second high-frequency clock signal are sampled at the rising edge and the falling edge respectively. The generated output sequences of the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal are relatively random. An output sequence of a true random number signal generated by performing an exclusive OR operation with one of the second up-sampling signal and the second down-sampling signal has high randomness.

Optionally, in an embodiment of the present application, the low frequency oscillator 203, the first high frequency oscillator 201, and the second high frequency oscillator 202 are all relaxation oscillators. The typical value of the average current of the low frequency oscillator 203 is less than 100 nanoamperes, and the typical value of the average current of the first high frequency oscillator 201 and the typical value of the average current of the second high frequency oscillator 202 are both greater than 500 microamperes.

Optionally, in an embodiment of the present application, the oscillator type of the first high frequency oscillator 201 and the second high frequency oscillator 202 is different from the oscillator type of the low frequency oscillator 203.

Exemplarily, the first high-frequency oscillator 201 and the second high-frequency oscillator 202 are relaxation oscillators, and the oscillator types of the low-frequency oscillator 203 include voltage-controlled oscillators, phase-locked loops, and crystal oscillators; or, the first A high-frequency oscillator 201 and a second high-frequency oscillator 202 are both phase-locked loops. The oscillator types of the low-frequency oscillator 203 include relaxation oscillators, voltage-controlled oscillators, and crystal oscillators; or, the first high-frequency oscillator 201. The second high-frequency oscillator 202 is a crystal oscillator. The oscillator types of the low-frequency oscillator 203 include relaxation oscillators, voltage-controlled oscillators, and phase-locked loops; or, the first high-frequency oscillator 201 and the second high-frequency oscillator 201 The frequency oscillators 202 are all voltage controlled oscillators, and the oscillator types of the low frequency oscillator 203 include relaxation oscillators, phase-locked loops, and crystal oscillators.

In the electronic device provided by the embodiment of the present application, compared with the first high-frequency oscillator 201, the second high-frequency oscillator 202, and the low-frequency oscillator 203 being the same oscillator type, when the first high-frequency oscillator 201 , When the type of the second high frequency oscillator 202 is different from the type of the low frequency oscillator 203, the independence between the first high frequency oscillator 201 or the second high frequency oscillator 202 and the low frequency oscillator 203 is better, and the first The high-frequency clock signal or the second high-frequency clock signal is more independent from the low-frequency clock signal, and the first high-frequency clock signal and the second high-frequency clock signal are respectively sampled on the rising edge and the falling edge according to the low-frequency clock signal The generated output sequence of the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal are more random. The randomness of the true random number signal generated by XORing one of the signals in the second up-sampling signal and the second down-sampling signal.

Optionally, in an embodiment of the present application, the electronic device 300 includes a chip or a chipset, and the chip or a chipset includes a low-frequency oscillator 203, a first high-frequency oscillator 201, and a second high-frequency oscillator 202. The low-frequency oscillator The device 203 is a wake-up clock source of the chip or chipset, and the first high-frequency oscillator 301 and the second high-frequency oscillator 202 are both system reference clock sources of the chip. The chip or chipset may contain the true random number generator, and the chip may also contain other functional modules or circuits. For example, in one example, the electronic device may be a mobile terminal with NFC recognition function, which contains an NFC controller chip And the security chip, the NFC controller chip is connected with the security chip, and the security chip contains a true random number generator, which is used to generate a true random number, and is used for the NFC controller to identify the NFC card reader within the detection range Verification, and the low-frequency oscillator 203, the first high-frequency oscillator 201, and the second high-frequency oscillator 202 can be distributed in the NFC controller and/or the security chip. In other words, the low-frequency oscillator 203, the first high-frequency oscillator 201, and the second high-frequency oscillator 202 not only provide clock signals for the true random number generator, but are also used to provide the true random number generator in the electronic device. Function modules other than the generator provide wake-up clock and system reference clock.

The electronic device provided by the embodiment of the application uses the wake-up clock source contained in the chip or chipset as the low-frequency oscillator, and uses multiple reference clock sources contained in the system as the first high-frequency oscillator and the second high-frequency oscillator. Oscillator, under the premise of not affecting the generation of true random number signals, multiplexing the oscillator in the chip as the clock source, improving the utilization of circuit modules in the device, and avoiding adding more oscillators to the electronic device. Reduce the manufacturing cost of electronic equipment.

The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the difference from other embodiments. In particular, as for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment.

The above descriptions are only examples of the present application, and are not used to limit the present application. For those skilled in the art, this application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the scope of the claims of this application.

Claims

A true random number generator, characterized in that the true random number generator includes a first up-sampling circuit, a first down-sampling circuit, a second up-sampling circuit, and a second down-sampling circuit;

The first up-sampling circuit receives a first high-frequency clock signal output by a first high-frequency oscillator and a low-frequency clock signal output by a low-frequency oscillator. Sampling the rising edge of the first high-frequency clock signal, and outputting the first up-sampling signal;

The first down-sampling circuit receives the first high-frequency clock signal and the low-frequency clock signal, and the first down-sampling circuit is configured to perform a falling edge on the first high-frequency clock signal according to the low-frequency clock signal Sampling, output the first down-sampled signal;

The second up-sampling circuit receives a second high-frequency clock signal output by a second high-frequency oscillator and the low-frequency clock signal. Sampling the rising edge of the high-frequency clock signal, and output the second up-sampling signal;

The second down-sampling circuit receives the second high-frequency clock signal and the low-frequency clock signal, and the second down-sampling circuit is configured to perform a falling edge on the second high-frequency clock signal according to the low-frequency clock signal Sampling, output the second down-sampling signal;

The post-processing circuit receives the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal, and the post-processing circuit is used for processing the first One of the up-sampled signal and the first down-sampled signal is XORed with one of the second up-sampled signal and the second down-sampled signal to generate and output a true random number signal.
The true random number generator according to claim 1, wherein the true random number generator further comprises a third up-sampling circuit and a third down-sampling circuit;

The third up-sampling circuit receives a third high-frequency clock signal output by a third high-frequency oscillator and a low-frequency clock signal output by a low-frequency oscillator. The third high-frequency clock signal is sampled at the rising edge, and a third up-sampling signal is output;

The third down-sampling circuit receives the third high-frequency clock signal and the low-frequency clock signal, and the third down-sampling circuit is configured to perform a falling edge on the third high-frequency clock signal according to the low-frequency clock signal Sampling, output the third down-sampling signal;

The post-processing circuit receives the third up-sampling signal and the third down-sampling signal, and the post-processing circuit is used to obtain one of the first up-sampling signal, the first down-sampling signal, Select any two signals among the second up-sampled signal, one of the second down-sampled signals, and one of the third up-sampled signal and the third down-sampled signal to perform an exclusive OR operation , To generate and output the true random number signal.
The true random number generator according to claim 1, wherein the post-processing circuit comprises a first switch, a second switch and an exclusive OR gate;

The first input terminal of the first switch receives the first up-sampling signal, the second input terminal of the first switch receives the first down-sampling signal, and the first switch is used to output a first switch signal , The first switch signal is the first up-sampling signal or the first down-sampling signal;

The first input terminal of the second switch receives the second up-sampling signal, the second input terminal of the second switch receives the second down-sampling signal, and the second switch is used to output a second switch signal , The second switch signal is the second up-sampling signal or the second down-sampling signal;

The first input terminal of the XOR gate receives the first switch signal, the second input terminal of the XOR gate receives the second switch signal, and the XOR gate is used to compare the first switch signal. And the second switch signal performs an exclusive OR operation to generate and output the true random number signal.
The true random number generator according to claim 3, wherein the control terminal of the first switch receives a first control signal, and the first switch outputs the first upper switch in response to the first control signal. Sample signal

Or, the control terminal of the first switch receives a second control signal, and the first switch outputs the first down-sampling signal in response to the second control signal.
The true random number generator according to claim 3, wherein the control terminal of the second switch receives a third control signal, and the second switch outputs the second upper switch in response to the third control signal. Sample signal

Or, the control terminal of the second switch receives a fourth control signal, and the second switch outputs the second down-sampling signal in response to the fourth control signal.
The true random number generator according to any one of claims 1 to 5, wherein the true random number generator further comprises a differential circuit, and the input terminal of the differential circuit receives the true random number signal, The first output terminal of the differential circuit outputs the true random number signal, and the second output terminal of the differential circuit outputs a differential output signal. The differential output signal and the true random number signal form a pair of differential signals.
The true random number generator according to claim 6, wherein the differential circuit comprises an inverter, the input terminal of the inverter receives the true random number signal, and the output terminal of the inverter The differential output signal is output.
The true random number generator according to any one of claims 1-7, wherein the period value of the first high-frequency clock signal and the period value of the second high-frequency clock signal are high-frequency clock Period value, the ratio of the standard deviation value of the phase jitter of the low-frequency clock signal to the period value of the high-frequency clock is greater than or equal to 100 and less than or equal to 1000.
The true random number generator according to any one of claims 1-7, wherein the frequency of the low-frequency clock signal is 32K Hz, and the first high-frequency clock signal and the second high-frequency clock The frequency of the signal is greater than or equal to 80 MHz and less than or equal to 100 MHz.
An electronic device, characterized by comprising a low-frequency oscillator, a first high-frequency oscillator, a second high-frequency oscillator, and the true random number generator according to any one of claims 1-9, the first The high frequency oscillator is used to output a first high frequency clock signal, the second high frequency oscillator is used to output a second high frequency clock signal, and the low frequency oscillator is used to output a low frequency clock signal.
The electronic device according to claim 10, wherein the oscillator types of the first high-frequency oscillator and the second high-frequency oscillator include a crystal oscillator, a phase-locked loop, and a voltage-controlled oscillator.
The electronic device according to claim 10, wherein the low-frequency oscillator, the first high-frequency oscillator, and the second high-frequency oscillator are all relaxation oscillators, and the average current of the low-frequency oscillator is The typical value of is less than 100 nanoamperes, and the typical value of the average current of the first high-frequency oscillator and the typical value of the average current of the second high-frequency oscillator are both greater than 500 microamperes.
The electronic device according to claim 10, wherein the first high-frequency oscillator and the second high-frequency oscillator are relaxation oscillators, and the oscillator type of the low-frequency oscillator includes a voltage-controlled oscillator , Phase-locked loop, crystal oscillator;

Or, the first high-frequency oscillator and the second high-frequency oscillator are both phase-locked loops, and the oscillator types of the low-frequency oscillator include relaxation oscillators, voltage-controlled oscillators, and crystal oscillators;

Or, the first high-frequency oscillator and the second high-frequency oscillator are both crystal oscillators, and the oscillator types of the low-frequency oscillator include relaxation oscillators, voltage-controlled oscillators, and phase-locked loops;

Or, the first high-frequency oscillator and the second high-frequency oscillator are both voltage-controlled oscillators, and the oscillator types of the low-frequency oscillator include relaxation oscillators, phase-locked loops, and crystal oscillators.
The electronic device according to any one of claims 10-13, wherein the electronic device comprises a chip or a chipset connected to the true random number generator, and the low-frequency oscillator is also used to provide Or the chipset provides a wake-up clock, and the first high-frequency oscillator and the second high-frequency oscillator are also used to provide a system reference clock for the chip or chipset.