WO2021241268A1

WO2021241268A1 - Pll circuit

Info

Publication number: WO2021241268A1
Application number: PCT/JP2021/018361
Authority: WO
Inventors: 智宏松本; 健一丸子
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2020-05-27
Filing date: 2021-05-14
Publication date: 2021-12-02
Also published as: JP2021190779A

Abstract

A PLL circuit (4) comprises: an oscillation circuit (5) that operates using a power source (VDD) of a semiconductor chip (2) making up a solid-state imaging device (3); a PLL (7) that provides control according to a parameter (FCW); a monitoring unit (8) that includes, in the monitoring target thereof, at least the voltage of the power source (VDD); and a correction unit (9) that corrects the parameter (FCW) on the basis of the monitoring result from the monitoring unit (8). The PLL (7) generates a PLL clock signal (PLLCLK), which is determined on the basis of the parameter (FCW) that was corrected by the correction unit (9) and a reference clock signal (REFCLK) that is obtained from an oscillation clock signal (OSCLK) of the oscillation circuit (5).

Description

PLL circuit

This disclosure relates to a PLL circuit.

Non-Patent Document 1 proposes a method for correcting frequency deviation due to temperature fluctuation of a MEMS oscillation circuit.

The oscillation circuit is mounted on an electronic device such as a solid-state image sensor (image sensor). If the power supply of the semiconductor chip constituting the solid-state image sensor is used as the power supply of the oscillation circuit, it is considered that compact mounting is possible. However, the fluctuation of the power supply voltage causes a frequency shift in the oscillation circuit. This problem has not been examined in Non-Patent Document 1.

One aspect of the present disclosure is to provide a PLL circuit that can be compactly mounted on a solid-state image sensor.

The PLL circuit according to one aspect of the present disclosure includes an oscillation circuit that operates using the power supply of the semiconductor chip constituting the solid-state imaging device, a PLL controlled by parameters, and a monitor unit that includes at least the voltage of the power supply for the monitoring target. , A correction unit that corrects parameters based on the monitor result of the monitoring unit, and a PLL is defined based on a reference clock signal obtained from an oscillation clock signal of an oscillation circuit and parameters corrected by the correction unit. Generate a clock signal.

It is a figure which shows the example of the schematic structure of the solid-state image pickup apparatus which mounts the PLL circuit which concerns on embodiment. It is a figure which shows the example of the schematic structure of the PLL circuit. It is a figure which shows the example of the schematic structure of the oscillation circuit. It is a figure which shows the example of the schematic structure of the oscillation circuit. It is a figure which shows the example of the schematic structure of the oscillation circuit. It is a figure which shows the example of the schematic structure of the oscillation circuit. It is a figure which shows the example of the schematic structure of the oscillation circuit. It is a figure which shows the example of the schematic structure of the digital PLL. It is a figure which shows typically the influence on the frequency by the voltage fluctuation of a power source. It is a figure which shows typically the influence on the frequency by the temperature fluctuation of an oscillation circuit. It is a figure which shows the example of the time division monitor. It is a figure which shows the example of the time division monitor. It is a figure which shows the example of the time division monitor. It is a figure which shows the example of the time division monitor. It is a figure which shows the correction of a frequency deviation schematically. It is a figure which shows the correction of a frequency deviation schematically. It is a figure which shows the correction of a frequency deviation schematically. It is a flowchart which shows the example of the acquisition method of the correction coefficient. It is a figure which shows the example of the schematic structure of the PLL circuit. It is a figure which shows the example of the schematic structure of the image sensor system. It is a figure which shows the example of the schematic structure of the image sensor system. It is a figure which shows the example of the schematic structure of the image sensor system. It is a figure which shows the example of the schematic structure of the image sensor system. It is a figure which shows the example of the schematic structure of the image sensor system. It is a figure which shows the example of the schematic structure of the image sensor system. It is a figure which shows the example of the schematic structure of the oscillation circuit. It is a figure which shows the example of the schematic structure of the correction part.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. By assigning the same reference numerals to the same parts, duplicate explanations will be omitted.

The present disclosure will be described according to the order of items shown below.
1. 1. Introduction 2. Embodiment 3. effect

1. 1. Introduction In a semiconductor chip such as an LSI that constitutes a mobile electronic device such as a solid-state image sensor, a reference clock is indispensable. Generally, the reference clock is mainly generated by using a crystal oscillator circuit (crystal oscillator). The frequency accuracy of the crystal oscillator circuit is high, but the size (physical size) is large. Therefore, there is a demand for generating a reference clock using an oscillation circuit that is smaller than the crystal oscillation circuit. In the miniaturized oscillation circuit, as described above, it is conceivable to use the power supply of the semiconductor chip as the power supply of the oscillation circuit. However, the frequency of the oscillation circuit deviates due to the fluctuation of the power supply voltage.

From the above, in an oscillating circuit that is smaller than a crystal oscillating circuit (for example, in an on-chip configuration), a technique for improving the frequency deviation of the oscillating circuit due to fluctuations in the power supply voltage is desired.

2. 2. Embodiment FIG. 1 is a diagram showing an example of a schematic configuration of a solid-state image pickup device on which a PLL circuit according to an embodiment is mounted. The clock signal generated by the PLL circuit is used in various parts of the solid-state image sensor.

The solid-state image sensor 3 exemplified in FIG. 1 is a CMOS image sensor. In the solid-state image sensor 3, the semiconductor chip 1 and the semiconductor chip 2 are laminated so as to constitute the solid-state image sensor 3.

The semiconductor chip 1 is a pixel chip. A pixel array portion 1a (pixel portion) is formed on the semiconductor chip 1. The pixel array unit 1a includes a plurality of pixels 1b arranged two-dimensionally. Each pixel 1b includes a photoelectric conversion element (not shown). A pad portion 1c and a via portion 1d are provided on the peripheral portion of the semiconductor chip 1. The pad portion 1c is used for electrical connection between the semiconductor chip 1 and the outside of the semiconductor chip 1. The via portion 1d is used for electrical connection between the semiconductor chip 1 and the semiconductor chip 2. For example, a pixel signal (here, an analog signal) read from each pixel 1b is transmitted to the semiconductor chip 2 via the via portion 1d. In the example shown in FIG. 1, the pad portion 1c is a pair of pad portions provided on both sides of the pixel array portion 1a. The via portion 1d is a pair of via portions provided on both sides of the pixel array portion 1a. Even if a configuration is adopted in which a pad portion is provided on the semiconductor chip 2 to open the semiconductor chip 1 and bonded to the pad on the semiconductor chip 2 side, or a configuration is adopted in which the semiconductor chip 2 is mounted on a substrate by TSV (Through Silicon Via). good.

The semiconductor chip 2 may be a circuit chip. In the semiconductor chip 2, in addition to a drive unit (not shown) that drives each pixel 1b, peripheral circuit units such as a signal processing unit 2a, a memory unit 2b, a data processing unit 2c, an interface unit 2d, and a control unit 2e are formed. .. Power is supplied to each circuit from a power source (not shown in FIG. 1), and this power source is shown as a power supply VDD in FIG. 2 and the like described later.

The signal processing unit 2a processes the pixel signal of each pixel 1b. The process includes AD conversion and the like. The memory unit 2b stores a pixel signal (pixel data) processed by the signal processing unit 2a. The data processing unit 2c reads the pixel data stored in the data processing unit 2c in order and sends it to the interface unit 2d. The interface unit 2d may be a high-speed interface that outputs pixel data to the outside of the semiconductor chip 2 in a format according to a given standard.

The control unit 2e has the drive unit, the signal processing unit 2a, the memory unit 2b, and the data processing unit 2c described above based on the given horizontal synchronization signal XHS, vertical synchronization signal XVS, and reference clock such as the master clock MCK. And the operation of the interface unit 2d and the like is controlled while synchronizing with the circuit of the semiconductor chip 1 (pixel array unit 1a and the like). The control unit 2e can also control the PLL circuit 4 (FIG. 2) described later.

In the semiconductor chip 1 having a laminated structure of the semiconductor chip 1 and the semiconductor chip 2, the semiconductor chip 1 can be brought close to the size (area) of the pixel array portion 1a, and therefore the size of the entire semiconductor chip should be reduced. Can be done. Further, since a process suitable for forming the pixel 1b can be applied to the semiconductor chip 1 and a process suitable for forming peripheral circuits such as the signal processing unit 2a can be applied to the semiconductor chip 2, the process is optimized. You can also do it.

High-speed processing is realized by configuring peripheral circuit parts such as the signal processing unit 2a that performs processing such as AD conversion on the semiconductor chip 2 (on the same substrate). When digital data is transmitted between different semiconductor chips, a clock delay due to the influence of parasitic capacitance or the like may occur, which may hinder high-speed processing, but such a problem does not occur.

For example, the PLL circuit according to the embodiment is used to generate the reference clock supplied to the signal processing unit 2a, the interface unit 2d, the control unit 2e, etc. that perform the AD conversion processing described above. The PLL circuit will be described with reference to FIGS. 2 and 2.

FIG. 2 is a diagram showing an example of a schematic configuration of a PLL circuit according to an embodiment. The example PLL circuit 4 includes an oscillation circuit 5, a divider 6, a PLL 7 (Phase Locked Loop), a monitor unit 8, and a correction unit 9.

The oscillation circuit 5 corresponds to Genshin and operates based on the voltage of the power supply VDD. The power supply VDD is a power supply for a chip (for example, the semiconductor chip 2 in FIG. 1) constituting the solid-state image sensor 3. The oscillation circuit 5 has a small size so that the semiconductor chip 2 and the power supply can be used in common. The oscillation circuit 5 is smaller than, for example, a crystal oscillation circuit. The oscillation circuit 5 may be integrated in the semiconductor chip 2. The oscillation circuit 5 can oscillate at a frequency higher than the crystal oscillation frequency (for example, on the order of GHz) by having a small circuit constant suitable for miniaturization. Hereinafter, the oscillation circuit 5 will be described as generating a clock signal. The oscillation signal of the oscillation circuit 5 is referred to as a clock signal OSCLK and is shown in the figure. Some configuration examples of the oscillation circuit 5 will be described with reference to FIGS. 3 to 7.

3 to 7 are diagrams showing an example of a schematic configuration of an oscillation circuit. Since the operating principle of the oscillation circuit itself is known, a detailed description will not be given below, but an example of the configuration will be briefly described.

FIGS. 3 to 5 illustrate an LC oscillation circuit. The oscillation circuit 51 illustrated in FIG. 3 is a single-ended circuit that operates at the voltage of the power supply VDD. The output end of the amplifier 511 is connected to the input end of the amplifier 511 via a coil 512 and a capacitor 513 connected in parallel with each other.

The oscillation circuit 52 exemplified in FIG. 4 is a differential circuit that operates based on the voltage of the power supply VDD. The output end (drain in this example) of one of the

transistors

521a and 521b (a pair of differential transistors) is the input end (in this example) of the other transistor via a coil 522 and a capacitor 523 connected in parallel with each other. It is connected to the gate). The resistor 524 is connected between the other output end (source in this example) of the transistor 521a and the transistor 521b and ground. The resistor 525 is connected between the power supply VDD and the coil 522.

The oscillation circuit 53 exemplified in FIG. 5 is different from the oscillation circuit 52 (FIG. 4) in that it does not have a resistor 524 and a resistor 525, but has a current source 536. The current source 536 is connected between the transistor 521a and the transistor 521b and the ground so that a current flows from the source of the transistor 521a and the transistor 521b toward the ground.

FIG. 6 illustrates an RING (RC) oscillator circuit that operates based on the voltage of the power supply VDD. The output ends of each of an odd number of longitudinally connected NOT circuits 541 (three in this example) are connected to the ground via capacitors 542 and resistors 543 provided in parallel with each other. The power supply VDD of each NOT circuit 541 may be the same power supply (common power supply).

The oscillation circuit as described with reference to FIGS. 3 to 6 described above can be configured by, for example, on-chip circuit elements (coils, capacitors, resistors), and can eliminate the need for external components. Therefore, it can be made smaller than the crystal oscillator circuit. This merit becomes apparent as the area of the coil and the capacitor becomes smaller as the oscillation frequency becomes higher.

FIG. 7 exemplifies a MEMS oscillation circuit that operates based on the voltage of the power supply VDD. In the oscillation circuit 55 illustrated in FIG. 7, the output end of the amplifier 551 is connected to the input end of the amplifier 551 via MEMS552. The voltage of the power supply VDD is boosted by the charge pump 553 and then applied to the MEMS 552. This is because the voltage of the power supply VDD is only about 1V to 5V, for example, whereas the voltage of about 10V is required to drive the MEMS552. The voltage boosted by the charge pump 553 is stepped down by the level shifter 554 and returned to the voltage of the power supply VDD again. The voltage after step-down can be monitored as the voltage of the power supply VDD by the monitor unit 8 (FIG. 2) described later. Such a MEMS oscillation circuit can also be made smaller than the crystal oscillation circuit, and may be provided in the vicinity of the semiconductor chip 2 (FIG. 1), for example.

The oscillation circuit described with reference to FIGS. 3 to 7 is merely an example of the oscillation circuit 5, and other than these, oscillation circuits having various configurations may be used as the oscillation circuit 5.

Returning to FIG. 2, the frequency divider 6 divides the clock signal OSCLK of the oscillation circuit 5. The signal divided by the frequency divider 6 is referred to as a clock signal REFCLK and is shown in the figure. The clock signal REFCLK is used as a reference clock for PLL7. The clock signal OSCLK is divided by the frequency divider 6 because, as described above, the frequency of the clock signal OSCLK can be considerably higher than, for example, the crystal oscillation frequency. If there is no need for frequency division, the PLL circuit 4 may not include the frequency divider 6. In this case, the clock signal OSCLK itself of the oscillation circuit 5 becomes the clock signal REFCLK.

PLL7 generates a clock signal PLLCLK. The clock signal PLLCLK is determined based on the clock signal REFCLK and the FCW (Frequency Command Word) parameter. The FCW parameter is a numerical value that specifies the ratio of the frequency of the clock signal PLLCLK to the frequency of the clock signal REFCLK. FCW parameters are given from outside the PLL 7. When the PLL circuit 4 is applied to the solid-state image sensor 3 (FIG. 1), the FCW parameter is given, for example, by the control unit 2e of the solid-state image sensor 3. The numerical range shown in the FCW parameter is determined according to the parameter length (number of bits) of the FCW parameter. For example, when the PLL 7 is an analog PLL, the FCW parameter may have a parameter length of about 2 to 3 bits in order to improve the resolution by using ΔΣ modulation. When the PLL 7 is a digital PLL, the FCW parameter may have a parameter length of about 20 bits, which is longer than the analog PLL. The larger the parameter length (the larger the number of bits), the better the frequency control resolution of the clock signal PLLCLK.

In one embodiment, the PLL 7 is a digital PLL. In the digital PLL, the Divider utilizing ΔΣ used in the analog PLL becomes unnecessary. Therefore, unlike the analog PLL, it is not necessary to narrow the band of the PLL in order to reduce the high band noise generated in ΔΣ, and the increase of the phase noise is suppressed. An example of the configuration of the digital PLL will be described with reference to FIG.

FIG. 8 is a diagram showing an example of a schematic configuration of a digital PLL. The illustrated digital PLL 71 is also referred to as ADPLL (All Digital PLL) or the like, as shown in Non-Patent Document 2, for example, and only DCO (Digitally Controlled Oscillator) and TDC (Time to Digital Converter) are analog circuits. Others (ie, most) are digital circuits. The digital PLL 71 generates a signal having a frequency obtained by multiplying the clock signal REFCLK by the FCW parameter as the clock signal PLLCLK.

Accumulator 1 and Accumulator 2 shown are synonymous with the Counter circuit. Accumulator 1 is a low-speed accumulator to which FCW parameters are input. The Accumulator 2 is a high-speed operation Accumulator to which a DCO clock (corresponding to a clock signal PLLCLK) is input. Both Accumulator 1 and Accumulator 2 output a digital code for each clock of the clock signal REFCLK.

Accumulator1 can set a value to count up for each clock, and the set value is an FCW parameter. Since the FCW parameter is a digital word, a value including a small number (for example, 4.25, etc.) can be set by having a wide bit width. Since it counts up at the frequency of the clock signal REFCLK, the output code of the Accumulator 1 becomes the reference phase information.

Accumulator 2 outputs the count value of the DCO clock for each clock signal REFCLK. Since the count is increased for each clock of the DCO, the Accumulator 2 detects the phase in units of one cycle of the DCO. The TDC, which can measure a finer time, plays a role in detecting a period (phase) of one period or less.

The code obtained by adding the output codes of Accumulator 2 and TDC is the phase information of DCO. The code obtained by subtracting the output codes of the Accumulator 2 and the TDC from the output code of the Accumulator 1 becomes the phase error information between the clock signal REFCLK and the DCO clock. If the frequency of the DCO deviates from a desired frequency, the phase error becomes large, and feedback control is performed so that the phase error becomes small.

LoopFilter reduces the effect of quantization error. The quantization error results from the TDC having a finite resolution. As for the quantization error, the noise spectrum is uniformly generated from the low frequency to the high frequency, similar to the quantization error of the ADC. Band limitation by LoopFiler reduces the effect of quantization error. The output of LoopFilter is a noise-free code that makes the frequency of DCO a desired frequency. The Loop Filter also has a role of controlling the stability of the feedback loop, and the values of zero and zero so that the loop becomes stable are set.

The frequency of the clock signal REFCLK and _{F REF,} the value of the FCW parameters and FCW, when the frequency of the DCO clock and _{F _DCO,} relationship F DCO = FCW × _{F REF} is established. As can be understood from this, the FCW parameter can be said to be a frequency expressed by a digital word standardized by the frequency of the clock signal REFCLK. It is also understood again that the output code of the Accumulator 1 that integrates the FCW parameter information becomes the reference phase information.

Finally, a configuration example of TDC and DCO will be described. As shown in Non-Patent Document 3, for example, the TDC is composed of a delay element (Delay element) by an inverter or the like and a flip-flop circuit connected to each delay element. The clock of the DCO is delayed by the delay element, and the data is taken into the flip-flop circuit at the rising timing of the clock signal REFCLK. The edge position can be read from the read data of the flip-flop circuit. The time resolution of the TDC is the delay time of the delay element. The DCO is configured to control the value of the capacity bank according to the digital code, for example, as shown in Non-Patent Document 4. A capacitance bank indicates a plurality of capacitors (capacitors) connected in parallel to a coil (inductor), controls a switch according to a digital code, and changes the number of capacitors connected in parallel. The frequency is controlled by the change of the capacitance value. In addition to the coil and the capacitor, various frequency-controllable configurations may be used.

The digital PLL 71 shown in FIG. 8 is only an example of a digital PLL, and a digital PLL having various configurations other than this may be used as the PLL 7.

Returning to FIG. 2, the frequency of the clock signal OSCLK of the oscillation circuit 5 changes under the influence of the voltage fluctuation of the power supply VDD and the temperature fluctuation of the oscillation circuit 5. The frequency of the clock signal REFCLK and thus the frequency of the clock signal PLLCLK are also affected. This will be described with reference to FIGS. 9 and 10.

FIG. 9 is a diagram schematically showing the influence on the frequency due to the voltage fluctuation of the power supply. The horizontal axis of the graph shows the voltage of the power supply VDD, and the vertical axis shows the frequency. As shown in FIG. 9, when the power supply VDD changes, the frequency also changes. That is, due to the voltage fluctuation of the power supply VDD, a frequency shift occurs in the clock signal OSCLK, the clock signal REFCLK, and eventually the clock signal PLLCLK (frequency error occurs).

FIG. 10 is a diagram schematically showing the influence on the frequency due to the temperature fluctuation of the oscillation circuit. The horizontal axis of the graph shows the temperature of the oscillation circuit 5, and the vertical axis shows the frequency. As shown in FIG. 10, when the temperature of the oscillation circuit 5 changes, the frequency also changes. That is, due to the temperature fluctuation of the oscillation circuit 5, a frequency shift occurs in the clock signal OSCLK, the clock signal REFCLK, and eventually the clock signal PLLCLK. As a comparative example with the crystal oscillator circuit, for example, in the temperature range of -40 ° C to 120 ° C, the frequency deviation of the crystal oscillator circuit is about several tens of ppm, whereas the LC oscillator circuit (FIGS. 3 to 5, etc.) ) Is about several thousand ppm.

The frequency deviation of the clock signal PLLCLK due to voltage fluctuation and temperature fluctuation is reduced by the monitor unit 8 and the correction unit 9 described below.

The monitor unit 8 monitors various states of the oscillation circuit 5. In the example shown in FIG. 2, the monitor target of the monitor unit 8 includes the voltage of the power supply VDD and the temperature of the oscillation circuit 5. The voltage of the monitored power supply VDD is referred to as a monitor voltage V and is shown in the figure. The temperature of the monitored oscillation circuit 5 is referred to as a monitor temperature T and is shown in the figure. As a configuration for monitoring the monitor voltage V and the monitor temperature T, the monitor unit 8 includes a switch 81, a filter 82, a temperature sensor 83, a switch 84, an AD converter 85, a selector 86, and a filter 87. , Includes a filter 88 and a NOT circuit 89.

The monitor voltage V and the monitor temperature T are acquired (detected) as digital voltage values by the AD converter 85. The monitor voltage V is acquired by inputting the voltage of the power supply VDD to the AD converter 85 via the switch 81 and the filter 82. The filter 82 (analog filter in this example) suppresses aliases generated by the inclusion of high frequency components in the voltage of the power supply VDD. The monitor temperature T is acquired by inputting the output (analog value in this example) of the temperature sensor 83 provided for the oscillation circuit 5 to the AD converter 85 via the switch 84. A filter (analog filter) (not shown) may also be provided between the temperature sensor 83 and the AD converter 85. Further, a digital filter (not shown) may be provided after the AD converter 85 so as to remove circuit noise (excluding noise in the vicinity of DC) that may be mixed. The monitor voltage V acquired by the AD converter 85 is input to the correction unit 9 via the selector 86 and the filter 87. The monitor temperature T is input to the correction unit 9 via the selector 86 and the filter 88.

The switch 81, the switch 84 and the selector 86 are controlled by the control signal CS1. The control signal CS1 is given from the outside of the PLL circuit 4, for example, from the control unit 2e of the solid-state image pickup device 3. In this example, the selector 86 is a multiplexer (MUX). The control signal CS1 is directly supplied to the switch 84 and the selector 86. The control signal CS1 is supplied to the switch 81 via the NOT circuit 89. By exclusively switching the switch 81 and the switch 84, the monitor voltage V and the monitor temperature T are time-division-monitored. The time division monitor may be implemented in various embodiments. Some examples will be described with reference to FIGS. 11-14.

11 to 14 are diagrams showing an example of a time-division monitor. In the example shown in FIGS. 11 and 12, the monitor period of the monitor voltage V and the monitor period of the monitor temperature T are set so that the monitors of the monitor voltage V and the monitor temperature T operate continuously. In the example shown in FIG. 11, the monitoring period of the monitor temperature T is shorter than the monitoring period of the monitor voltage V. As shown in FIG. 12, the monitor period of the monitor temperature T and the monitor period of the monitor voltage V may be set equally. In the example shown in FIG. 13, the monitor period of the monitor voltage V and the monitor period of the monitor temperature T are set so that the monitors of the monitor voltage V and the monitor temperature T operate intermittently. In the example shown in FIG. 14, the monitor period of the monitor voltage V and the monitor period of the monitor temperature T are set to operate intermittently alternately. In the time-divided monitor, there may be a period in which neither the monitor voltage V nor the monitor temperature T is monitored (see, for example, FIGS. 13 and 14), and the operation of the AD converter 85 may be stopped during the period. .. This reduces power consumption.

The time-division monitor as described above is possible because the fluctuation of the monitor temperature T is very slow, for example, about several Hz, and the monitor voltage V is also a voltage value close to DC. This is because it can be sufficiently obtained. Generally, the band of temperature fluctuation is low and low rate monitoring is possible, and the power supply monitor is not an AC fluctuation monitor but the average frequency of the oscillator because the PLL acts as a low frequency pass type filter. A low-rate monitor close to DC is sufficient for the purpose of suppressing fluctuations. Since there are cases where the voltage fluctuation of the power supply fluctuates greatly in terms of AC due to the operation of other circuits on the same chip, the monitor voltage V is monitored so as to avoid the timing when the AC fluctuation becomes large. It's okay.

For example, by performing the time division monitor as described above, the monitor voltage V and the monitor temperature T can be monitored by a single AD converter 85 (FIG. 2). Since it is not necessary to provide a plurality of AD converters corresponding to the monitor voltage V and the monitor temperature T, the PLL circuit 4 can be miniaturized. The configuration of the monitor unit 8 shown in FIG. 2 is merely an example, and various configurations capable of monitoring the voltage of the power supply VDD and the temperature of the oscillation circuit 5 may be adopted.

Returning to FIG. 2, the correction unit 9 corrects the FCW parameter based on the monitor result of the monitor unit 8. In this example, the correction unit 9 includes a calculation unit 91, a calculation unit 92, a storage unit 95, a multiplication unit 96, and a multiplication unit 97.

The calculation unit 91 calculates the correction value CV1. The correction value CV1 is a correction value (first correction value) corresponding to the monitor voltage V. More specifically, the correction value CV1 is a correction value for correcting the frequency deviation of the clock signal PLLCLK due to the voltage fluctuation of the power supply VDD. When the reference voltage (e.g., typ voltage value of the power supply VDD) and the reference voltage _{V 0,} the correction value CV1 is calculated, for example according to the following polynomial. The correction coefficient α (α ₁ , α ₂ , α ₃ ) in the equation is a coefficient (voltage correction coefficient) for calculating the correction value CV1.
CV1 = 1 + α ₁ (VV ₀ ) + α ₂ (VV ₀ ) ² + α ₃ (VV ₀ ) ³

The calculation unit 92 calculates the correction value CV2. The correction value CV2 is a correction value (second correction value) corresponding to the monitor temperature T. More specifically, the correction value CV2 is a correction value for correcting the frequency deviation of the clock signal PLLCLK due to the temperature fluctuation of the oscillation circuit 5. Assuming that the reference temperature (for example, type temperature) is the reference temperature T ₀ , the correction value CV2 is calculated according to, for example, the following polynomial. The correction coefficient β (β _1k , β _2k , β _3k ) in the equation is a coefficient (temperature correction coefficient) for calculating the correction value CV2.
CV2 = 1 + β _1k ( _{TT 0} ) + β _2k ( _TT ₀ ) ² + β 3k ( _{TT 0} ) ³

The correction value may be a correction value in consideration of the dependency between the monitor target corresponding to the correction value and another monitor target. For example, the correction coefficient β used for calculating the above correction value CV2 may be a coefficient different depending on the voltage of the power supply VDD, not an independent coefficient determined only by the monitor temperature T. In order to obtain the correction coefficient β in which such a dependency is taken into consideration, a look-up table describing the dependency may be referred to. The look-up table contains, for example, the following description.
V ₀ <= V <V ₁ : β ₁₀ , β ₂₀ , β ₃₀ ...
V ₁ <= V <V ₂ : β ₁₁ , β ₂₁ , β ₃₁ ...
V ₂ <= V <V ₃ : β ₁₂ , β ₂₂ , β ₃₂ ...

According to the lookup table, the reference voltage _{V 0,} as well as the voltage _{V 1} predetermined by the voltage _{V 2} and the voltage _{V 3,} the reference voltage greater than or equal to _{V 0} voltage _V smaller than _1, the voltage _{V 1} or the voltage _{V 2} Multiple voltage ranges are defined, such as less than, voltage V _{2 and} above, and voltage V _{less than 3.} The correction coefficient β is set to a different value depending on which voltage range of the plurality of voltage ranges includes the monitor voltage V. For example, when the monitor voltage V is equal to or more than the _{reference voltage V 0} _{and less than the voltage V 1} , the correction coefficient β is set to _{β 10} , β ₂₀ , β _{30, and the like.} When the monitor voltage V is the voltage V ₁ or more and the voltage V _{2 or} less, the correction coefficient β is set to _{β 11} , β ₂₁ , β _{31, and the like.} When the monitor voltage V is equal to or greater than the voltage V2 and less than the voltage V3, the correction coefficients β are set to _{β 12} , β ₂₂ , β _{32, and the like.}

The storage unit 95 stores the information necessary for the calculation of the calculation unit 91 and the calculation unit 92. Examples of information are the correction factors α and the correction factors β described above. The correction coefficient α and the correction coefficient β may be stored in the storage unit 95 by writing to the non-volatile memory. In this case, the correction coefficient α and the correction coefficient β are always read and set when the power is turned on, when the operation is started, and the like. The above-mentioned look-up table may be stored in the storage unit 95 in the same manner.

The correction coefficient α and the correction coefficient β (including the look-up table) described above may be acquired by using the evaluation data of a large number of samples of the PLL circuit 4. For example, for each of the mass-produced products acquired in the test before mass production shipment, the profile of the frequency deviation of the clock signal PLLCLK due to the voltage fluctuation of the power supply VDD and the temperature fluctuation of the oscillation circuit 5 is acquired, and fitting is performed to the profile. Thereby, the correction coefficient α and the correction coefficient β are determined. An example of a method for acquiring the correction coefficient α and the correction coefficient β will be described later with reference to FIG.

The multiplication unit 96 corrects the FCW parameter using the correction value CV1 calculated by the calculation unit 91. In this example, the multiplication unit 96 corrects (changes) the numerical value of the FCW parameter by multiplying the correction value CV1 by the FCW parameter. As a result, the frequency shift of the clock signal PLLCLK due to the voltage fluctuation of the power supply VDD is corrected (voltage compensation is performed).

The multiplication unit 97 corrects the FCW parameter using the correction value CV2 calculated by the calculation unit 92. In this example, the multiplication unit 97 corrects (changes) the numerical value of the FCW parameter by multiplying the correction value CV2 by the FCW parameter. As a result, the frequency shift of the clock signal PLLCLK due to the temperature fluctuation of the oscillation circuit 5 is corrected (temperature compensation is performed).

The correction of the frequency deviation of the clock signal PLLCLK using the correction value as described above will be described with reference to FIGS. 15 to 17. The outline of the correction of the frequency deviation of the clock signal PLLCLK due to the voltage fluctuation of the power supply VDD will be described below.

FIGS. 15 to 17 are diagrams schematically showing the correction of frequency deviation. In the state before the correction, as shown in FIG. 15, the frequency shift of the clock signal PLLCLK occurs due to the voltage fluctuation of the power supply VDD. A correction value CV1 that gives a frequency shift correction amount as shown in FIG. 16 is calculated by the calculation unit 91 so as to cancel this. By correcting the FCW parameter using the correction value CV1 by the multiplication unit 96, the frequency deviation of the clock signal PLLCLK due to the voltage fluctuation of the power supply VDD is reduced as shown in FIG. The frequency deviation of the clock signal PLLCLK due to the temperature fluctuation of the oscillation circuit 5 will be similarly described.

An example of a method for acquiring a coefficient such as the correction coefficient α and the correction coefficient β described above will be described with reference to FIG. FIG. 18 is a flowchart showing an example of a method of acquiring a correction coefficient.

In step S1, the PLL circuit is operated at the representative temperature and the representative voltage. The representative temperature is, for example, the reference temperature T ₀ (type temperature) of the above-mentioned oscillation circuit 5. The representative voltage is, for example, the reference voltage V ₀ (type voltage value) of the above-mentioned power supply VDD. The accurate voltage and temperature are monitored as the monitor voltage V and the monitor temperature T by the monitor unit 8 during the operation of the PLL circuit 4.

In step S2, the FCW parameter that becomes the desired clock frequency is calculated. This provides FCW parameters for the PLL 7 to generate a clock signal PLLCLK with a desired frequency at a reference temperature and a reference voltage.

In step S3, the voltage fluctuation characteristic and the temperature fluctuation characteristic are acquired. For example, the voltage of the power supply VDD is changed (voltage sweep) while monitoring the frequency of the clock signal PLLCLK. As a result, a voltage fluctuation characteristic showing the relationship between the voltage fluctuation of the power supply VDD and the frequency of the clock signal PLLCLK can be obtained. Further, the temperature of the oscillation circuit 5 is changed (temperature sweep) while monitoring the frequency of the clock signal PLLCLK. As a result, a temperature fluctuation characteristic showing the relationship between the temperature fluctuation of the oscillation circuit 5 and the frequency of the clock signal PLLCLK can be obtained.

In step S4, the correction coefficient is calculated. For example, the correction coefficient α for calculating the correction value CV1 that cancels the voltage fluctuation characteristic acquired in the previous step S3 is calculated by fitting. Further, the correction coefficient β for calculating the correction value CV2 that cancels the temperature fluctuation characteristic acquired in the previous step S3 is calculated by fitting. The calculation result may also include the dependency between the coefficients (the description content of the above-mentioned look-up table).

In step S5, the calculation result is stored. That is, the correction coefficient α and the correction coefficient β calculated in the previous step S4 are stored in the storage unit 95, for example, by writing to the non-volatile memory.

After the processing of step S5 is completed, the processing of the flowchart ends. For example, by the above processing, the correction coefficient α and the correction coefficient β are acquired.

In one embodiment, the oscillation circuit is configured so that the oscillation frequency can be switched. In that case, the correction value CV1 and the correction value CV2 are calculated according to the switching of the oscillation frequency. This will be described with reference to FIG.

FIG. 19 is a diagram showing an example of a schematic configuration of a PLL circuit. Compared with the PLL circuit 4 (FIG. 2), the PLL circuit 4A shown in FIG. 19 includes an oscillation circuit 5A and a correction unit 9A instead of the oscillation circuit 5 and the correction unit 9, and further, the control signal CS2 is provided. It differs in that it is used.

The oscillation circuit 5A is configured so that the oscillation frequency can be switched. In this example, the oscillation circuit 5A includes a configuration in which a capacitor 514 and a switch 515 are added to the oscillation circuit 51 described above with reference to FIG. The capacitor 514 is connected in parallel to the capacitor 513 with the switch 515 connected in series. The switch 515 is switched by the control signal CS2. The control signal CS2 is given from the outside of the PLL circuit 4, for example, from the control unit 2e of the solid-state image pickup device 3. As a result, the capacitance of the capacitor connected in parallel to the coil 512 is switched between the capacitance value of the capacitor 513 and the combined capacitance value of the capacitor 513 and the capacitor 514. By such capacitance switching, the oscillation frequency of the oscillation circuit 5A, that is, the frequency of the clock signal OSCLK is switched.

The control signal CS2 is input to the correction unit 9A. The calculation unit 91A and the calculation unit 92A calculate the correction value CV1 and the correction value CV2 according to the switching of the oscillation frequency of the oscillation circuit 5A. The correction coefficient α and the correction coefficient β may be defined as a function of the oscillation frequency of the oscillation circuit 5A, that is, the correction coefficient α (f) and the correction coefficient β (f). When the oscillation frequency of the oscillation circuit 5A _{is switched between the oscillation frequency f 0} and the oscillation frequency f ₁ , the correction coefficient α is switched between the correction coefficient α (f ₀ ) and the correction coefficient α (f ₁ ). .. The correction coefficient β is switched between the correction coefficient β (f ₀ ) and the correction coefficient β (f _1). These correction coefficients α (f) and correction coefficients β (f) are stored in the storage unit 95A (for example, a non-volatile memory). The values of the reference voltage Vo and the reference temperature To may also be changed according to the switching of the oscillation frequency of the oscillation circuit 5A.

By switching the oscillation frequency using the oscillation circuit 5A having a capacitance bank like the PLL circuit 4A, EMI (Electromagnetic Interface) measures such as preventing interference with other circuits become easy. The oscillation circuit 5A shown in FIG. 9 is merely an example, and other than this, oscillation circuits having various configurations capable of switching the oscillation frequency may be used.

The PLL circuit is used in an electronic device such as the solid-state image sensor 3 described above with reference to FIG. Various configurations can be considered as an electronic device (system) having a built-in PLL circuit including an oscillation circuit. An example of a system is a camera system with a built-in oscillation circuit. The camera system is not limited to an image sensor system (solid-state image sensor) for image pickup, but also includes a TOF (Time Of Flight) system capable of measuring a distance. Some examples of system configurations will be described with reference to FIGS. 20-25.

20 to 25 are diagrams showing an example of a schematic configuration of an image sensor system.

In the system 100 exemplified in FIG. 20, the clock signal OSCLK of the oscillation circuit 5 is supplied to the ADC / DAC / CP circuit 21. The ADC / DAC / CP circuit 21 points to at least one of an AD conversion process (ADC) circuit, a DA conversion process (DAC) circuit, and a charge pump (CP) circuit. This is because the ADC / DAC / CP circuit 21 has a relatively small influence of frequency fluctuations and can supply the clock signal OSCLK as it is. The ADC / DAC / CP circuit 21 is included in, for example, the signal processing unit 2a, the data processing unit 2c, the control unit 2e, and the like described above with reference to FIG. On the other hand, the clock signal PLLCLK in which the frequency deviation is reduced as described above is supplied to the high-speed IF circuit 22 that connects to the outside. This is because the high-speed IF circuit 22 is relatively greatly affected by frequency fluctuations and requires high frequency accuracy. The high-speed IF circuit 22 is included in the interface unit 2d described above with reference to FIG. 1, for example. In the system 100, the frequency of the clock signal OSCLK and the frequency of the clock signal PLLCLK may both be frequencies on the order of GHz.

Here, the ADC / DAC / CP circuit 21 is often used together with a logic circuit (signal processing circuit) that performs various processing including clock-based counting processing. In this case, if a deviation occurs in the clock frequency, the frame rate of imaging may fluctuate, for example. The monitor result (monitor voltage V and monitor temperature T in this example) of the monitor unit 8 may be supplied to the ADC / DAC / CP circuit 21 so that this fluctuation can be corrected inside the circuit.

FIG. 21 illustrates a system including a CP circuit 212d, a DAC circuit 213d and an ADC circuit 214d, and a signal processing circuit 215d after the ADC circuit 214d. In the setting unit 211, setting values corresponding to each process are set. An example of the set value is Gain of the corresponding processing circuit.

The set value corresponding to the CP circuit 212d passes through the adjusting unit 212a and the adjusting unit 212b and is written to the register 212c. The set value corresponding to the DAC circuit 213d is adjusted by the adjusting unit 213a and the adjusting unit 213b, and then written to the register 213c of the DAC circuit 213d. The set value corresponding to the ADC circuit 214d is written to the register 214c after being adjusted by the adjusting unit 214a and the adjusting unit 214b. The set value corresponding to the signal processing circuit 215d is adjusted by the adjusting unit 215a and the adjusting unit 215b, and then written to the register 215c of the signal processing circuit 215d.

The adjusting unit 212a, the adjusting unit 213a, the adjusting unit 214a, and the adjusting unit 215a adjust the set value based on the monitor voltage V. The adjusting unit 212a, the adjusting unit 213a, the adjusting unit 214a, and the adjusting unit 215a have a function of scaling the value of the monitor voltage V, a function of correcting using a polynomial such as the calculation unit 91 and the calculation unit 92, a look-up table, and the like. You may be prepared. As a result, the processing deviation (for example, Gain deviation) of the CP circuit 212d, the DAC circuit 213d, the ADC circuit 214d, and the signal processing circuit 215d due to the voltage fluctuation of the power supply VDD is corrected. The adjusting unit 212b, the adjusting unit 213b, the adjusting unit 214b, and the adjusting unit 215b adjust the set value based on the monitor temperature T. The adjusting unit 212b, the adjusting unit 213b, the adjusting unit 214b, and the adjusting unit 215b have a function of scaling the value of the monitor temperature T, a function of correcting using a polynomial such as the calculation unit 91 and the calculation unit 92, a look-up table, and the like. You may be prepared. As a result, the processing deviation of the CP circuit 212d, the DAC circuit 213d, the ADC circuit 214d, and the signal processing circuit 215d due to the temperature fluctuation of the oscillation circuit 5 is corrected.

The clock signal PLLCLK of the PLL 7 may be supplied to the ADC / DAC / CP circuit 21 instead of the clock signal OSCLK of the oscillation circuit 5. As a result, the clock with high frequency accuracy can be supplied to the ADC / DAC / CP circuit 21 as well.

In the system 100A exemplified in FIG. 22, PLL 7 is also provided between the frequency divider 6 and the ADC / DAC / CP circuit 21. The PLL signal of the PLL 7 is supplied to the ADC / DAC / CP circuit 21. The FCW parameters input to each of the illustrated PLL7s may be set to different values. In FIG. 22, the monitor unit 8 and the correction unit 9 described so far are not shown. The same applies to FIGS. 23 to 25, which will be described later.

In the system 100B exemplified in FIG. 23, a frequency divider 6 is also provided between the PLL 7 and the ADC / DAC / CP circuit 21. The PLL signal of the PLL 7 is divided by the divider 6 and then supplied to the ADC / DAC / CP circuit 21. As a result, a clock having a frequency accuracy equivalent to that of the clock supplied to the high-speed IF circuit 22 and having a frequency lower than that of the clock can be supplied to the ADC / DAC / CP circuit 21. The frequency division ratio of each of the illustrated frequency dividers 6 may be set to a different value, and this point is the same in FIGS. 24 and 25 described later.

In the system 100C exemplified in FIG. 24, a frequency divider 6 is also provided between the oscillation circuit 5 and the logic circuit 23. As a result, the clock signal OSCLK of the oscillation circuit 5 can be divided into appropriate frequencies and supplied to the logic circuit 23.

In the system 100D exemplified in FIG. 25, a frequency divider 6 provided between the PLL 7 and the ADC / DAC / CP circuit 21 and a frequency divider 6 are further provided between the logic circuit 23. The PLL signal of the PLL 7 is divided by the two dividers 6 and then supplied to the logic circuit 23. As a result, the clock signal PLLCLK can be divided into appropriate frequencies other than the clock frequency supplied to the ADC / DAC / CP circuit 21 and supplied to the logic circuit 23.

The system configurations described with reference to FIGS. 20 to 25 are merely examples, and the PLL circuit according to the embodiment may be applied to various system configurations other than these.

In the above embodiment, an example of correcting the frequency deviation of the clock signal PLLCLK due to the fluctuation of two parameters, the power supply voltage and the temperature of the oscillation circuit, has been described. However, in addition to these, frequency deviations due to various parameters related to the oscillation circuit may be corrected. Examples of other parameters are process and current. An example of the process is the threshold voltage of the transistor. This will be described with reference to FIGS. 26 and 27.

FIG. 26 is a diagram showing an example of a schematic configuration of an oscillation circuit. FIG. 26 schematically shows the transistor 511a and the current source 511b included in the amplifier 511 of the oscillation circuit 51 described above with reference to FIG. The threshold voltage of the transistor 511a is referred to as a threshold voltage Vth and is shown in the figure. The current flowing through the current source 511b is referred to as current Is and is shown in the figure. Fluctuations in the threshold voltage Vth and the current Is may also cause an oscillation frequency shift in the oscillation circuit 51. Therefore, the FCW parameter may be corrected in consideration of the monitor results of the threshold voltage Vth and the current Is. In this case, the monitor unit 8 (FIG. 2) is configured to include the threshold voltage Vth and the current Is as the monitoring target. The monitor may be a monitor of the threshold voltage Vth of the transistor 511a itself included in the oscillation circuit 51, or a monitor of the threshold voltage (corresponding to the threshold voltage Vth) of the replica circuit from which the circuit portion of the transistor 511a is extracted. It is also good. In order to reduce the power consumption of the replica circuit, the size and current value of the transistor may be scaled. Similarly, the current Is may be a replica circuit or a scaled current value. An example of the configuration of the correction unit for correcting the FCW parameter based on the monitor result of the monitor unit will be described with reference to FIG. 27.

FIG. 27 is a diagram showing an example of a schematic configuration of a correction unit. The exemplified correction unit 9C further includes a calculation unit 93, a calculation unit 94, a multiplication unit 98, and a multiplication unit 99 as compared with the correction unit 9 (FIG. 1), and includes a storage unit 95C in place of the storage unit 95. It differs in that.

The calculation unit 93 calculates a correction value CV3 (third correction value) for correcting the frequency deviation of the clock signal PLLCLK due to the fluctuation of the threshold voltage Vth. The calculation unit 94 calculates a correction value CV4 (fourth correction value) for correcting the frequency deviation of the clock signal PLLCLK due to the fluctuation of the current Is. Since the calculation method of the correction value CV3 and the correction value CV4 is the same as the calculation method of the correction value CV1 and the correction value CV2 described so far, the description is not repeated here.

The multiplication unit 98 corrects the FCW parameter using the correction value CV3. As a result, the frequency shift of the clock signal PLLCLK due to the fluctuation of the threshold voltage Vth is corrected (process compensation is performed). The multiplication unit 99 corrects the FCW parameter by using the correction value CV4. As a result, the frequency shift of the clock signal PLLCLK due to the fluctuation of the current Is is corrected (current compensation is performed). The frequency accuracy of the clock signal PLLCLK is further improved by the frequency shift correction in consideration of the fluctuation of the threshold voltage Vth and the current Is.

As an example of other parameters, the resistance value of the resistor included in the transmission circuit can also be mentioned. For example, in the case of the oscillation circuit 52 described above with reference to FIG. 2, the resistance value of the resistor 524 and the resistance value of the resistor 525 may be included in the monitoring target of the monitor unit 8. In the case of the oscillation circuit 54 described above with reference to FIG. 6, the resistance value of the resistor 543 may be included in the monitor target of the monitor unit 8. The resistance value monitor may be the resistance value monitor of the replica circuit, and the size may be scaled.

In the above embodiment, the FCW parameter has been described as an example of the correction symmetry of the correction unit 9. However, not limited to the FCW parameter, any parameter whose frequency of the PLL 7 can be adjusted can be the correction symmetry of the correction unit 9.

In the above embodiment, an example in which the multiplication unit 96 to the multiplication unit 99 correct the FCW parameter by multiplying the correction value CV1 to the correction value CV4 by the FCW parameter has been described. However, the FCW parameter may be corrected in various modes including addition / subtraction, division, etc., not limited to multiplication.

In the above embodiment, an example in which the PLL circuit 4 is applied to the solid-state image sensor 3 has been described. However, the PLL circuit 4 may be applied to various mobile electronic devices (for example, laptops, smartphones, etc.) other than the solid-state image sensor 3.

3. 3. Effect The PLL circuit described above is specified as follows, for example. As described with reference to FIGS. 1 and 2, the PLL circuit 4 includes an oscillation circuit 5, a PLL 7, a monitor unit 8, and a correction unit 9. The oscillation circuit 5 operates using the power supply VDD of the semiconductor chip 2 constituting the solid-state image pickup device 3. PLL7 is controlled by FCW parameters. The monitor unit 8 includes at least the voltage of the power supply VDD (monitor voltage V) in the monitor target. The correction unit 9 corrects the FCW parameter based on the monitor result of the monitor unit 8. The PLL 7 generates a clock signal PLLCLK determined based on the reference clock signal REFCLK obtained from the oscillation clock signal OSCLK of the oscillation circuit 5 and the FCW parameter corrected by the correction unit 9.

According to the PLL circuit 4 described above, the FCW parameter that controls the PLL 7 is corrected based on the monitor result of the voltage of the power supply VDD, so that the frequency deviation of the clock signal PLLCLK can be reduced. Further, by using the power supply VDD of the semiconductor chip 2 constituting the solid-state image pickup device 3 in the oscillation circuit 5, it becomes possible to compactly mount the semiconductor chip 2 on the solid-state image pickup device 3.

The FCW parameter is a numerical value indicating the ratio of the frequency of the clock signal PLLCLK to the frequency of the clock signal REFCLK, and the correction unit 9 may correct the numerical value. For example, in this way, the frequency deviation of the clock signal PLLCLK can be corrected.

The monitor target of the monitor unit 8 may also include the temperature of the oscillation circuit 5 (monitor temperature T). As a result, the frequency shift of the clock signal PLLCLK due to the temperature fluctuation of the oscillation circuit 5 can also be corrected.

The correction unit 9 corrects the FCW parameter by using the correction values (for example, the correction value CV1 and the correction value CV2) corresponding to each of the monitoring targets (for example, the monitor voltage V and the monitor temperature T) included in the monitor result of the monitor unit 8. You can do it. As a result, the frequency shift of the clock signal PLLCLK can be corrected according to the monitor result of each monitor target.

At least one correction value (for example, correction value CV2) is a correction value in consideration of the dependency between the corresponding monitor target (for example, monitor temperature T) and another monitor target (for example, monitor voltage V). good. In this case, the correction unit 9 may refer to a look-up table that describes the dependency. As a result, even if there is a dependency between the monitored objects, the frequency deviation of the clock signal PLLCLK can be appropriately corrected.

As described with reference to FIGS. 11 to 14, the monitor unit 8 may monitor each of the monitored objects (for example, the monitor voltage V and the monitor temperature T) in a time-divided manner. As a result, each monitor target can be performed by a single monitor device (for example, AD converter 85), so that it is not necessary to provide a plurality of monitor devices corresponding to each monitor target. The PLL circuit 4 can be downsized by that amount.

The oscillation circuit 5 may be integrated in the semiconductor chip 2. In this case, as described with reference to FIGS. 3 to 5, the oscillation circuit 5 may be, for example, an LC oscillation circuit such as an oscillation circuit 51, an oscillation circuit 52, and an oscillation circuit 53. As described with reference to FIG. 6 and the like, the oscillation circuit 5 may be an RC oscillation circuit such as an oscillation circuit 54, for example. By using the oscillation circuit having such a configuration, the PLL circuit 4 can be easily integrated (on-chip) in the semiconductor chip 2. As a result, the PLL circuit 4 can be easily mounted on the solid-state image sensor 3, and the volume of the solid-state image sensor 3 can be reduced.

As described with reference to FIG. 19, the oscillation circuit 5A may be configured so that the clock signal OSCLK can be switched. This facilitates EMI (Electromagnetic Interface) measures such as preventing interference with other circuits.

As described with reference to FIGS. 26 and 27, the oscillation circuit 51 may include the transistor 511a, and the monitor target of the monitor unit 8 may include the threshold voltage Vth of the transistor 511a. Thereby, the frequency deviation of the clock signal PLLCLK due to the fluctuation of the threshold voltage Vth can be corrected. The oscillation circuit 51 may include the current source 511b, and the monitor target of the monitor unit 8 may include the current Is of the current source 511b. This makes it possible to correct the frequency shift of the clock signal PLLCLK due to the fluctuation of the current Is. In the case of an oscillation circuit including a resistor as shown in FIGS. 4 and 6, the resistance value of the resistor may be included in the monitor target of the monitor unit 8. This makes it possible to correct the frequency shift of the clock signal PLLCLK due to the fluctuation of the resistance value.

As described with reference to FIG. 8 and the like, the PLL 7 may be a digital PLL. As a result, it is possible to realize a higher frequency control resolution than the analog PLL and suppress an increase in phase noise.

Note that the effects described in this disclosure are merely examples and are not limited to the disclosed contents. There may be other effects.

Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments as they are, and various changes can be made without departing from the gist of the present disclosure. In addition, components spanning different embodiments and modifications may be combined as appropriate.

Further, the effects in each embodiment described in the present specification are merely examples and are not limited, and other effects may be obtained.

The present technology can also have the following configurations.
(1)
An oscillation circuit that operates using the power supply of the semiconductor chip that constitutes the solid-state image sensor,
The PLL controlled by the parameters and
A monitor unit that includes at least the voltage of the power supply as a monitor target,
A correction unit that corrects the parameters based on the monitor result of the monitor unit, and a correction unit.
Equipped with
The PLL generates a PLL clock signal determined based on a reference clock signal obtained from the oscillation clock signal of the oscillation circuit and the parameter corrected by the correction unit.
PLL circuit.
(2)
The parameter is a numerical value that specifies the ratio of the frequency of the PLL clock signal to the frequency of the reference clock signal.
The correction unit corrects the numerical value.
The PLL circuit according to (1).
(3)
The monitor target of the monitor unit includes the temperature of the oscillation circuit.
The PLL circuit according to (1) or (2).
(4)
The correction unit corrects the parameter by using the correction value corresponding to each of the monitoring targets included in the monitor result of the monitor unit.
The PLL circuit according to (3).
(5)
At least one of the correction values is a correction value in which the dependency between the corresponding monitor target and another monitor target is taken into consideration.
The PLL circuit according to (4).
(6)
The correction unit refers to a look-up table that describes the dependency.
The PLL circuit according to (5).
(7)
The monitor unit monitors each of the monitored objects in a time-division manner.
The PLL circuit according to any one of (2) to (6).
(8)
The oscillation circuit is integrated in the semiconductor chip.
The PLL circuit according to any one of (1) to (7).
(9)
The oscillation circuit is either an LC oscillation circuit or an RC oscillation circuit.
The PLL circuit according to (8).
(10)
The oscillation circuit is configured so that the oscillation frequency can be switched.
The PLL circuit according to any one of (1) to (9).
(11)
The oscillation circuit includes a transistor and includes a transistor.
The monitor target of the monitor unit includes the threshold voltage of the transistor.
The PLL circuit according to any one of (1) to (10).
(12)
The oscillator circuit includes a current source.
The monitor target of the monitor unit includes a current flowing through the current source.
The PLL circuit according to any one of (1) to (11).
(13)
The oscillation circuit includes a resistor and includes a resistor.
The monitor target of the monitor unit includes the resistance value of the resistor.
The PLL circuit according to any one of (1) to (12).
(14)
The PLL is a digital PLL.
The PLL circuit according to any one of (1) to (13).

1 Semiconductor chip 2 Semiconductor chip 3 Solid-state imager 4 PLL circuit 5 Oscillator circuit 6 Divider 7 PLL
8 Monitor unit 9 Correction unit 71 Digital PLL
83 Temperature sensor 91 Calculation unit 92 Calculation unit 93 Calculation unit 94 Calculation unit 95 Storage unit 96 Multiplication unit 97 Multiplication unit 98 Multiplication unit 99 Multiplication unit 100 System Is Current T Monitor temperature V Monitor voltage VDD Power supply Vth Threshold voltage

Claims

An oscillation circuit that operates using the power supply of the semiconductor chip that constitutes the solid-state image sensor,
The PLL controlled by the parameters and
A monitor unit that includes at least the voltage of the power supply as a monitor target,
A correction unit that corrects the parameters based on the monitor result of the monitor unit, and a correction unit.
Equipped with
The PLL generates a PLL clock signal determined based on a reference clock signal obtained from the oscillation clock signal of the oscillation circuit and the parameter corrected by the correction unit.
PLL circuit.
The parameter is a numerical value that specifies the ratio of the frequency of the PLL clock signal to the frequency of the reference clock signal.
The correction unit corrects the numerical value.
The PLL circuit according to claim 1.
The monitor target of the monitor unit includes the temperature of the oscillation circuit.
The PLL circuit according to claim 1.
The correction unit corrects the parameter by using the correction value corresponding to each of the monitoring targets included in the monitor result of the monitor unit.
The PLL circuit according to claim 3.
At least one of the correction values is a correction value in which the dependency between the corresponding monitor target and another monitor target is taken into consideration.
The PLL circuit according to claim 4.
The correction unit refers to a look-up table that describes the dependency.
The PLL circuit according to claim 5.
The monitor unit monitors each of the monitored objects in a time-division manner.
The PLL circuit according to claim 2.
The oscillation circuit is integrated in the semiconductor chip.
The PLL circuit according to claim 1.
The oscillation circuit is either an LC oscillation circuit or an RC oscillation circuit.
The PLL circuit according to claim 8.
The oscillation circuit is configured so that the oscillation frequency can be switched.
The PLL circuit according to claim 1.
The oscillation circuit includes a transistor and includes a transistor.
The monitor target of the monitor unit includes the threshold voltage of the transistor.
The PLL circuit according to claim 1.
The oscillator circuit includes a current source.
The monitor target of the monitor unit includes a current flowing through the current source.
The PLL circuit according to claim 1.
The oscillation circuit includes a resistor and includes a resistor.
The monitor target of the monitor unit includes the resistance value of the resistor.
The PLL circuit according to claim 1.
The PLL is a digital PLL.
The PLL circuit according to claim 1.