WO2021035942A1

WO2021035942A1 - Pixel compensation circuit

Info

Publication number: WO2021035942A1
Application number: PCT/CN2019/115240
Authority: WO
Inventors: 张娣
Original assignee: 武汉华星光电半导体显示技术有限公司
Priority date: 2019-08-27
Filing date: 2019-11-04
Publication date: 2021-03-04
Also published as: CN110634440A; CN110634440B

Abstract

A pixel compensation circuit, comprising a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a fifth thin film transistor (T5), a sixth thin film transistor (T6), a first capacitor (C1), and an organic light emitting diode (OLED). A reset function and an internal threshold voltage compensation function are implemented by a 6T1C pixel compensation circuit.

Description

Pixel compensation circuit

Technical field

The invention relates to the field of pixel circuits of collective tubes, and in particular to a pixel compensation circuit.

Background technique

Display panels, such as Organic Light-Emitting Diode (OLED for short), have attracted great attention from academia and industry because of their huge development potential in the direction of solid-state lighting and flat panel displays. Organic light-emitting diode (OLED) panels can be made lighter and thinner, so flexible display technology will be the future development trend.

OLED has a wide color gamut, high contrast ratio, energy saving, and foldability. It has strong competitiveness in the new generation of displays. AMOLED technology is one of the key development directions for flexible displays. The basic driving circuit of AMOLED is 2T1C, including a driving thin film transistor TFT (T1), a switching thin film transistor TFT (T2) and a storage capacitor Cst. The driving current of the OLED is controlled by the driving thin film transistor TFT, and its current size is: I _OLED =k (V _gs -V _th ) ² ; where k is the current amplification factor of the driving thin film transistor TFT, which is determined by the characteristics of the driving thin film transistor TFT itself , Vth is the threshold voltage of the thin film transistor TFT. Since the threshold voltage (Vth) of the driving thin film transistor TFT easily drifts, the driving current of the OLED changes, which makes the OLED panel defective and affects the image quality.

With the development of display panels, people are pursuing larger screens, higher resolutions, and more exciting visual effects, which undoubtedly puts forward higher requirements on the panel manufacturing process, materials and craftsmanship. In order to achieve a more stable, high-quality and clear display effect, OLED display technology has developed along the way. OLED pixel circuits can compensate for screen unevenness and device differences through internal and external compensation.

technical problem

In the driving circuit of the prior art, the threshold voltage (Vth) of the driving thin film transistor TFT easily drifts, which causes the OLED driving current to fluctuate, which makes the OLED panel defective and affects the image quality.

Technical solutions

In order to solve the above technical problems, the present invention proposes a pixel compensation circuit designed to internally compensate the threshold voltage of an OLED self-luminous device.

A pixel compensation circuit includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor and an organic light emitting diode, wherein,

The source of the first thin film transistor is electrically connected to a first node, the drain of the first thin film transistor is electrically connected to a second node, and the gate of the first thin film transistor is electrically connected to a third node;

The source of the second thin film transistor is electrically connected to the third node, the drain of the second thin film transistor is electrically connected to the first node, and the gate of the second thin film transistor is electrically connected to the third node. Scan signal

The source of the third thin film transistor is electrically connected to the second node, the drain of the third thin film transistor is electrically connected to a data line signal, and the gate of the third thin film transistor is electrically connected to a second scan signal ；

The source of the fourth thin film transistor is electrically connected to the power supply voltage, the drain of the fourth thin film transistor is electrically connected to the first node, and the gate of the fourth thin film transistor is electrically connected to the first control signal;

The source of the fifth thin film transistor is electrically connected to the second node, the drain of the fifth thin film transistor is electrically connected to the anode of the organic light emitting diode, and the gate of the fifth thin film transistor is electrically connected to Second control signal;

The source of the sixth thin film transistor is electrically connected to the first node, the drain of the sixth thin film transistor outputs a reset signal, and the gate of the sixth thin film transistor is electrically connected to the first scan signal;

One end of the first capacitor is electrically connected to the power supply voltage, and the other end of the first capacitor is electrically connected to the third node; and

The anode of the organic light emitting diode is electrically connected to the drain of the fifth thin film transistor, and the cathode of the organic light emitting diode is electrically connected to the negative electrode of a power supply;

The combination of the first scan signal, the second scan signal, the third scan signal, the first control signal, and the second control signal sequentially corresponds to the reset phase, the data writing phase, and the light emitting phase ；

The first to sixth thin film transistors include amorphous indium gallium zinc oxide materials.

According to the pixel compensation circuit provided by the embodiment of the present invention, in the reset phase, the first scan signal is at a low level, the second scan signal is at a high level, and the third scan signal is at a low level , The first control signal is at a high level, and the second control signal is at a low level.

According to the pixel compensation circuit provided by the embodiment of the present invention, in the data writing stage, the first scan signal is at a high level, the second scan signal is at a low level, and the third scan signal is at a low level. Level, the first control signal is at a high level, and the second control signal is at a high level.

According to the pixel compensation circuit provided by the embodiment of the present invention, in the light-emitting phase, the first scan signal is at a high level, the second scan signal is at a high level, and the third scan signal is at a high level , The first control signal is at a low level, and the second control signal is at a low level.

According to the pixel compensation circuit provided by the embodiment of the present invention, in the reset phase, the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned on, and the gate of the first thin film transistor is turned on. The pole position is reset to a reset signal, and the reset signal is lower than the potential of the negative pole of the power supply.

According to the pixel compensation circuit provided by the embodiment of the present invention, in the data writing stage, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off, and the second thin film transistor and the The third thin film transistor is turned on.

According to the pixel compensation circuit provided by the embodiment of the present invention, in the light-emitting phase, the second thin film transistor, the third thin film transistor, and the sixth thin film transistor are turned off, and the fourth thin film transistor and the first thin film transistor are turned off. Five thin film transistors are turned on.

According to the pixel compensation circuit provided by the embodiment of the present invention, the second thin film transistor, the third thin film transistor, and the sixth thin film transistor are dual-channel thin film transistors.

An embodiment of the present invention also provides a pixel compensation circuit, including: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor, and an organic Light-emitting diodes, among them,

The anode of the organic light emitting diode is electrically connected to the drain of the fifth thin film transistor, and the cathode of the organic light emitting diode is electrically connected to the negative electrode of a power supply.

According to the pixel compensation circuit provided by the embodiment of the present invention, the combination of the first scan signal, the second scan signal, the third scan signal, the first control signal, and the second control signal corresponds in sequence In the reset phase, data writing phase and light emitting phase.

According to the pixel compensation circuit provided by the embodiment of the present invention, the first thin film transistor to the sixth thin film transistor comprise amorphous indium gallium zinc oxide material

Beneficial effect

The 6T1C (six thin film transistors and one capacitor) pixel compensation circuit proposed in the embodiment of the present invention realizes the reset function and the function of internally compensating the threshold voltage.

Description of the drawings

FIG. 1 is a diagram of a pixel compensation circuit provided by an embodiment of the present invention.

FIG. 2 is a signal timing diagram of a pixel compensation circuit provided by an embodiment of the present invention.

The best mode of the present invention

The description of the following embodiments refers to the attached drawings to illustrate specific embodiments that the present disclosure can be implemented.

In order to make the above and other objectives, features, and advantages of the present disclosure more obvious and understandable, the following will specifically illustrate the preferred embodiments of the present disclosure, in conjunction with the accompanying drawings, and describe in detail as follows. Furthermore, the directional terms mentioned in this disclosure, such as up, down, top, bottom, front, back, left, right, inside, outside, side layer, surrounding, center, horizontal, horizontal, vertical, vertical, axial , Radial, uppermost or lowermost layers, etc., are only the direction of reference to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present disclosure, rather than to limit the present disclosure.

In the figure, units with similar structures are indicated by the same reference numerals.

FIG. 1 is a diagram of a pixel compensation circuit provided by an embodiment of the present invention. As shown in FIG. 1, the present invention provides a pixel compensation circuit including: a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a second thin film transistor T2. Four thin film transistors T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a first capacitor C1, and an organic light emitting diode OLED, each of the first thin film transistor T1 to the sixth thin film transistor T6 includes a drain , Source and gate, among them,

The source of the first thin film transistor T1 is electrically connected to the first node A, the drain is electrically connected to the second node B, and the gate is electrically connected to the third node C;

The source of the second thin film transistor T2 is electrically connected to the third node C, the drain is electrically connected to the first node A, and the gate is electrically connected to the third scan signal SCAN3;

The source of the third thin film transistor T3 is electrically connected to the second node B, the drain is electrically connected to the data line signal Data, and the gate is electrically connected to the second scan signal SCAN2;

The source of the fourth thin film transistor T4 is electrically connected to the power supply voltage V _DD , the drain is electrically connected to the first node A, and the gate is electrically connected to the first control signal EM1;

The source of the fifth thin film transistor T5 is electrically connected to the second node B, the drain is electrically connected to the anode of the organic light emitting diode OLED, and the gate is electrically connected to the second control signal EM2;

The source of the sixth thin film transistor T6 is electrically connected to the first node A, the drain outputs the reset signal VI, and the gate is electrically connected to the first scan signal SCAN1;

One end of the first capacitor C1 is electrically connected to the power supply voltage V _DD , and the other end is electrically connected to the third node C; and

The anode of the organic light emitting diode OLED is electrically connected to the drain of the fifth thin film transistor T5, and the cathode of the organic light emitting diode OLED is connected to the negative electrode V _SS of the power supply.

In this embodiment, the first thin film transistor T1 is used as a driving transistor, and the second thin film transistor T2 to the sixth thin film transistor T6 are used as switching transistors.

The working principle of the pixel compensation circuit in the embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 2, it is a signal timing diagram of the pixel compensation circuit provided by the embodiment of the present invention. In this embodiment, the combination of the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the first control signal EM1, and the second control signal EM2 sequentially corresponds to A reset stage (I), a data writing stage (II), and a light-emitting stage (III).

In the reset phase (I), as shown in FIG. 2, the first scan signal SCAN1 is at a low level, the second scan signal SCAN2 is at a high level, and the third scan signal SCAN3 is at a low level. Level, the first control signal EM1 is at a high level, and the second control signal EM2 is at a low level.

Further, in the circuit diagram shown in FIG. 1, in the reset phase (I), the first scan signal SCAN1 is at a low level, so that the sixth thin film transistor is turned on; the second scan signal SCAN2 Is high, making the third thin film transistor turn off; the third scan signal SCAN3 is low, making the second thin film transistor turn on; the first control signal EM1 is high, making the The fourth thin film transistor is turned off; the second control signal EM2 is at a low level, so that the fifth thin film transistor is turned on. At this time, the gate point of the first thin film transistor is reset to the reset signal VI, and the anode of the organic light emitting diode OLED is reset to VI+V _th ₍ _T1 ₎ , wherein the reset signal VI must be lower than the negative electrode of the power supply. Potential V _SS .

In the data writing stage (II), as shown in FIG. 2, the first scan signal SCAN1 is at a high level, the second scan signal SCAN2 is at a low level, and the third scan signal SCAN3 is Low level, the first control signal EM1 is high level, and the second control signal EM2 is high level.

Further, in the circuit diagram shown in FIG. 1, in the data writing stage (II), the first scan signal SCAN1 is at a high level, so that the sixth thin film transistor is turned off; the second scan The signal SCAN2 is at a low level, so that the third thin film transistor is turned on; the third scan signal SCAN3 is at a low level, so that the second thin film transistor is turned on; the first control signal EM1 is at a high level, so that The fourth thin film transistor is turned off; the second control signal EM2 is at a high level, so that the fifth thin film transistor is turned off. Subsequently, the data signal Data enters the first thin film transistor through the third thin film transistor, and under the action of the second thin film transistor, the gate of the first thin film transistor writes V _Data —V _th ₍ _T1 ₎ potential, and record the V _{th of} the first thin film transistor.

In the light-emitting stage (III), as shown in FIG. 2, the first scan signal SCAN1 is at a high level, the second scan signal SCAN2 is at a high level, and the third scan signal SCAN3 is at a high level. Level, the first control signal EM1 is at a low level, and the second control signal EM2 is at a low level.

Further, in the circuit diagram shown in FIG. 1, in the light-emitting stage (III), the first scan signal SCAN1 is at a high level, so that the sixth thin film transistor is turned off; the second scan signal SCAN2 Is a high level, so that the third thin film transistor is turned off; the third scan signal SCAN3 is at a high level, so that the second thin film transistor is turned off; and the first control signal EM1 is a low level, so that the The fourth thin film transistor is turned on; the second control signal EM2 is at a low level, so that the fifth thin film transistor is turned on. Therefore, the current flows from the power supply voltage V _DD to the negative electrode V _{SS of the} power supply and passes through the organic light emitting diode OLED device to make it emit light. Wherein, the magnitude of the current is controlled by the first thin film transistor:

I _OLED =k(V _gs —V _th ) ² = k(VDD—(data—V _th )—V _th )

In this embodiment, the first thin film transistor T1 is a driving thin film transistor, the second thin film transistor T2 is responsible for grabbing the V _th −V _T1 of the first thin film transistor T1, and the second thin film transistor T2 Leakage current requirements are relatively strict, and are usually made into dual-channel thin film transistors. The third thin film transistor T3 controls the writing of the data signal Data. In order to reduce the influence of the leakage current of the third thin film transistor T3 on the anode of the organic light emitting diode OLED, the third thin film transistor T3 can also be made into a double channel.道Thin Film Transistor. The fourth thin film transistor T4 controls the writing of _{the power supply voltage V DD signal.} The fifth thin film transistor T5 controls the writing of the anode of the organic light emitting diode OLED, the sixth thin film transistor T6 is a reset thin film transistor, in order to reduce the leakage current of the sixth thin film transistor T6 to the anode of the organic light emitting diode OLED The sixth thin film transistor T6 can also be made into a dual-channel thin film transistor. In this embodiment, the first to sixth thin film transistors are preferably made of amorphous indium gallium zinc oxide materials.

Although the present disclosure has been shown and described with respect to one or more implementation manners, those skilled in the art will think of equivalent variations and modifications based on the reading and understanding of the specification and the accompanying drawings. The present disclosure includes all such modifications and variations, and is limited only by the scope of the appended claims. Especially with regard to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (for example, it is functionally equivalent) , Even if the structure is not equivalent to the disclosed structure that performs the functions in the exemplary implementation of the present specification shown herein. In addition, although a specific feature of this specification has been disclosed with respect to only one of several implementations, this feature can be combined with one or more of other implementations that may be desirable and advantageous for a given or specific application. Other feature combinations. Moreover, as far as the terms "including", "having", "containing" or their variants are used in specific embodiments or claims, such terms are intended to be included in a similar manner to the term "comprising".

The above are only the preferred embodiments of the present disclosure. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present disclosure, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the present disclosure. protected range.

Claims

A pixel compensation circuit includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor and an organic light emitting diode, wherein,

The source of the first thin film transistor is electrically connected to a first node, the drain of the first thin film transistor is electrically connected to a second node, and the gate of the first thin film transistor is electrically connected to a third node;

The source of the second thin film transistor is electrically connected to the third node, the drain of the second thin film transistor is electrically connected to the first node, and the gate of the second thin film transistor is electrically connected to the third node. Scan signal

The source of the third thin film transistor is electrically connected to the second node, the drain of the third thin film transistor is electrically connected to a data line signal, and the gate of the third thin film transistor is electrically connected to a second scan signal ；

The source of the fourth thin film transistor is electrically connected to the power supply voltage, the drain of the fourth thin film transistor is electrically connected to the first node, and the gate of the fourth thin film transistor is electrically connected to the first control signal;

The source of the fifth thin film transistor is electrically connected to the second node, the drain of the fifth thin film transistor is electrically connected to the anode of the organic light emitting diode, and the gate of the fifth thin film transistor is electrically connected to Second control signal;

The source of the sixth thin film transistor is electrically connected to the first node, the drain of the sixth thin film transistor outputs a reset signal, and the gate of the sixth thin film transistor is electrically connected to the first scan signal;

One end of the first capacitor is electrically connected to the power supply voltage, and the other end of the first capacitor is electrically connected to the third node; and

The anode of the organic light emitting diode is electrically connected to the drain of the fifth thin film transistor, and the cathode of the organic light emitting diode is electrically connected to the negative electrode of a power supply;

The combination of the first scan signal, the second scan signal, the third scan signal, the first control signal, and the second control signal sequentially corresponds to the reset phase, the data writing phase, and the light emitting phase ；

The first to sixth thin film transistors include amorphous indium gallium zinc oxide materials.
4. The pixel compensation circuit according to claim 1, wherein in the reset phase, the first scan signal is at a low level, the second scan signal is at a high level, and the third scan signal is at a low level , The first control signal is at a high level, and the second control signal is at a low level.
The pixel compensation circuit according to claim 2, wherein in the data writing stage, the first scan signal is at a high level, the second scan signal is at a low level, and the third scan signal is at a low level. Level, the first control signal is at a high level, and the second control signal is at a high level.
4. The pixel compensation circuit according to claim 3, wherein in the light-emitting phase, the first scan signal is at a high level, the second scan signal is at a high level, and the third scan signal is at a high level , The first control signal is at a low level, and the second control signal is at a low level.
The pixel compensation circuit according to claim 1, wherein in the reset phase, the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned on, and the gate of the first thin film transistor The pole position is reset to a reset signal, and the reset signal is lower than the potential of the negative pole of the power supply.
The pixel compensation circuit according to claim 2, wherein in the data writing stage, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off, and the second thin film transistor and the second thin film transistor are turned off. The third thin film transistor is turned on.
4. The pixel compensation circuit according to claim 3, wherein in the light-emitting phase, the second thin film transistor, the third thin film transistor, and the sixth thin film transistor are turned off, and the fourth thin film transistor and the first thin film transistor are turned off. Five thin film transistors are turned on.
The pixel compensation circuit according to claim 1, wherein the second thin film transistor, the third thin film transistor, and the sixth thin film transistor are dual-channel thin film transistors.
A pixel compensation circuit includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor and an organic light emitting diode, wherein,

The source of the first thin film transistor is electrically connected to a first node, the drain of the first thin film transistor is electrically connected to a second node, and the gate of the first thin film transistor is electrically connected to a third node;

The source of the second thin film transistor is electrically connected to the third node, the drain of the second thin film transistor is electrically connected to the first node, and the gate of the second thin film transistor is electrically connected to the third node. Scan signal

The source of the third thin film transistor is electrically connected to the second node, the drain of the third thin film transistor is electrically connected to a data line signal, and the gate of the third thin film transistor is electrically connected to a second scan signal ；

The source of the fourth thin film transistor is electrically connected to the power supply voltage, the drain of the fourth thin film transistor is electrically connected to the first node, and the gate of the fourth thin film transistor is electrically connected to the first control signal;

The source of the fifth thin film transistor is electrically connected to the second node, the drain of the fifth thin film transistor is electrically connected to the anode of the organic light emitting diode, and the gate of the fifth thin film transistor is electrically connected to Second control signal;

The source of the sixth thin film transistor is electrically connected to the first node, the drain of the sixth thin film transistor outputs a reset signal, and the gate of the sixth thin film transistor is electrically connected to the first scan signal;

One end of the first capacitor is electrically connected to the power supply voltage, and the other end of the first capacitor is electrically connected to the third node; and

The anode of the organic light emitting diode is electrically connected to the drain of the fifth thin film transistor, and the cathode of the organic light emitting diode is electrically connected to the negative electrode of a power supply.
9. The pixel compensation circuit according to claim 9, wherein the combination of the first scan signal, the second scan signal, the third scan signal, the first control signal, and the second control signal corresponds to In the reset phase, data writing phase and light emitting phase.
11. The pixel compensation circuit according to claim 10, wherein in the reset phase, the first scan signal is at a low level, the second scan signal is at a high level, and the third scan signal is at a low level , The first control signal is at a high level, and the second control signal is at a low level.
11. The pixel compensation circuit according to claim 11, wherein in the data writing stage, the first scan signal is at a high level, the second scan signal is at a low level, and the third scan signal is at a low level. Level, the first control signal is at a high level, and the second control signal is at a high level.
11. The pixel compensation circuit according to claim 12, wherein in the light-emitting phase, the first scan signal is at a high level, the second scan signal is at a high level, and the third scan signal is at a high level , The first control signal is at a low level, and the second control signal is at a low level.
11. The pixel compensation circuit according to claim 10, wherein in the reset phase, the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned on, and the gate of the first thin film transistor The pole position is reset to a reset signal, and the reset signal is lower than the potential of the negative pole of the power supply.
11. The pixel compensation circuit according to claim 11, wherein in the data writing phase, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off, and the second thin film transistor and the second thin film transistor are turned off. The third thin film transistor is turned on.
The pixel compensation circuit according to claim 12, wherein in the light-emitting phase, the second thin film transistor, the third thin film transistor, and the sixth thin film transistor are turned off, and the fourth thin film transistor and the first thin film transistor are turned off. Five thin film transistors are turned on.
9. The pixel compensation circuit according to claim 9, wherein the second thin film transistor, the third thin film transistor, and the sixth thin film transistor are dual-channel thin film transistors.
9. The pixel compensation circuit according to claim 9, wherein the first to sixth thin film transistors comprise amorphous indium gallium zinc oxide material.