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WO2020234534A1 - Optoelectronic device comprising light-emitting diodes - Google Patents

Optoelectronic device comprising light-emitting diodes Download PDF

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Publication number
WO2020234534A1
WO2020234534A1 PCT/FR2020/050819 FR2020050819W WO2020234534A1 WO 2020234534 A1 WO2020234534 A1 WO 2020234534A1 FR 2020050819 W FR2020050819 W FR 2020050819W WO 2020234534 A1 WO2020234534 A1 WO 2020234534A1
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WO
WIPO (PCT)
Prior art keywords
light
semiconductor portion
optoelectronic device
emitting diode
chemical element
Prior art date
Application number
PCT/FR2020/050819
Other languages
French (fr)
Inventor
Ivan-Christophe Robin
Wei-Sin Tan
Frédéric Mayer
Original Assignee
Aledia
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aledia filed Critical Aledia
Priority to CN202080036339.0A priority Critical patent/CN113875012A/en
Priority to KR1020217037465A priority patent/KR20220010495A/en
Priority to JP2021568396A priority patent/JP7555128B2/en
Priority to US17/609,357 priority patent/US20220320367A1/en
Priority to EP20737244.2A priority patent/EP3973574A1/en
Publication of WO2020234534A1 publication Critical patent/WO2020234534A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
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    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
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    • H01L33/0004—Devices characterised by their operation
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    • H01L33/0025—Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds
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    • H01L33/0041—Devices characterised by their operation characterised by field-effect operation
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    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
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    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0083—Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
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    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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    • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region

Definitions

  • the present application relates to an opto-electronic device, in particular a display screen or an image projection device, comprising light-emitting diodes, based on semiconductor materials, and their manufacturing processes.
  • a pixel of an image corresponds to the unitary element of the image displayed by the optoelectronic device.
  • the optoelectronic device is a color image display screen, it generally comprises for the display of each pixel of the image at least three components, also called display sub-pixels, which each emit light radiation. substantially in one color (eg, red, green, and blue). The superposition of the radiations emitted by these three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image.
  • the display pixel of the optoelectronic device is called the set formed by the three display sub-pixels used for displaying one pixel of an image.
  • Each display subpixel can include at least one light emitting diode.
  • an object of an embodiment is to at least partially overcome the drawbacks of optoelectronic devices comprising light-emitting diodes described above.
  • Another object of an embodiment is to reduce, or even eliminate, the use of phosphors.
  • Another object of an embodiment is to be able to produce simultaneously by common steps several light-emitting diodes suitable for emitting electromagnetic radiation at different wavelengths.
  • Another object of an embodiment is that the optoelectronic devices can be manufactured on an industrial scale and at low cost.
  • an optoelectronic device comprising at least first and second light-emitting diodes each comprising a first P-type doped semiconductor portion and a second N-type doped semiconductor portion, an active area comprising wells multiple quantum between the first and second semiconductor portions, a conductive layer covering the side walls of the active area and at least part of the first semiconductor portion and an insulating layer interposed between the side walls of the active area and at least part of the conductive layer, the device comprising means for controlling the conductive layer of the first light-emitting diode independently of the conductive layer of the second light-emitting diode, the optoelectronic device comprising, for each of the first and second light-emitting diodes, a first conductive pad electrically coupled to the first semiconductor portion, a second conductive pad electrically coupled to the second semiconductor portion, and a third conductive pad electrically coupled to the conductive layer.
  • the active area comprises multiple quantum wells.
  • the composition of the quantum well closest to the first semiconductor portion is different from the composition of the quantum well closest to the second semiconductor portion.
  • each quantum well comprises a ternary compound with first, second and third chemical elements.
  • the mass concentrations of the first chemical element in quantum wells are identical.
  • the mass concentrations of the second chemical element of quantum wells are the same, and the mass concentration of the third chemical element of the quantum well closest to the first semiconductor portion is different from the mass concentration of the third chemical element of the quantum well closest to the second semiconductor portion.
  • the difference between the mass concentration of the third chemical element of the quantum well closest to the first semiconductor portion and the mass concentration of the third chemical element of the quantum well closest to the second semiconductor portion is greater than 10 percentage points.
  • the first chemical element is an element from group III.
  • the first chemical element is gallium.
  • the second chemical element is an element of group V.
  • the second chemical element is nitrogen.
  • the third chemical element is an element from group III. [0020] According to one embodiment, the third chemical element is indium.
  • each light-emitting diode has a "mesa" structure.
  • the second semiconductor portion is in the form of a wire.
  • each light-emitting diode further comprises, between the active area and the first semiconductor portion, an electron blocking layer.
  • the first and second conductive pads are electrically insulated from the conductive layer.
  • One embodiment also provides for a method of emitting light from an optoelectronic device as defined above, comprising the application of a first electrical voltage between the first and second semiconductor portions of each of the first and second light emitting diodes, applying a second electrical voltage between the conductive layer and the first semiconductor portion of the first light emitting diode, and applying a third electrical voltage between the conductive layer and the first semiconductor portion of the second diode electroluminescent, the third electric voltage being different from the second electric voltage.
  • FIG. 1 represents an embodiment of an optoelectronic device comprising light emitting diodes
  • FIG. 2 represents another embodiment of an optoelectronic device
  • FIG. 3 represents another embodiment of an optoelectronic device
  • FIG. 4 represents an embodiment of a light emitting diode used to carry out simulations
  • FIG. 5 represents curves of the evolution of the internal quantum efficiency of the light-emitting diode of FIG. 4 as a function of the surface density of the current passing through the light-emitting diode;
  • FIG. 6 represents curves of the evolution of the energy conversion efficiency of the light-emitting diode of FIG. 4 as a function of the surface density of the current passing through the light-emitting diode;
  • FIG. 7 represents the curves of the evolution of the surface density of the current passing through the light-emitting diode of FIG. 4 as a function of the anode-cathode voltage applied to the light-emitting diode;
  • FIG. 8 represents curves for the evolution of the rate of radiative recombinations in the active zone of the light-emitting diode of FIG. 4;
  • FIG. 9 represents curves of the evolution of the valence band energy in the active zone of the light-emitting diode of FIG. 4;
  • FIG. 10 represents a curve of the evolution of the concentration of holes in the active zone of the light-emitting diode of FIG. 4;
  • FIG. 11 represents an evolution curve of the rate of radiative recombinations in the active zone of the light-emitting diode of FIG. 4;
  • Figure 12 is similar to Figure 10;
  • Figure 13 is similar to Figure 11;
  • FIG. 14 illustrates a step of an embodiment of a method of manufacturing the optoelectronic device of FIG. 1;
  • FIG. 15 illustrates another step of the method
  • FIG. 16 illustrates another step of the method
  • FIG. 17 illustrates another step of the method
  • FIG. 18 illustrates another step of the method
  • FIG. 19 illustrates another step of the method
  • FIG. 20 illustrates another step of the method
  • FIG. 21 illustrates a step of an embodiment of a method of manufacturing the optoelectronic device of FIG. 2;
  • FIG. 22 illustrates another step of the method
  • FIG. 23 illustrates another step of the method
  • FIG. 24 illustrates another step of the method
  • FIG. 25 illustrates another step of the method
  • FIG. 26 illustrates another step of the method
  • FIG. 27 illustrates another step of the method
  • FIG. 28 illustrates another step of the method
  • FIG. 29 illustrates a step of an embodiment of a method of manufacturing the optoelectronic device of FIG. 3;
  • FIG. 30 illustrates another step of the method
  • FIG. 31 illustrates another step of the method
  • FIG. 32 illustrates another step of the method
  • FIG. 33 illustrates another step of the method
  • FIG. 34 illustrates another step of the method
  • FIG. 35 illustrates another step of the method
  • FIG. 36 illustrates another step of the method.
  • insulator and “conductor” mean respectively “electrically insulating” and “electrically conductive”.
  • FIG. 1 is a sectional view, partial and schematic, of an embodiment of an optoelectronic device 10 adapted to the emission of light.
  • the optoelectronic device 10 comprises at least two electronic circuits 12 and 14.
  • the first circuit 12 comprises light emitting diodes LEDs.
  • the second circuit 14 comprises electronic components, not shown, in particular transistors, used for controlling the light-emitting diodes of the first circuit 12.
  • the first circuit 12 is fixed to the second circuit 14, for example by molecular bonding or by a connection of the "type”.
  • Flip-Chip ", in particular a" Flip-Chip process by balls or by microtubes.
  • the first circuit 12 is called an optoelectronic circuit in the remainder of the description and the second circuit 14 can be an integrated circuit and is called a control circuit or control chip in the remainder of the description.
  • the optoelectronic device 10 is intended, in operation, to emit light upwards.
  • the optoelectronic circuit 12 comprises, from top to bottom in FIG. 1:
  • a substrate 16 for example an insulating substrate, at least partially transparent to the electromagnetic radiation emitted by the light-emitting diodes and which delimits an emission face 18 of the optoelectronic device 10, the substrate 16 possibly not being present;
  • trenches d side insulation 22 which extend over the entire thickness of the semiconductor layer 20 and which delimit portions of substrate 24 in the semiconductor layer 20, three portions of substrate 24 being shown in FIG. 1, the trenches d side insulation 22 may not be present;
  • each light-emitting diode LED comprising an upper semiconductor portion 26 in contact with the corresponding substrate portion 24, an active area 28, and a lower semiconductor portion 30, the active area 28 being interposed between the upper semiconductor portion 26 and the lower semiconductor portion 30, the lower semiconductor portion 30 comprising a lower face 32 on the side opposite to the active zone 28, the stack comprising the upper semiconductor portion 26, the active zone 28 and the lower semiconductor portion 30 forming an island delimited by side walls 34 and the lower face 32;
  • an insulating layer 36 covering the portion of substrate 24 around the light-emitting diode LED and covering the side walls 34 of the light-emitting diode LED;
  • a conductive layer 38 for each light-emitting diode LED, a conductive layer 38, called the gate hereafter, covering the insulating layer 36;
  • an insulating layer 40 covering the gate 38 and part of the lower face 32 of the lower semiconductor portion 30, the insulating layer 40 possibly not being present;
  • a first conductive pad 42 in contact with the corresponding substrate portion 24, a second conductive pad 44 in contact with the lower face 32 of the lower semiconductor portion 30 and a third conductive pad 46 in contact with the grid 38.
  • the control chip 14 comprises, on the side of the optoelectronic circuit 12, for each light-emitting diode LED, three conductive pads 48, 50, 52, the conductive pad
  • the conductive pads 48, 50, 52 may be in contact with the conductive pads 42, 44,
  • each light emitting diode LED is said to be of the "mesa” type, that is to say it comprises a stack of flat layers which has been etched to form an island.
  • FIG. 2 is a sectional view, partial and schematic, of another embodiment of an optoelectronic device 55 adapted to the emission of light.
  • the optoelectronic device 55 comprises all the elements of the optoelectronic device 10 shown in FIG. 1, with the difference that the substrate 16 is not present and each light-emitting diode LED is of the axial type, that is to say that the semiconductor portions lower and upper 26 and 30 were made in the form of wires.
  • two light-emitting diodes LEDs have been shown for each portion of substrate 24, the associated conductive pad 44 being connected to the lower semiconductor portions 30 of each of the two light-emitting diodes DEL.
  • FIG. 3 is a sectional view, partial and schematic, of another embodiment of an optoelectronic device 60 adapted to the emission of light.
  • the optoelectronic device 60 comprises all the elements of the optoelectronic device 10 shown in FIG. 1, with the difference that the substrate 16 and the semiconductor layer 20 are not present.
  • the light emitting diodes LEDs are divided into groups of at least two light emitting diodes LEDs, and, for each light emitting diode LED, the upper semiconductor portion 26 has a wire shape, the active area 28 has at least partially a conical shape or frustoconical which widens out from the upper semiconductor portion 26, and the lower semiconductor portion 30 is common for the light emitting diodes LEDs of the same group.
  • the conductive pad 42 is electrically connected to the upper semiconductor portion 26 by a conductive element 61.
  • the active zone 28 is the layer from which is emitted the majority of the electromagnetic radiation supplied by the optoelectronic circuit 12.
  • the active zone 28 comprises multiple quantum wells. It then comprises an alternation of first semiconductor layers 62, called quantum well layers, and of second semiconductor layers 64, called barrier layers, each quantum well layer 62 being made of a semiconductor material having a forbidden band less than that of the material forming the upper and lower portions 26, 30.
  • III-V compounds for example a III-N compound, II-VI compounds or semiconductors or compounds of group IV.
  • Group III elements include gallium (Ga), indium (In) or aluminum (Al).
  • III-N compounds are GaN, AIN, InN, InGaN, AlGaN or AlInGaN.
  • Other elements of group V can also be used, for example, phosphorus or arsenic.
  • Group II elements include Group IIA elements including beryllium (Be) and magnesium (Mg) and Group IIB elements including zinc (Zn), cadmium (Cd) and mercury ( Hg).
  • Group VI elements include elements of Group VIA, including oxygen (O) and tellurium (Te).
  • Examples of compounds II-VI are ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe or HgTe.
  • Examples of materials group IV semiconductors are silicon (Si), carbon (C), germanium (Ge), silicon carbide alloys (SiC), silicon-germanium alloys (SiGe) or germanium carbide alloys (GeC) ).
  • the semiconductor layers and portions 20, 26, 30, 62, 64 may include a dopant.
  • the dopant can be chosen from the group comprising a dopant of type P from group II, for example magnesium (Mg), zinc (Zn), cadmium (Cd) or mercury (Hg), a type P dopant of group IV, for example carbon (C), or a type N dopant of group IV, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn).
  • a dopant of type P from group II for example magnesium (Mg), zinc (Zn), cadmium (Cd) or mercury (Hg)
  • a type P dopant of group IV for example carbon (C)
  • a type N dopant of group IV for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn).
  • Each barrier layer 64 can be in the same material as that of the upper and lower portions 26, 30, in particular not intentionally doped.
  • each quantum well layer 62 comprises the same III-V or II-VI compound as that forming the upper and lower portions 26, 30 and further comprises an additional element.
  • each quantum well layer 64 can be of InGaN with a mass concentration of In of between 10% and 30%.
  • the thickness of each quantum well layer 62 can be between 3 nm and 10 nm.
  • the thickness of each barrier layer 64 can be between 3 nm and 50 nm.
  • the mass concentration of the additional element in the quantum well layer 64 closest to the upper semiconductor portion 26 is different from the mass concentration of the additional element in the quantum well layer. 64 closest to the lower semiconductor portion 30. According to one embodiment, the difference between the mass concentration of the additional element in the quantum well layer 64 closest to the upper semiconductor portion 26 and the mass concentration of the additional element in the quantum well layer 64 closest to the lower semiconductor portion 30 is greater to 10 percentage points.
  • the upper semiconductor portion 26 consists mainly of a III-N compound, for example gallium nitride, doped with a first type of conductivity, for example of type N.
  • the dopant of type N can be silicon.
  • the concentration of dopants in the upper semiconductor portion 26 may be between 10 17 atoms / cm 3 and 5 * 10 20 atoms / cm 3 .
  • the lower semiconductor portion 30 is, for example, at least partially produced in a III-N compound, for example gallium nitride.
  • the portion 30 can be doped with the second type of conductivity, for example of type P.
  • the concentration of dopants in the lower semiconductor portion 30 can be between 10 17 atoms / cm 3 and 5 * 10 20 atoms / cm 3 .
  • the lower semiconductor portion 30 may comprise a stack of at least two semiconductor layers 30 of the same material with different dopant mass concentrations, the layer furthest from the active zone 28 being the most doped.
  • Each optoelectronic device 10, 55, 60 may further comprise an electron blocking layer 66 interposed between the active area 28 and the P-type doped semiconductor portion 30, preferably in contact with the active area 28 and the P-type doped semiconductor portion 30
  • the electron blocking layer 66 ensures a good distribution of the electric carriers in the active zone 28 and reduces the diffusion of electrons towards the P-type doped semiconductor portion 30.
  • the blocking layer electron 66 may be formed from a ternary alloy, for example gallium aluminum nitride (AlGaN) or indium aluminum nitride (AlInN).
  • the thickness of the electron blocking layer 66 may be of the order of 20 nm
  • the conductive layer 38 preferably corresponds to a metal layer, for example made of aluminum, silver, copper, titanium, titanium nitride or zinc.
  • the material forming the conductive layer 38 may be a conductive material and at least partially transparent to the radiation emitted by the light-emitting diode LED such as indium tin oxide (or ITO, acronym for Indium Tin Oxide), from l zinc oxide doped or not with aluminum or gallium, or graphene.
  • the thickness of the conductive layer 38 can be between 0.5 ⁇ m and 10 ⁇ m
  • Each insulating layer 36, 40 can be made of a dielectric material, for example of silicon oxide (SZO 2) , of silicon nitride (Si x N y , where x is approximately equal to 3 and y is approximately equal to 4, for example Si 3 N 4) , in silicon oxynitride (SiO x N y where x can be approximately equal to 1/2 and y can be approximately equal to 1, for example Si 2 0N 2) , in oxide aluminum (AI 2 O 3) , or hafnium oxide (Hf0 2)
  • the minimum thickness of the insulating layer 36 in the parts where it covers the side walls 34 of the light emitting diodes LEDs can be between 1 nm and 10 ym.
  • the insulating layer 40 can be made of an organic material.
  • the insulating layer 36 is a silicone polymer, an epoxy polymer, an acrylic polymer or a polycarbonate, a white resin, a black resin or a transparent resin loaded, in particular with titanium oxide particles.
  • Each conductive pad 42, 44, 46, 48, 50, 52 can be at least in part made of a material chosen from the group comprising copper, titanium, tantalum, tungsten or their associated nitrides, nickel, gold, tin, aluminum and the alloys of at least two of these compounds.
  • At least some of the light-emitting diodes LEDs can be covered with a photoluminescent layer comprising suitable phosphors, when they are excited by the light emitted by the associated light-emitting diode LED, to emit light at a wavelength different from the wavelength of the light emitted by the associated light-emitting diode LED.
  • a photoluminescent layer comprising suitable phosphors, when they are excited by the light emitted by the associated light-emitting diode LED, to emit light at a wavelength different from the wavelength of the light emitted by the associated light-emitting diode LED.
  • no light emitting diode LED is covered with a photoluminescent layer.
  • each upper semiconductor portion 26 and optionally each lower semiconductor portion 30 has an elongated shape, for example cylindrical, conical or frustoconical, in a preferred direction including at least two dimensions , called minor dimensions, are between 5 nm and 2.5 ym, preferably between 50 nm and 2.5 ym, the third dimension, called major dimension, being greater than or equal to 1 time, preferably greater than or equal to 5 times and even more preferably greater than or equal to 10 times, the greater of the minor dimensions.
  • the minor dimensions may be less than or equal to about 1 ⁇ m, preferably between 100 nm and 1 ⁇ m, more preferably between 100 nm and 800 nm.
  • each semiconductor portion 26 may be greater than or equal to 500 nm, preferably between 1 ⁇ m and 20 ⁇ m.
  • the base of the upper semiconductor portion 26 has, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal.
  • the semiconductor portions 26 and 30 of the light-emitting diode LED were cylinders with a circular base with a radius equal to 5 ⁇ m.
  • the upper semiconductor portion 26 and the semiconductor layer 20 were made of N-type doped GaN with a dopant concentration equal to 10 19 atoms / cm 3 .
  • the lower semiconductor portion 30 was made of P-type doped GaN with a dopant concentration equal to 10 19 atoms / cm 3 .
  • the active area 28 comprised multiple quantum wells comprising an alternation of layers 62 of InGaN, each having a mass indium concentration of 16% and a thickness equal to 3 nm, and layers 64 of GaN, unintentionally doped, each having a thickness equal to 10 nm.
  • the active zone 28 comprised five layers 62 of InGaN and six layers 64 of GaN, the layer of the active zone 28 closest to the lower semiconductor portion 30 and the layer of the active zone 28 closest to the upper semiconductor portion 26 being one of the barrier layers 64.
  • the light emitting diode LED further comprised an electron blocking layer 66 made of AlGaN with a mass concentration of aluminum equal to 20%, having a thickness equal to 20 nm and located between the portion lower semiconductor 30 and the active zone 28.
  • the insulating layer 36 when it was present in the simulations, was made of Si0 2 and had a thickness of 3 nm.
  • the cathode C of the light emitting diode DEL was simulated by a first constant potential taken equal to 0 V applied to the face 32 of the lower semiconductor portion 30.
  • the anode A of the light-emitting diode LED was simulated by a second constant potential which, unless otherwise specified, was equal to 2.5 V and which was applied to a wall of the substrate portion 24.
  • the gate 38 when present in the simulations, was simulated by a third controllable potential applied to the insulating layer 36 on the side opposite to the side wall 34. For simulations in which the gate 38 is not present, the layer insulator 36 is considered to have infinite thickness.
  • a donor-type trap is electrically positive until it has trapped an electron and is electrically neutral when it has trapped an electron. electron.
  • An acceptor-type trap is electrically neutral as long as it has not trapped an electron and exhibits a negative charge when it has trapped an electron.
  • the surface density of the traps was 10 17 atoms / cm 2
  • the average duration of recombination of the trap was 10 -11 s and the energy of the trap was equal to half of l energy from quantum wells.
  • FIG. 5 represents evolution curves C1 to C6 of the internal quantum efficiency IQE of the active zone 28 of the light-emitting diode LED, as shown in FIG. 4, as a function of the surface density of the current of power supply I supplied to the anode A and expressed in A / cm 2 on a logarithmic scale.
  • Internal quantum efficiency IQE is equal to the ratio between the number of photons created in the active zone 28 and the number of electrons crossing the active zone 28.
  • the internal quantum efficiency is a number without unit which varies between 0 and 1.
  • FIG. 6 represents the evolution curves DI to D6 of the energy conversion efficiency WPE (acronym for Wall Plug Efficiency) of the light-emitting diode LED, as shown in FIG. 4, as a function of the surface density of the supply current I supplied to the anode A and expressed in A / cm 2 on a logarithmic scale
  • the energy conversion efficiency WPE is equal to the ratio between the optical power supplied by the light emitting diode and the power power consumed by the light emitting diode.
  • the energy conversion efficiency WPE takes into account the efficiency of extracting light from the light-emitting diode LED, the efficiency of electric injection and the loss of energy between the incident electron and the photon created.
  • the curves C1 and DI were obtained without a grid and without traps.
  • the curves C2 and D2 were obtained without a grid and with traps of the donor type.
  • Curves C3 and D3 were obtained without a grid and with acceptor type traps.
  • Curves C4 and D4 were obtained without a grid and with acceptor type traps and donor type traps.
  • Curves C5 and D5 were obtained without traps and with the grid maintained at -2 V.
  • Curves C6 and D6 were obtained with traps of the donor type and with the grid maintained at -2 V.
  • Curves C7 and D7 have were obtained with acceptor type traps and with the grid maintained at -2 V.
  • each evolution curve C1 to C7 passes through a maximum before decreasing. Applying a negative voltage to the grid allows, in in the case where donor type traps are present, to increase the maximum value of the IQE and makes it possible, in the case where acceptor type traps are present, to keep the maximum value of the IQE and to postpone the decrease in the IQE.
  • FIG. 7 represents evolution curves E1 and E2 of the surface density of current I, expressed in A / cm 2 according to a logarithmic scale, crossing the light-emitting diode as a function of the anode-cathode voltage VAC applied to the light-emitting diode LED.
  • Curve E1 was obtained without traps and without grid.
  • Curve E2 was obtained without traps and with the gate held at -2 V.
  • the threshold voltage of the light emitting diode when the gate is set to -2 V is lower than the threshold voltage of the light emitting diode without gate. Therefore, when the anode-cathode voltage is constant, the intensity of the current flowing through the light-emitting diode and therefore the light power emitted by the light-emitting diode can be controlled by the voltage applied to the grid 38.
  • the optoelectronic device 10, 55, 60 comprises light-emitting diodes LEDs to which a substantially constant anode-cathode voltage is applied, and the extinction or ignition of each of these light-emitting diodes and / or the control of the light power emitted by each of these light-emitting diodes is carried out by controlling the voltage applied to the gate 38 of each of these light-emitting diodes.
  • the voltage applied to the grid 38, which is to be modulated, is advantageously less than the anode-cathode voltage.
  • FIG. 8 represents, as a function of the position, of the evolution curves F1 to F4 of the radiative recombination rate TRR in the layers 62, 64 of the active zone 28 of the light emitting diode LED, only the four quantum well layers 62 closest to the upper semiconductor portion 26 of N-type doped GaN being shown, the leftmost quantum well layer 62 in FIG. 8 being the closest to the upper semiconductor portion 26 of N-type doped GaN.
  • Curves F1 to F4 were obtained without traps and with an anode-cathode voltage of 2.5 V. Curve F1 was obtained with a gate voltage of 1 V. curve F2 was obtained with a gate voltage of 0 V. Curve F3 was obtained with a gate voltage of -1 V. Curve F4 was obtained with a gate voltage of -2 V. It appears that the InGaN layer 62 closest to the upper semiconductor portion 26 of N-type doped GaN is activated when the gate voltage decreases.
  • FIG. 9 represents evolution curves G1, G2, G3 and G4 of the energy of the valence band BV in the layers 62 and 64 of the active zone 28, in the electron blocking layer 66 and in the upper semiconductor portion 30 of the light-emitting diode DEL obtained under the same conditions respectively as the curves F1, F2, F3 and F4.
  • the application of a negative voltage to the gate 38 causes a decrease in the potential barrier seen by the holes coming from the lower semiconductor portion 30 of P-type doped GaN.
  • FIG. 10 represents an evolution curve H of the concentration of CH holes, expressed in holes / cm 3 on a logarithmic scale, in the layers 62, 64 of the active zone 28 of the light-emitting diode DEL.
  • Curve H was obtained without traps, with an anode-cathode voltage of 2.5 V and without a grid.
  • the concentration of holes decreases as one moves away from the semiconductor portion 30 of P-type doped GaN.
  • FIG. 11 represents an evolution curve J of the rate of radiative recombination TRR, expressed in number of occurrences / cm 3 , in the layers 62, 64 of the active zone.
  • Curve H was obtained without traps, with an anode-cathode voltage of 2.5 V and without a grid. As shown in this figure, in the absence of a gate, only the quantum well 62 closest to the semiconductor portion 30 of P-type doped GaN is activated.
  • FIG. 12 represents an evolution curve K of the concentration of holes, expressed in holes / cm 3 on a logarithmic scale, in the layers 62, 64 of the active zone 28 of the light-emitting diode LED.
  • the K curve was obtained without traps, with an anode-cathode voltage of 2.5 V and with a gate voltage of -2 V.
  • the hole concentration increases as one moves away from the semiconductor portion 30 of P-type doped GaN.
  • FIG. 13 represents an evolution curve L of the radiative recombination rate TRR, expressed in number of occurrences / cm 3 , in the layers 62, 64 of the active zone.
  • Curve H was obtained without traps, with an anode-cathode voltage of 2.5 V and with a gate voltage of -2 V. As shown in this figure, in the presence of the gate 38 to which a voltage is applied. of -2 V, substantially only the quantum well 62 closest to the semiconductor portion 30 of P-type doped GaN is activated.
  • FIGS. 10 to 13 illustrate the fact that the quantum well or the activated quantum wells can be selected by controlling the voltage applied to the gate 38.
  • at least two wells quantum cells of each light-emitting diode LED are adapted to emit electromagnetic radiation at different wavelengths, for example the quantum well closest to the semiconductor portion 26 and the quantum well closest to the semiconductor portion 30. This means that 'at least a first quantum well of each light emitting diode LED is adapted to emit a first electromagnetic radiation at a first wavelength and a second quantum well of each light emitting diode LED is adapted to emit a second electromagnetic radiation at a second length of wave different from the first wavelength.
  • the quantum wells are in InGaN, this can be obtained by forming these quantum wells with different mass concentrations of indium.
  • the gate voltage of the first light emitting diode can be controlled to activate substantially only the first quantum well and, for a second light emitting diode, the gate voltage of the second light emitting diode can be controlled to activate substantially only the second quantum well. In this way, two light-emitting diodes of the same structure are obtained which emit electromagnetic radiation at different wavelengths.
  • Figures 14 to 21 are sectional views, partial and schematic, of structures obtained in successive steps of an embodiment of a method of manufacturing the optoelectronic device 10 shown in Figure 1.
  • the method comprises the following steps:
  • the conductive layer 38 covering the insulating layer 36 that is to say covering the semiconductor layer 20 and the side walls 34 of the island and not covering the face 32 of the island, and formation of the insulating layer 40 covering the conductive layer 38 and the face 32 of each light-emitting diode LED (figure 17)
  • the method can comprise subsequent steps of removing the support 16 and cutting to delimit the optoelectronic devices 10.
  • FIGS. 21 to 28 are partial and schematic sectional views of structures obtained in successive steps of an embodiment of a method of manufacturing the optoelectronic device 55 shown in FIG. 2. The method comprises the following steps:
  • Figures 29 to 36 are sectional views, partial and schematic, of structures obtained in successive steps of an embodiment of a method of manufacturing the optoelectronic device 60 shown in Figure 3.
  • the method comprises the following steps:
  • the assembly comprising a gate 38 and the insulating layer 36 can be replaced by one or more metal portions forming one or more Schottky contacts with the materials of the quantum wells.
  • the metallic portion or portions are in direct contact with the semiconductor materials of the quantum wells, without any insulation material placed between the semiconductor materials and the metallic material.
  • the metal used is preferably chosen from metals exhibiting a work of important output, such as for example tungsten whose work output is equal to about 6.1 eV, or platinum.
  • the choice of metal used to form such Schottky contacts depends in particular on the semiconductor materials used.

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Abstract

The present invention concerns an optoelectronic device (10) comprising at least first and second light-emitting diodes (DEL) each comprising a first, p-type semiconductor portion (30) and a second, n-type semiconductor portion (26), an active region (28) comprising multiple quantum wells between the first and second semiconductor portions, a conductive layer (38) covering the side walls (34) of the active region (28) and at least a part of the first semiconductor portion and an insulating layer (36) inserted between the side walls (34) of the active region (28) and at least a part of the conductive layer. The device comprises means for controlling the conductive layer of the first light-emitting diode independently of the conductive layer of the second light-emitting diode.

Description

DESCRIPTION DESCRIPTION
Dispositif optoélectronique à diodes électroluminescentesLight-emitting diode optoelectronic device
La présente demande de brevet revendique la priorité de la demande de brevet français FR19/05332 qui sera considérée comme faisant partie intégrante de la présente description.The present patent application claims the priority of the French patent application FR19 / 05332 which will be considered as forming an integral part of the present description.
Domaine technique Technical area
[0001] La présente demande concerne un dispositif opto électronique, notamment un écran d'affichage ou un dispositif de projection d'images, comprenant des diodes électroluminescentes, à base de matériaux semiconducteurs, et leurs procédés de fabrication. The present application relates to an opto-electronic device, in particular a display screen or an image projection device, comprising light-emitting diodes, based on semiconductor materials, and their manufacturing processes.
Technique antérieure Prior art
[0002] Un pixel d'une image correspond à l'élément unitaire de l'image affichée par le dispositif optoélectronique. Lorsque le dispositif optoélectronique est un écran d'affichage d'images couleur, il comprend en général pour l'affichage de chaque pixel de l'image au moins trois composants, également appelés sous-pixels d'affichage, qui émettent chacun un rayonnement lumineux sensiblement dans une seule couleur (par exemple, le rouge, le vert et le bleu) . La superposition des rayonnements émis par ces trois sous-pixels d'affichage fournit à l'observateur la sensation colorée correspondant au pixel de l'image affichée. Dans ce cas, on appelle pixel d'affichage du dispositif optoélectronique l'ensemble formé par les trois sous-pixels d'affichage utilisés pour l'affichage d'un pixel d'une image. Chaque sous- pixel d'affichage peut comprendre au moins une diode électroluminescente . A pixel of an image corresponds to the unitary element of the image displayed by the optoelectronic device. When the optoelectronic device is a color image display screen, it generally comprises for the display of each pixel of the image at least three components, also called display sub-pixels, which each emit light radiation. substantially in one color (eg, red, green, and blue). The superposition of the radiations emitted by these three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the display pixel of the optoelectronic device is called the set formed by the three display sub-pixels used for displaying one pixel of an image. Each display subpixel can include at least one light emitting diode.
[0003] Il peut être avantageux de réaliser simultanément plusieurs diodes électroluminescentes par des mêmes étapes d'un même procédé de fabrication, notamment pour des raisons de coûts. Les zones actives des diodes électroluminescentes vont alors émettre un rayonnement électromagnétique à la même longueur d'onde. Pour obtenir des sous-pixels d'affichage émettant des rayonnements électromagnétiques à des longueurs d'ondes différentes, une possibilité est de recouvrir certaines diodes électroluminescentes d'une couche de luminophores adaptés à convertir le rayonnement électromagnétique émis par la diode électroluminescente en un rayonnement électromagnétique à une longueur d'onde différente. Toutefois, il peut être difficile d'obtenir les couleurs souhaitées avec précision. En outre, le coût des luminophores peut être élevé. [0003] It may be advantageous to simultaneously produce several light-emitting diodes by the same steps of the same manufacturing process, in particular for reasons of cost. Active areas of light emitting diodes will then emit electromagnetic radiation at the same wavelength. To obtain display subpixels emitting electromagnetic radiation at different wavelengths, one possibility is to cover certain light emitting diodes with a layer of phosphors suitable for converting the electromagnetic radiation emitted by the light emitting diode into electromagnetic radiation. at a different wavelength. However, it can be difficult to get the desired colors precisely. In addition, the cost of phosphors can be high.
[0004] Il existe donc un besoin d'un dispositif optoélectronique à diodes électroluminescentes comprenant des sous-pixels d'affichage émettant des rayonnements électromagnétiques à des longueurs d'ondes différentes dans lequel l'utilisation de luminophores est réduite voire supprimée . [0004] There is therefore a need for an optoelectronic device with light-emitting diodes comprising display sub-pixels emitting electromagnetic radiation at different wavelengths in which the use of phosphors is reduced or even eliminated.
[0005] Par ailleurs, pour certaines applications, il existe un besoin de commander l'allumage et l'extinction d'une diode électroluminescente sans modifier la tension appliquée entre les électrodes de la diode électroluminescente. [0005] Furthermore, for certain applications, there is a need to control the switching on and off of a light-emitting diode without modifying the voltage applied between the electrodes of the light-emitting diode.
Résumé de 1 ' invention Summary of the invention
[0006] Ainsi, un objet d'un mode de réalisation est de pallier au moins en partie les inconvénients des dispositifs optoélectroniques comprenant des diodes électroluminescentes décrits précédemment. [0006] Thus, an object of an embodiment is to at least partially overcome the drawbacks of optoelectronic devices comprising light-emitting diodes described above.
[0007] Un autre objet d'un mode de réalisation est de réduire, voire de supprimer, l'utilisation de luminophores. [0007] Another object of an embodiment is to reduce, or even eliminate, the use of phosphors.
[0008] Un autre objet d'un mode de réalisation est de pouvoir réaliser simultanément par des étapes communes plusieurs diodes électroluminescentes adaptées à émettre des rayonnements électromagnétiques à des longueurs d'ondes différentes . Another object of an embodiment is to be able to produce simultaneously by common steps several light-emitting diodes suitable for emitting electromagnetic radiation at different wavelengths.
[0009] Un autre objet d'un mode de réalisation est que les dispositifs optoélectroniques puissent être fabriqués à une échelle industrielle et à bas coût. [0009] Another object of an embodiment is that the optoelectronic devices can be manufactured on an industrial scale and at low cost.
[0010] Dans ce but, un mode de réalisation prévoit un dispositif optoélectronique comprenant au moins des première et deuxième diodes électroluminescentes comprenant chacune une première portion semiconductrice dopée de type P et une deuxième portion semiconductrice dopée de type N, une zone active comprenant des puits quantiques multiples entre les première et deuxième portions semiconductrices , une couche conductrice recouvrant les parois latérales de la zone active et d'au moins d'une partie de la première portion semiconductrice et une couche isolante interposée entre les parois latérales de la zone active et au moins une partie de la couche conductrice, le dispositif comprenant des moyens de commande de la couche conductrice de la première diode électroluminescente indépendamment de la couche conductrice de la deuxième diode électroluminescente, le dispositif optoélectronique comprenant, pour chacune des première et deuxième diodes électroluminescentes, un premier plot conducteur couplé électriquement à la première portion semiconductrice, un deuxième plot conducteur couplé électriquement à la deuxième portion semiconductrice, et un troisième plot conducteur couplé électriquement à la couche conductrice . [0010] For this purpose, one embodiment provides an optoelectronic device comprising at least first and second light-emitting diodes each comprising a first P-type doped semiconductor portion and a second N-type doped semiconductor portion, an active area comprising wells multiple quantum between the first and second semiconductor portions, a conductive layer covering the side walls of the active area and at least part of the first semiconductor portion and an insulating layer interposed between the side walls of the active area and at least part of the conductive layer, the device comprising means for controlling the conductive layer of the first light-emitting diode independently of the conductive layer of the second light-emitting diode, the optoelectronic device comprising, for each of the first and second light-emitting diodes, a first conductive pad electrically coupled to the first semiconductor portion, a second conductive pad electrically coupled to the second semiconductor portion, and a third conductive pad electrically coupled to the conductive layer.
[0011] Selon un mode de réalisation, pour chacune des première et deuxième diodes électroluminescentes, la zone active comprend des puits quantiques multiples. [0011] According to one embodiment, for each of the first and second light-emitting diodes, the active area comprises multiple quantum wells.
[0012] Selon un mode de réalisation, pour chaque zone active, la composition du puits quantique le plus proche de la première portion semiconductrice est différente de la composition du puits quantique le plus proche de la deuxième portion semiconductrice. [0012] According to one embodiment, for each active zone, the composition of the quantum well closest to the first semiconductor portion is different from the composition of the quantum well closest to the second semiconductor portion.
[0013] Selon un mode de réalisation, pour chaque zone active, chaque puits quantique comprend un composé ternaire avec des premier, deuxième et troisième éléments chimiques. Les concentrations massiques du premier élément chimique des puits quantiques sont identiques. Les concentrations massiques du deuxième élément chimique des puits quantiques sont identiques, et la concentration massique du troisième élément chimique du puits quantique le plus proche de la première portion semiconductrice est différente de la concentration massique du troisième élément chimique du puits quantique le plus proche de la deuxième portion semiconductrice . [0013] According to one embodiment, for each active zone, each quantum well comprises a ternary compound with first, second and third chemical elements. The mass concentrations of the first chemical element in quantum wells are identical. The mass concentrations of the second chemical element of quantum wells are the same, and the mass concentration of the third chemical element of the quantum well closest to the first semiconductor portion is different from the mass concentration of the third chemical element of the quantum well closest to the second semiconductor portion.
[0014] Selon un mode de réalisation, la différence entre la concentration massique du troisième élément chimique du puits quantique le plus proche de la première portion semiconductrice et la concentration massique du troisième élément chimique du puits quantique le plus proche de la deuxième portion semiconductrice est supérieure à 10 points de pourcentage. [0014] According to one embodiment, the difference between the mass concentration of the third chemical element of the quantum well closest to the first semiconductor portion and the mass concentration of the third chemical element of the quantum well closest to the second semiconductor portion is greater than 10 percentage points.
[0015] Selon un mode de réalisation, le premier élément chimique est un élément du groupe III. [0015] According to one embodiment, the first chemical element is an element from group III.
[0016] Selon un mode de réalisation, le premier élément chimique est le gallium. [0016] According to one embodiment, the first chemical element is gallium.
[0017] Selon un mode de réalisation, le deuxième élément chimique est un élément du groupe V. According to one embodiment, the second chemical element is an element of group V.
[0018] Selon un mode de réalisation, le deuxième élément chimique est l'azote. [0018] According to one embodiment, the second chemical element is nitrogen.
[0019] Selon un mode de réalisation, le troisième élément chimique est un élément du groupe III. [0020] Selon un mode de réalisation, le troisième élément chimique est l'indium. [0019] According to one embodiment, the third chemical element is an element from group III. [0020] According to one embodiment, the third chemical element is indium.
[0021] Selon un mode de réalisation, chaque diode électroluminescente a une structure "mesa". [0021] According to one embodiment, each light-emitting diode has a "mesa" structure.
[0022] Selon un mode de réalisation, pour chaque diode électroluminescente, la deuxième portion semiconductrice a la forme d'un fil. [0022] According to one embodiment, for each light-emitting diode, the second semiconductor portion is in the form of a wire.
[0023] Selon un mode de réalisation, chaque diode électroluminescente comprend, en outre, entre la zone active et la première portion semiconductrice, une couche de blocage d'électrons. Selon un mode de réalisation, les premier et deuxième plots conducteurs sont isolés électriquement de la couche conductrice. [0023] According to one embodiment, each light-emitting diode further comprises, between the active area and the first semiconductor portion, an electron blocking layer. According to one embodiment, the first and second conductive pads are electrically insulated from the conductive layer.
[0024] Un mode de réalisation prévoit également un procédé d'émission lumineuse à partir d'un dispositif optoélectronique tel que défini précédemment, comportant l'application d'une première tension électrique entre les première et deuxième portions semiconductrices de chacune des première et deuxième diodes électroluminescentes, l'application d'une deuxième tension électrique entre la couche conductrice et la première portion semiconductrice de la première diode électroluminescente, et l'application d'une troisième tension électrique entre la couche conductrice et la première portion semiconductrice de la deuxième diode électroluminescente, la troisième tension électrique étant différente de la deuxième tension électrique. [0024] One embodiment also provides for a method of emitting light from an optoelectronic device as defined above, comprising the application of a first electrical voltage between the first and second semiconductor portions of each of the first and second light emitting diodes, applying a second electrical voltage between the conductive layer and the first semiconductor portion of the first light emitting diode, and applying a third electrical voltage between the conductive layer and the first semiconductor portion of the second diode electroluminescent, the third electric voltage being different from the second electric voltage.
Brève description des dessins Brief description of the drawings
[0025] Ces caractéristiques et avantages, ainsi que d'autres, seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non limitatif en relation avec les figures jointes parmi lesquelles : [0026] la figure 1 représente un mode de réalisation d'un dispositif optoélectronique comprenant des diodes électroluminescentes ; These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the accompanying figures, among which: [0026] FIG. 1 represents an embodiment of an optoelectronic device comprising light emitting diodes;
[0027] la figure 2 représente un autre mode de réalisation d'un dispositif optoélectronique ; [0027] FIG. 2 represents another embodiment of an optoelectronic device;
[0028] la figure 3 représente un autre mode de réalisation d'un dispositif optoélectronique ; FIG. 3 represents another embodiment of an optoelectronic device;
[0029] la figure 4 représente un mode de réalisation d'une diode électroluminescente utilisée pour réaliser des simulations ; FIG. 4 represents an embodiment of a light emitting diode used to carry out simulations;
[0030] la figure 5 représente des courbes d'évolution de l'efficacité quantique interne de la diode électroluminescente de la figure 4 en fonction de la densité surfacique de courant traversant la diode électroluminescente ; [0030] FIG. 5 represents curves of the evolution of the internal quantum efficiency of the light-emitting diode of FIG. 4 as a function of the surface density of the current passing through the light-emitting diode;
[0031] la figure 6 représente des courbes d'évolution de l'efficacité de conversion d'énergie de la diode électroluminescente de la figure 4 en fonction de la densité surfacique de courant traversant la diode électroluminescente ; [0031] FIG. 6 represents curves of the evolution of the energy conversion efficiency of the light-emitting diode of FIG. 4 as a function of the surface density of the current passing through the light-emitting diode;
[0032] la figure 7 représente des courbes d'évolution de la densité surfacique de courant traversant la diode électroluminescente de la figure 4 en fonction de la tension anode-cathode appliquée à la diode électroluminescente ; [0032] FIG. 7 represents the curves of the evolution of the surface density of the current passing through the light-emitting diode of FIG. 4 as a function of the anode-cathode voltage applied to the light-emitting diode;
[0033] la figure 8 représente des courbes d'évolution du taux de recombinaisons radiatives dans la zone active de la diode électroluminescente de la figure 4 ; [0033] FIG. 8 represents curves for the evolution of the rate of radiative recombinations in the active zone of the light-emitting diode of FIG. 4;
[0034] la figure 9 représente des courbes d'évolution de l'énergie de bande de valence dans la zone active de la diode électroluminescente de la figure 4 ; [0035] la figure 10 représente une courbe d'évolution de la concentration de trous dans la zone active de la diode électroluminescente de la figure 4 ; [0034] FIG. 9 represents curves of the evolution of the valence band energy in the active zone of the light-emitting diode of FIG. 4; [0035] FIG. 10 represents a curve of the evolution of the concentration of holes in the active zone of the light-emitting diode of FIG. 4;
[0036] la figure 11 représente une courbe d'évolution du taux de recombinaisons radiatives dans la zone active de la diode électroluminescente de la figure 4 ; FIG. 11 represents an evolution curve of the rate of radiative recombinations in the active zone of the light-emitting diode of FIG. 4;
[0037] la figure 12 est analogue à la figure 10 ; [0037] Figure 12 is similar to Figure 10;
[0038] la figure 13 est analogue à la figure 11 ; Figure 13 is similar to Figure 11;
[0039] la figure 14 illustre une étape d'un mode de réalisation d'un procédé de fabrication du dispositif optoélectronique de la figure 1 ; [0039] FIG. 14 illustrates a step of an embodiment of a method of manufacturing the optoelectronic device of FIG. 1;
[0040] la figure 15 illustre une autre étape du procédé ; [0040] FIG. 15 illustrates another step of the method;
[0041] la figure 16 illustre une autre étape du procédé ; [0041] FIG. 16 illustrates another step of the method;
[0042] la figure 17 illustre une autre étape du procédé ; [0042] FIG. 17 illustrates another step of the method;
[0043] la figure 18 illustre une autre étape du procédé ; [0043] FIG. 18 illustrates another step of the method;
[0044] la figure 19 illustre une autre étape du procédé ; [0044] FIG. 19 illustrates another step of the method;
[0045] la figure 20 illustre une autre étape du procédé ; FIG. 20 illustrates another step of the method;
[0046] la figure 21 illustre une étape d'un mode de réalisation d'un procédé de fabrication du dispositif optoélectronique de la figure 2 ; [0046] FIG. 21 illustrates a step of an embodiment of a method of manufacturing the optoelectronic device of FIG. 2;
[0047] la figure 22 illustre une autre étape du procédé ; FIG. 22 illustrates another step of the method;
[0048] la figure 23 illustre une autre étape du procédé ; [0048] FIG. 23 illustrates another step of the method;
[0049] la figure 24 illustre une autre étape du procédé ; FIG. 24 illustrates another step of the method;
[0050] la figure 25 illustre une autre étape du procédé ; [0050] FIG. 25 illustrates another step of the method;
[0051] la figure 26 illustre une autre étape du procédé ; [0051] FIG. 26 illustrates another step of the method;
[0052] la figure 27 illustre une autre étape du procédé ; FIG. 27 illustrates another step of the method;
[0053] la figure 28 illustre une autre étape du procédé ; [0054] la figure 29 illustre une étape d'un mode de réalisation d'un procédé de fabrication du dispositif optoélectronique de la figure 3 ; [0053] FIG. 28 illustrates another step of the method; [0054] FIG. 29 illustrates a step of an embodiment of a method of manufacturing the optoelectronic device of FIG. 3;
[0055] la figure 30 illustre une autre étape du procédé ; FIG. 30 illustrates another step of the method;
[0056] la figure 31 illustre une autre étape du procédé ; FIG. 31 illustrates another step of the method;
[0057] la figure 32 illustre une autre étape du procédé ; [0057] FIG. 32 illustrates another step of the method;
[0058] la figure 33 illustre une autre étape du procédé ; [0058] FIG. 33 illustrates another step of the method;
[0059] la figure 34 illustre une autre étape du procédé ; FIG. 34 illustrates another step of the method;
[0060] la figure 35 illustre une autre étape du procédé ; et [0060] FIG. 35 illustrates another step of the method; and
[0061] la figure 36 illustre une autre étape du procédé. [0061] FIG. 36 illustrates another step of the method.
Description des modes de réalisation Description of embodiments
[0062] De mêmes éléments ont été désignés par de mêmes références dans les différentes figures et, de plus, comme cela est habituel dans la représentation des circuits électroniques, les diverses figures ne sont pas tracées à l'échelle. En particulier, les éléments structurels et/ou fonctionnels communs aux différents modes de réalisation peuvent présenter les mêmes références et peuvent disposer de propriétés structurelles, dimensionnelles et matérielles identiques. En outre, seuls les éléments utiles à la compréhension de la présente description ont été représentés et sont décrits. En particulier, la structure d'une diode électroluminescente est bien connue de l'homme de l'art et n'est pas décrite en détail. The same elements have been designated by the same references in the various figures and, moreover, as is usual in the representation of electronic circuits, the various figures are not drawn to scale. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. In addition, only the elements useful for understanding the present description have been shown and are described. In particular, the structure of a light emitting diode is well known to those skilled in the art and is not described in detail.
[0063] Dans la description qui suit, lorsque l'on fait référence à des qualificatifs de position relative, tels que les termes "supérieur", "inférieur", etc., il est fait référence à l'orientation des figures ou à un dispositif optoélectronique dans une position normale d'utilisation. Sauf indication contraire, les termes "sensiblement", "environ", "approximativement" et "de l'ordre de" signifient "à 10 % près", de préférence à "5 % près". En outre, on appelle "zone active" d'une diode électroluminescente la région de la diode électroluminescente depuis laquelle est émise la majorité du rayonnement électromagnétique fourni par la diode électroluminescente. Sauf précision contraire, lorsque l'on fait référence à deux éléments connectés entre eux, cela signifie directement connectés électriquement sans éléments intermédiaires autres que des conducteurs, et lorsque l'on fait référence à deux éléments reliés ou couplés entre eux, cela signifie que ces deux éléments peuvent être connectés ou être reliés électriquement ou couplés électriquement par l'intermédiaire d'un ou plusieurs autres éléments. En outre, on considère ici que les termes "isolant" et "conducteur" signifient respectivement "isolant électriquement" et "conducteur électriquement". In the following description, when reference is made to qualifiers of relative position, such as the terms "upper", "lower", etc., reference is made to the orientation of the figures or to a optoelectronic device in a normal position of use. Unless otherwise indicated, the terms "substantially", "about", "approximately" and "on the order of" mean "to within 10%", preferably to "within 5%". In addition, the region of the light emitting diode from which the majority of the electromagnetic radiation supplied by the light emitting diode is emitted is called the "active area" of a light emitting diode. Unless otherwise specified, when referring to two elements connected together, it means directly electrically connected without intermediate elements other than conductors, and when referring to two elements connected or coupled together, it means that these two elements may be connected or be electrically connected or electrically coupled through one or more other elements. In addition, it is considered here that the terms "insulator" and "conductor" mean respectively "electrically insulating" and "electrically conductive".
[0064] La figure 1 est une vue en coupe, partielle et schématique, d'un mode de réalisation d'un dispositif optoélectronique 10 adapté à l'émission de lumière. Selon un mode de réalisation, le dispositif optoélectronique 10 comprend au moins deux circuits électroniques 12 et 14. Le premier circuit 12 comprend des diodes électroluminescentes DEL. Le deuxième circuit 14 comprend des composants électroniques non représentés, notamment des transistors, utilisés pour la commande des diodes électroluminescentes du premier circuit 12. Le premier circuit 12 est fixé au deuxième circuit 14, par exemple par collage moléculaire ou par une liaison de type "Flip-Chip", notamment un procédé "Flip-Chip" par billes ou par microtubes. Le premier circuit 12 est appelé circuit optoélectronique dans la suite de la description et le deuxième circuit 14 peut être un circuit intégré et est appelé circuit de commande ou puce de commande dans la suite de la description. [0065] Le dispositif optoélectronique 10 est destiné, en fonctionnement, à émettre de la lumière vers le haut. Le circuit optoélectronique 12 comprend, du haut vers le bas en figure 1 : Figure 1 is a sectional view, partial and schematic, of an embodiment of an optoelectronic device 10 adapted to the emission of light. According to one embodiment, the optoelectronic device 10 comprises at least two electronic circuits 12 and 14. The first circuit 12 comprises light emitting diodes LEDs. The second circuit 14 comprises electronic components, not shown, in particular transistors, used for controlling the light-emitting diodes of the first circuit 12. The first circuit 12 is fixed to the second circuit 14, for example by molecular bonding or by a connection of the "type". Flip-Chip ", in particular a" Flip-Chip "process by balls or by microtubes. The first circuit 12 is called an optoelectronic circuit in the remainder of the description and the second circuit 14 can be an integrated circuit and is called a control circuit or control chip in the remainder of the description. The optoelectronic device 10 is intended, in operation, to emit light upwards. The optoelectronic circuit 12 comprises, from top to bottom in FIG. 1:
- un substrat 16, par exemple un substrat isolant, au moins partiellement transparent aux rayonnements électromagnétiques émis par les diodes électroluminescentes et qui délimite une face d'émission 18 du dispositif optoélectronique 10, le substrat 16 pouvant ne pas être présent ; a substrate 16, for example an insulating substrate, at least partially transparent to the electromagnetic radiation emitted by the light-emitting diodes and which delimits an emission face 18 of the optoelectronic device 10, the substrate 16 possibly not being present;
- une couche semiconductrice 20 dopée d'un premier type de conductivité, au moins partiellement transparente aux rayonnements électromagnétiques émis par les diodes électroluminescentes DEL ; a semiconductor layer 20 doped with a first type of conductivity, at least partially transparent to the electromagnetic radiation emitted by the light-emitting diodes DEL;
- des tranchées d'isolation latérales 22 qui s'étendent sur toute l'épaisseur de la couche semiconductrice 20 et qui délimitent des portions de substrat 24 dans la couche semiconductrice 20, trois portions de substrat 24 étant représentées en figure 1, les tranchées d'isolation latérales 22 pouvant ne pas être présentes ; - lateral insulation trenches 22 which extend over the entire thickness of the semiconductor layer 20 and which delimit portions of substrate 24 in the semiconductor layer 20, three portions of substrate 24 being shown in FIG. 1, the trenches d side insulation 22 may not be present;
- pour chaque portion de substrat 24, au moins une diode électroluminescente DEL, chaque diode électroluminescente DEL comprenant une portion semiconductrice supérieure 26 en contact avec la portion de substrat 24 correspondante, une zone active 28, et une portion semiconductrice inférieure 30, la zone active 28 étant interposée entre la portion semiconductrice supérieure 26 et la portion semiconductrice inférieure 30, la portion semiconductrice inférieure 30 comprenant une face inférieure 32 du côté opposé à la zone active 28, l'empilement comprenant la portion semiconductrice supérieure 26, la zone active 28 et la portion semiconductrice inférieure 30 formant un îlot délimité par des parois latérales 34 et la face inférieure 32 ; - pour chaque diode électroluminescente DEL, une couche isolante 36 recouvrant la portion de substrat 24 autour de la diode électroluminescente DEL et recouvrant les parois latérales 34 de la diode électroluminescente DEL ; - for each portion of substrate 24, at least one light-emitting diode LED, each light-emitting diode LED comprising an upper semiconductor portion 26 in contact with the corresponding substrate portion 24, an active area 28, and a lower semiconductor portion 30, the active area 28 being interposed between the upper semiconductor portion 26 and the lower semiconductor portion 30, the lower semiconductor portion 30 comprising a lower face 32 on the side opposite to the active zone 28, the stack comprising the upper semiconductor portion 26, the active zone 28 and the lower semiconductor portion 30 forming an island delimited by side walls 34 and the lower face 32; - for each light-emitting diode LED, an insulating layer 36 covering the portion of substrate 24 around the light-emitting diode LED and covering the side walls 34 of the light-emitting diode LED;
- pour chaque diode électroluminescente DEL, une couche conductrice 38, appelée grille par la suite, recouvrant la couche isolante 36 ; - for each light-emitting diode LED, a conductive layer 38, called the gate hereafter, covering the insulating layer 36;
- pour chaque diode électroluminescente DEL, une couche isolante 40 recouvrant la grille 38 et une partie de la face inférieure 32 de la portion semiconductrice inférieure 30, la couche isolante 40 pouvant ne pas être présente ; et - for each light-emitting diode LED, an insulating layer 40 covering the gate 38 and part of the lower face 32 of the lower semiconductor portion 30, the insulating layer 40 possibly not being present; and
- pour chaque diode électroluminescente DEL, un premier plot conducteur 42 au contact de la portion de substrat 24 correspondante, un deuxième plot conducteur 44 au contact de la face inférieure 32 de la portion semiconductrice inférieure 30 et un troisième plot conducteur 46 au contact de la grille 38. - for each light-emitting diode LED, a first conductive pad 42 in contact with the corresponding substrate portion 24, a second conductive pad 44 in contact with the lower face 32 of the lower semiconductor portion 30 and a third conductive pad 46 in contact with the grid 38.
[0066] La puce de commande 14 comprend, du côté du circuit optoélectronique 12, pour chaque diode électroluminescente DEL, trois plots conducteurs 48, 50, 52, le plot conducteur The control chip 14 comprises, on the side of the optoelectronic circuit 12, for each light-emitting diode LED, three conductive pads 48, 50, 52, the conductive pad
48 étant connecté au plot conducteur 42, le plot conducteur 50 étant connecté au plot conducteur 44 et le plot conducteur 52 étant connecté au plot conducteur 46. Dans le cas où la puce de commande 14 est fixée au circuit optoélectronique 12 par collage moléculaire, les plots conducteurs 48, 50, 52 peuvent être en contact avec les plots conducteurs 42, 44,48 being connected to the conductive pad 42, the conductive pad 50 being connected to the conductive pad 44 and the conductive pad 52 being connected to the conductive pad 46. In the case where the control chip 14 is attached to the optoelectronic circuit 12 by molecular bonding, the conductive pads 48, 50, 52 may be in contact with the conductive pads 42, 44,
46. Dans le cas où la puce de commande 14 est fixée au circuit optoélectronique 12 par une liaison de type "flip chip", des billes de soudure ou des microtubes peuvent être interposés entre les plots conducteurs 42, 44, 46 et les plots conducteurs 48, 50, 52. [0067] Dans le mode de réalisation représenté en figure 1, chaque diode électroluminescente DEL est dite de type "mesa", c'est-à-dire qu'elle comprend un empilement de couches planes qui a été gravé pour former un îlot. 46. In the case where the control chip 14 is attached to the optoelectronic circuit 12 by a connection of the "flip chip" type, solder balls or microtubes can be interposed between the conductive pads 42, 44, 46 and the conductive pads 48, 50, 52. In the embodiment shown in Figure 1, each light emitting diode LED is said to be of the "mesa" type, that is to say it comprises a stack of flat layers which has been etched to form an island.
[0068] La figure 2 est une vue en coupe, partielle et schématique, d'un autre mode de réalisation d'un dispositif optoélectronique 55 adapté à l'émission de lumière. Le dispositif optoélectronique 55 comprend tous les éléments du dispositif optoélectronique 10 représenté en figure 1, à la différence que le substrat 16 n'est pas présent et chaque diode électroluminescente DEL est de type axial, c'est-à-dire que les portions semiconductrices inférieure et supérieure 26 et 30 ont été fabriquées sous la forme de fils. En figure 2, on a représenté deux diodes électroluminescentes DEL pour chaque portion de substrat 24, le plot conducteur 44 associé étant connecté aux portions semiconductrices inférieures 30 de chacune des deux diodes électroluminescentes DEL. Figure 2 is a sectional view, partial and schematic, of another embodiment of an optoelectronic device 55 adapted to the emission of light. The optoelectronic device 55 comprises all the elements of the optoelectronic device 10 shown in FIG. 1, with the difference that the substrate 16 is not present and each light-emitting diode LED is of the axial type, that is to say that the semiconductor portions lower and upper 26 and 30 were made in the form of wires. In FIG. 2, two light-emitting diodes LEDs have been shown for each portion of substrate 24, the associated conductive pad 44 being connected to the lower semiconductor portions 30 of each of the two light-emitting diodes DEL.
[0069] La figure 3 est une vue en coupe, partielle et schématique, d'un autre mode de réalisation d'un dispositif optoélectronique 60 adapté à l'émission de lumière. Le dispositif optoélectronique 60 comprend tous les éléments du dispositif optoélectronique 10 représenté en figure 1, à la différence que le substrat 16 et la couche semiconductrice 20 ne sont pas présents. En outre, les diodes électroluminescentes DEL sont réparties en groupes d'au moins deux diodes électroluminescentes DEL, et, pour chaque diode électroluminescente DEL, la portion semiconductrice supérieure 26 a une forme filaire, la zone active 28 a au moins partiellement une forme conique ou tronconique qui s'évase depuis la portion semiconductrice supérieure 26, et la portion semiconductrice inférieure 30 est commune pour les diodes électroluminescentes DEL d'un même groupe. De plus, pour chaque diode électroluminescente DEL, le plot conducteur 42 est relié électriquement à la portion semiconductrice supérieure 26 par un élément conducteur 61. Figure 3 is a sectional view, partial and schematic, of another embodiment of an optoelectronic device 60 adapted to the emission of light. The optoelectronic device 60 comprises all the elements of the optoelectronic device 10 shown in FIG. 1, with the difference that the substrate 16 and the semiconductor layer 20 are not present. Further, the light emitting diodes LEDs are divided into groups of at least two light emitting diodes LEDs, and, for each light emitting diode LED, the upper semiconductor portion 26 has a wire shape, the active area 28 has at least partially a conical shape or frustoconical which widens out from the upper semiconductor portion 26, and the lower semiconductor portion 30 is common for the light emitting diodes LEDs of the same group. In addition, for each light-emitting diode LED, the conductive pad 42 is electrically connected to the upper semiconductor portion 26 by a conductive element 61.
[0070] La figure 4 est une vue en coupe, partielle et schématique, plus détaillée de la diode électroluminescente DEL. Selon un mode de réalisation, la zone active 28 est la couche depuis laquelle est émise la majorité du rayonnement électromagnétique fourni par le circuit optoélectronique 12. Selon un mode de réalisation, la zone active 28 comprend des puits quantiques multiples. Elle comprend alors une alternance de premières couches semiconductrices 62, appelées couches de puits quantique, et de deuxièmes couches semiconductrices 64, appelées couches barrière, chaque couche de puits quantique 62 étant en un matériau semiconducteur ayant une bande interdite inférieure à celle du matériau formant les portions supérieure et inférieure 26, 30. Figure 4 is a sectional view, partial and schematic, more detailed of the light emitting diode LED. According to one embodiment, the active zone 28 is the layer from which is emitted the majority of the electromagnetic radiation supplied by the optoelectronic circuit 12. According to one embodiment, the active zone 28 comprises multiple quantum wells. It then comprises an alternation of first semiconductor layers 62, called quantum well layers, and of second semiconductor layers 64, called barrier layers, each quantum well layer 62 being made of a semiconductor material having a forbidden band less than that of the material forming the upper and lower portions 26, 30.
[0071] Les couches et portions semiconductrices 20, 26, 30, The semiconductor layers and portions 20, 26, 30,
62, 64 sont, au moins en partie, formées à partir d'au moins un matériau semiconducteur. Le matériau semiconducteur est choisi parmi le groupe comprenant les composés III-V, par exemple un composé III-N, les composés II-VI ou les semiconducteurs ou composés du groupe IV. Des exemples d'éléments du groupe III comprennent le gallium (Ga) , l'indium (In) ou l'aluminium (Al) . Des exemples de composés III-N sont GaN, AIN, InN, InGaN, AlGaN ou AlInGaN. D'autres éléments du groupe V peuvent également être utilisés, par exemple, le phosphore ou l'arsenic. Des exemples d'éléments du groupe II comprennent des éléments du groupe IIA, notamment le béryllium (Be) et le magnésium (Mg) et des éléments du groupe IIB, notamment le zinc (Zn) , le cadmium (Cd) et le mercure (Hg) . Des exemples d'éléments du groupe VI comprennent des éléments du groupe VIA, notamment l'oxygène (O) et le tellure (Te) . Des exemples de composés II-VI sont ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe ou HgTe. Des exemples de matériaux semiconducteurs du groupe IV sont le silicium (Si) , le carbone (C) , le germanium (Ge) , les alliages de carbure de silicium (SiC) , les alliages silicium-germanium (SiGe) ou les alliages de carbure de germanium (GeC) . Les couches et portions semiconductrices 20, 26, 30, 62, 64 peuvent comprendre un dopant. A titre d'exemple, pour des composés III-V, le dopant peut être choisi parmi le groupe comprenant un dopant de type P du groupe II, par exemple du magnésium (Mg) , du zinc (Zn) , du cadmium (Cd) ou du mercure (Hg) , un dopant du type P du groupe IV, par exemple du carbone (C) , ou un dopant de type N du groupe IV, par exemple du silicium (Si) , du germanium (Ge) , du sélénium (Se) , du soufre (S) , du terbium (Tb) ou de 1 ' étain ( Sn) . 62, 64 are, at least in part, formed from at least one semiconductor material. The semiconductor material is chosen from the group comprising III-V compounds, for example a III-N compound, II-VI compounds or semiconductors or compounds of group IV. Examples of Group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AIN, InN, InGaN, AlGaN or AlInGaN. Other elements of group V can also be used, for example, phosphorus or arsenic. Examples of Group II elements include Group IIA elements including beryllium (Be) and magnesium (Mg) and Group IIB elements including zinc (Zn), cadmium (Cd) and mercury ( Hg). Examples of Group VI elements include elements of Group VIA, including oxygen (O) and tellurium (Te). Examples of compounds II-VI are ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe or HgTe. Examples of materials group IV semiconductors are silicon (Si), carbon (C), germanium (Ge), silicon carbide alloys (SiC), silicon-germanium alloys (SiGe) or germanium carbide alloys (GeC) ). The semiconductor layers and portions 20, 26, 30, 62, 64 may include a dopant. By way of example, for III-V compounds, the dopant can be chosen from the group comprising a dopant of type P from group II, for example magnesium (Mg), zinc (Zn), cadmium (Cd) or mercury (Hg), a type P dopant of group IV, for example carbon (C), or a type N dopant of group IV, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn).
[0072] Chaque couche barrière 64 peut être dans le même matériau que celui des portions supérieure et inférieure 26, 30, notamment non intentionnellement dopé. Selon un mode de réalisation, chaque couche de puits quantique 62 comprend le même composé III-V ou II-VI que celui formant les portions supérieure et inférieure 26, 30 et comprend, en outre, un élément supplémentaire. Selon un mode de réalisation, lorsque les portions supérieure et inférieure 26, 30 sont en GaN, chaque couche de puits quantique 64 peut être en InGaN avec une concentration massique de In comprise entre 10 % et 30 %. L'épaisseur de chaque couche de puits quantique 62 peut être comprise entre 3 nm et 10 nm. L'épaisseur de chaque couche barrière 64 peut être comprise entre 3 nm et 50 nm. Each barrier layer 64 can be in the same material as that of the upper and lower portions 26, 30, in particular not intentionally doped. According to one embodiment, each quantum well layer 62 comprises the same III-V or II-VI compound as that forming the upper and lower portions 26, 30 and further comprises an additional element. According to one embodiment, when the upper and lower portions 26, 30 are made of GaN, each quantum well layer 64 can be of InGaN with a mass concentration of In of between 10% and 30%. The thickness of each quantum well layer 62 can be between 3 nm and 10 nm. The thickness of each barrier layer 64 can be between 3 nm and 50 nm.
[0073] Selon un mode de réalisation, la concentration massique de l'élément supplémentaire dans la couche de puits quantique 64 la plus proche de la portion semiconductrice supérieure 26 est différente de la concentration massique de l'élément supplémentaire dans la couche de puits quantique 64 la plus proche de la portion semiconductrice inférieure 30. Selon un mode de réalisation, la différence entre la concentration massique de l'élément supplémentaire dans la couche de puits quantique 64 la plus proche de la portion semiconductrice supérieure 26 et la concentration massique de l'élément supplémentaire dans la couche de puits quantique 64 la plus proche de la portion semiconductrice inférieure 30 est supérieure à 10 points de pourcentage. According to one embodiment, the mass concentration of the additional element in the quantum well layer 64 closest to the upper semiconductor portion 26 is different from the mass concentration of the additional element in the quantum well layer. 64 closest to the lower semiconductor portion 30. According to one embodiment, the difference between the mass concentration of the additional element in the quantum well layer 64 closest to the upper semiconductor portion 26 and the mass concentration of the additional element in the quantum well layer 64 closest to the lower semiconductor portion 30 is greater to 10 percentage points.
[0074] Selon un mode de réalisation, la portion semiconductrice supérieure 26 est principalement constituée d'un composé III-N, par exemple du nitrure de gallium, dopé d'un premier type de conductivité, par exemple de type N. Le dopant de type N peut être le silicium. La concentration de dopants de la portion semiconductrice supérieure 26 peut être comprise entre 1017 atomes/cm3 et 5*1020 atomes/cm3. Selon un mode de réalisation, la portion semiconductrice inférieure 30 est, par exemple, au moins partiellement réalisée dans un composé III-N, par exemple du nitrure de gallium. La portion 30 peut être dopée du deuxième type de conductivité, par exemple de type P. La concentration de dopants de la portion semiconductrice inférieure 30 peut être comprise entre 1017 atomes/cm3 et 5*1020 atomes/cm3. La portion semiconductrice inférieure 30 peut comprendre un empilement d'au moins deux couches semiconductrices 30 du même matériau avec des concentrations massiques de dopants différentes, la couche la plus éloignée de la zone active 28 étant la plus dopée. According to one embodiment, the upper semiconductor portion 26 consists mainly of a III-N compound, for example gallium nitride, doped with a first type of conductivity, for example of type N. The dopant of type N can be silicon. The concentration of dopants in the upper semiconductor portion 26 may be between 10 17 atoms / cm 3 and 5 * 10 20 atoms / cm 3 . According to one embodiment, the lower semiconductor portion 30 is, for example, at least partially produced in a III-N compound, for example gallium nitride. The portion 30 can be doped with the second type of conductivity, for example of type P. The concentration of dopants in the lower semiconductor portion 30 can be between 10 17 atoms / cm 3 and 5 * 10 20 atoms / cm 3 . The lower semiconductor portion 30 may comprise a stack of at least two semiconductor layers 30 of the same material with different dopant mass concentrations, the layer furthest from the active zone 28 being the most doped.
[0075] Chaque dispositif optoélectronique 10, 55, 60 peut en outre comprendre une couche de blocage d'électrons 66 interposée entre la zone active 28 et la portion semiconductrice 30 dopée de type P, de préférence en contact avec la zone active 28 et la portion semiconductrice 30 dopée de type P. La couche de blocage d'électrons 66 assure une bonne répartition des porteurs électriques dans la zone active 28 et réduit la diffusion des électrons vers la portion semiconductrice 30 dopée de type P. La couche de blocage d'électrons 66 peut être formée d'un alliage ternaire, par exemple du nitrure de gallium et d'aluminium (AlGaN) ou du nitrure d'indium et d'aluminium (AlInN) . L'épaisseur de la couche de blocage d'électrons 66 peut être de l'ordre de 20 nmEach optoelectronic device 10, 55, 60 may further comprise an electron blocking layer 66 interposed between the active area 28 and the P-type doped semiconductor portion 30, preferably in contact with the active area 28 and the P-type doped semiconductor portion 30 The electron blocking layer 66 ensures a good distribution of the electric carriers in the active zone 28 and reduces the diffusion of electrons towards the P-type doped semiconductor portion 30. The blocking layer electron 66 may be formed from a ternary alloy, for example gallium aluminum nitride (AlGaN) or indium aluminum nitride (AlInN). The thickness of the electron blocking layer 66 may be of the order of 20 nm
[0076] La couche conductrice 38 correspond, de préférence, à une couche métallique, par exemple en aluminium, en argent, en cuivre, en titane, en nitrure de titane ou en zinc. Le matériau formant la couche conductrice 38 peut être un matériau conducteur et au moins partiellement transparent au rayonnement émis par la diode électroluminescente DEL tel que de l'oxyde d'indium-étain (ou ITO, acronyme anglais pour Indium Tin Oxide), de l'oxyde de zinc dopé ou non à l'aluminium ou au gallium, ou du graphène . L'épaisseur de la couche conductrice 38 peut être comprise entre 0,5 ym et 10 ymThe conductive layer 38 preferably corresponds to a metal layer, for example made of aluminum, silver, copper, titanium, titanium nitride or zinc. The material forming the conductive layer 38 may be a conductive material and at least partially transparent to the radiation emitted by the light-emitting diode LED such as indium tin oxide (or ITO, acronym for Indium Tin Oxide), from l zinc oxide doped or not with aluminum or gallium, or graphene. The thickness of the conductive layer 38 can be between 0.5 µm and 10 µm
[0077] Chaque couche isolante 36, 40 peut être en un matériau diélectrique, par exemple en oxyde de silicium (SZO2) , en nitrure de silicium (SixNy, où x est environ égal à 3 et y est environ égal à 4, par exemple du Si3N4) , en oxynitrure de silicium (SiOxNy où x peut être environ égal à 1/2 et y peut être environ égal à 1, par exemple du Si20N2) , en oxyde d'aluminium (AI2O3) , ou en oxyde d'hafnium (Hf02) · L'épaisseur minimale de la couche isolante 36 dans les parties où elle recouvre les parois latérales 34 des diodes électroluminescentes DEL peut être comprise entre 1 nm et 10 ym. La couche isolante 40 peut être réalisée en un matériau organique. A titre d'exemple, la couche isolante 36 est un polymère silicone, un polymère époxyde, un polymère acrylique ou un polycarbonate, une résine blanche, une résine noire ou une résine transparente chargée, notamment en particules d'oxyde de titane. Each insulating layer 36, 40 can be made of a dielectric material, for example of silicon oxide (SZO 2) , of silicon nitride (Si x N y , where x is approximately equal to 3 and y is approximately equal to 4, for example Si 3 N 4) , in silicon oxynitride (SiO x N y where x can be approximately equal to 1/2 and y can be approximately equal to 1, for example Si 2 0N 2) , in oxide aluminum (AI 2 O 3) , or hafnium oxide (Hf0 2) The minimum thickness of the insulating layer 36 in the parts where it covers the side walls 34 of the light emitting diodes LEDs can be between 1 nm and 10 ym. The insulating layer 40 can be made of an organic material. By way of example, the insulating layer 36 is a silicone polymer, an epoxy polymer, an acrylic polymer or a polycarbonate, a white resin, a black resin or a transparent resin loaded, in particular with titanium oxide particles.
[0078] Chaque plot conducteur 42, 44, 46, 48, 50, 52 peut être au moins en partie en un matériau choisi dans le groupe comprenant le cuivre, le titane, le tantale, le tungstène ou leurs nitrures associés, le nickel, l'or, l'étain, l'aluminium et les alliages d'au moins deux de ces composés. Each conductive pad 42, 44, 46, 48, 50, 52 can be at least in part made of a material chosen from the group comprising copper, titanium, tantalum, tungsten or their associated nitrides, nickel, gold, tin, aluminum and the alloys of at least two of these compounds.
[0079] Selon un mode de réalisation, au moins certaines des diodes électroluminescentes DEL peuvent être recouvertes d'une couche photoluminescente comprenant des luminophores adaptés, lorsqu'ils sont excités par la lumière émise par la diode électroluminescente DEL associée, à émettre de la lumière à une longueur d'onde différente de la longueur d'onde de la lumière émise par la diode électroluminescente DEL associée. De préférence, aucune diode électroluminescente DEL n'est recouverte d'une couche photoluminescente. According to one embodiment, at least some of the light-emitting diodes LEDs can be covered with a photoluminescent layer comprising suitable phosphors, when they are excited by the light emitted by the associated light-emitting diode LED, to emit light at a wavelength different from the wavelength of the light emitted by the associated light-emitting diode LED. Preferably, no light emitting diode LED is covered with a photoluminescent layer.
[0080] Dans les modes de réalisation illustrés sur les figures 2 et 3, chaque portion semiconductrice supérieure 26 et éventuellement chaque portion semiconductrice inférieure 30 a une forme allongée, par exemple cylindrique, conique ou tronconique, selon une direction privilégiée dont au moins deux dimensions, appelées dimensions mineures, sont comprises entre 5 nm et 2,5 ym, de préférence entre 50 nm et 2,5 ym, la troisième dimension, appelée dimension majeure, étant supérieure ou égale à 1 fois, de préférence supérieure ou égale à 5 fois et encore plus préférentiellement supérieure ou égale à 10 fois, la plus grande des dimensions mineures. Dans certains modes de réalisation, les dimensions mineures peuvent être inférieures ou égales à environ 1 ym, de préférence comprises entre 100 nm et 1 ym, plus préférentiellement entre 100 nm et 800 nm. Dans certains modes de réalisation, la hauteur de chaque portion semiconductrice 26 peut être supérieure ou égale à 500 nm, de préférence comprise entre 1 ym et 20 ym. La base de la portion semiconductrice supérieure 26 a, par exemple, une forme ovale, circulaire ou polygonale, notamment triangulaire, rectangulaire, carrée ou hexagonale. [0081] Des simulations du fonctionnement d'une diode électroluminescente DEL ont été réalisées avec la structure de diode électroluminescente DEL représentée en figure 4. La diode électroluminescente DEL avait une structure à symétrie de révolution. La figure 4 est une vue en coupe de la moitié de la diode électroluminescente DEL, l'axe des ordonnées correspondant à l'axe de révolution de la diode électroluminescente DEL. Pour les simulations, les portions semiconductrices 26 et 30 de la diode électroluminescente DEL étaient des cylindres à base circulaire de rayon égal à 5 ym. La portion semiconductrice supérieure 26 et la couche semiconductrice 20 étaient en GaN dopé de type N avec une concentration de dopants égale à 1019 atomes/cm3. La portion semiconductrice inférieure 30 était en GaN dopé de type P avec une concentration de dopants égale à 1019 atomes/cm3. La zone active 28 comprenait des puits quantiques multiples comprenant une alternance de couches 62 de InGaN, ayant chacune une concentration massique d'indium de 16 % et une épaisseur égale à 3 nm, et de couches 64 de GaN, non intentionnellement dopé, ayant chacune une épaisseur égale à 10 nm. La zone active 28 comprenait cinq couches 62 de InGaN et six couches 64 de GaN, la couche de la zone active 28 la plus proche de la portion semiconductrice inférieure 30 et la couche de la zone active 28 la plus proche de la portion semiconductrice supérieure 26 étant l'une des couches barrière 64. La diode électroluminescente DEL comprenait en outre une couche de blocage d'électrons 66 en AlGaN avec une concentration massique d'aluminium égale à 20 %, ayant une épaisseur égale à 20 nm et située entre la portion semiconductrice inférieure 30 et la zone active 28. La couche isolante 36, lorsqu'elle était présente dans les simulations, était en Si02 et avait une épaisseur de 3 nm. La cathode C de la diode électroluminescente DEL était simulée par un premier potentiel constant pris égal à 0 V appliqué à la face 32 de la portion semiconductrice inférieure 30. L'anode A de la diode électroluminescente DEL était simulée par un deuxième potentiel constant qui, sauf indication contraire, était égal à 2,5 V et qui était appliqué à une paroi de la portion de substrat 24. La grille 38, lorsqu'elle était présente dans les simulations, était simulée par un troisième potentiel commandable appliqué à la couche isolante 36 du côté opposé à la paroi latérale 34. Pour les simulations dans lesquelles la grille 38 n'est pas présente, la couche isolante 36 est considérée comme ayant une épaisseur infinie. In the embodiments illustrated in Figures 2 and 3, each upper semiconductor portion 26 and optionally each lower semiconductor portion 30 has an elongated shape, for example cylindrical, conical or frustoconical, in a preferred direction including at least two dimensions , called minor dimensions, are between 5 nm and 2.5 ym, preferably between 50 nm and 2.5 ym, the third dimension, called major dimension, being greater than or equal to 1 time, preferably greater than or equal to 5 times and even more preferably greater than or equal to 10 times, the greater of the minor dimensions. In some embodiments, the minor dimensions may be less than or equal to about 1 µm, preferably between 100 nm and 1 µm, more preferably between 100 nm and 800 nm. In some embodiments, the height of each semiconductor portion 26 may be greater than or equal to 500 nm, preferably between 1 µm and 20 µm. The base of the upper semiconductor portion 26 has, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal. [0081] Simulations of the operation of a light emitting diode LED were carried out with the light emitting diode LED structure shown in FIG. 4. The light emitting diode LED had a structure of symmetry of revolution. Figure 4 is a sectional view of half of the light emitting diode LED, the ordinate axis corresponding to the axis of revolution of the light emitting diode LED. For the simulations, the semiconductor portions 26 and 30 of the light-emitting diode LED were cylinders with a circular base with a radius equal to 5 µm. The upper semiconductor portion 26 and the semiconductor layer 20 were made of N-type doped GaN with a dopant concentration equal to 10 19 atoms / cm 3 . The lower semiconductor portion 30 was made of P-type doped GaN with a dopant concentration equal to 10 19 atoms / cm 3 . The active area 28 comprised multiple quantum wells comprising an alternation of layers 62 of InGaN, each having a mass indium concentration of 16% and a thickness equal to 3 nm, and layers 64 of GaN, unintentionally doped, each having a thickness equal to 10 nm. The active zone 28 comprised five layers 62 of InGaN and six layers 64 of GaN, the layer of the active zone 28 closest to the lower semiconductor portion 30 and the layer of the active zone 28 closest to the upper semiconductor portion 26 being one of the barrier layers 64. The light emitting diode LED further comprised an electron blocking layer 66 made of AlGaN with a mass concentration of aluminum equal to 20%, having a thickness equal to 20 nm and located between the portion lower semiconductor 30 and the active zone 28. The insulating layer 36, when it was present in the simulations, was made of Si0 2 and had a thickness of 3 nm. The cathode C of the light emitting diode DEL was simulated by a first constant potential taken equal to 0 V applied to the face 32 of the lower semiconductor portion 30. The anode A of the light-emitting diode LED was simulated by a second constant potential which, unless otherwise specified, was equal to 2.5 V and which was applied to a wall of the substrate portion 24. The gate 38, when present in the simulations, was simulated by a third controllable potential applied to the insulating layer 36 on the side opposite to the side wall 34. For simulations in which the gate 38 is not present, the layer insulator 36 is considered to have infinite thickness.
[0082] Pour certaines simulations, il a été simulé la présence de défauts sur les parois latérales 34 de la diode électroluminescente DEL entraînant une accumulation d'électrons sur les parois latérales 34 par une densité surfacique QssD de pièges non radiatifs de type donneur et/ou entraînant une accumulation de trous sur les parois latérales 34 par une densité surfacique QssA de pièges de type accepteur Un piège de type donneur est positif électriquement tant qu'il n'a pas piégé un électron et est neutre électriquement lorsqu'il a piégé un électron. Un piège de type accepteur est neutre électriquement tant qu'il n'a pas piégé un électron et présente une charge négative lorsqu'il a piégé un électron. Pour ces défauts, lorsqu'ils sont présents, la densité surfacique de pièges était de 1017 atomes/cm2, la durée moyenne de recombinaison du piège était de 10-11 s et l'énergie du piège était égale à la moitié de l'énergie des puits quantiques . For some simulations, it was simulated the presence of defects on the side walls 34 of the light-emitting diode LED causing an accumulation of electrons on the side walls 34 by a surface density QssD of non-radiative traps of the donor type and / or resulting in an accumulation of holes on the sidewalls 34 by a surface density QssA of acceptor-type traps A donor-type trap is electrically positive until it has trapped an electron and is electrically neutral when it has trapped an electron. electron. An acceptor-type trap is electrically neutral as long as it has not trapped an electron and exhibits a negative charge when it has trapped an electron. For these defects, when present, the surface density of the traps was 10 17 atoms / cm 2 , the average duration of recombination of the trap was 10 -11 s and the energy of the trap was equal to half of l energy from quantum wells.
[0083] La figure 5 représente des courbes d'évolution Cl à C6 de l'efficacité quantique interne IQE de la zone active 28 de la diode électroluminescente DEL, telle que représentée en figure 4, en fonction de la densité surfacique du courant d'alimentation I fourni à l'anode A et exprimée en A/cm2 selon une échelle logarithmique. L'efficacité quantique interne IQE est égale au rapport entre le nombre de photons créés dans la zone active 28 et le nombre d'électrons traversant la zone active 28. L'efficacité quantique interne est un nombre sans unité qui varie entre 0 et 1. FIG. 5 represents evolution curves C1 to C6 of the internal quantum efficiency IQE of the active zone 28 of the light-emitting diode LED, as shown in FIG. 4, as a function of the surface density of the current of power supply I supplied to the anode A and expressed in A / cm 2 on a logarithmic scale. Internal quantum efficiency IQE is equal to the ratio between the number of photons created in the active zone 28 and the number of electrons crossing the active zone 28. The internal quantum efficiency is a number without unit which varies between 0 and 1.
[0084] La figure 6 représente des courbes d'évolution DI à D6 de l'efficacité de conversion d'énergie WPE (sigle anglais pour Wall Plug Efficiency) de la diode électroluminescente DEL, telle que représentée en figure 4, en fonction de la densité surfacique du courant d'alimentation I fourni à l'anode A et exprimée en A/cm2 selon une échelle logarithmique L'efficacité de conversion d'énergie WPE est égale au rapport entre la puissance optique fournie par la diode électroluminescente et la puissance électrique consommée par la diode électroluminescente. Par rapport à l'efficacité quantique interne IQE, l'efficacité de conversion d'énergie WPE tient compte de l'efficacité d'extraction de la lumière hors de la diode électroluminescente DEL, de l'efficacité de l'injection électrique et de la perte d'énergie entre l'électron incident et le photon créé. FIG. 6 represents the evolution curves DI to D6 of the energy conversion efficiency WPE (acronym for Wall Plug Efficiency) of the light-emitting diode LED, as shown in FIG. 4, as a function of the surface density of the supply current I supplied to the anode A and expressed in A / cm 2 on a logarithmic scale The energy conversion efficiency WPE is equal to the ratio between the optical power supplied by the light emitting diode and the power power consumed by the light emitting diode. Compared with the internal quantum efficiency IQE, the energy conversion efficiency WPE takes into account the efficiency of extracting light from the light-emitting diode LED, the efficiency of electric injection and the loss of energy between the incident electron and the photon created.
[0085] Les courbes Cl et DI ont été obtenues sans grille et sans pièges. Les courbes C2 et D2 ont été obtenues sans grille et avec des pièges de type donneur. Les courbes C3 et D3 ont été obtenues sans grille et avec des pièges de type accepteur. Les courbes C4 et D4 ont été obtenues sans grille et avec des pièges de type accepteur et des pièges de type donneur. Les courbes C5 et D5 ont été obtenues sans pièges et avec la grille maintenue à -2 V. Les courbes C6 et D6 ont été obtenues avec des pièges de type donneur et avec la grille maintenue à -2 V. Les courbes C7 et D7 ont été obtenues avec des pièges de type accepteur et avec la grille maintenue à -2 V. The curves C1 and DI were obtained without a grid and without traps. The curves C2 and D2 were obtained without a grid and with traps of the donor type. Curves C3 and D3 were obtained without a grid and with acceptor type traps. Curves C4 and D4 were obtained without a grid and with acceptor type traps and donor type traps. Curves C5 and D5 were obtained without traps and with the grid maintained at -2 V. Curves C6 and D6 were obtained with traps of the donor type and with the grid maintained at -2 V. Curves C7 and D7 have were obtained with acceptor type traps and with the grid maintained at -2 V.
[0086] Comme cela apparaît sur la figure, chaque courbe d'évolution Cl à C7 passe par un maximum avant de diminuer. L'application d'une tension négative à la grille permet, dans le cas où des pièges de type donneur sont présents, d'augmenter la valeur maximale du IQE et permet, dans le cas où des pièges de type accepteur sont présents, de conserver la valeur maximale du IQE et de repousser la diminution du IQE. As shown in the figure, each evolution curve C1 to C7 passes through a maximum before decreasing. Applying a negative voltage to the grid allows, in in the case where donor type traps are present, to increase the maximum value of the IQE and makes it possible, in the case where acceptor type traps are present, to keep the maximum value of the IQE and to postpone the decrease in the IQE.
[0087] La figure 7 représente des courbes d'évolution El et E2 de la densité surfacique de courant I, exprimée en A/cm2 selon une échelle logarithmique, traversant la diode électroluminescente en fonction de la tension anode-cathode VAC appliquée à la diode électroluminescente DEL. La courbe El a été obtenue sans pièges et sans grille. La courbe E2 a été obtenue sans pièges et avec la grille maintenue à -2 V. La tension de seuil de la diode électroluminescente lorsque la grille est mise à -2 V est inférieure à la tension de seuil de la diode électroluminescente sans grille. De ce fait, lorsque la tension anode-cathode est constante, l'intensité du courant traversant la diode électroluminescente et donc la puissance lumineuse émise par la diode électroluminescente peut être commandée par la tension appliquée à la grille 38. FIG. 7 represents evolution curves E1 and E2 of the surface density of current I, expressed in A / cm 2 according to a logarithmic scale, crossing the light-emitting diode as a function of the anode-cathode voltage VAC applied to the light-emitting diode LED. Curve E1 was obtained without traps and without grid. Curve E2 was obtained without traps and with the gate held at -2 V. The threshold voltage of the light emitting diode when the gate is set to -2 V is lower than the threshold voltage of the light emitting diode without gate. Therefore, when the anode-cathode voltage is constant, the intensity of the current flowing through the light-emitting diode and therefore the light power emitted by the light-emitting diode can be controlled by the voltage applied to the grid 38.
[0088] Selon un mode de réalisation, le dispositif optoélectronique 10, 55, 60 comprend des diodes électroluminescentes DEL auxquelles est appliquée une tension anode-cathode sensiblement constante, et l'extinction ou l'allumage de chacune de ces diodes électroluminescentes et/ou la commande de la puissance lumineuse émise par chacune de ces diodes électroluminescentes est réalisée par la commande de la tension appliquée à la grille 38 de chacune de ces diodes électroluminescentes. La tension appliquée à la grille 38, qui est à moduler, est de façon avantageuse inférieure à la tension anode-cathode. According to one embodiment, the optoelectronic device 10, 55, 60 comprises light-emitting diodes LEDs to which a substantially constant anode-cathode voltage is applied, and the extinction or ignition of each of these light-emitting diodes and / or the control of the light power emitted by each of these light-emitting diodes is carried out by controlling the voltage applied to the gate 38 of each of these light-emitting diodes. The voltage applied to the grid 38, which is to be modulated, is advantageously less than the anode-cathode voltage.
[0089] La figure 8 représente, en fonction de la position, des courbes d'évolution Fl à F4 du taux de recombinaison radiative TRR dans les couches 62, 64 de la zone active 28 de la diode électroluminescente DEL, seules les quatre couches 62 de puits quantique les plus proches de la portion semiconductrice supérieure 26 de GaN dopé de type N étant représentées, la couche 62 de puits quantique la plus à gauche en figure 8 étant la plus proche de la portion semiconductrice supérieure 26 de GaN dopé de type N. Les courbes Fl à F4 ont été obtenues sans pièges et avec une tension anode-cathode de 2,5 V. La courbe Fl a été obtenue avec une tension de grille de 1 V. La courbe F2 a été obtenue avec une tension de grille de 0 V. La courbe F3 a été obtenue avec une tension de grille de -1 V. La courbe F4 a été obtenue avec une tension de grille de -2 V. Il apparaît que la couche 62 de InGaN la plus proche de la portion semiconductrice supérieure 26 de GaN dopé de type N est activée lorsque la tension de grille diminue. FIG. 8 represents, as a function of the position, of the evolution curves F1 to F4 of the radiative recombination rate TRR in the layers 62, 64 of the active zone 28 of the light emitting diode LED, only the four quantum well layers 62 closest to the upper semiconductor portion 26 of N-type doped GaN being shown, the leftmost quantum well layer 62 in FIG. 8 being the closest to the upper semiconductor portion 26 of N-type doped GaN. Curves F1 to F4 were obtained without traps and with an anode-cathode voltage of 2.5 V. Curve F1 was obtained with a gate voltage of 1 V. curve F2 was obtained with a gate voltage of 0 V. Curve F3 was obtained with a gate voltage of -1 V. Curve F4 was obtained with a gate voltage of -2 V. It appears that the InGaN layer 62 closest to the upper semiconductor portion 26 of N-type doped GaN is activated when the gate voltage decreases.
[0090] La figure 9 représente des courbes d'évolution Gl, G2 , G3 et G4 de l'énergie de la bande de valence BV dans les couches 62 et 64 de la zone active 28, dans la couche de blocage d'électrons 66 et dans la portion semiconductrice supérieure 30 de la diode électroluminescente DEL obtenues dans les mêmes conditions respectivement que les courbes Fl, F2, F3 et F4. L'application d'une tension négative sur la grille 38 entraîne une diminution de la barrière de potentiel vue par les trous provenant de la portion semiconductrice inférieure 30 de GaN dopé de type P. FIG. 9 represents evolution curves G1, G2, G3 and G4 of the energy of the valence band BV in the layers 62 and 64 of the active zone 28, in the electron blocking layer 66 and in the upper semiconductor portion 30 of the light-emitting diode DEL obtained under the same conditions respectively as the curves F1, F2, F3 and F4. The application of a negative voltage to the gate 38 causes a decrease in the potential barrier seen by the holes coming from the lower semiconductor portion 30 of P-type doped GaN.
[0091] La figure 10 représente une courbe d'évolution H de la concentration de trous CH, exprimée en trous/cm3 selon une échelle logarithmique, dans les couches 62, 64 de la zone active 28 de la diode électroluminescente DEL. La courbe H a été obtenue sans pièges, avec une tension anode-cathode de 2,5 V et sans grille. Comme cela apparaît sur cette figure, en l'absence de grille, la concentration de trous diminue lorsqu'on s'éloigne de la portion semiconductrice 30 de GaN dopé de type P. [0092] La figure 11 représente une courbe d'évolution J du taux de recombinaison radiative TRR, exprimé en nombre d'occurrence/cm3, dans les couches 62, 64 de la zone activeFIG. 10 represents an evolution curve H of the concentration of CH holes, expressed in holes / cm 3 on a logarithmic scale, in the layers 62, 64 of the active zone 28 of the light-emitting diode DEL. Curve H was obtained without traps, with an anode-cathode voltage of 2.5 V and without a grid. As shown in this figure, in the absence of a gate, the concentration of holes decreases as one moves away from the semiconductor portion 30 of P-type doped GaN. FIG. 11 represents an evolution curve J of the rate of radiative recombination TRR, expressed in number of occurrences / cm 3 , in the layers 62, 64 of the active zone.
28, et dans la couche de blocage d'électrons 66 de la diode électroluminescente DEL. La courbe H a été obtenue sans pièges, avec une tension anode-cathode de 2,5 V et sans grille. Comme cela apparaît sur cette figure, en l'absence de grille, seul le puits quantique 62 le plus proche de la portion semiconductrice 30 de GaN dopé de type P est activé. 28, and in the electron blocking layer 66 of the light emitting diode LED. Curve H was obtained without traps, with an anode-cathode voltage of 2.5 V and without a grid. As shown in this figure, in the absence of a gate, only the quantum well 62 closest to the semiconductor portion 30 of P-type doped GaN is activated.
[0093] La figure 12 représente une courbe d'évolution K de la concentration de trous, exprimée en trous/cm3 selon une échelle logarithmique, dans les couches 62, 64 de la zone active 28 de la diode électroluminescente DEL. La courbe K a été obtenue sans pièges, avec une tension anode-cathode de 2,5 V et avec une tension de grille de -2 V. Comme cela apparaît sur cette figure, en présence de la grille 38 à laquelle est appliquée une tension de -2 V, la concentration de trous augmente lorsqu'on s'éloigne de la portion semiconductrice 30 de GaN dopé de type P. FIG. 12 represents an evolution curve K of the concentration of holes, expressed in holes / cm 3 on a logarithmic scale, in the layers 62, 64 of the active zone 28 of the light-emitting diode LED. The K curve was obtained without traps, with an anode-cathode voltage of 2.5 V and with a gate voltage of -2 V. As shown in this figure, in the presence of the gate 38 to which a voltage is applied. of -2 V, the hole concentration increases as one moves away from the semiconductor portion 30 of P-type doped GaN.
[0094] La figure 13 représente une courbe d'évolution L du taux de recombinaison radiative TRR, exprimé en nombre d'occurrence/cm3, dans les couches 62, 64 de la zone activeFIG. 13 represents an evolution curve L of the radiative recombination rate TRR, expressed in number of occurrences / cm 3 , in the layers 62, 64 of the active zone.
28 de la diode électroluminescente DEL. La courbe H a été obtenue sans pièges, avec une tension anode-cathode de 2,5 V et avec une tension de grille de -2 V. Comme cela apparaît sur cette figure, en présence de la grille 38 à laquelle est appliquée une tension de -2 V, sensiblement seul le puits quantique 62 le plus proche de la portion semiconductrice 30 de GaN dopé de type P est activé. 28 of the light emitting diode LED. Curve H was obtained without traps, with an anode-cathode voltage of 2.5 V and with a gate voltage of -2 V. As shown in this figure, in the presence of the gate 38 to which a voltage is applied. of -2 V, substantially only the quantum well 62 closest to the semiconductor portion 30 of P-type doped GaN is activated.
[0095] Les figures 10 à 13 illustrent le fait que le puits quantique ou les puits quantiques activés peuvent être sélectionnés par la commande de la tension appliquée à la grille 38. Selon un mode de réalisation, au moins deux puits quantiques de chaque diode électroluminescente DEL sont adaptés à émettre des rayonnements électromagnétiques à des longueurs d'ondes différentes, par exemples le puits quantique le plus proche de la portion semiconductrice 26 et le puits quantique le plus proche de la portion semiconductrice 30. Ceci signifie qu'au moins un premier puits quantique de chaque diode électroluminescente DEL est adapté à émettre un premier rayonnement électromagnétique à une première longueur d'onde et un deuxième puits quantique de chaque diode électroluminescente DEL est adapté à émettre un deuxième rayonnement électromagnétique à une deuxième longueur d'onde différente de la première longueur d'onde. Lorsque les puits quantiques sont en InGaN, ceci peut être obtenu en formant ces puits quantiques avec des concentrations massiques d'indium différentes. Pour une première diode électroluminescente, la tension de grille de la première diode électroluminescente peut être commandée pour activer sensiblement seulement le premier puits quantique et, pour une deuxième diode électroluminescente, la tension de grille de la deuxième diode électroluminescente peut être commandée pour activer sensiblement seulement le deuxième puits quantique. On obtient ainsi deux diodes électroluminescentes de même structure qui émettent des rayonnements électromagnétiques à des longueurs d'ondes différentes. FIGS. 10 to 13 illustrate the fact that the quantum well or the activated quantum wells can be selected by controlling the voltage applied to the gate 38. According to one embodiment, at least two wells quantum cells of each light-emitting diode LED are adapted to emit electromagnetic radiation at different wavelengths, for example the quantum well closest to the semiconductor portion 26 and the quantum well closest to the semiconductor portion 30. This means that 'at least a first quantum well of each light emitting diode LED is adapted to emit a first electromagnetic radiation at a first wavelength and a second quantum well of each light emitting diode LED is adapted to emit a second electromagnetic radiation at a second length of wave different from the first wavelength. When the quantum wells are in InGaN, this can be obtained by forming these quantum wells with different mass concentrations of indium. For a first light emitting diode, the gate voltage of the first light emitting diode can be controlled to activate substantially only the first quantum well and, for a second light emitting diode, the gate voltage of the second light emitting diode can be controlled to activate substantially only the second quantum well. In this way, two light-emitting diodes of the same structure are obtained which emit electromagnetic radiation at different wavelengths.
[0096] Les figures 14 à 21 sont des vues en coupe, partielles et schématiques, de structures obtenues à des étapes successives d'un mode de réalisation d'un procédé de fabrication du dispositif optoélectronique 10 représenté sur la figure 1. Le procédé comprend les étapes suivantes : Figures 14 to 21 are sectional views, partial and schematic, of structures obtained in successive steps of an embodiment of a method of manufacturing the optoelectronic device 10 shown in Figure 1. The method comprises the following steps:
[0097] 1) formation sur le support 16, par exemple par croissance par épitaxie, d'un empilement comprenant la couche semiconductrice 20, une couche semiconductrice 70 de même composition que la portion semiconductrice supérieure 26 décrite précédemment, des couches semiconductrices 72 de même composition que les couches semiconductrices 62, 64 de la zone active 28 décrite précédemment, une couche semiconductrice 73 de même composition que la couche de blocage d'électrons 66 décrite précédemment, et une couche semiconductrice 74 de même composition que la portion semiconductrice inférieure 30 décrite précédemment (figure 14) . 1) formation on the support 16, for example by growth by epitaxy, of a stack comprising the semiconductor layer 20, a semiconductor layer 70 of the same composition as the upper semiconductor portion 26 previously described, semiconductor layers 72 of the same composition as the semiconductor layers 62, 64 of the active zone 28 described previously, a semiconductor layer 73 of the same composition as the electron blocking layer 66 described previously, and a semiconductor layer 74 of same composition as the lower semiconductor portion 30 described above (FIG. 14).
[0098] 2) gravure des couches semiconductrices 70, 72, 73 et 74 pour délimiter, pour chaque diode électroluminescente DEL, la portion semiconductrice supérieure 26, la zone active 28, la couche de blocage d'électrons 66 et la portion semiconductrice inférieure 30 (figure 15) . 2) etching of the semiconductor layers 70, 72, 73 and 74 to define, for each light-emitting diode LED, the upper semiconductor portion 26, the active area 28, the electron blocking layer 66 and the lower semiconductor portion 30 (figure 15).
[0099] 3) formation des tranchées d'isolation latérales, non représentées, dans la couche semiconductrice 20 et formation, pour chaque diode électroluminescente DEL, de la couche isolante 36 recouvrant la couche semiconductrice 20 et les parois latérales 34 de l'îlot et ne recouvrant pas la face 32 de l'îlot (figure 16) . 3) forming the side insulating trenches, not shown, in the semiconductor layer 20 and forming, for each light-emitting diode LED, the insulating layer 36 covering the semiconductor layer 20 and the side walls 34 of the island and not covering the face 32 of the island (figure 16).
[0100] 4) formation, pour chaque diode électroluminescente [0100] 4) training, for each light-emitting diode
DEL, de la couche conductrice 38 recouvrant la couche isolante 36, c'est-à-dire recouvrant la couche semiconductrice 20 et les parois latérales 34 de l'îlot et ne recouvrant pas la face 32 de l'îlot, et formation de la couche isolante 40 recouvrant la couche conductrice 38 et la face 32 de chaque diode électroluminescente DEL (figure 17) LED, the conductive layer 38 covering the insulating layer 36, that is to say covering the semiconductor layer 20 and the side walls 34 of the island and not covering the face 32 of the island, and formation of the insulating layer 40 covering the conductive layer 38 and the face 32 of each light-emitting diode LED (figure 17)
[0101] 5) gravure des couches 36, 38 et 40 pour exposer une partie de la face 32 de chaque diode électroluminescente DEL, une partie de la couche conductrice 20 et une partie de la couche 38 (figure 18) . [0101] 5) etching of layers 36, 38 and 40 to expose part of face 32 of each light-emitting diode LED, part of conductive layer 20 and part of layer 38 (FIG. 18).
[0102] 6) formation des plots conducteurs 42, 44 et 46 pour chaque diode électroluminescente DEL (figure 19). [0103] 7) fixation du dispositif optoélectronique représenté en figure 19 au circuit de commande 14 (figure 20) . [0102] 6) forming the conductive pads 42, 44 and 46 for each light-emitting diode LED (FIG. 19). [0103] 7) fixing the optoelectronic device shown in FIG. 19 to the control circuit 14 (FIG. 20).
[0104] Le procédé peut comprendre des étapes ultérieures de retrait du support 16 et de découpe pour délimiter les dispositifs optoélectroniques 10. The method can comprise subsequent steps of removing the support 16 and cutting to delimit the optoelectronic devices 10.
[0105] Les figures 21 à 28 sont des vues en coupe, partielles et schématiques, de structures obtenues à des étapes successives d'un mode de réalisation d'un procédé de fabrication du dispositif optoélectronique 55 représenté sur la figure 2. Le procédé comprend les étapes suivantes : [0105] FIGS. 21 to 28 are partial and schematic sectional views of structures obtained in successive steps of an embodiment of a method of manufacturing the optoelectronic device 55 shown in FIG. 2. The method comprises the following steps:
[0106] l') formation, sur le support 16, de la couche semiconductrice 20 et formation, pour chaque portion de substrat 24, par exemple par croissance épitaxiale d'au moins deux empilements comprenant chacun la portion semiconductrice 26 de forme filaire, la zone active 28 et la portion semiconductrice 30 de forme filaire décrite précédemment (figure 21), la couche de blocage d'électrons 66 n'étant pas représentée. Des exemples de procédés de croissance de portions semiconductrices de forme filaire sont décrits dans le document US 9 245 948. [0106] the) formation, on the support 16, of the semiconductor layer 20 and formation, for each portion of substrate 24, for example by epitaxial growth of at least two stacks each comprising the semiconductor portion 26 of wire form, the active zone 28 and the semiconductor portion 30 of wire form described above (FIG. 21), the electron blocking layer 66 not being shown. Examples of methods of growing semiconductor portions of wire form are described in US 9,245,948.
[0107] 2') formation des tranchées d'isolation latérales, non représentées, dans la couche semiconductrice 20 et formation, pour chaque groupe de diodes électroluminescentes DEL, de la couche isolante 36 recouvrant la couche semiconductrice 20 et les parois latérales 34 des fils (figure 22) . [0107] 2 ') forming the side insulating trenches, not shown, in the semiconductor layer 20 and forming, for each group of light-emitting diodes LEDs, the insulating layer 36 covering the semiconductor layer 20 and the side walls 34 of the wires (figure 22).
[0108] 3') formation, pour chaque groupe de diodes électroluminescentes DEL, de la couche conductrice 38 recouvrant une partie de la couche isolante 36 (figure 23) . [0108] 3 ') formation, for each group of light-emitting diodes DEL, of the conductive layer 38 covering part of the insulating layer 36 (FIG. 23).
[0109] 4') formation, pour chaque groupe de diodes électroluminescentes DEL, du plot conducteur 46 au contact de la couche conductrice 38 (figure 24) . [0110] 5') formation de la couche isolante 40 (figure 25) . [0109] 4 ') forming, for each group of light-emitting diodes DEL, the conductive pad 46 in contact with the conductive layer 38 (FIG. 24). [0110] 5 ') formation of the insulating layer 40 (Figure 25).
[0111] 6') formation, pour chaque diode électroluminescente[0111] 6 ') formation, for each light-emitting diode
DEL, du plot conducteur 44 au contact de la face 32 de chaque fil (figure 26) . LED, the conductive pad 44 in contact with the face 32 of each wire (Figure 26).
[0112] 7') formation, pour chaque groupe de diodes électroluminescentes DEL, au travers des couches isolantes 40 et 36, du plot conducteur 42 au contact de la couche semiconductrice 20 (figure 27) . [0112] 7 ') formation, for each group of light-emitting diodes DEL, through insulating layers 40 and 36, of the conductive pad 42 in contact with the semiconductor layer 20 (FIG. 27).
[0113] 8') fixation du dispositif optoélectronique représenté en figure 27 au circuit de commande 14 et retrait du support 16 (figure 28) . [0113] 8 ') fixing the optoelectronic device shown in FIG. 27 to the control circuit 14 and removing the support 16 (FIG. 28).
[0114] Les figures 29 à 36 sont des vues en coupe, partielles et schématiques, de structures obtenues à des étapes successives d'un mode de réalisation d'un procédé de fabrication du dispositif optoélectronique 60 représenté sur la figure 3. Le procédé comprend les étapes suivantes : Figures 29 to 36 are sectional views, partial and schematic, of structures obtained in successive steps of an embodiment of a method of manufacturing the optoelectronic device 60 shown in Figure 3. The method comprises the following steps:
[0115] 1") formation, sur le support 16, de la couche semiconductrice 20 et, pour chaque groupe de diodes électroluminescentes DEL, d'au moins deux empilements, trois empilements étant représentés, comprenant chacun la portion semiconductrice 26 de forme filaire, la zone active 28 de forme évasée et formation de la portion semiconductrice 30 au contact des zones actives 28 (figure 29), la couche de blocage d'électrons 66 n'étant pas représentée. [0115] 1 ") formation, on the support 16, of the semiconductor layer 20 and, for each group of light-emitting diodes LEDs, of at least two stacks, three stacks being shown, each comprising the semiconductor portion 26 of wire form, the active zone 28 of flared shape and formation of the semiconductor portion 30 in contact with the active zones 28 (FIG. 29), the electron blocking layer 66 not being shown.
[0116] 2") formation des tranchées d'isolation latérales, non représentées, dans la couche semiconductrice 20 et formation, pour chaque groupe de diodes électroluminescentes DEL, du plot conducteur 42 au contact de la couche semiconductrice 20 et du plot conducteur 44 au contact de la face 32 (figure 30) . [0116] 2 ") forming the lateral insulating trenches, not shown, in the semiconductor layer 20 and forming, for each group of light-emitting diodes LEDs, the conductive pad 42 in contact with the semiconductor layer 20 and the conductive pad 44 at the contact of face 32 (figure 30).
[0117] 3") fixation du dispositif optoélectronique représenté en figure 30 au circuit de commande 14 (figure 31) . [0118] 4") retrait du substrat 16 (figure 32) . [0117] 3 ") fixing the optoelectronic device shown in Figure 30 to the control circuit 14 (Figure 31). [0118] 4 ") removal of the substrate 16 (Figure 32).
[0119] 5") formation, pour chaque groupe de diodes électroluminescentes DEL, de la couche isolante 36 (figure[0119] 5 ") formation, for each group of light-emitting diodes DEL, of the insulating layer 36 (FIG.
33) . 33).
[0120] 6") formation, pour chaque groupe de diodes électroluminescentes DEL, d'une ouverture 82 dans la couche isolante 36 pour exposer une partie de la couche conductrice 20, et formation de la couche conductrice 38 recouvrant la couche isolante 36 et s'étendant dans l'ouverture 82 (figure[0120] 6 ") forming, for each group of light emitting diodes LEDs, an opening 82 in the insulating layer 36 to expose a part of the conductive layer 20, and forming the conductive layer 38 covering the insulating layer 36 and s 'extending into opening 82 (figure
34) . 34).
[0121] 7") formation, pour chaque groupe de diodes électroluminescentes DEL, du plot conducteur 46 au contact de la couche conductrice 38 dans l'ouverture 82 (figure 35) . [0121] 7 ") formation, for each group of light-emitting diodes DEL, of the conductive pad 46 in contact with the conductive layer 38 in the opening 82 (FIG. 35).
[0122] 8") formation, pour chaque groupe de diodes électroluminescentes DEL, de l'élément conducteur 61 reliant le plot conducteur 42 aux portions semiconductrices 26 (figure 36) . [0122] 8 ") formation, for each group of light-emitting diodes DEL, of the conductive element 61 connecting the conductive pad 42 to the semiconductor portions 26 (FIG. 36).
[0123] Divers modes de réalisation et variantes ont été décrits. L'homme de l'art comprendra que certaines caractéristiques de ces divers modes de réalisation et variantes pourraient être combinées, et d'autres variantes apparaîtront à l'homme de l'art. En particulier, dans les modes de réalisation décrits précédemment, l'ensemble comportant une grille 38 et la couche isolante 36 peut être remplacé par une ou plusieurs portions métalliques formant un ou plusieurs contacts Schottky avec les matériaux des puits quantiques. Dans ce cas, la ou les portions métalliques sont directement en contact avec les matériaux semiconducteurs des puits quantiques, sans matériau d'isolation disposé entre les matériaux semiconducteurs et le matériau métallique. Pour former un tel contact Schottky, le métal utilisé est de préférence choisi parmi des métaux présentant un travail de sortie important, comme par exemple le tungstène dont le travail de sortie est égal à environ 6,1 eV, ou du platine. Le choix du métal utilisé pour former de tels contacts Schottky dépend notamment des matériaux semiconducteurs utilisés. Enfin, la mise en oeuvre pratique des modes de réalisation et variantes décrits est à la portée de l'homme du métier à partir des indications fonctionnelles données ci- dessus . Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will be apparent to those skilled in the art. In particular, in the embodiments described above, the assembly comprising a gate 38 and the insulating layer 36 can be replaced by one or more metal portions forming one or more Schottky contacts with the materials of the quantum wells. In this case, the metallic portion or portions are in direct contact with the semiconductor materials of the quantum wells, without any insulation material placed between the semiconductor materials and the metallic material. To form such a Schottky contact, the metal used is preferably chosen from metals exhibiting a work of important output, such as for example tungsten whose work output is equal to about 6.1 eV, or platinum. The choice of metal used to form such Schottky contacts depends in particular on the semiconductor materials used. Finally, the practical implementation of the embodiments and variants described is within the abilities of those skilled in the art based on the functional indications given above.

Claims

REVENDICATIONS
1. Dispositif optoélectronique (10 ; 55 ; 60) comprenant au moins des première et deuxième diodes électroluminescentes (DEL) comprenant chacune une première portion semiconductrice (30) dopée de type P et une deuxième portion semiconductrice (26) dopée de type N, une zone active (28) comprenant des puits quantiques multiples entre les première et deuxième portions semiconductrices , une couche conductrice (38) recouvrant les parois latérales (34) de la zone active (28) et au moins une partie de la première portion semiconductrice et une couche isolante (36) interposée entre les parois latérales (34) de la zone active (28) et d'au moins une partie de la couche conductrice, le dispositif comprenant des moyens de commande de la couche conductrice de la première diode électroluminescente indépendamment de la couche conductrice de la deuxième diode électroluminescente, le dispositif optoélectronique comprenant, pour chacune des première et deuxième diodes électroluminescentes, un premier plot conducteur (44) couplé électriquement à la première portion semiconductrice, un deuxième plot conducteur (42) couplé électriquement à la deuxième portion semiconductrice, et un troisième plot conducteur (46) couplé électriquement à la couche conductrice. 1. Optoelectronic device (10; 55; 60) comprising at least first and second light-emitting diodes (LEDs) each comprising a first semiconductor portion (30) doped P type and a second semiconductor portion (26) doped N type, a active area (28) comprising multiple quantum wells between the first and second semiconductor portions, a conductive layer (38) covering the side walls (34) of the active area (28) and at least part of the first semiconductor portion and a insulating layer (36) interposed between the side walls (34) of the active area (28) and at least part of the conductive layer, the device comprising means for controlling the conductive layer of the first light-emitting diode independently of the conductive layer of the second light-emitting diode, the optoelectronic device comprising, for each of the first and second light-emitting diodes, a first pl ot conductor (44) electrically coupled to the first semiconductor portion, a second conductive pad (42) electrically coupled to the second semiconductor portion, and a third conductive pad (46) electrically coupled to the conductive layer.
2. Dispositif optoélectronique selon la revendication 1, dans lequel, pour chacune des première et deuxième diodes électroluminescentes (DEL), la zone active (28) comprend des puits quantiques multiples. 2. An optoelectronic device according to claim 1, wherein, for each of the first and second light-emitting diodes (LEDs), the active area (28) comprises multiple quantum wells.
3. Dispositif optoélectronique selon la revendication 2, dans lequel, pour chaque zone active (28) , la composition du puits quantique (62) le plus proche de la première portion semiconductrice (30) est différente de la composition du puits quantique (62) le plus proche de la deuxième portion semiconductrice (26). 3. Optoelectronic device according to claim 2, in which, for each active area (28), the composition of the quantum well (62) closest to the first semiconductor portion (30) is different from the composition of the quantum well (62) closest to the second semiconductor portion (26).
4. Dispositif optoélectronique selon la revendication 3, dans lequel, pour chaque zone active (28), chaque puits quantique (62) comprend un composé ternaire avec des premier, deuxième et troisième éléments chimiques, dans lequel les concentrations massiques du premier élément chimique des puits quantiques (62) sont identiques, dans lequel les concentrations massiques du deuxième élément chimique des puits quantiques (62) sont identiques, et dans lequel la concentration massique du troisième élément chimique du puits quantique (62) le plus proche de la première portion semiconductrice (30) est différente de la concentration massique du troisième élément chimique du puits quantique (62) le plus proche de la deuxième portion semiconductrice (26). 4. An optoelectronic device according to claim 3, wherein, for each active area (28), each quantum well (62) comprises a ternary compound with first, second and third chemical elements, wherein the mass concentrations of the first chemical element of the quantum wells (62) are identical, in which the mass concentrations of the second chemical element of the quantum wells (62) are identical, and in which the mass concentration of the third chemical element of the quantum well (62) closest to the first semiconductor portion (30) is different from the mass concentration of the third chemical element of the quantum well (62) closest to the second semiconductor portion (26).
5. Dispositif optoélectronique selon la revendication 4, dans lequel la différence entre la concentration massique du troisième élément chimique du puits quantique (62) le plus proche de la première portion semiconductrice (30) et la concentration massique du troisième élément chimique du puits quantique (62) le plus proche de la deuxième portion semiconductrice (30) est supérieure à 10 points de pourcentage . The optoelectronic device according to claim 4, wherein the difference between the mass concentration of the third chemical element of the quantum well (62) closest to the first semiconductor portion (30) and the mass concentration of the third chemical element of the quantum well ( 62) closest to the second semiconductor portion (30) is greater than 10 percentage points.
6. Dispositif optoélectronique selon la revendication 4 ou 5, dans lequel le premier élément chimique est un élément du groupe III. 6. An optoelectronic device according to claim 4 or 5, wherein the first chemical element is an element of group III.
7. Dispositif optoélectronique selon l'une quelconque des revendications 3 à 6, dans lequel le premier élément chimique est le gallium. 7. An optoelectronic device according to any one of claims 3 to 6, wherein the first chemical element is gallium.
8. Dispositif optoélectronique selon l'une quelconque des revendications 3 à 7, dans lequel le deuxième élément chimique est un élément du groupe V. 8. An optoelectronic device according to any one of claims 3 to 7, wherein the second chemical element is a group V element.
9. Dispositif optoélectronique selon l'une quelconque des revendications 3 à 8, dans lequel le deuxième élément chimique est l'azote. 9. An optoelectronic device according to any one of claims 3 to 8, wherein the second chemical element is nitrogen.
10. Dispositif optoélectronique selon l'une quelconque des revendications 3 à 9, dans lequel le troisième élément chimique est un élément du groupe III. 10. An optoelectronic device according to any one of claims 3 to 9, wherein the third chemical element is a group III element.
11. Dispositif optoélectronique selon l'une quelconque des revendications 3 à 10, dans lequel le troisième élément chimique est l'indium. 11. An optoelectronic device according to any one of claims 3 to 10, wherein the third chemical element is indium.
12. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 11, dans lequel chaque diode électroluminescente (DEL) a une structure "mesa". 12. An optoelectronic device according to any one of claims 1 to 11, wherein each light emitting diode (LED) has a "mesa" structure.
13. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 12, dans lequel, pour chaque diode électroluminescente (DEL) , la deuxième portion semiconductrice (26) a la forme d'un fil. 13. An optoelectronic device according to any one of claims 1 to 12, wherein, for each light emitting diode (LED), the second semiconductor portion (26) is in the form of a wire.
14. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 13, dans lequel chaque diode électroluminescente (DEL) comprend, en outre, entre la zone active (28) et la première portion semiconductrice (30), une couche (66) de blocage d'électrons. 14. An optoelectronic device according to any one of claims 1 to 13, wherein each light emitting diode (LED) further comprises, between the active area (28) and the first semiconductor portion (30), a layer (66) of electron blocking.
15. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 14, dans lequel les premier et deuxième plots conducteurs (44, 42) sont isolés électriquement de la couche conductrice (38). 15. An optoelectronic device according to any one of claims 1 to 14, wherein the first and second conductive pads (44, 42) are electrically insulated from the conductive layer (38).
16. Procédé d'émission lumineuse à partir d'un dispositif optoélectronique (10 ; 55 ; 60) selon l'une quelconque des revendications 1 à 15, comportant l'application d'une première tension électrique entre les première et deuxième portions semiconductrices (26, 30) de chacune des première et deuxième diodes électroluminescentes (DEL) , l'application d'une deuxième tension électrique entre la couche conductrice (38) et la première portion semiconductrice (30) de la première diode électroluminescente et l'application d'une troisième tension électrique entre la couche conductrice (38) et la première portion semiconductrice (30) de la deuxième diode électroluminescente, la troisième tension électrique étant différente de la deuxième tension électrique. 16. A method of light emission from an optoelectronic device (10; 55; 60) according to any one of claims 1 to 15, comprising applying a first electrical voltage between the first and second semiconductor portions (26, 30) of each of the first and second light emitting diodes (LEDs), applying a second electrical voltage between the conductive layer (38) and the first semiconductor portion (30) of the first light emitting diode and the application of a third electrical voltage between the conductive layer (38) and the first semiconductor portion (30) of the second light emitting diode, the third electric voltage being different from the second electric voltage.
PCT/FR2020/050819 2019-05-21 2020-05-18 Optoelectronic device comprising light-emitting diodes WO2020234534A1 (en)

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KR1020217037465A KR20220010495A (en) 2019-05-21 2020-05-18 Optoelectronic device having light emitting diodes
JP2021568396A JP7555128B2 (en) 2019-05-21 2020-05-18 Optoelectronic devices with light emitting diodes
US17/609,357 US20220320367A1 (en) 2019-05-21 2020-05-18 Optoelectronic device comprising light-emitting diodes
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150063395A1 (en) * 2009-03-30 2015-03-05 Osram Opto Semiconductors Gmbh Optoelectronic Semiconductor Chip
EP2960951A1 (en) * 2014-06-27 2015-12-30 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Optoelectronic device with p-n junction enabling the ionisation of dopants by field effect
US9245948B2 (en) 2012-09-18 2016-01-26 Aledia Optoelectric device with semiconductor microwires or nanowires and method for manufacturing the same
EP3185294A1 (en) * 2015-12-23 2017-06-28 Commissariat à l'énergie atomique et aux énergies alternatives Optoelectronic light-emitting device
WO2017216445A1 (en) * 2016-06-17 2017-12-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for making a gallium nitride light-emitting diode

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002141495A (en) 2000-11-02 2002-05-17 Takashi Katoda Electronic device and optical device having micro structure manufactured using focused ion beam
JP2007184566A (en) 2005-12-06 2007-07-19 Canon Inc Semiconductor element using semiconductor nanowire, and display device and imaging device employing same
US20110089400A1 (en) 2008-04-15 2011-04-21 Qunano Ab Nanowire wrap gate devices
JP4778107B1 (en) * 2010-10-19 2011-09-21 有限会社ナプラ Light emitting device and manufacturing method thereof
FR3004005B1 (en) * 2013-03-28 2016-11-25 Commissariat Energie Atomique MULTI-QUANTUM WELL ELECTROLUMINESCENT DIODE AND ASYMMETRIC P-N JUNCTION
FR3066320B1 (en) * 2017-05-11 2019-07-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR MANUFACTURING EMISSIVE LED DISPLAY DEVICE
FR3073669B1 (en) * 2017-11-10 2021-11-05 Commissariat Energie Atomique METHOD OF MANUFACTURING AN OPTOELECTRONIC DEVICE INCLUDING A PLURALITY OF DIODES

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150063395A1 (en) * 2009-03-30 2015-03-05 Osram Opto Semiconductors Gmbh Optoelectronic Semiconductor Chip
US9245948B2 (en) 2012-09-18 2016-01-26 Aledia Optoelectric device with semiconductor microwires or nanowires and method for manufacturing the same
EP2960951A1 (en) * 2014-06-27 2015-12-30 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Optoelectronic device with p-n junction enabling the ionisation of dopants by field effect
EP3185294A1 (en) * 2015-12-23 2017-06-28 Commissariat à l'énergie atomique et aux énergies alternatives Optoelectronic light-emitting device
WO2017216445A1 (en) * 2016-06-17 2017-12-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for making a gallium nitride light-emitting diode

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