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WO2020224422A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2020224422A1
WO2020224422A1 PCT/CN2020/085692 CN2020085692W WO2020224422A1 WO 2020224422 A1 WO2020224422 A1 WO 2020224422A1 CN 2020085692 W CN2020085692 W CN 2020085692W WO 2020224422 A1 WO2020224422 A1 WO 2020224422A1
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WIPO (PCT)
Prior art keywords
coupled
node
transistor
pull
electrode
Prior art date
Application number
PCT/CN2020/085692
Other languages
English (en)
French (fr)
Inventor
王迎
蔡莲姬
李红敏
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2020224422A1 publication Critical patent/WO2020224422A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • the gate drive circuit (also called the scan drive circuit) is an important part of the display device.
  • the gate drive circuit includes a multi-stage cascaded shift register, each stage of which is coupled to a row of gate lines in the display screen. Pick up.
  • the function of the gate drive circuit is to output the switching state voltage of the TFT (Thin Film Transistor) device in an orderly manner line by line, that is, output scan signals to the gate lines in the display screen line by line (also called gate signals) , So that the multiple TFTs coupled to the same gate line in the display screen are turned on row by row, and when multiple TFTs coupled to a row of gate lines are turned on, the pixel voltage is input to the pixel electrode of each sub-pixel through the data line To display the screen.
  • TFT Thin Film Transistor
  • a shift register including: an input sub-circuit; the input sub-circuit is coupled to a signal input terminal.
  • the input sub-circuit includes: a first input control unit and a boosting unit.
  • the first input control unit is coupled to a first clock signal terminal, a first node, a second node, and a pull-up node; the first node is configured to receive an input signal transmitted by the signal input terminal.
  • the supercharging unit is coupled between the first node and the second node.
  • the first input control unit is configured to: under the control of the voltage of the first node, transmit the first clock signal received at the first clock signal terminal to the upper node via the second node. Pull the node.
  • the boosting unit is configured to: under the action of the first clock signal, when the potential of the second node rises, boost the voltage of the first node, so that the first clock signal is controlled by the The voltage loss during the transmission of the first input control unit to the pull-up node is reduced.
  • the first input control unit includes: a first transistor and a second transistor.
  • the control electrode of the first transistor is coupled to the first node, the first electrode of the first transistor is coupled to the first clock signal terminal, and the second electrode of the first transistor is coupled to the first node.
  • the control electrode of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the pull-up node Coupling.
  • the boosting unit includes: a first capacitor; a first pole of the first capacitor is coupled to the first node, and a second pole of the first capacitor is coupled to the second node.
  • the signal input terminal is coupled to the first node.
  • the input sub-circuit further includes: a second input control unit.
  • the signal input terminal is coupled to the first node through the second input control unit; the second input control unit is configured to respond to the input signal received at the signal input terminal to input The signal is transmitted to the first node.
  • the shift register when the shift register further includes a second input control unit: the second input control unit includes a third transistor; the control electrode and the first electrode of the third transistor are connected to the The signal input terminal is coupled, and the second electrode of the third transistor is coupled to the first node.
  • the shift register further includes: an input reset sub-circuit.
  • the input reset sub-circuit is coupled to the second clock signal terminal, the first voltage signal terminal, and the first node; the input reset sub-circuit is configured to respond to the second clock signal terminal received at the second clock signal terminal A second clock signal, transmitting the first voltage signal received at the first voltage signal terminal to the first node, so as to reset the first node.
  • the input reset sub-circuit includes a fourth transistor.
  • the control electrode of the fourth transistor is coupled to the second clock signal terminal, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the The first node is coupled.
  • the shift register further includes: an output sub-circuit.
  • the output sub-circuit is coupled to the second clock signal terminal, the pull-up node, the scan signal output terminal and the cascade signal output terminal; the output sub-circuit is configured to control the voltage of the pull-up node Next, the second clock signal received at the second clock signal terminal is transmitted to the scan signal output terminal and the cascade signal output terminal.
  • the output sub-circuit includes a fifth transistor, a sixth transistor, and a second capacitor.
  • the control electrode of the fifth transistor is coupled to the pull-up node, the first electrode of the fifth transistor is coupled to the second clock signal terminal, and the second electrode of the fifth transistor is coupled to the stage The signal output terminal is coupled.
  • the control electrode of the sixth transistor is coupled to the pull-up node, the first electrode of the sixth transistor is coupled to the second clock signal terminal, and the second electrode of the sixth transistor is coupled to the scan The signal output terminal is coupled.
  • the first pole of the second capacitor is coupled to the pull-up node, and the second pole is coupled to the cascade signal output terminal.
  • the shift register further includes an initialization sub-circuit, a pull-down control sub-circuit, a first noise reduction sub-circuit, and a second noise reduction sub-circuit.
  • the initialization sub-circuit is coupled to the initialization signal terminal, the first voltage signal terminal and the pull-up node; the initialization sub-circuit is configured to respond to the initialization signal received at the initialization signal terminal, The first voltage signal received at the first voltage signal terminal is transmitted to the pull-up node.
  • the pull-down control sub-circuit is coupled to the reset signal terminal, the third clock signal terminal, the first voltage signal terminal, the pull-up node, and the pull-down node; the pull-down control circuit is configured to respond to the The third clock signal received at the third clock signal terminal transmits the reset signal received at the reset signal terminal to the pull-down node; and, under the control of the voltage of the pull-up node, the The first voltage signal received at the first voltage signal terminal is transmitted to the pull-down node.
  • the first noise reduction sub-circuit is coupled to the pull-down node, the first voltage signal terminal and the pull-up node; the first noise reduction sub-circuit is configured to control the voltage at the pull-down node Next, transmitting the first voltage signal received at the first voltage signal terminal to the pull-up node.
  • the second noise reduction circuit is coupled to the pull-down node, the first voltage signal terminal, the scan signal output terminal, and the cascade signal output terminal; the second noise reduction sub-circuit is configured to: Under the control of the voltage of the node, the first voltage signal received at the first voltage signal terminal is transmitted to the scan signal output terminal and the cascade signal output terminal.
  • the initialization sub-circuit includes a seventh transistor; the control electrode of the seventh transistor is coupled to the initialization signal terminal, and the first electrode of the seventh transistor is connected to the first voltage signal terminal. Coupled, the second electrode of the seventh transistor is coupled to the pull-up node.
  • the pull-down control circuit includes an eighth transistor and a ninth transistor.
  • the control electrode of the eighth transistor is coupled to the third clock signal terminal, the first electrode of the eighth transistor is coupled to the reset signal terminal, and the second electrode of the eighth transistor is coupled to the pull-down terminal. Node coupling; the control electrode of the ninth transistor is coupled to the pull-up node, the first electrode of the ninth transistor is coupled to the first voltage signal terminal, and the second electrode of the ninth transistor Coupled with the pull-down node.
  • the first noise reduction sub-circuit includes a tenth transistor; the control electrode of the tenth transistor is coupled to the pull-down node, and the first electrode of the tenth transistor is coupled to the first voltage signal terminal, so The second electrode of the tenth transistor is coupled to the pull-up node.
  • the second noise reduction sub-circuit includes an eleventh transistor and a twelfth transistor.
  • the control electrode of the eleventh transistor is coupled to the pull-down node, the first electrode of the eleventh transistor is coupled to the first voltage signal terminal, and the second electrode of the eleventh transistor is coupled to the The cascade signal output terminal is coupled; the control electrode of the twelfth transistor is coupled to the pull-down node, the first electrode of the twelfth transistor is coupled to the first voltage signal terminal, and the The second pole of the twelve transistor is coupled to the scan signal output terminal.
  • the shift register further includes: an input reset sub-circuit, an output sub-circuit, an initialization sub-circuit, a pull-down control sub-circuit, a first noise reduction sub-circuit, and a second noise reduction sub-circuit.
  • the input sub-circuit includes a first transistor, a second transistor, a third transistor, and a first capacitor
  • the input reset sub-circuit includes a fourth transistor
  • the output sub-circuit includes a fifth transistor, a sixth transistor, and a first capacitor.
  • the initialization sub-circuit includes a seventh transistor; the pull-down control sub-circuit includes an eighth transistor and a ninth transistor; the first noise reduction sub-circuit includes a tenth transistor; the second noise reduction sub-circuit includes The eleventh transistor and the twelfth transistor.
  • the control electrode of the first transistor is coupled to the first node, the first electrode of the first transistor is coupled to the first clock signal terminal, and the second electrode of the first transistor is coupled to the first node.
  • Two-node coupling The control electrode of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the pull-up node Coupling.
  • the control electrode and the first electrode of the third transistor are coupled to the signal input terminal, and the second electrode of the third transistor is coupled to the first node.
  • the first pole of the first capacitor is coupled to the first node, and the second pole of the first capacitor is coupled to the second node.
  • the control electrode of the fourth transistor is coupled to the second clock signal terminal, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the The first node is coupled.
  • the control electrode of the fifth transistor is coupled to the pull-up node, the first electrode of the fifth transistor is coupled to the second clock signal terminal, and the second electrode of the fifth transistor is coupled to the stage The signal output terminal is coupled.
  • the control electrode of the sixth transistor is coupled to the pull-up node, the first electrode of the sixth transistor is coupled to the second clock signal terminal, and the second electrode of the sixth transistor is coupled to the scan The signal output terminal is coupled.
  • the first pole of the second capacitor is coupled to the pull-up node, and the second pole is coupled to the cascade signal output terminal.
  • the control electrode of the seventh transistor is coupled to the initialization signal terminal, the first electrode of the seventh transistor is coupled to the first voltage signal terminal, and the second electrode of the seventh transistor is coupled to the upper Pull node coupling.
  • the control electrode of the eighth transistor is coupled to the third clock signal terminal, the first electrode of the eighth transistor is coupled to the reset signal terminal, and the second electrode of the eighth transistor is coupled to the pull-down terminal. Node coupling.
  • the control electrode of the ninth transistor is coupled to the pull-up node, the first electrode of the ninth transistor is coupled to the first voltage signal terminal, and the second electrode of the ninth transistor is coupled to the pull-down node. Node coupling.
  • the control electrode of the tenth transistor is coupled to the pull-down node, the first electrode of the tenth transistor is coupled to the first voltage signal terminal, and the second electrode of the tenth transistor is coupled to the pull-up node. Node coupling.
  • the control electrode of the eleventh transistor is coupled to the pull-down node, the first electrode of the eleventh transistor is coupled to the first voltage signal terminal, and the second electrode of the eleventh transistor is coupled to the The cascade signal output terminal is coupled.
  • the control electrode of the twelfth transistor is coupled to the pull-down node, the first electrode of the twelfth transistor is coupled to the first voltage terminal signal, and the second electrode of the twelfth transistor is coupled to the The scanning signal output terminal is coupled.
  • one frame period includes a precharge phase and an input phase
  • the first node receives the input signal transmitted by the signal input terminal .
  • the first input control unit is turned on, and the first clock signal received at the first clock signal terminal is transmitted to the all through the second node.
  • the pull-up node is described.
  • the boosting unit boosts the voltage of the first node, so that the first clock signal is transmitted from the first input control unit to the pull-up node. The voltage loss is reduced.
  • the input sub-circuit of the shift register further includes a second input control unit, in the precharge stage: under the control of the input signal transmitted by the signal input terminal, the The second input control unit is turned on and transmits the input signal to the first node.
  • one frame period further includes an output stage located after the input stage, in the output stage: in the second Under the control of the second clock signal transmitted by the clock signal terminal, the input reset sub-circuit is turned on, and the first voltage signal received at the first voltage signal terminal is transmitted to the first node to correct the A node is reset. Under the control of the voltage of the pull-up node, the output sub-circuit is turned on, and the second clock signal received at the second clock signal terminal is transmitted to the scan signal output terminal and the cascade signal output end.
  • a gate driving circuit comprising the shift register according to any one of claims 1 to 11 with N stages cascaded; wherein, N is a positive integer.
  • the gate drive In the circuit: the signal input terminal of the first stage shift register is coupled with the start signal terminal; the signal input terminal of the second stage shift register is coupled with the start signal terminal.
  • the signal input terminal of the i-th stage shift register is coupled to the cascade signal output terminal of the i-2th stage shift register; wherein, 3 ⁇ i ⁇ N; i is a positive integer.
  • the reset signal end of the j-th shift register is coupled to the cascade signal output end of the j+1-th shift register; 1 ⁇ j ⁇ N-1; j is a positive integer.
  • the reset signal terminal of the Nth stage shift register is set separately or coupled to the start signal terminal.
  • the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal of the 3t+1 stage shift register are connected to the first system clock signal terminal, the second system clock signal terminal, and the The three system clock signal terminals are coupled.
  • the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal of the 3t+2 stage shift register are respectively connected to the second system clock signal terminal, the third system clock signal terminal, and the A system clock signal terminal is coupled.
  • the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal of the 3t+3 stage shift register are respectively connected to the third system clock signal terminal, the first system clock signal terminal, and the Two system clock signal terminals are coupled.
  • 3t+3 ⁇ N, and t is a non-negative integer.
  • a display device including the gate driving circuit described above.
  • FIG. 1 is a structural diagram of a shift register according to some embodiments of related technologies
  • FIG. 2A is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • 2B is another structural diagram of a display panel according to some embodiments of the present disclosure.
  • Fig. 3 is a structural diagram of a shift register according to some embodiments of the present disclosure.
  • Fig. 4 is another structural diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 5 is a structural diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 6 is a timing diagram of a driving method of a shift register according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [the stated condition or event] is detected” or “in response to the detection of [stated condition or event]”.
  • the shift register in the gate drive circuit is mainly composed of transistors, capacitors and other devices. During the operation of the shift register, the potential of the internal control node is controlled by the transistors and capacitors to realize the output of scanning signals. However, due to the threshold loss of the electrical signal in the process of transmitting through the transistor, the voltage of the control node is likely to be insufficient, which causes the output of the shift register to be abnormal, and thus the display is abnormal.
  • the shift register includes an input sub-circuit, an output sub-circuit, a noise reduction sub-circuit, and a control sub-circuit, etc., to achieve basic input, output, and control nodes
  • the potential control function includes a pull-up node PU and a pull-down node PD.
  • the transistor T1 is turned on under the control of the first clock signal clk1 transmitted by the first clock signal terminal CLK1, and will be at the signal input terminal Iput.
  • the received input signal input is transmitted to the pull-up node PU, the storage capacitor C stores the voltage of the pull-up node, and the transistor T2 is turned on under the control of the voltage of the pull-up node PU.
  • the level of the second clock signal clk2 transmitted by the second clock signal terminal CLK2 changes to a high level, and the storage capacitor C raises the voltage of the pull-up node PU through the bootstrap action, so that the transistor T2 is at the pull-up node Continuously conducting under the control of the voltage of, the second clock signal clk2 is transmitted to the signal output terminal Oput, so that the shift register outputs the scanning signal.
  • the voltage value V input of the input signal input has a threshold loss, that is, the transistor T1 cannot input the complete voltage value V input of the input signal
  • the voltage of the pull-up node PU can only reach V clk1 -Vth, where V clk1 is the high-level voltage of the first clock signal clk1, and Vth is the threshold voltage of the transistor T1.
  • the condition that the transistor T1 is turned on is that the gate-source voltage difference Vgs of the transistor is greater than its threshold voltage Vth.
  • the input signal is input from its first pole. (Drain) transfer to the second electrode (source), the voltage of the second electrode of the transistor T1 gradually increases, when the voltage value reaches V clk1 -Vth, if the voltage of the second electrode of the transistor T1 continues to increase If it is large, the conduction condition cannot be satisfied.
  • the voltage value of the signal generated by the system is usually specific, for example, the voltage value V input of the input signal input is equal to the high-level voltage V clk1 of the first clock signal clk1.
  • the voltage of the pull-up node PU is insufficient, that is, the potential of the control electrode of the transistor T2 is low, which will affect the conduction degree of the transistor T2, thereby affecting the transmission of the second clock signal clk2 to the signal output terminal Oput.
  • the second clock signal clk2 also has the problem of threshold voltage loss during the process of transmitting the second clock signal clk2 from the transistor T2 to the signal output terminal Oput, resulting in the voltage value of the scan signal output by the shift register If it is lower, the output is abnormal, which affects the stability of the shift register, and the setting causes the display effect of the display device to be affected.
  • some embodiments of the present disclosure provide a shift register and a driving method thereof, as well as a gate driving circuit and a display device, so as to solve the problem of abnormal scanning signal output due to the threshold loss in the transmission process of electrical signals in the related art , which in turn leads to the problem of abnormal display.
  • the following describes the display device, the gate driving circuit, and the shift register in order from largest to smallest.
  • An embodiment of the present disclosure provides a display device, which may be any device that displays an image regardless of motion (for example, video) or fixed (for example, still image) and regardless of text or image. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/n
  • the display device includes a frame, a display panel arranged in the frame, a circuit board, a display driver IC (Integrated Circuit, integrated circuit), and other electronic accessories.
  • a display driver IC Integrated Circuit, integrated circuit
  • the above-mentioned display panel may be: Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) display panel, Quantum Dot Light Emitting Diodes (QLED) display panel, etc., This disclosure does not specifically limit this.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • the following embodiments of the present disclosure are all examples of the above-mentioned display panel being a liquid crystal display panel to illustrate the present disclosure.
  • the above-mentioned display panel PNL includes: a display area (active display area, AA; AA area for short; also called an effective display area) and a peripheral area arranged in a circle around the AA area.
  • a display area active display area, AA; AA area for short; also called an effective display area
  • a peripheral area arranged in a circle around the AA area.
  • the sub-pixels P of multiple colors are arranged in the AA area of the above-mentioned display panel PNL.
  • the sub-pixels of multiple colors include at least a first color sub pixel, a second color sub pixel, and a third color sub pixel.
  • the first color, the second color, and the third color are three primary colors (for example, red, green, and blue).
  • the above-mentioned multiple sub-pixels P in the present application are described by taking the arrangement of a matrix as an example.
  • the sub-pixels P arranged in a row along the horizontal direction X are called sub-pixels in the same row; the sub-pixels P arranged in a row along the vertical direction Y are called sub-pixels in the same column.
  • each sub-pixel P is provided with a pixel driving circuit S
  • the pixel driving circuit S includes a transistor T and a liquid crystal capacitor C.
  • the two plates of the liquid crystal capacitor C are respectively composed of a pixel electrode and a common electrode.
  • the control electrode (gate) of the transistor T in the pixel driving circuit S located in the same row is coupled to the same gate line (Gate Line) GL to be turned on under the control of the scanning signal transmitted by the gate line GL, and located in the same column
  • One pole (for example, the source) of the transistor T of the pixel driving circuit S is coupled to the same data line (Data Line) DL, so as to receive the data signal transmitted by the data line DL when the transistor T is turned on.
  • the peripheral area of the display panel PNL is provided with a gate driving circuit 01 and a data driving circuit 02.
  • the gate driving circuit 01 may be disposed on the side along the extension direction of the gate line GL
  • the data driving circuit 02 may be disposed on the side along the extension direction of the data line DL to drive the display panel.
  • Pixel drive circuit for display may be disposed on the side along the extension direction of the data line DL.
  • the aforementioned gate driving circuit 01 may be a gate driving IC.
  • the gate driving circuit 01 may be a GOA (Gate Driver on Array) circuit, that is, the gate driving circuit 01 is directly integrated in the array substrate of the display panel PNL.
  • the gate driving circuit 01 is configured as a GOA circuit.
  • the manufacturing cost of the display panel can be reduced, and on the other hand, the frame width of the display device can be narrowed.
  • the following embodiments are all described by taking the gate driving circuit 01 as a GOA circuit as an example.
  • FIGS. 2A and 2B are only schematic.
  • the display panel PNL is used to set the gate driving circuit 01 on a single side of the peripheral area, and the gate lines GL are driven row by row from the single side, that is, the single side driving is Example to illustrate.
  • the display panel PNL may be provided with gate driving circuits on two sides along the extension direction of the gate line GL in the peripheral area, and the two gate driving circuits are simultaneously driven row by row from both sides.
  • Each gate line GL is driven on both sides.
  • the display panel PNL may be provided with gate driving circuits on two sides along the extension direction of the gate line GL in the peripheral area, and the two gate driving circuits alternately from both sides, row by row.
  • the gate lines GL are sequentially driven, that is, cross-driving.
  • the gate driving circuit 01 includes N stages of cascaded shift registers (RS1, RS2...RS(N)).
  • the display panel PNL It includes N stages of cascaded shift registers (RS1, RS2...RS(N)) respectively correspondingly coupled to N gate lines (G1, G2...G(N)), where N is a positive integer.
  • the terminal outputs cascaded signals (such as input signals, reset signals, etc.) to other shift registers, resulting in unstable output of the gate drive circuit 01; as shown in FIG.
  • each shift register is independently set with a scan signal output terminal Output_o (hereinafter and in the drawings, Output is abbreviated as Oput) and a cascade signal output terminal Oput_c, thereby outputting a gate scanning signal to the gate line GL coupled to the scanning signal output terminal Oput_o, and outputting a cascading signal through the cascading signal output terminal Oput_c, thereby ensuring the stability of the signal output of the gate driving circuit 01.
  • Output_o hereinafter and in the drawings, Output is abbreviated as Oput
  • Oput_c cascade signal output terminal
  • the shift register (RS1, RS2...RS(N)) of the gate drive circuit 01 of the present disclosure is also provided with a signal input terminal Input (the drawings and the following are both Abbreviated as Iput), reset signal terminal Reset (abbreviated as RST in the drawings and below), and the circuit structure of the shift registers at all levels in the gate drive circuit 01 is the same.
  • Iput the drawings and the following are both Abbreviated as Iput
  • RST reset signal terminal Reset
  • the signal input terminal Iput of the previous stage or multi-stage shift register is coupled to the start signal terminal STV, except for the shift register coupled to the start signal terminal STV, the signal input terminal of any other stage shift register Iput is coupled to the signal output terminal Oput of the shift register at the previous stage; the reset signal terminal RST of the last stage or multi-stage shift register is independently set or coupled to the aforementioned start signal terminal STV; except for the last stage Or in addition to the multi-stage shift register, the reset signal terminal RST of any shift register is coupled to the signal output terminal Oput of the shift register at the subsequent stage.
  • the signal input terminal Iput of the first-stage shift register RS1 is coupled to the start signal terminal STV, and other shift registers (RS2, RS3...RS( N)), the signal input terminal Iput of the shift register of any stage is coupled to the signal output terminal Oput of the shift register at the previous stage.
  • the reset signal terminal RST of the last stage shift register RS(N) is set independently; other shift registers (RS1, RS2...RS(N-1)) except the last stage shift register RS(N), any The reset signal terminal RST of the shift register of one stage is coupled to the signal output terminal Oput of the shift register of the subsequent stage.
  • a pull-up node PU and a pull-down node PD are also provided in the shift register.
  • Potential control to realize normal output of shift register during the operation of the shift register, the potentials of the pull-up node PU and the pull-down node PD are always a set of inverted potentials; for example, when the potential of the pull-up node PU is high, the potential of the pull-down node PD The potential is low; when the potential of the pull-up node PU is low, the potential of the pull-down node PD is high.
  • the shift register provided by some embodiments of the present disclosure further includes: an input sub-circuit 100, which is coupled to the signal input terminal Iput.
  • the first node A is configured to receive the input signal input transmitted by the signal input terminal Iput.
  • the aforementioned input sub-circuit 100 includes: a first input control unit 101 and a boosting unit 102.
  • the above-mentioned first input control unit 101 is coupled to the first clock signal terminal CLK1, the first node A, the second node B, and the pull-up node PU; the first input control unit 101 is configured to: the voltage at the first node A Under the control of, the first clock signal clk1 received at the first clock signal terminal CLK1 is output to the pull-up node PU via the second node B.
  • the above-mentioned boosting unit 102 is coupled between the first node A and the second node B; the boosting unit 102 is configured to: under the action of the first clock signal clk1, boost the voltage of the first node A to make the first node A
  • the voltage loss of a clock signal clk1 in the process of being transmitted from the first input control unit to the pull-up node PU is reduced, and the voltage loss here refers to the threshold voltage loss.
  • the aforementioned first input control unit 101 includes: a first transistor M1 and a second transistor M2.
  • control electrode of the first transistor M1 is coupled to the first node A
  • first electrode of the first transistor M1 is coupled to the first clock signal terminal CLK1
  • second electrode of the first transistor M2 is coupled to the second node B .
  • the first transistor M1 is configured to be turned on under the control of the voltage of the first node A, and transmits the first clock signal clk1 to the second node B.
  • the control electrode of the second transistor M2 is coupled to the first node A, the first electrode of the second transistor M2 is coupled to the second node B, and the second electrode of the second transistor M2 is coupled to the pull-up node PU.
  • the second transistor M2 is configured to be turned on under the control of the voltage of the first node A, and transmits the first clock signal clk1 transmitted to the second node B to the pull-up node PU.
  • the boosting unit 102 includes: a first capacitor C1; wherein, a first pole of the first capacitor C1 is coupled to a first node A, and a second pole of the first capacitor C1 is coupled to The second node B is coupled. According to the bootstrap action of the capacitor, under the action of the first clock signal clk1 transmitted to the second node B, the voltage of the second node B rises, so that the voltage of the first node A is raised.
  • the first node A receives the input signal input transmitted by the signal input terminal Iput, for example, the voltage of the first node A at this time is the voltage value V input of the input signal input .
  • the first transistor M1 and the second transistor M2 are turned on, and the first clock signal clk1 is transmitted to the second node B, and then to the pull-up node PU. In this process, the second The potential of the node B rises.
  • the voltage of the second node B at this time is the high-level voltage value V clk1 of the first clock signal clk1 , so that under the bootstrap action of the first capacitor C1, the potential of the first node A rises, It becomes V input +V clk1 .
  • the voltage of the control electrodes of the first transistor M1 and the second transistor M2 increases to V input +V clk1 , so that the gate-source voltage difference Vgs of the first transistor M1 and the second transistor M2 increases, which is much larger than the first transistor M1 and the second transistor M2.
  • the threshold voltages of the transistor M1 and the second transistor M2 so that the first transistor M1 can transmit the complete voltage value V clk1 of the first clock signal clk1 to the second node B, and the second transistor M2 can transmit the first signal received by the second node B
  • the complete voltage value V clk1 of a clock signal clk1 is transmitted to the pull-up node PU.
  • the first transistor M1 and the second transistor M2 can always meet the conduction condition, and the first clock signal clk1 is The threshold voltage loss during the transmission from the first input control unit 101 to the pull-up node PU is reduced, or even no threshold voltage loss, so that the voltage value of the pull-up node PU can meet the requirements, for example, the voltage value of the pull-up node PU is the first The complete voltage value V clk1 of a clock signal clk1 .
  • the first node A receives the input signal transmitted by the signal input terminal Iput, so that the voltage of the first node A increases ( For example, approximately V input ), under the voltage control of the first node A, the first clock signal clk1 received at the first clock signal terminal CLK1 is output to the pull-up node via the second node B through the first input control unit 101 PU, at the same time, the voltage of the second node B rises under the action of the first clock signal clk1, so that the voltage of the first node A is further raised by the boosting unit 102 (for example, the voltage of the first node A is The voltage can reach approximately V input +V clk1 ), which means that the voltage of the control electrode of the transistor in the first input control unit 101 is raised, so that the first clock signal clk1 is transmitted from the first input control unit 101 to the pull-up node PU.
  • the threshold voltage loss in the process is reduced or even no voltage loss, so that the completed voltage value V clk1 of the first clock signal clk1 can be transmitted to the pull-up node PU, thereby avoiding the phenomenon of insufficient potential of the pull-up node PU, thereby ensuring Stable output of shift register.
  • the signal input terminal Iput is coupled to the first node A.
  • the input sub-circuit 100 further includes a second input control unit 103.
  • the signal input terminal Iput is coupled to the first node A through the second input control unit 103; the second input control unit 103 is configured to transmit the input signal input to the first node A in response to the input signal input received at the signal input terminal Iput One node A.
  • the aforementioned second input control unit 103 includes a third transistor M3.
  • the control electrode and the first electrode of the third transistor M3 are coupled to the signal input terminal Iput, and the second electrode of the third transistor M3 is coupled to the first node A.
  • the third transistor M3 is configured to be turned on under the control of the input signal input to transmit the input signal input to the first node A.
  • the shift register further includes: an input reset sub-circuit 200.
  • the input reset sub-circuit 200 is coupled to the second clock signal terminal CLK2, the first voltage signal terminal VGL and the first node A.
  • the input reset sub-circuit 200 is configured to: in response to the second clock signal clk2 received at the second clock signal terminal CLK2, transmit the first voltage signal vgl received at the first voltage signal terminal VGL to the first node A. Therefore, the first node A is reset by the first voltage signal vgl to improve the output stability of the shift register.
  • the aforementioned input reset sub-circuit 200 includes a fourth transistor M4.
  • the control electrode of the fourth transistor M4 is coupled to the second clock signal terminal CLK2, the first electrode of the fourth transistor M4 is coupled to the first voltage signal terminal VGL, and the second electrode of the fourth transistor M4 is coupled to the first node A Coupling.
  • the fourth transistor M4 is configured to be turned on under the control of the second clock signal clk2 to transmit the first voltage signal vgl to the first node A.
  • the shift register also includes an output sub-circuit, a noise reduction sub-circuit, and a pull-up node PU,
  • Other related control circuits coupled to the pull-down node PD are not specifically limited in the present disclosure. In practice, appropriate related circuits can be selected and set according to requirements.
  • the shift register provided by the present disclosure further includes an output sub-circuit 300, the output sub-circuit 300 and the second clock signal terminal CLK2, the pull-up node PU, and the scan signal output terminal Oput_o is coupled to the cascade signal output terminal Oput_c.
  • the output sub-circuit 300 is configured to: under the control of the voltage of the pull-up node PU, transmit the second clock signal clk2 received at the second clock signal terminal CLK2 to the scan signal output terminal Oput_o and the cascade signal output terminal Oput_c .
  • the aforementioned output sub-circuit 300 includes a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.
  • the control electrode of the fifth transistor M5 is coupled to the pull-up node PU, the first electrode of the fifth transistor M5 is coupled to the second clock signal terminal CLK2, and the second electrode of the fifth transistor M5 is coupled to the cascade signal output terminal Oput_c .
  • the fifth transistor M5 is configured to be turned on under the control of the voltage of the pull-up node PU, and transmit the second clock signal clk2 to the cascade signal output terminal Oput_c.
  • the control electrode of the sixth transistor M6 is coupled to the pull-up node PU, the first electrode of the sixth transistor M6 is coupled to the second clock signal terminal CLK2, and the second electrode of the sixth transistor M6 is coupled to the scan signal output terminal Oput_o.
  • the sixth transistor M6 is configured to be turned on under the control of the voltage of the pull-up node PU, and transmit the second clock signal clk2 to the scan signal output terminal Oput_o.
  • the first pole of the second capacitor C2 is coupled to the pull-up node PU, and the second pole of the second capacitor C2 is coupled to the cascade signal output terminal Oput_c.
  • the second capacitor C2 is configured to store the voltage of the pull-up node PU, and under the action of the second clock signal clk2, through the bootstrap action of the capacitor, the voltage of the pull-up node PU is raised.
  • the shift register includes the aforementioned input sub-circuit 100, input reset sub-circuit 200, and output sub-circuit 300, and further includes: an initialization sub-circuit 400, a pull-down control sub-circuit The circuit 500, the first noise reduction sub-circuit 600 and the second noise reduction sub-circuit 700.
  • the initialization sub-circuit 400 described above is coupled to the initialization signal terminal T_RST, the first voltage signal terminal VGL and the pull-up node PU.
  • the initialization sub-circuit 300 is configured to transmit the first voltage signal vgl received at the first voltage signal terminal VGL to the pull-up node PU in response to the initialization signal t_rst received at the initialization signal terminal T_RST.
  • the initialization sub-circuit 300 includes a seventh transistor M7.
  • the control electrode of the seventh transistor M7 is coupled to the initialization signal terminal T_RST, the first electrode of the seventh transistor M7 is coupled to the first voltage signal terminal VGL, and the second electrode of the seventh transistor M7 is coupled to the pull-up node PU .
  • the seventh transistor M7 is configured to transmit the first voltage signal vgl to the pull-up node PU under the control of the initialization signal t_rst.
  • the aforementioned pull-down control sub-circuit 400 is coupled to the reset signal terminal RST, the third clock signal terminal CLK3 and the pull-down node PD.
  • the pull-down control sub-circuit 400 is configured to transmit the reset signal rst received at the reset signal terminal RST to the pull-down node PD in response to the third clock signal clk3 received at the third clock signal terminal CLK3; and, in the pull-up Under the control of the voltage of the node PU, the first voltage signal vgl received at the first voltage signal terminal VGL is transmitted to the pull-down node PD.
  • the above-mentioned reset control circuit 400 includes an eighth transistor M8 and a ninth transistor M9.
  • the control electrode of the eighth transistor M8 is coupled to the third clock signal terminal CLK3, the first electrode of the eighth transistor M8 is coupled to the reset signal terminal RST, and the second electrode of the eighth transistor M8 is coupled to the pull-down node PU.
  • the eighth transistor M8 is configured to be turned on under the control of the third clock signal clk3 to transmit the reset signal rst to the pull-down node PD.
  • the control electrode of the ninth transistor M9 is coupled to the pull-up node PU, the first electrode of the ninth transistor M9 is coupled to the first voltage signal terminal VGL, and the second electrode of the ninth transistor M9 is coupled to the pull-down node PD.
  • the ninth transistor M9 is configured to be turned on under the control of the voltage of the pull-up node PU, and transmit the first voltage signal vgl to the pull-down node PD.
  • the aforementioned first noise reduction sub-circuit 600 is coupled to the pull-down node PD, the first voltage signal terminal VGL and the pull-up node PU.
  • the first noise reduction sub-circuit 500 is configured to: under the control of the voltage of the pull-down node PD, transmit the first voltage signal vgl received at the first voltage signal terminal VGL to the pull-up node PU, so as to contact the pull-up node PU. Perform noise reduction.
  • the above-mentioned first noise reduction sub-circuit 600 includes a tenth transistor M10.
  • the control electrode of the tenth transistor M10 is coupled to the pull-down node PD
  • the first electrode of the tenth transistor M10 is coupled to the first voltage signal terminal VGL
  • the second electrode of the tenth transistor M10 is coupled to the pull-up node PU.
  • the tenth transistor M10 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the pull-up node PU, so as to reduce the noise of the pull-up node PU.
  • the second noise reduction sub-circuit 700 is coupled to the pull-down node PD, the first voltage signal terminal VGL, the scan signal output terminal Oput_o, and the cascade signal output terminal Oput_c.
  • the second noise reduction sub-circuit 700 is configured to: under the control of the voltage of the pull-down node PD, transmit the first voltage signal vgl received at the first voltage signal terminal VGL to the scan signal output terminal Oput_o and the cascade signal output End Oput_c.
  • the second noise reduction sub-circuit 700 includes an eleventh transistor M11 and a twelfth transistor M12.
  • the control electrode of the eleventh transistor M11 is coupled to the pull-down node PD, the first electrode of the eleventh transistor M11 is coupled to the first voltage terminal VGL, and the second electrode of the eleventh transistor M11 is coupled to the cascade signal output terminal Oput_c Coupling.
  • the eleventh transistor M11 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the cascade signal output terminal Oput_c.
  • the control electrode of the twelfth transistor M12 is coupled to the pull-down node PD, the first electrode of the twelfth transistor M12 is coupled to the first voltage terminal VGL, and the second electrode of the twelfth transistor M12 is coupled to the scan signal output terminal Oput_o .
  • the twelfth transistor M12 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the scan signal output terminal Oput_o.
  • the shift register includes: an input sub-circuit 100, an input reset sub-circuit 200, an output sub-circuit 300, an initialization sub-circuit 400, a pull-down control sub-circuit 500, a first noise reduction sub-circuit 600, and a second noise reduction sub-circuit 700.
  • the input sub-circuit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, and a first capacitor C1.
  • the input reset sub-circuit 200 includes a fourth transistor M4.
  • the output sub-circuit 300 includes a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.
  • the initialization sub-circuit 400 includes a seventh transistor M7.
  • the pull-down control sub-circuit 500 includes an eighth transistor M8 and a ninth transistor M9.
  • the first noise reduction sub-circuit 600 includes a tenth transistor M10.
  • the second noise reduction sub-circuit 700 includes an eleventh transistor M11 and a twelfth transistor M12.
  • the control electrode of the first transistor M1 is coupled to the first node A, the first electrode of the first transistor M1 is coupled to the first clock signal terminal CLK1, and the second electrode of the first transistor M2 is coupled to the second node B.
  • the first transistor M1 is configured to be turned on under the control of the voltage of the first node A, and transmits the first clock signal clk1 to the second node B.
  • the control electrode of the second transistor M2 is coupled to the first node A, the first electrode of the second transistor M2 is coupled to the second node B, and the second electrode of the second transistor M2 is coupled to the pull-up node PU.
  • the second transistor M2 is configured to be turned on under the control of the voltage of the first node A, and transmits the first clock signal clk1 transmitted to the second node B to the pull-up node PU.
  • the first pole of the first capacitor C1 is coupled to the first node A, and the second pole of the first capacitor C1 is coupled to the second node B.
  • the first capacitor C1 is configured to raise the voltage of the first node A when the voltage of the second node B rises.
  • the control electrode and the first electrode of the third transistor M3 are coupled to the signal input terminal Iput, and the second electrode of the third transistor M3 is coupled to the first node A.
  • the third transistor M3 is configured to be turned on under the control of the input signal input to transmit the input signal input to the first node A.
  • the control electrode of the fourth transistor M4 is coupled to the second clock signal terminal CLK2, the first electrode of the fourth transistor M4 is coupled to the first voltage signal terminal VGL, and the second electrode of the fourth transistor M4 is coupled to the first node A .
  • the fourth transistor M4 is configured to be turned on under the control of the second clock signal clk2 to transmit the first voltage signal vgl to the first node A.
  • the control electrode of the fifth transistor M5 is coupled to the pull-up node PU, the first electrode of the fifth transistor M5 is coupled to the second clock signal terminal CLK2, and the second electrode of the fifth transistor M5 is coupled to the cascade signal output terminal Oput_c .
  • the fifth transistor M5 is configured to be turned on under the control of the voltage of the pull-up node PU, and transmit the second clock signal clk2 to the cascade signal output terminal Oput_c.
  • the control electrode of the sixth transistor M6 is coupled to the pull-up node PU, the first electrode of the sixth transistor M6 is coupled to the second clock signal terminal CLK2, and the second electrode of the sixth transistor M6 is coupled to the scan signal output terminal Oput_o.
  • the sixth transistor M6 is configured to be turned on under the control of the voltage of the pull-up node PU, and transmit the second clock signal clk2 to the scan signal output terminal Oput_o.
  • the first pole of the second capacitor C2 is coupled to the pull-up node PU, and the second pole of the second capacitor C2 is coupled to the cascade signal output terminal Oput_c.
  • the second capacitor C2 is configured to store the voltage of the pull-up node PU, and under the action of the second clock signal clk2, through the bootstrap action of the capacitor, the voltage of the pull-up node PU is raised.
  • the control electrode of the seventh transistor M7 is coupled to the initialization signal terminal T_RST, the first electrode of the seventh transistor M7 is coupled to the first voltage terminal VGL, and the second electrode of the seventh transistor M7 is coupled to the pull-up node PU.
  • the seventh transistor M7 is configured to transmit the first voltage signal vgl to the pull-up node PU under the control of the initialization signal t_rst.
  • the control electrode of the eighth transistor M8 is coupled to the third clock signal terminal CLK3, the first electrode of the eighth transistor M8 is coupled to the reset signal terminal RST, and the second electrode of the eighth transistor M8 is coupled to the pull-down node PU.
  • the eighth transistor M8 is configured to be turned on under the control of the third clock signal clk3 to transmit the reset signal rst to the pull-down node PD.
  • the control electrode of the ninth transistor M9 is coupled to the pull-up node PU, the first electrode of the ninth transistor M9 is coupled to the first voltage signal terminal VGL, and the second electrode of the ninth transistor M9 is coupled to the pull-down node PU.
  • the ninth transistor M9 is configured to be turned on under the control of the voltage of the pull-up node PU, and transmit the first voltage signal vgl to the pull-down node PD.
  • the control electrode of the tenth transistor M10 is coupled to the pull-down node PD, the first electrode of the tenth transistor M10 is coupled to the first voltage signal terminal VGL, and the second electrode of the tenth transistor M10 is coupled to the pull-up node PU.
  • the tenth transistor M10 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the pull-up node PU, so as to reduce the noise of the pull-up node PU.
  • the control electrode of the eleventh transistor M11 is coupled to the pull-down node PD, the first electrode of the eleventh transistor M11 is coupled to the first voltage terminal VGL, and the second electrode of the eleventh transistor M11 is coupled to the cascade signal output terminal Oput_c Pick up.
  • the eleventh transistor M11 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the cascade signal output terminal Oput_c.
  • the control electrode of the twelfth transistor M12 is coupled to the pull-down node PD, the first electrode of the twelfth transistor M12 is coupled to the first voltage terminal VGL, and the second electrode of the twelfth transistor M12 is coupled to the scan signal output terminal Oput_o .
  • the twelfth transistor M12 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the scan signal output terminal Oput_o.
  • the signal input terminal Iput of the first stage shift register RS1 is coupled to the start signal terminal (STV1); the signal input terminal Iput of the second stage shift register RS2 is coupled to the start signal terminal (STV2).
  • STV1 and STV2 can be coupled to each other; or, STV1 and STV2 can be set independently.
  • the signal input terminal Iput of the i-th stage shift register RSi is coupled to the cascade signal output terminal Oput_c of the i-2th stage shift register RS(i-2); among them, 3 ⁇ i ⁇ N; i is a positive integer variable.
  • the reset signal terminal RST of the j-th shift register RSj is coupled to the cascade signal output terminal Oput_c of the j+1-th shift register RS(j+1); 1 ⁇ j ⁇ N-1; j is a positive integer variable.
  • the reset signal terminal RST of the N-th stage shift register RS(N) is set separately or coupled to the aforementioned start signal terminal.
  • the first clock signal terminal CLK1, the second clock signal terminal CLK2, and the third clock signal terminal CLK3 of the 3t+1 stage shift register (RS1, RS4, RS7...) are in sequence with the first system clock signal terminal ck1, The second system clock signal terminal ck2 and the third system clock signal terminal ck3 are coupled.
  • the first clock signal terminal CLK1, the second clock signal terminal CLK2, and the third clock signal terminal CLK3 of the 3t+2 stage shift register (RS2, RS5, RS8...) are in turn with the second system clock signal terminal ck2 and the The third system clock signal terminal ck3 and the first system clock signal terminal ck1 are coupled.
  • the first clock signal terminal CLK1, the second clock signal terminal CLK2, and the third clock signal terminal CLK3 of the 3t+3 stage shift register (RS3, RS6, RS9...) are in turn with the third system clock signal terminal ck3 and the third system clock signal terminal ck3, respectively.
  • a system clock signal terminal ck1 and a second system clock signal terminal ck2 are coupled; wherein, 3t+3 ⁇ N, and t is a variable of a natural number.
  • Some embodiments of the present disclosure also provide a driving method of the shift register. Before introducing the driving method, the display process of the display device is first introduced.
  • a frame of image refers to "drawing" an image on the display screen by means of progressive scanning or interlacing scanning.
  • a plurality of sub-pixels P included in the display panel PNL are arranged in an array, including N rows and M columns. During the display process, a row-by-row scan is used.
  • the first gate line GL to the Nth gate line GL sequentially input scan signals to the first row of sub-pixels P to the Nth row of sub-pixels P row by row to turn on the sub-pixels P row by row, and turn on the sub-pixels P in each row
  • the data line DL inputs the corresponding data signal to each sub-pixel (including M sub-pixels in total) in the row of sub-pixels P to sequentially light up the plurality of sub-pixels P from the first row to the Nth row.
  • the corresponding image is displayed, so that the "drawing" or display of a frame of image is completed.
  • the multiple sub-pixels P are sequentially lit from the first line to the N-th line to display the corresponding image, so that the "drawing" or display of the next frame of image is completed.
  • the refresh rate of the display device can be 60HZ or 100HZ, that is, the display device can display 60 frames of images or 100 frames of images in one second, and the display period of each frame of image is 1/60 second or 1/100 second. Due to the persistence of vision in the human eye, such a situation may occur. When a still picture is displayed, although the human eye cannot perceive any change in the image on the display device within one second, in fact, The image on the display device has been repeatedly displayed 60 or 100 times. If the refresh frequency of the display device is sufficiently high, human eyes will not feel the flicker caused by the screen switching.
  • the display process of the display device includes multiple frame periods, and each frame period completes the scanning of N rows of sub-pixels P to display one frame of image.
  • the N-stage shift registers included in the gate driving circuit sequentially output scan signals, that is, the scan signals are sequentially output from the first-stage shift register to the Nth-stage shift register, so that each gate line GL is scanned row by row.
  • the driving process of each shift register includes a pre-charge phase S1, an input phase S2, an output phase S3, and a reset phase S4, according to the cascade of multiple shift registers in the gate drive circuit
  • the above four periods of each shift register have a corresponding corresponding relationship with the above four periods of adjacent shift registers. For example, taking the gate driving circuit shown in FIG.
  • the reset signal terminal RST of the first-stage shift register RS1 is coupled to the cascade signal output terminal Oput_c of the second-stage shift register RS2, and the first-stage shift
  • the cascade signal output terminal Oput_c of the register RS1 is coupled to the signal input terminal Iput of the third-stage shift register RS3, so that the reset stage S4 of the first-stage shift register corresponds to the output stage S3 of the second-stage shift register.
  • the output stage S3 of the first-stage shift register corresponds to the input stage S2 of the second-stage shift register, and so on, and will not be repeated here.
  • the following takes the first-stage shift register RS1 in the gate drive circuit 01 shown in FIG. 5 (which is formed by cascading the shift registers in FIG. 4) as an example, combined with the timing in FIG. 6
  • the control diagram describes the driving method of the shift register of the present disclosure in one image frame (one frame period).
  • the signal input terminal Iput is coupled to the first start signal terminal STV1, and the reset signal terminal RST is connected to the cascade signal output of the second stage shift register RS2.
  • Terminal (Oput_c' in Figure 6) is coupled; the first clock signal terminal CLK1 is coupled to the first system clock signal terminal ck1, the second clock signal terminal CLK2 is coupled to the second system clock signal terminal ck2, and the third clock signal The terminal CLK3 is coupled to the third system clock signal terminal ck3.
  • the driving method of the first-stage shift register RS1 includes: one frame period includes a precharge phase S1, an input phase S2, an output phase S3, and a reset phase S4.
  • the input sub-circuit 100 receives the input signal input (turn-on voltage) transmitted by the signal input terminal Iput.
  • the first The two-input control unit 103 is turned on, and transmits the input signal input to the first node A, so as to precharge the first node A.
  • the initialization signal t_rst is input to the initialization signal terminal T_RST, the level of the initialization signal t_rst is high, and under the control of the initialization signal t_rst, the initialization sub-circuit 400 is turned on, and the first voltage signal received at the first voltage signal terminal VGL The vgl is transmitted to the pull-up node PU to initialize the voltage of the pull-up node PU.
  • the second input control unit 103 of the input sub-circuit 100 includes a third transistor M3.
  • the pre-charging stage S1 includes:
  • the level of the first start signal stv1 (input signal input) transmitted by the first start signal terminal STV1 is high, the third transistor M3 is turned on, and the signal received at the first start signal terminal STV1
  • the first start signal stv1 (that is, the input signal input) is transmitted to the first node A, the potential of the first node A rises, and the first capacitor C1 is charged.
  • the potential of the first node A rises, and the first input control unit 101 is turned on, that is, the first transistor M1 and the second transistor M2 are turned on, and the signal will be received at the first clock signal terminal CLK1.
  • the first clock signal clk1 is transmitted to the second node B and the pull-up node PU. At this time, the level of the first clock signal clk1 is low.
  • the initialization signal t_rst is input to the initialization signal terminal T_RST, the level of the initialization signal t_rst is high, the seventh transistor M7 is turned on, and the first voltage signal vgl received at the first voltage terminal VGL is transmitted to the pull-up node PU to Initialize the pull-up node PU.
  • the pull-up nodes PU in all shift registers are initialized at this time.
  • the initialization signal t_rst in the precharge stage, can be input to both the signal input terminal Iput and the initialization signal terminal T_RST of the first stage shift register, that is, the signal input terminal Iput is not coupled to the first start signal terminal STV1 , But connect to the port that inputs the initialization signal t_rst, so that the pre-charging of the first node A and the initialization of the pull-up node PU can also be realized in the pre-charging stage S1.
  • the first input control unit 101 Under the control of the voltage of the first node A, the first input control unit 101 is continuously turned on, and outputs the first clock signal clk1 received at the first clock signal terminal CLK1 to the pull-up node PU via the second node B.
  • the level of the first clock signal clk1 is high, so that the voltage of the pull-up node PU rises.
  • the boosting unit 102 boosts the voltage of the first node A under the action of the first clock signal clk1, so that the voltage loss of the first clock signal clk1 during the transmission from the first input control unit 101 to the pull-up node PU Decrease.
  • the output sub-circuit 300 is turned on, and the second clock signal received at the second clock signal terminal CLK2 (ie, the second system clock signal terminal ck2)
  • the clk is transmitted to the cascade signal output terminal Oput_c and the scan signal output terminal Oput_o.
  • the level of the second clock signal clk is low.
  • the pull-down control sub-circuit 500 is turned on, and transmits the first voltage signal vgl received at the first voltage signal terminal VGL to the pull-down node PD, thereby reducing the potential of the pull-down node PD Pull down.
  • both the first noise reduction sub-circuit 600 and the second noise reduction sub-circuit 700 are turned off.
  • the input sub-circuit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, and a first capacitor C1;
  • the output sub-circuit 300 includes a fifth transistor M5 and a sixth transistor. M6 and the second capacitor C2;
  • the pull-down control sub-circuit 500 includes an eighth transistor M8 and a ninth transistor M9;
  • the first noise reduction sub-circuit 600 includes a tenth transistor M10;
  • the second noise reduction sub-circuit 700 includes an eleventh transistor M11 and
  • the input stage S2 includes:
  • the first transistor M1 and the second transistor M2 are turned on, and the first clock received at the first clock signal terminal CLK1 (ie, the first system clock signal terminal ck1)
  • the signal clk1 is output to the pull-up node PU via the second node B.
  • the level of the first clock signal clk1 is high, so that the voltage of the second node B rises and the voltage of the pull-up node PU rises.
  • the first capacitor C1 bootstraps under the action of the high-level voltage of the second node B, and further raises the potential of the first node A, so that the first transistor M1 and the The voltage of the control electrode of the second transistor M2 increases and is much larger than its threshold voltage, so that the threshold voltage loss of the first clock signal clk1 during the transmission from the first input control unit 101 to the pull-up node PU is reduced or even no voltage loss,
  • the voltage loss of the first clock signal clk1 in the process of outputting the first clock signal clk1 to the pull-up node PU via the second node B is reduced, and the pull-up node PU has a sufficient potential.
  • the second capacitor C2 is charged, the fifth transistor M5 and the sixth transistor M6 are turned on, and they will be received at the second clock signal terminal CLK2.
  • the second clock signal clk is transmitted to the cascade signal output terminal Oput_c and the scan signal output terminal Oput_o. At this time, the level of the second clock signal clk is low.
  • the ninth transistor M9 is turned on to transmit the first voltage signal vgl received at the first voltage signal terminal VGL to the pull-down node PD, thereby reducing the The potential is pulled low.
  • the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are all turned off.
  • the level of the second clock signal clk2 transmitted by the second clock signal terminal CLK2 is high, and the output sub-circuit 300 is kept on under the control of the voltage of the pull-up node PU, and the first clock signal received at the second clock signal terminal CLK2
  • the second clock signal clk2 is transmitted to the cascade signal output terminal Oput_c and the scan signal output terminal Oput_o.
  • the cascade signal output terminal Oput_c outputs the cascade signal
  • the scan signal output terminal Oput_o outputs the scan signal.
  • the potential of the pull-up node PU further rises.
  • the input reset sub-circuit 200 is turned on, and the first voltage signal vgl received at the first voltage signal terminal VGL is transmitted to the first node A so as to change the voltage of the first node A Perform a reset.
  • the pull-down control sub-circuit 500 Under the control of the voltage of the pull-up node PU, the pull-down control sub-circuit 500 remains on, and transmits the first voltage signal vgl received at the first voltage signal terminal VGL to the pull-down node PD, thereby pulling the potential of the pull-down node PD low. In this way, under the control of the voltage of the pull-down node PD, both the first noise reduction sub-circuit 600 and the second noise reduction sub-circuit 700 are turned off.
  • the input sub-circuit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, and a first capacitor C1;
  • the output sub-circuit 300 includes a fifth transistor M5 and a sixth transistor. M6 and the second capacitor C2;
  • the pull-down control sub-circuit 500 includes an eighth transistor M8 and a ninth transistor M9;
  • the first noise reduction sub-circuit 600 includes a tenth transistor M10;
  • the second noise reduction sub-circuit 700 includes an eleventh transistor M11 and
  • the output stage S3 includes:
  • the second capacitor C2 discharges the pull-up node PU, the pull-up node PU maintains a high-level voltage, the fifth transistor M5 and the sixth transistor M6 are turned on, and respectively transmit the second clock signal clk2 at the second clock signal terminal CLK2 To cascade signal output terminal Oput_c and scan signal output terminal Oput_o. And in this stage, the second capacitor C2 further raises the potential of the pull-up node PU through bootstrapping under the action of the high-level voltage output from the cascade signal output terminal Oput_c.
  • the ninth transistor M9 is turned on to transmit the first voltage signal vgl received at the first voltage signal terminal VGL to the pull-down node PD, thereby reducing the power of the pull-down node PD The potential is pulled low.
  • the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are all turned off.
  • the reset signal reset is input to the reset signal terminal RST.
  • the level of the reset signal reset is high, and the level of the third clock signal clk3 is high.
  • the pull-down control sub-circuit 500 is turned on, and transmits the reset signal reset received at the reset signal terminal RST to the pull-down node PD to raise the potential of the pull-down node PD.
  • the first noise reduction sub-circuit 600 Under the control of the voltage of the pull-down node PD, the first noise reduction sub-circuit 600 is turned on, and transmits the first voltage signal vgl received at the first voltage signal terminal VGL to the pull-up node PU to reset the pull-up node PU.
  • the second noise reduction sub-circuit 700 is turned on, and transmits the first voltage signal vgl received at the first voltage signal terminal VGL to the cascade signal output terminal Oput_c and the scanning signal output terminal Oput_o , To reset the cascaded signal output terminal Oput_c and the scan signal output terminal Oput_o.
  • the pull-down control sub-circuit 500 includes an eighth transistor M8 and a ninth transistor M9; the first noise reduction sub-circuit 600 includes a tenth transistor M10; the second noise reduction sub-circuit 700 includes a first In the case of the eleventh transistor M11 and the twelfth transistor M12, the reset stage S4 includes:
  • the reset signal reset is input to the reset signal terminal RST, and under the control of the high-level voltage of the third clock signal terminal CLK3 (the third system clock signal terminal ck3), the eighth transistor M8 is turned on and will be at the reset signal terminal RST The received reset signal reset is transmitted to the pull-down node PD.
  • the tenth transistor M10 Under the control of the high-level voltage of the pull-down node PD, the tenth transistor M10 is turned on, and transmits the first voltage signal vgl received at the first voltage signal terminal VGL to the pull-up node PU to reset the pull-up node PU .
  • the eleventh transistor M11 and the twelfth transistor M12 are turned on, and the first voltage signal vgl received at the first voltage signal terminal VGL is transmitted to the cascade signal output
  • the terminal Oput_c and the scanning signal output terminal Oput_o are used to reset the cascaded signal output terminal Oput_c and the scanning signal output terminal Oput_o.
  • the pull-up node PU and the pull-down node PD maintain the state of the reset stage S4, that is, the potential of the pull-up node PU is low, and the potential of the pull-down node PD is high.
  • the first noise reduction sub-circuit 600 and the second noise reduction sub-circuit 700 are turned on (that is, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned on).
  • the first voltage signal vgl received at the first voltage terminal VGL is transmitted to the pull-up node PU, the cascade signal output terminal Oput_c, and the scan signal output terminal Oput_o for noise reduction.
  • the inventor of the present disclosure has compared the shift register provided by some embodiments of the present disclosure, as shown in FIG. 4, with the shift register in the related art through actual simulations.
  • the voltage of the pull-up node PU can reach about 20V, while the shift register in the related art is in the input stage.
  • the voltage of the pull-up node PU is about 16.8V. It can be seen that with the shift register in the present disclosure, the potential of the pull-up node PU is raised by about 3.2V.
  • the insufficient potential of the pull-up node PU in the input phase of the shift register in the related art will be more obvious.
  • the effect of the shift register on the voltage rise of the pull-up node will be more obvious.
  • the transistors used in the shift register provided by the embodiments of the present disclosure may be thin film transistors, field-effect transistors, or other switching devices with the same characteristics.
  • the transistors in the present disclosure may be enhancement transistors or The present disclosure does not limit the depletion transistor.
  • the control pole of each transistor used in the shift register is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor.
  • the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable, that is, the first and second electrodes of the transistor in the embodiment of the present disclosure
  • the two poles can be indistinguishable in structure.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain
  • the second pole is the source.
  • the transistors are all N-type transistors as an example for description. It should be noted that the embodiments of the present disclosure include but are not limited to this.
  • one or more transistors in the shift register provided by the embodiments of the present disclosure can also be P-type transistors, and only the poles of the selected type of transistors can be referred to the poles of the corresponding transistors in the embodiments of the present disclosure. Connect accordingly, and make the corresponding voltage terminal provide the corresponding high voltage or low voltage.

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Abstract

一种移位寄存器，包括：输入子电路(100)；输入子电路(100)与信号输入端(Iput)耦接。输入子电路(100)包括：第一输入控制单元(101)和增压单元(102)。第一输入控制单元(101)与第一时钟信号端(CLK1)、第一节点(A)、第二节点(B)和上拉节点(PU)耦接；第一节点(A)被配置为接收信号输入端(Iput)所传输的输入信号(input)。增压单元(102)耦接在第一节点(A)和第二节点(B)之间。第一输入控制单元(101)被配置为：在第一节点(A)的电压的控制下，将在第一时钟信号端(CLK1)处接收的第一时钟信号(clk1)经第二节点(B)传输至上拉节点(PU)。增压单元(102)被配置为：在第一时钟信号(clk1)的作用下，在第二节点(B)的电位升高时，抬升第一节点(A)的电压，以使第一时钟信号(clk1)在由第一输入控制单元(101)传输至上拉节点(PU)的过程中的电压损失减小。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置
本申请要求于2019年05月07日提交的、申请号为201910376408.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
栅极驱动电路(也称扫描驱动电路)是显示装置中的重要组成部分，栅极驱动电路包括多级级联的移位寄存器，每一级移位寄存器分别与显示屏中的一行栅线耦接。栅极驱动电路的功能是一行一行地有序输出TFT(Thin Film Transistor，薄膜晶体管)器件的开关态电压，也即逐行向显示屏中的栅线输出扫描信号(也可以称为栅信号)，从而逐行开启显示屏中与同一栅线耦接的多个TFT，在其中一行栅线耦接的多个TFT开启的情况下，通过数据线将像素电压输入至各亚像素的像素电极中，从而进行画面显示。
公开内容
一方面，提供一种移位寄存器，包括：输入子电路；所述输入子电路与信号输入端耦接。所述输入子电路包括：第一输入控制单元和增压单元。所述第一输入控制单元与第一时钟信号端、第一节点、第二节点和上拉节点耦接；所述第一节点被配置为接收所述信号输入端所传输的输入信号。所述增压单元耦接在所述第一节点和所述第二节点之间。
所述第一输入控制单元被配置为：在所述第一节点的电压的控制下，将在所述第一时钟信号端处接收的第一时钟信号经所述第二节点传输至所述上拉节点。所述增压单元被配置为：在所述第一时钟信号的作用下，在第二节点的电位升高时，抬升所述第一节点的电压，以使所述第一时钟信号在由所述第一输入控制单元传输至所述上拉节点的过程中的电压损失减小。
在一些实施例中，所述第一输入控制单元包括：第一晶体管和第二晶体管。所述第一晶体管的控制极与所述第一节点耦接，所述第一晶体管的第一极与所述第一时钟信号端耦接，所述第一晶体管的第二极与所述第二节点耦接。所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第二节点耦接，所述第二晶体管的第二极与所述上拉节点耦接。所述增压单元包括：第一电容器；所述第一电容器的第一极与所述第一节点耦接，所述第一电容器的第二极与所述第二节点耦接。
在一些实施例中，所述信号输入端与所述第一节点耦接。或者，所述输入子电路还包括：第二输入控制单元。所述信号输入端通过所述第二输入控制单元与所述第一节点耦接；所述第二输入控制单元被配置为响应于在所述信号输入端处接收的输入信号，将所述输入信号传输至所述第一节点。
在一些实施例中，在所述移位寄存器还包括第二输入控制单元的情况下：所述第二输入控制单元包括第三晶体管；所述第三晶体管的控制极和第一极与所述信号输入端耦接，第三晶体管的第二极与所述第一节点耦接。
在一些实施例中，移位寄存器还包括：输入复位子电路。所述输入复位子电路与第二时钟信号端、第一电压信号端和所述第一节点耦接；所述输入复位子电路被配置为响应于在所述第二时钟信号端处接收的第二时钟信号，将在所述第一电压信号端处接收的第一电压信号传输至所述第一节点，以对所述第一节点复位。
在一些实施例中，所述输入复位子电路包括第四晶体管。所述第四晶体管的控制极与所述第二时钟信号端耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第一节点耦接。
在一些实施例中，移位寄存器还包括：输出子电路。所述输出子电路与第二时钟信号端、所述上拉节点、扫描信号输出端和级联信号输出端耦接；所述输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述扫描信号输出端和所述级联信号输出端。
在一些实施例中，所述输出子电路包括第五晶体管、第六晶体管和第二电容器。所述第五晶体管的控制极与所述上拉节点耦接，所述第五晶体管的第一极与所述第二时钟信号端耦接，所述第五晶体管的第二极与所述级联信号输出端耦接。所述第六晶体管的控制极与所述上拉节点耦接，所述第六晶体管的第一极与所述第二时钟信号端耦接，所述第六晶体管的第二极与所述扫描信号输出端耦接。所述第二电容器的第一极与所述上拉节点耦接，第二极与所述级联信号输出端耦接。
在一些实施例中，移位寄存器还包括：初始化子电路、下拉控制子电路、第一降噪子电路、第二降噪子电路。所述初始化子电路与初始化信号端、第一电压信号端和所述上拉节点耦接；所述初始化子电路被配置为响应于在所述初始化信号端处接收的初始化信号，将在所述第一电压信号端处接收的第一电压信号传输至所述上拉节点。所述下拉控制子电路与复位信号端、第三时钟信号端、所述第一电压信号端、所述上拉节点和下拉节点耦接；所述下 拉控制电路被配置为，响应于在所述第三时钟信号端处接收的第三时钟信号，将在所述复位信号端处接收的复位信号传输至所述下拉节点；及，在所述上拉节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述下拉节点。
所述第一降噪子电路与所述下拉节点、所述第一电压信号端和所述上拉节点耦接；所述第一降噪子电路被配置为在所述下拉节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述上拉节点。所述第二降噪电路与所述下拉节点、所述第一电压信号端、扫描信号输出端和级联信号输出端耦接；所述第二降噪子电路被配置为：在所述下拉节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述扫描信号输出端和所述级联信号输出端。
在一些实施例中，所述初始化子电路包括第七晶体管；所述第七晶体管的控制极与所述初始化信号端耦接，所述第七晶体管的第一极与所述第一电压信号端耦接，所述第七晶体管的第二极与所述上拉节点耦接。
所述下拉控制电路包括第八晶体管和第九晶体管。所述第八晶体管的控制极与所述第三时钟信号端耦接，所述第八晶体管的第一极与所述复位信号端耦接，所述第八晶体管的第二极与所述下拉节点耦接；所述第九晶体管的控制极与所述上拉节点耦接，所述第九晶体管的第一极与所述第一电压信号端耦接，所述第九晶体管的第二极与所述下拉节点耦接。
所述第一降噪子电路包括第十晶体管；所述第十晶体管的控制极与所述下拉节点耦接，所述第十晶体管的第一极与所述第一电压信号端耦接，所述第十晶体管的第二极与所述上拉节点耦接。
所述第二降噪子电路包括第十一晶体管和第十二晶体管。所述第十一晶体管的控制极与所述下拉节点耦接，所述第十一晶体管的第一极与所述第一电压信号端耦接，所述第十一晶体管的第二极与所述级联信号输出端耦接；所述第十二晶体管的控制极与所述下拉节点耦接，所述第十二晶体管的第一极与所述第一电压信号端耦接，所述第十二晶体管的第二极与所述扫描信号输出端耦接。
在一些实施例中，移位寄存器还包括：输入复位子电路、输出子电路、初始化子电路、下拉控制子电路、第一降噪子电路和第二降噪子电路。其中，所述输入子电路包括第一晶体管、第二晶体管、第三晶体管和第一电容器；所述输入复位子电路包括第四晶体管；所述输出子电路包括第五晶体管、第六晶体管和第二电容器；所述初始化子电路包括第七晶体管；所述下拉控制 子电路包括第八晶体管和第九晶体管；所述第一降噪子电路包括第十晶体管；所述第二降噪子电路包括第十一晶体管和第十二晶体管。
所述第一晶体管的控制极与所述第一节点耦接，所述第一晶体管的第一极与所述第一时钟信号端耦接，所述第一晶体管的第二极与所述第二节点耦接。所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第二节点耦接，所述第二晶体管的第二极与所述上拉节点耦接。所述第三晶体管的控制极和第一极与所述信号输入端耦接，第三晶体管的第二极与所述第一节点耦接。所述第一电容器的第一极与所述第一节点耦接，所述第一电容器的第二极与所述第二节点耦接。
所述第四晶体管的控制极与所述第二时钟信号端耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第一节点耦接。所述第五晶体管的控制极与所述上拉节点耦接，所述第五晶体管的第一极与所述第二时钟信号端耦接，所述第五晶体管的第二极与所述级联信号输出端耦接。所述第六晶体管的控制极与所述上拉节点耦接，所述第六晶体管的第一极与所述第二时钟信号端耦接，所述第六晶体管的第二极与所述扫描信号输出端耦接。所述第二电容器的第一极与所述上拉节点耦接，第二极与所述级联信号输出端耦接。
所述第七晶体管的控制极与所述初始化信号端耦接，所述第七晶体管的第一极与所述第一电压信号端耦接，所述第七晶体管的第二极与所述上拉节点耦接。所述第八晶体管的控制极与所述第三时钟信号端耦接，所述第八晶体管的第一极与所述复位信号端耦接，所述第八晶体管的第二极与所述下拉节点耦接。所述第九晶体管的控制极与所述上拉节点耦接，所述第九晶体管的第一极与所述第一电压信号端耦接，所述第九晶体管的第二极与所述下拉节点耦接。
所述第十晶体管的控制极与所述下拉节点耦接，所述第十晶体管的第一极与所述第一电压信号端耦接，所述第十晶体管的第二极与所述上拉节点耦接。所述第十一晶体管的控制极与所述下拉节点耦接，所述第十一晶体管的第一极与所述第一电压信号端耦接，所述第十一晶体管的第二极与所述级联信号输出端耦接。所述第十二晶体管的控制极与所述下拉节点耦接，所述第十二晶体管的第一极与所述第一电压端信号耦接，所述第十二晶体管的第二极与所述扫描信号输出端耦接。
另一方面，提供一种如上所述的移位寄存器的驱动方法，包括：一个帧周期包括预充电阶段和输入阶段，在所述预充电阶段：第一节点接收信号输 入端所传输的输入信号。在所述输入阶段，在所述第一节点的电压的控制下，第一输入控制单元开启，将在所述第一时钟信号端处接收的第一时钟信号经所述第二节点传输至所述上拉节点。增压单元在所述第一时钟信号的作用下，抬升所述第一节点的电压，以使所述第一时钟信号在由所述第一输入控制单元传输至所述上拉节点的过程中的电压损失减小。
在一些实施例中，在所述移位寄存器的输入子电路还包括第二输入控制单元的情况下，在所述预充电阶段：在所述信号输入端传输的输入信号的控制下，所述第二输入控制单元开启，将所述输入信号传输至所述第一节点。
在一些实施例中，在所述移位寄存器还包括输入复位子电路和输出子电路的情况下，一个帧周期还包括位于所述输入阶段之后的输出阶段，在所述输出阶段：在第二时钟信号端传输的第二时钟信号的控制下，所述输入复位子电路开启，将在所述第一电压信号端处接收的第一电压信号传输至所述第一节点，以对所述第一节点复位。在所述上拉节点的电压的控制下，所述输出子电路开启，将在所述第二时钟信号端处接收的第二时钟信号传输至所述扫描信号输出端和所述级联信号输出端。
再一方面，提供一种栅极驱动电路，包括N级级联的如权利要求1～11中任一项所述的移位寄存器；其中，N为正整数。
在一些实施例中，在所述移位寄存器还包括输出子电路、初始化子电路、下拉控制子电路、第一降噪子电路和第二降噪子电路的情况下，在所述栅极驱动电路中：第一级移位寄存器的信号输入端与起始信号端耦接；第二级移位寄存器的信号输入端与起始信号端耦接。
第i级移位寄存器的信号输入端与第i-2级移位寄存器的级联信号输出端耦接；其中，3≤i≤N；i为正整数。第j级移位寄存器的复位信号端与第j+1级移位寄存器的级联信号输出端耦接；1≤j≤N-1；j为正整数。第N级移位寄存器的复位信号端单独设置，或者与所述起始信号端耦接。
在一些实施例中，第3t+1级移位寄存器的第一时钟信号端、第二时钟信号端、第三时钟信号端分别依次与第一系统时钟信号端、第二系统时钟信号端、第三系统时钟信号端耦接。第3t+2级移位寄存器的第一时钟信号端、第二时钟信号端、第三时钟信号端分别依次与所述第二系统时钟信号端、所述第三系统时钟信号端、所述第一系统时钟信号端耦接。第3t+3级移位寄存器的第一时钟信号端、第二时钟信号端、第三时钟信号端分别依次与所述第三系统时钟信号端、所述第一系统时钟信号端、所述第二系统时钟信号端耦接。其中，3t+3≤N，t为非负整数。
又一方面，提供一种显示装置，包括如上所述的栅极驱动电路。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术的一些实施例的移位寄存器的结构图；
图2A为根据本公开的一些实施例的显示面板的一种结构图；
图2B为根据本公开的一些实施例的显示面板的另一种结构图；
图3为根据本公开的一些实施例的的移位寄存器的一种结构图；
图4为根据本公开的一些实施例的移位寄存器的另一种结构图；
图5为根据本公开的一些实施例的栅极驱动电路的结构图；
图6为根据本公开的一些实施例的移位寄存器的驱动方法的时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。即，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
栅极驱动电路中的移位寄存器主要由晶体管、电容器等器件组成，在移位寄存器的工作过程中，通过晶体管、电容器对内部的控制节点的电位进行控制，进而实现扫描信号的输出。然而，由于电信号在经过晶体管传输的过程中会存在阈值损失，容易导致控制节点的电压不足，从而造成移位寄存器输出异常，进而导致显示异常。
相关技术中，以图1所示的移位寄存器为例，移位寄存器包括输入子电路、输出子电路、降噪子电路和控制子电路等，以实现基本的输入、输出、 以及对控制节点的电位控制功能。移位寄存器中的控制节点包括上拉节点PU和下拉节点PD，在输入阶段，晶体管T1在第一时钟信号端CLK1传输的第一时钟信号clk1的控制下导通，将在信号输入端Iput处接收的输入信号input传输至上拉节点PU，存储电容器C将上拉节点的电压进行存储，同时晶体管T2在上拉节点PU的电压的控制下导通。在输出阶段，第二时钟信号端CLK2传输的第二时钟信号clk2的电平变为高电平，存储电容器C通过自举作用，将上拉节点PU的电压抬升，从而晶体管T2在上拉节点的电压的控制下持续导通，将第二时钟信号clk2传输至信号输出端Oput，从而移位寄存器输出扫描信号。
在上述移位寄存器中，在晶体管T1将输入信号input传输至上拉节点PU的过程中，输入信号input的电压值V input存在阈值损失，即晶体管T1无法将输入信号input的完整的电压值V input传输至上拉节点，上拉节点PU的电压只能达到V clk1-Vth，其中，V clk1为第一时钟信号clk1的高电平电压，Vth为晶体管T1的阈值电压。
这是由于：以晶体管T1为N型晶体管为例，晶体管T1导通的条件为：晶体管的栅源电压差Vgs大于其阈值电压Vth，当晶体管T1导通，将输入信号input从其第一极(漏极)传输至第二极(源极)的过程中，晶体管T1的第二极的电压逐渐增大，当电压值达到V clk1-Vth时，若晶体管T1的第二极的电压继续增大，则无法满足导通条件。因此，输入信号input在由晶体管T1传输至上拉节点PU的过程中存在阈值电压损失，造成上拉节点PU的电压只能达到V clk1-Vth，尤其是在晶体管T1存在阈值电压漂移的情况下，传输至上拉节点PU的电压值会更小，造成上拉节点PU的电位不足。需要说明的是，在显示装置中，通常系统所产生的信号的电压值是特定的，例如输入信号input的电压值V input与第一时钟信号clk1的高电平电压V clk1相等。
这样，上拉节点PU的电压不足，也就是说晶体管T2的控制极的电位较低，会造成晶体管T2的导通程度受到影响，从而影响第二时钟信号clk2向信号输出端Oput的传输。并且，由于上拉节点PU的电压较低，第二时钟信号clk2在由晶体管T2传输至信号输出端Oput的过程中同样会存在阈值电压损失的问题，导致移位寄存器输出的扫描信号的电压值较低，出现输出异常，从而影响移位寄存器的稳定性，设置导致显示装置的显示效果受到影响。
基于此，本公开的一些实施例提供一种移位寄存器及其驱动方法，以及栅极驱动电路和显示装置，以解决相关技术中由于电信号在传输过程中存在阈值损失，造成扫描信号输出异常，进而导致显示异常的问题，为了便于理 解，以下按照从大到小的顺序，对显示装置、栅极驱动电路和移位寄存器分别进行介绍。
本公开实施例提供一种显示装置，该显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些实施例中，显示装置包括框架、设置于框架内的显示面板、电路板、显示驱动IC((Integrated Circuit，集成电路)以及其他电子配件等。
上述显示面板可以为：液晶显示面板(Liquid Crystal Display，简称LCD)有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板等，本公开对此不做具体限定。
本公开以下实施例均是以上述显示面板为液晶显示面板为例，对本公开进行说明的。
如图2A和2B所示，上述显示面板PNL包括：显示区(active display area，AA；简称AA区；也可称为有效显示区)和围绕AA区一圈设置的周边区。
上述显示面板PNL的AA区内设置有多种颜色的亚像素(sub pixel)P，该多种颜色的亚像素至少包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素，第一颜色、第二颜色和第三颜色为三基色(例如红色、绿色和蓝色)。
为了方便说明，本申请中上述多个亚像素P是以矩阵形式排列为例进行的说明。在此情况下，沿水平方向X排列成一排的亚像素P称为同一行亚像素；沿竖直方向Y排列成一排的亚像素P称为同一列亚像素。
如图2B所示，每一亚像素P中均设置有像素驱动电路S，该像素驱动电路S包括晶体管T和液晶电容器C。该液晶电容器C的两个极板分别由像素电极和公共电极构成。其中，位于同一行的像素驱动电路S中的晶体管T的控制极(栅极)与同一栅线(Gate Line)GL耦接，以在栅线GL传输的扫描信号的控制下打开，位于同一列的像素驱动电路S的晶体管T的一极(例如 源极)与同一数据线(Data Line)DL耦接，以在晶体管T打开的情况下，接收数据线DL传输的数据信号。
如图2A所示，显示面板PNL的周边区设置有栅极驱动电路01和数据驱动电路02。在一些实施例中，栅极驱动电路01可以设置在沿栅线GL的延伸方向上的侧边，数据驱动电路02可以设置在沿数据线DL的延伸方向上的侧边，以驱动显示面板中的像素驱动电路进行显示。
在一些实施例中，上述栅极驱动电路01可以为栅极驱动IC。在另一些实施例中，上述栅极驱动电路01可以为GOA(Gate Driver on Array)电路，也即上述栅极驱动电路01直接集成在显示面板PNL的阵列基板中。其中，将栅极驱动电路01设置为GOA电路的方式，一方面，可以降低显示面板的制作成本，另一方面，可以窄化显示装置的边框宽度。以下实施例均是以栅极驱动电路01为GOA电路为例进行说明。
需要说明的是的，图2A和图2B仅是示意的，以显示面板PNL在周边区的单侧设置栅极驱动电路01，从单侧逐行依次驱动各栅线GL，即单侧驱动为例进行说明的。在另一些实施例中，显示面板PNL可以在周边区中沿栅线GL的延伸方向上的两个侧边分别设置栅极驱动电路，通过两个栅极驱动电路同时从两侧逐行依次驱动各栅线GL，即双侧驱动。在另一些实施例中，显示面板PNL可以在周边区中沿栅线GL的延伸方向上的两个侧边，分别设置栅极驱动电路，通过两个栅极驱动电路交替从两侧，逐行依次驱动各栅线GL，即交叉驱动。本公开以下实施例均是以单侧驱动为例进行说明的。
本公开的一些实施例中，如图2B所示，栅极驱动电路01中包括N级级联的移位寄存器(RS1、RS2……RS(N))，在此情况下，显示面板PNL中包括N级级联的移位寄存器(RS1、RS2……RS(N))分别一一对应耦接的N条栅线(G1、G2……G(N))，其中，N为正整数。
对于上述移位寄存器而言，在一些实施例中，为了避免通过同一信号输出端作为扫描信号输出端向显示面板PLN中与其耦接的栅线输出栅极扫描信号，同时又作为级联信号输出端向其他移位寄存器输出级联信号(例如输入信号、复位信号等)，导致栅极驱动电路01的输出不稳定；如图2B所示，在本公开的一些实施例中，在栅极驱动电路01的移位寄存器(RS1、RS2……RS(N))中，每个移位寄存器均独立设置扫描信号输出端Output_o(下文以及附图均将Output简写为Oput)和级联信号输出端Oput_c，从而通过扫描信号输出端Oput_o向与其耦接的栅线GL输出栅极扫描信号，通过级联信号输出端Oput_c输出级联信号，从而保证了栅极驱动电路01的信号输出的稳定性。
另外，在一些实施例中，如图2所示，本公开栅极驱动电路01的移位寄存器(RS1、RS2……RS(N))中还设置有信号输入端Input(附图以及下文均简写为Iput)，复位信号端Reset(附图以及下文均简写为RST)，并且栅极驱动电路01中各级移位寄存器的电路结构相同。
在此基础上，对于栅极驱动电路01中各级移位寄存器的级联情况而言：
除前一级或者多级移位寄存器的信号输入端Iput与起始信号端STV耦接，除与起始信号端STV耦接的移位寄存器以外，其他任一级移位寄存器的信号输入端Iput与位于其前级的移位寄存器的信号输出端Oput耦接；最后一级或多级移位寄存器的复位信号端RST独立设置或者与前述的起始信号端STV耦接；除最后一级或多级移位寄存器以外，任一级移位寄存器的复位信号端RST与位于其后级的移位寄存器的信号输出端Oput耦接。
示例性地，如图2B所示，第一级移位寄存器RS1信号输入端Iput与起始信号端STV耦接，除移位寄存器RS1之外的其他移位寄存器(RS2、RS3……RS(N))，任一级移位寄存器的信号输入端Iput与位于其前级的移位寄存器的信号输出端Oput耦接。最后一级移位寄存器RS(N)的复位信号端RST独立设置；除最后一级移位寄存器RS(N)以外的其他移位寄存器(RS1、RS2……RS(N-1))，任一级移位寄存器的复位信号端RST与位于其后级的移位寄存器的信号输出端Oput耦接。
另外，本领域的技术人员应当理解到，对于移位寄存器本身而言，如图3所示，其内部还设置有上拉节点PU和下拉节点PD，通过对上拉节点PU和下拉节点PD的电位控制，实现移位寄存器正常输出。其中，在移位寄存器的工作过程中，上拉节点PU和下拉节点PD的电位始终互为一组反相电位；示例性的，在上拉节点PU的电位为高电位时，下拉节点PD的电位为低电位；在上拉节点PU的电位为低电位时，下拉节点PD的电位为高电位。
在此基础上，如图3或图4所示，本公开的一些实施例提供的移位寄存器还包括：输入子电路100，输入子电路100与信号输入端Iput耦接。在该输入子电路100中，第一节点A被配置为接收信号输入端Iput所传输的输入信号input。
如图3或图4所示，上述输入子电路100包括：第一输入控制单元101和增压单元102。
上述第一输入控制单元101与第一时钟信号端CLK1、第一节点A、第二节点B和上拉节点PU耦接；该第一输入控制单元101被配置为：在第一节点A的电压的控制下，将在第一时钟信号端CLK1处接收的第一时钟信号clk1 经第二节点B输出至上拉节点PU。
上述增压单元102耦接在第一节点A和第二节点B之间；该增压单元102被配置为：在第一时钟信号clk1的作用下，抬升第一节点A的电压，以使第一时钟信号clk1在由第一输入控制单元传输至上拉节点PU的过程中的电压损失减小，此处的电压损失指的是阈值电压损失。
示例性的，如图3所示，上述第一输入控制单元101包括：第一晶体管M1和第二晶体管M2。
其中，第一晶体管M1的控制极与第一节点A耦接，第一晶体管M1的第一极与第一时钟信号端CLK1耦接，第一晶体管M2的第二极与第二节点B耦接。第一晶体管M1被配置为第一节点A的电压的控制下导通，将第一时钟信号clk1传输至第二节点B。
第二晶体管M2的控制极与第一节点A耦接，第二晶体管M2的第一极与第二节点B耦接，第二晶体管M2的第二极与上拉节点PU耦接。第二晶体管M2被配置为第一节点A的电压的控制下导通，将传输至第二节点B的第一时钟信号clk1传输至上拉节点PU。
示例性的，如图3所示，上述增压单元102包括：第一电容器C1；其中，该第一电容器C1的第一极与第一节点A耦接，第一电容器C1的第二极与第二节点B耦接。根据电容器的自举作用，在传输至第二节点B的第一时钟信号clk1的作用下，第二节点B的电压升高，从而第一节点A的电压被抬升。
示例性地，第一节点A接收信号输入端Iput所传输的输入信号input，例如此时第一节点A的电压为输入信号input的电压值V input。在第一节点A的电压的控制下，第一晶体管M1和第二晶体管M2导通，将第一时钟信号clk1传输至第二节点B，进而传输至上拉节点PU，在这个过程中，第二节点B的电位上升，例如此时第二节点B的电压为第一时钟信号clk1的高电平电压值V clk1，从而在第一电容器C1的自举作用下，第一节点A的电位抬升，变为V input+V clk1。
也就是说，第一晶体管M1和第二晶体管M2的控制极的电压增大为V input+V clk1，从而第一晶体管M1和第二晶体管M2的栅源电压差Vgs增大，远大于第一晶体管M1和第二晶体管M2的阈值电压，从而第一晶体管M1能够将第一时钟信号clk1的完整的电压值V clk1传输至第二节点B，第二晶体管M2能够将第二节点B接收的第一时钟信号clk1的完整的电压值V clk1传输至上拉节点PU，在第一时钟信号clk1的传输过程中，第一晶体管M1和第二晶体管M2始终能够满足导通条件，第一时钟信号clk1在由第一输入控制单元 101传输至上拉节点PU的过程中的阈值电压损失减小，甚至没有阈值电压损失，从而上拉节点PU的电压值能够达到要求，例如上拉节点PU的电压值为第一时钟信号clk1的完整的电压值V clk1。
综上所述，对于本公开实施例提供的移位寄存器而言，在输入子电路100中，第一节点A接收信号输入端Iput所传输的输入信号，从而第一节点A的电压升高(例如，大约为V input)，在第一节点A的电压控制下，通过第一输入控制单元101将在第一时钟信号端CLK1处接收的第一时钟信号clk1经第二节点B输出至上拉节点PU，与此同时，第二节点B的电压在第一时钟信号clk1的作用下升高，从而通过增压单元102来进一步的抬升第一节点A的电压(例如，此时第一节点A的电压大约可达到V input+V clk1)，也就是说使得第一输入控制单元101中晶体管的控制极的电压抬升，从而使得第一时钟信号clk1在由第一输入控制单元101传输至上拉节点PU的过程中的阈值电压损失减小甚至没有电压损失，能够使得第一时钟信号clk1的完成的电压值V clk1传输至上拉节点PU，进而避免了上拉节点PU出现电位不足的现象，从而保证了移位寄存器的稳定输出。
在此基础上，对于上述与输入子电路100耦接的信号输入端Iput而言：
在一些实施例中，如图3所示，信号输入端Iput与第一节点A耦接。
在另一些实施例中，如图4所示，输入子电路100还包括第二输入控制单元103。信号输入端Iput通过第二输入控制单元103与第一节点A耦接；该第二输入控制单元103被配置为响应于在信号输入端Iput处接收的输入信号input，将输入信号input传输至第一节点A。
示例性的，如图4所示，上述第二输入控制单元103包括第三晶体管M3。该第三晶体管M3的控制极和第一极与信号输入端Iput耦接，第三晶体管M3的第二极与第一节点A耦接。第三晶体管M3被配置为在输入信号input的控制下导通，将输入信号input传输至第一节点A。
在此基础上，如图4所示，在一些实施例中，该移位寄存器还包括：输入复位子电路200。其中，该输入复位子电路200与第二时钟信号端CLK2、第一电压信号端VGL和第一节点A耦接。该输入复位子电路200被配置为：响应于在第二时钟信号端CLK2处接收的第二时钟信号clk2，将在第一电压信号端VGL的处接收的第一电压信号vgl传输至第一节点A。从而通过第一电压信号vgl对第一节点A进行复位，以提高移位寄存器的输出稳定性。
示例性的，如图4所示，上述输入复位子电路200包括第四晶体管M4。其中，第四晶体管M4的控制极与第二时钟信号端CLK2耦接，第四晶体管 M4的第一极与第一电压信号端VGL耦接，第四晶体管M4的第二极与第一节点A耦接。第四晶体管M4被配置为在第二时钟信号clk2的控制下导通，将第一电压信号vgl传输至第一节点A。
另外，本领域的技术人员应当理解到，移位寄存器在包括前述的输入子电路100、输入复位子电路200的基础上，还包括输出子电路、降噪子电路、以及与上拉节点PU、下拉节点PD耦接的其他相关的控制电路，本公开对此不作具体限定，实际中可以根据需求选择设置合适的相关电路即可。
在一些实施例中，如图3和图4所示，本公开提供的移位寄存器还包括输出子电路300，输出子电路300与第二时钟信号端CLK2、上拉节点PU、扫描信号输出端Oput_o和级联信号输出端Oput_c耦接。该输出子电路300被配置为：在上拉节点PU的电压的控制下，将在第二时钟信号端CLK2处接收的第二时钟信号clk2传输至扫描信号输出端Oput_o和级联信号输出端Oput_c。
示例性的，如图4所示，上述输出子电路300包括第五晶体管M5、第六晶体管M6和第二电容器C2。
第五晶体管M5的控制极与上拉节点PU耦接，第五晶体管M5的第一极与第二时钟信号端CLK2耦接，第五晶体管M5的第二极与级联信号输出端Oput_c耦接。第五晶体管M5被配置为在上拉节点PU的电压的控制下导通，将第二时钟信号clk2传输至级联信号输出端Oput_c。
第六晶体管M6的控制极与上拉节点PU耦接，第六晶体管M6的第一极与第二时钟信号端CLK2耦接，第六晶体管M6的第二极与扫描信号输出端Oput_o耦接。第六晶体管M6被配置为在上拉节点PU的电压的控制下导通，将第二时钟信号clk2传输至扫描信号输出端Oput_o。
第二电容器C2的第一极与上拉节点PU耦接，第二电容器C2的第二极与级联信号输出端Oput_c耦接。第二电容器C2被配置为存储上拉节点PU的电压，并在第二时钟信号clk2的作用下，通过电容器的自举作用，抬升上拉节点PU的电压。
在一些实施例中，如图4所示，该移位寄存器在包括前述的输入子电路100、输入复位子电路200和输出子电路300的基础上，还包括：初始化子电路400、下拉控制子电路500、第一降噪子电路600和第二降噪子电路700。
上述初始化子电路400与初始化信号端T_RST、第一电压信号端VGL和上拉节点PU耦接。该初始化子电路300被配置为响应于在初始化信号端T_RST处接收的初始化信号t_rst，将在第一电压信号端VGL处接收的第一电 压信号vgl传输至上拉节点PU。
示例性的，如图4所示，上述初始化子电路300包括第七晶体管M7。其中，第七晶体管M7的控制极与初始化信号端T_RST耦接，第七晶体管M7的第一极与第一电压信号端VGL耦接，第七晶体管M7的第二极与上拉节点PU耦接。第七晶体管M7被配置为在初始化信号t_rst的控制下，将第一电压信号vgl传输至上拉节点PU。
上述下拉控制子电路400与复位信号端RST、第三时钟信号端CLK3和下拉节点PD耦接。该下拉控制子电路400被配置为响应于在第三时钟信号端CLK3处接收的第三时钟信号clk3，将在复位信号端RST处接收的复位信号rst传输至下拉节点PD；及，在上拉节点PU的电压的控制下，将在第一电压信号端VGL处接收的第一电压信号vgl传输至下拉节点PD。
示例性的，如图4所示，上述复位控制电路400包括第八晶体管M8和第九晶体管M9。
其中，第八晶体管M8的控制极与第三时钟信号端CLK3耦接，第八晶体管M8的第一极与复位信号端RST耦接，第八晶体管M8的第二极与下拉节点PU耦接。第八晶体管M8被配置为在第三时钟信号clk3的控制下导通，将复位信号rst传输至下拉节点PD。
第九晶体管M9的控制极与上拉节点PU耦接，第九晶体管M9的第一极与第一电压信号端VGL耦接，第九晶体管M9的第二极与下拉节点PD耦接。第九晶体管M9被配置为在上拉节点PU的电压的控制下导通，将第一电压信号vgl传输至下拉节点PD。
上述第一降噪子电路600与下拉节点PD、第一电压信号端VGL和上拉节点PU耦接。该第一降噪子电路500被配置为：在下拉节点PD的电压的控制下，将在第一电压信号端VGL处接收的第一电压信号vgl传输至上拉节点PU，以对上拉节点PU进行降噪。
示例性的，如图4所示，上述第一降噪子电路600包括第十晶体管M10。其中，第十晶体管M10的控制极与下拉节点PD耦接，第十晶体管M10的第一极与第一电压信号端VGL耦接，第十晶体管M10的第二极与上拉节点PU耦接。第十晶体管M10被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至上拉节点PU，以对上拉节点PU进行降噪。
上述第二降噪子电路700与下拉节点PD、第一电压信号端VGL、扫描信号输出端Oput_o和级联信号输出端Oput_c耦接。该第二降噪子电路700被配置为：在下拉节点PD的电压的控制下，将在第一电压信号端VGL处接收 的第一电压信号vgl传输至扫描信号输出端Oput_o和级联信号输出端Oput_c。
示例性的，如图4所示，上述第二降噪子电路700包括第十一晶体管M11和第十二晶体管M12。
上述第十一晶体管M11的控制极与下拉节点PD耦接，第十一晶体管M11的第一极与第一电压端VGL耦接，第十一晶体管M11的第二极与级联信号输出端Oput_c耦接。第十一晶体管M11被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至级联信号输出端Oput_c。
第十二晶体管M12的控制极与下拉节点PD耦接，第十二晶体管M12的第一极与第一电压端VGL耦接，第十二晶体管M12的第二极与扫描信号输出端Oput_o耦接。第十二晶体管M12被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至扫描信号输出端Oput_o。
请再次参见图4，以下对本公开的一些实施例所提供的移位寄存器的结构做整体性、示例性的介绍。
移位寄存器包括：输入子电路100、输入复位子电路200、输出子电路300、初始化子电路400、下拉控制子电路500、第一降噪子电路600和第二降噪子电路700。
其中，输入子电路100包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第一电容器C1。输入复位子电路200包括第四晶体管M4。输出子电路300包括第五晶体管M5、第六晶体管M6和第二电容器C2。初始化子电路400包括第七晶体管M7。下拉控制子电路500包括第八晶体管M8和第九晶体管M9。第一降噪子电路600包括第十晶体管M10。第二降噪子电路700包括第十一晶体管M11和第十二晶体管M12。
第一晶体管M1的控制极与第一节点A耦接，第一晶体管M1的第一极与第一时钟信号端CLK1耦接，第一晶体管M2的第二极与第二节点B耦接。第一晶体管M1被配置为第一节点A的电压的控制下导通，将第一时钟信号clk1传输至第二节点B。
第二晶体管M2的控制极与第一节点A耦接，第二晶体管M2的第一极与第二节点B耦接，第二晶体管M2的第二极与上拉节点PU耦接。第二晶体管M2被配置为第一节点A的电压的控制下导通，将传输至第二节点B的第一时钟信号clk1传输至上拉节点PU。
第一电容器C1的第一极与第一节点A耦接，第一电容器C1的第二极与第二节点B耦接。第一电容器C1被配置为在第二节点B的电压升高时，抬升第一节点A的电压。
第三晶体管M3的控制极和第一极与信号输入端Iput耦接，第三晶体管M3的第二极与第一节点A耦接。第三晶体管M3被配置为在输入信号input的控制下导通，将输入信号input传输至第一节点A。
第四晶体管M4的控制极与第二时钟信号端CLK2耦接，第四晶体管M4的第一极与第一电压信号端VGL耦接，第四晶体管M4的第二极与第一节点A耦接。第四晶体管M4被配置为在第二时钟信号clk2的控制下导通，将第一电压信号vgl传输至第一节点A。
第五晶体管M5的控制极与上拉节点PU耦接，第五晶体管M5的第一极与第二时钟信号端CLK2耦接，第五晶体管M5的第二极与级联信号输出端Oput_c耦接。第五晶体管M5被配置为在上拉节点PU的电压的控制下导通，将第二时钟信号clk2传输至级联信号输出端Oput_c。
第六晶体管M6的控制极与上拉节点PU耦接，第六晶体管M6的第一极与第二时钟信号端CLK2耦接，第六晶体管M6的第二极与扫描信号输出端Oput_o耦接。第六晶体管M6被配置为在上拉节点PU的电压的控制下导通，将第二时钟信号clk2传输至扫描信号输出端Oput_o。
第二电容器C2的第一极与上拉节点PU耦接，第二电容器C2的第二极与级联信号输出端Oput_c耦接。第二电容器C2被配置为存储上拉节点PU的电压，并在第二时钟信号clk2的作用下，通过电容器的自举作用，抬升上拉节点PU的电压。
第七晶体管M7的控制极与初始化信号端T_RST耦接，第七晶体管M7的第一极与第一电压端VGL耦接，第七晶体管M7的第二极与上拉节点PU耦接。第七晶体管M7被配置为在初始化信号t_rst的控制下，将第一电压信号vgl传输至上拉节点PU。
第八晶体管M8的控制极与第三时钟信号端CLK3耦接，第八晶体管M8的第一极与复位信号端RST耦接，第八晶体管M8的第二极与下拉节点PU耦接。第八晶体管M8被配置为在第三时钟信号clk3的控制下导通，将复位信号rst传输至下拉节点PD。
第九晶体管M9的控制极与上拉节点PU耦接，第九晶体管M9的第一极与第一电压信号端VGL耦接，第九晶体管M9的第二极与下拉节点PU耦接。第九晶体管M9被配置为在上拉节点PU的电压的控制下导通，将第一电压信号vgl传输至下拉节点PD。
第十晶体管M10的控制极与下拉节点PD耦接，第十晶体管M10的第一极与第一电压信号端VGL耦接，第十晶体管M10的第二极与上拉节点PU耦 接。第十晶体管M10被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至上拉节点PU，以对上拉节点PU进行降噪。
第十一晶体管M11的控制极与下拉节点PD耦接，第十一晶体管M11的第一极与第一电压端VGL耦接，第十一晶体管M11的第二极与级联信号输出端Oput_c耦接。第十一晶体管M11被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至级联信号输出端Oput_c。
第十二晶体管M12的控制极与下拉节点PD耦接，第十二晶体管M12的第一极与第一电压端VGL耦接，第十二晶体管M12的第二极与扫描信号输出端Oput_o耦接。第十二晶体管M12被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至扫描信号输出端Oput_o。
对于采用图4中示出的移位寄存器级联而成的栅极驱动电路01而言，在一些实施例中，如图5所示，在该栅极驱动电路01中，N级移位寄存器的级联方式为：
第一级移位寄存器RS1的信号输入端Iput与起始信号端(STV1)耦接；第二级移位寄存器RS2的信号输入端Iput与起始信号端(STV2)耦接。在一些实施例中，STV1和STV2可以相互耦接；或者，STV1和STV2可以分别独立设置。
第i级移位寄存器RSi的信号输入端Iput与第i-2级移位寄存器RS(i-2)的级联信号输出端Oput_c耦接；其中，3≤i≤N；i为正整数的变量。
第j级移位寄存器RSj的复位信号端RST与第j+1级移位寄存器RS(j+1)的级联信号输出端Oput_c耦接；1≤j≤N-1；j为正整数的变量。
第N级移位寄存器RS(N)的复位信号端RST单独设置，或者与前述起始信号端耦接。
在一些实施例中，如图5所示，在上述栅极驱动电路01中：
第3t+1级移位寄存器(RS1、RS4、RS7……)的第一时钟信号端CLK1、第二时钟信号端CLK2、第三时钟信号端CLK3分别依次与第一系统时钟信号端ck1、第二系统时钟信号端ck2、第三系统时钟信号端ck3耦接。
第3t+2级移位寄存器(RS2、RS5、RS8……)的第一时钟信号端CLK1、第二时钟信号端CLK2、第三时钟信号端CLK3分别依次与第二系统时钟信号端ck2、第三系统时钟信号端ck3、第一系统时钟信号端ck1耦接。
第3t+3级移位寄存器(RS3、RS6、RS9……)的第一时钟信号端CLK1、第二时钟信号端CLK2、第三时钟信号端CLK3分别依次与第三系统时钟信号端ck3、第一系统时钟信号端ck1、第二系统时钟信号端ck2耦接；其中，3t+3 ≤N，t为自然数的变量。
本公开的一些实施例还提供了一种移位寄存器的驱动方法，在介绍该驱动方法之前，首先对显示装置的显示过程进行介绍。
在显示技术领域，例如对于液晶显示装置来说，一帧图像指的是通过逐行扫描或者隔行扫描的方式在显示屏幕上“绘制”一幅图像。示例性地，如图2B所示，在显示面板PNL中，显示面板PNL所包括的多个亚像素P呈阵列式排布，包括N行M列，在显示过程中，通过逐行扫描的方式，第一条栅线GL至第N条栅线GL逐行对第一行亚像素P至第N行亚像素P依次输入扫描信号，以逐行将亚像素P开启，在每一行亚像素P打开时，数据线DL将相应的数据信号输入该行亚像素P中的每个亚像素(一共包括M个亚像素)，以将多个亚像素P从第一行至第N行依次点亮以显示相应的图像，这样，就完成了一帧图像的“绘制”或显示。接着，同样以逐行扫描的方式，重新将多个亚像素P从第一行至第N行依次点亮以显示相应的图像，这样就完成下一帧图像的“绘制”或显示。
通常，显示装置的刷新频率可以为60HZ或100HZ，即显示装置一秒钟可以显示60帧图像或100帧图像，每帧图像的显示周期为1/60秒或1/100秒。由于人眼存在视觉暂留现象，可能会出现这样的情况，当显示一幅静止的画面时，虽然在一秒钟之内人眼感觉不出显示装置上的图像发生了任何变化，但实际上显示装置上的图像已经重复显示了60次或100次。在显示装置的刷新频率足够高的情况下，人眼不会感受到画面切换所造成的闪烁。
也就是说，显示装置的显示过程包括多个帧周期，每个帧周期完成N行亚像素P的扫描，从而进行一帧图像的显示，对于栅极驱动电路来说，在每个帧周期中，栅极驱动电路所包括的N级移位寄存器依次输出扫描信号，即从第一级移位寄存器至第N级移位寄存器依次输出扫描信号，从而逐行扫描各条栅线GL。
示例性地，在一个帧周期内，每个移位寄存器的驱动过程包括预充电阶段S1、输入阶段S2、输出阶段S3和复位阶段S4，根据栅极驱动电路中多级移位寄存器的级联方式的不同，每个移位寄存器的上述四个时段与相邻移位寄存器的上述四个时段有相应的对应关系。例如，以图5所示的栅极驱动电路为例，第一级移位寄存器RS1的复位信号端RST与第二级移位寄存器RS2的级联信号输出端Oput_c耦接，第一级移位寄存器RS1的级联信号输出端Oput_c与第三级移位寄存器RS3的信号输入端Iput耦接，这样，第一级移位寄存器的复位阶段S4对应第二级移位寄存器的输出阶段S3，第一级移位寄存 器的输出阶段S3对应第二级移位寄存器的输入阶段S2，以此类推，此处不再赘述。
在此基础上，以下以图5中示出的栅极驱动电路01(由图4的移位寄存器级联而成)中的第一级移位寄存器RS1为例，并结合图6中的时序控制图，对本公开的移位寄存器在一图像帧(一个帧周期)内的驱动方法进行说明。
参考图5和图6，对于第一级移位寄存器RS1而言，其信号输入端Iput与第一起始信号端STV1耦接，复位信号端RST与第二级移位寄存器RS2的级联信号输出端(图6中的Oput_c’)耦接；第一时钟信号端CLK1与第一系统时钟信号端ck1耦接，第二时钟信号端CLK2与第二系统时钟信号端ck2耦接、第三时钟信号端CLK3与第三系统时钟信号端ck3耦接。该第一级移位寄存器RS1的驱动方法包括：一个帧周期包括预充电阶段S1、输入阶段S2、输出阶段S3和复位阶段S4。
预充电阶段S1：
(通过第一起始信号端STV1)向信号输入端Iput输入开启电压，输入子电路100接收信号输入端Iput所传输的输入信号input(开启电压)，具体地，在输入信号input的控制下，第二输入控制单元103开启，并将该输入信号input传输至第一节点A，从而对第一节点A进行预充电。
向初始化信号端T_RST输入初始化信号t_rst，初始化信号t_rst的电平为高电平，在初始化信号t_rst的控制下，初始化子电路400开启，将在第一电压信号端VGL处接收的第一电压信号vgl传输至上拉节点PU，以对上拉节点PU的电压进行初始化。
示例性的，参考图4和图6，在输入子电路100的第二输入控制单元103包括第三晶体管M3，在初始化子电路400包括第七晶体管M7的情况下，预充电阶段S1包括：
在输入阶段S2，第一起始信号端STV1所传输的第一起始信号stv1(输入信号input)的电平为高电平，第三晶体管M3导通，将在第一起始信号端STV1处接收的第一起始信号stv1(即输入信号input)传输至第一节点A，第一节点A的电位升高，并对第一电容器C1进行充电。
可以理解的是，在该阶段，第一节点A的电位升高，第一输入控制单元101开启，也就是第一晶体管M1和第二晶体管M2导通，将在第一时钟信号端CLK1处接收的第一时钟信号clk1传输至第二节点B以及上拉节点PU，此时，第一时钟信号clk1的电平为低电平。
向初始化信号端T_RST输入初始化信号t_rst，初始化信号t_rst的电平为 高电平，第七晶体管M7导通，将在第一电压端VGL处接收的第一电压信号vgl传输至上拉节点PU，以对上拉节点PU进行初始化。对于栅极驱动电路01而言，此时所有的移位寄存器中的上拉节点PU均进行初始化。
在一些实施例中，在预充电阶段，可以向第一级移位寄存器的信号输入端Iput和初始化信号端T_RST均输入初始化信号t_rst，即信号输入端Iput不和第一起始信号端STV1耦接，而是连接输入初始化信号t_rst的端口，这样也能够在预充电阶段S1实现对第一节点A的预充电和对上拉节点PU的初始化。
输入阶段S2：
在第一节点A的电压的控制下，第一输入控制单元101持续开启，并将在第一时钟信号端CLK1处接收的第一时钟信号clk1经第二节点B输出至上拉节点PU，此时第一时钟信号clk1的电平为高电平，从而上拉节点PU的电压升高。
同时，增压单元102在第一时钟信号clk1的作用下，抬升第一节点A的电压，以使第一时钟信号clk1在由第一输入控制单元101传输至上拉节点PU的过程中的电压损失减小。
另外，在该输入阶段S2中，在上拉节点PU的电压的控制下，输出子路300开启，将在第二时钟信号端CLK2(即第二系统时钟信号端ck2)处接收的第二时钟信号clk传输至级联信号输出端Oput_c和扫描信号输出端Oput_o。此时，第二时钟信号clk的电平为低电平。
并且，在上拉节点PU的电压的控制下，下拉控制子电路500开启，将在第一电压信号端VGL处接收的第一电压信号vgl传输至至下拉节点PD，从而将下拉节点PD的电位拉低。
这样，在下拉节点PD的电压的控制下，第一降噪子电路600和第二降噪子电路700均关闭。
示例性的，参考图4和图6，在输入子电路100包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第一电容器C1；输出子电路300包括第五晶体管M5、第六晶体管M6和第二电容器C2；下拉控制子电路500包括第八晶体管M8和第九晶体管M9；第一降噪子电路600包括第十晶体管M10；第二降噪子电路700包括第十一晶体管M11和第十二晶体管M12的情况下，输入阶段S2包括：
在第一节点A的高电平电压的控制下，第一晶体管M1和第二晶体管M2导通，将在第一时钟信号端CLK1(即第一系统时钟信号端ck1)处接收的第 一时钟信号clk1经第二节点B输出至上拉节点PU，此时第一时钟信号clk1的电平为高电平，从而第二节点B的电压升高，上拉节点PU的电压升高。
在第一时钟信号clk1的传输过程中，第一电容器C1在第二节点B的高电平电压的作用下发生自举，进一步的抬升第一节点A的电位，从而使得第一晶体管M1和第二晶体管M2的控制极的电压增大，远大于其阈值电压，使得第一时钟信号clk1在由第一输入控制单元101传输至上拉节点PU的过程中的阈值电压损失减小甚至没有电压损失，降低了第一时钟信号clk1在经第二节点B输出至上拉节点PU过程中的电压损失，保证了上拉节点PU具有足够的电位。
同时，在该输入阶段S2，在上拉节点PU的高电压的控制下，第二电容器C2进行充电，第五晶体管M5和第六晶体管M6导通，分别将在第二时钟信号端CLK2处接收的第二时钟信号clk传输至级联信号输出端Oput_c和扫描信号输出端Oput_o。此时，第二时钟信号clk的电平为低电平。
并且，在上拉节点PU的高电压的控制下，第九晶体管M9导通，将在第一电压信号端VGL处接收的第一电压信号vgl传输至至下拉节点PD，从而将下拉节点PD的电位拉低。在下拉节点PD的电压的控制下，第十晶体管M10、第十一晶体管M11和第十二晶体管M12均截止。
输出阶段S3：
第二时钟信号端CLK2传输的第二时钟信号clk2的电平为高电平，输出子电路300在上拉节点PU的电压的控制下保持开启，将在第二时钟信号端CLK2处接收的第二时钟信号clk2传输至级联信号输出端Oput_c和扫描信号输出端Oput_o。此时级联信号输出端Oput_c输出级联信号，扫描信号输出端Oput_o输出扫描信号。同时，在输出子电路300中的第二电容器的自举作用下，上拉节点PU的电位进一步抬升。
另外，在第二时钟信号clk2的控制下，输入复位子电路200开启，将在第一电压信号端VGL处接收的第一电压信号vgl传输至第一节点A，以对第一节点A的电压进行复位。
在上拉节点PU的电压的控制下，下拉控制子电路500保持开启，将在第一电压信号端VGL处接收的第一电压信号vgl传输至至下拉节点PD，从而将下拉节点PD的电位拉低。这样，在下拉节点PD的电压的控制下，第一降噪子电路600和第二降噪子电路700均关闭。
示例性的，参考图4和图6，在输入子电路100包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第一电容器C1；输出子电路300包括第五 晶体管M5、第六晶体管M6和第二电容器C2；下拉控制子电路500包括第八晶体管M8和第九晶体管M9；第一降噪子电路600包括第十晶体管M10；第二降噪子电路700包括第十一晶体管M11和第十二晶体管M12的情况下，输出阶段S3包括：
第二电容器C2对上拉节点PU进行放电，上拉节点PU维持高电平电压，第五晶体管M5和第六晶体管M6导通，分别将在第二时钟信号端CLK2处第二时钟信号clk2传输至级联信号输出端Oput_c和扫描信号输出端Oput_o。并且在该阶段中，第二电容器C2在级联信号输出端Oput_c输出的高电平电压的作用下，通过自举进一步的抬升上拉节点PU的电位。
另外，在上拉节点PU的高电压的控制下，第九晶体管M9导通，将在第一电压信号端VGL处接收的第一电压信号vgl传输至至下拉节点PD，从而将下拉节点PD的电位拉低。这样，在下拉节点PD的电压的控制下，第十晶体管M10、第十一晶体管M11和第十二晶体管M12均截止。
复位阶段S4：
向复位信号端RST输入复位信号reset，此时复位信号reset的电平为高电平，的第三时钟信号clk3的电平为高电平，在第三时钟信号端CLK3(第三系统时钟信号端ck3)所传输的第三时钟信号clk3的控制下，下拉控制子电路500开启，将在复位信号端RST处接收的复位信号reset传输至下拉节点PD，以拉高下拉节点PD的电位。
在下拉节点PD的电压的控制下，第一降噪子电路600开启，将在第一电压信号端VGL处接收的第一电压信号vgl传输至上拉节点PU，以对上拉节点PU进行复位。并且在下拉节点PD的电压的控制下，第二降噪子电路700开启，将在第一电压信号端VGL处接收的第一电压信号vgl传输至级联信号输出端Oput_c和扫描信号输出端Oput_o，以对级联信号输出端Oput_c和扫描信号输出端Oput_o进行复位。
示例性的，参考图4和图6，在下拉控制子电路500包括第八晶体管M8和第九晶体管M9；第一降噪子电路600包括第十晶体管M10；第二降噪子电路700包括第十一晶体管M11和第十二晶体管M12的情况下，复位阶段S4包括：
向复位信号端RST输入复位信号reset，并在第三时钟信号端CLK3(第三系统时钟信号端ck3)的高电平电压的控制下，第八晶体管M8导通，将在复位信号端RST处接收的复位信号reset传输至下拉节点PD。
在下拉节点PD的高电平电压的控制下，第十晶体管M10导通，将在第 一电压信号端VGL处接收的第一电压信号vgl传输至上拉节点PU，以对上拉节点PU进行复位。同时在下拉节点PD的高电平电压的控制下，第十一晶体管M11和第十二晶体管M12导通，将在第一电压信号端VGL处接收的第一电压信号vgl传输至级联信号输出端Oput_c和扫描信号输出端Oput_o，以对级联信号输出端Oput_c和扫描信号输出端Oput_o进行复位。
在复位阶段S4之后到下一图像帧，上拉节点PU和下拉节点PD维持复位阶段S4的状态，即上拉节点PU的电位为低电位，下拉节点PD的电位为高电位。在下拉节点PD的电压的控制下，第一降噪子电路600和第二降噪子电路700开启(即第十晶体管M10、第十一晶体管M11和第十二晶体管M12导通)，将在第一电压端VGL处接收的第一电压信号vgl传输至上拉节点PU、级联信号输出端Oput_c和扫描信号输出端Oput_o，进行降噪。
在此基础上，本公开的发明人通过实际的模拟，将本公开的一些实施例所提供的，如图4中示出的移位寄存器，与相关技术中的移位寄存器进行对比，在相关对应的信号端的电压一致的情况下，采用本公开图4中示出的移位寄存器在输入阶段，上拉节点PU的电压能够达到20V左右，而相关技术中的移位寄存器在输入阶段，上拉节点PU的电压为16.8V左右，可见采用本公开中的移位寄存器，上拉节点PU的电位抬升了3.2V左右。在一些示例中，在移位寄存器中晶体管的阈值电压的出现正向飘移的情况下，相关技术中的移位寄存器在输入阶段，上拉节点PU的电位不足现象会更加明显，而采用本公开的移位寄存器对上拉节点的电压抬升作用会更加明显。
需要说明的是，本公开的实施例提供的移位寄存器中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开中的晶体管可以为增强型晶体管，也可以为耗尽型晶体管，本公开对此并不设限。
在一些实施例中，移位寄存器中所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
另外，在本公开的实施例提供的移位寄存器中，晶体管均以N型晶体管为例进行说明。需要说明的是，本公开的实施例包括但不限于此。例如，本公开的实施例提供的移位寄存器中的一个或多个晶体管也可以采用P型晶体 管，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种移位寄存器，包括：输入子电路；所述输入子电路与信号输入端耦接；
    所述输入子电路包括：第一输入控制单元和增压单元；
    所述第一输入控制单元与第一时钟信号端、第一节点、第二节点和上拉节点耦接；所述第一节点被配置为接收所述信号输入端所传输的输入信号；
    所述增压单元耦接在所述第一节点和所述第二节点之间；
    所述第一输入控制单元被配置为：在所述第一节点的电压的控制下，将在所述第一时钟信号端处接收的第一时钟信号经所述第二节点传输至所述上拉节点；
    所述增压单元被配置为：在所述第一时钟信号的作用下，在第二节点的电位升高时，抬升所述第一节点的电压，以使所述第一时钟信号在由所述第一输入控制单元传输至所述上拉节点的过程中的电压损失减小。
  2. 根据权利要求1所述的移位寄存器，其中，
    所述第一输入控制单元包括：第一晶体管和第二晶体管；
    所述第一晶体管的控制极与所述第一节点耦接，所述第一晶体管的第一极与所述第一时钟信号端耦接，所述第一晶体管的第二极与所述第二节点耦接；
    所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第二节点耦接，所述第二晶体管的第二极与所述上拉节点耦接；
    所述增压单元包括：第一电容器；所述第一电容器的第一极与所述第一节点耦接，所述第一电容器的第二极与所述第二节点耦接。
  3. 根据权利要求1或2所述的移位寄存器，其中，
    所述信号输入端与所述第一节点耦接；
    或者，所述输入子电路还包括：第二输入控制单元；
    所述信号输入端通过所述第二输入控制单元与所述第一节点耦接；
    所述第二输入控制单元被配置为响应于在所述信号输入端处接收的输入信号，将所述输入信号传输至所述第一节点。
  4. 根据权利要求3所述的移位寄存器，其中，在所述移位寄存器还包括第二输入控制单元的情况下：
    所述第二输入控制单元包括第三晶体管；所述第三晶体管的控制极和第一极与所述信号输入端耦接，第三晶体管的第二极与所述第一节点耦接。
  5. 根据权利要求1～4中任一项所述的移位寄存器，还包括：输入复位子电路；
    所述输入复位子电路与第二时钟信号端、第一电压信号端和所述第一节点耦接；所述输入复位子电路被配置为响应于在所述第二时钟信号端处接收的第二时钟信号，将在所述第一电压信号端处接收的第一电压信号传输至所述第一节点，以对所述第一节点复位。
  6. 根据权利要求5所述的移位寄存器，其中，所述输入复位子电路包括第四晶体管；
    所述第四晶体管的控制极与所述第二时钟信号端耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第一节点耦接。
  7. 根据权利要求1～6中任一项所述的移位寄存器，还包括：输出子电路；
    所述输出子电路与第二时钟信号端、所述上拉节点、扫描信号输出端和级联信号输出端耦接；所述输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述扫描信号输出端和所述级联信号输出端。
  8. 根据权利要求7所述的移位寄存器，其中，所述输出子电路包括第五晶体管、第六晶体管和第二电容器；
    所述第五晶体管的控制极与所述上拉节点耦接，所述第五晶体管的第一极与所述第二时钟信号端耦接，所述第五晶体管的第二极与所述级联信号输出端耦接；
    所述第六晶体管的控制极与所述上拉节点耦接，所述第六晶体管的第一极与所述第二时钟信号端耦接，所述第六晶体管的第二极与所述扫描信号输出端耦接；
    所述第二电容器的第一极与所述上拉节点耦接，第二极与所述级联信号输出端耦接。
  9. 根据权利要求1～8中任一项所述的移位寄存器，还包括：初始化子电路、下拉控制子电路、第一降噪子电路、第二降噪子电路；
    所述初始化子电路与初始化信号端、第一电压信号端和所述上拉节点耦接；所述初始化子电路被配置为响应于在所述初始化信号端处接收的初始化信号，将在所述第一电压信号端处接收的第一电压信号传输至所述上拉节点；
    所述下拉控制子电路与复位信号端、第三时钟信号端、所述第一电压信号端、所述上拉节点和下拉节点耦接；所述下拉控制电路被配置为，响应于在所述第三时钟信号端处接收的第三时钟信号，将在所述复位信号端处接收的复位信号传输至所述下拉节点；及，在所述上拉节点的电压的控制下，将 在所述第一电压信号端处接收的第一电压信号传输至所述下拉节点；
    所述第一降噪子电路与所述下拉节点、所述第一电压信号端和所述上拉节点耦接；所述第一降噪子电路被配置为在所述下拉节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述上拉节点；
    所述第二降噪电路与所述下拉节点、所述第一电压信号端、扫描信号输出端和级联信号输出端耦接；所述第二降噪子电路被配置为：在所述下拉节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述扫描信号输出端和所述级联信号输出端。
  10. 根据权利要求9所述的移位寄存器，其中，
    所述初始化子电路包括第七晶体管；所述第七晶体管的控制极与所述初始化信号端耦接，所述第七晶体管的第一极与所述第一电压信号端耦接，所述第七晶体管的第二极与所述上拉节点耦接；
    所述下拉控制电路包括第八晶体管和第九晶体管；
    所述第八晶体管的控制极与所述第三时钟信号端耦接，所述第八晶体管的第一极与所述复位信号端耦接，所述第八晶体管的第二极与所述下拉节点耦接；所述第九晶体管的控制极与所述上拉节点耦接，所述第九晶体管的第一极与所述第一电压信号端耦接，所述第九晶体管的第二极与所述下拉节点耦接；
    所述第一降噪子电路包括第十晶体管；所述第十晶体管的控制极与所述下拉节点耦接，所述第十晶体管的第一极与所述第一电压信号端耦接，所述第十晶体管的第二极与所述上拉节点耦接；
    所述第二降噪子电路包括第十一晶体管和第十二晶体管；
    所述第十一晶体管的控制极与所述下拉节点耦接，所述第十一晶体管的第一极与所述第一电压信号端耦接，所述第十一晶体管的第二极与所述级联信号输出端耦接；所述第十二晶体管的控制极与所述下拉节点耦接，所述第十二晶体管的第一极与所述第一电压信号端耦接，所述第十二晶体管的第二极与所述扫描信号输出端耦接。
  11. 根据权利要求1所述的移位寄存器，还包括：输入复位子电路、输出子电路、初始化子电路、下拉控制子电路、第一降噪子电路和第二降噪子电路；其中，
    所述输入子电路包括第一晶体管、第二晶体管、第三晶体管和第一电容器；所述输入复位子电路包括第四晶体管；所述输出子电路包括第五晶体管、第六晶体管和第二电容器；所述初始化子电路包括第七晶体管；所述下拉控 制子电路包括第八晶体管和第九晶体管；所述第一降噪子电路包括第十晶体管；所述第二降噪子电路包括第十一晶体管和第十二晶体管；
    所述第一晶体管的控制极与所述第一节点耦接，所述第一晶体管的第一极与所述第一时钟信号端耦接，所述第一晶体管的第二极与所述第二节点耦接；
    所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第二节点耦接，所述第二晶体管的第二极与所述上拉节点耦接；
    所述第三晶体管的控制极和第一极与所述信号输入端耦接，第三晶体管的第二极与所述第一节点耦接；
    所述第一电容器的第一极与所述第一节点耦接，所述第一电容器的第二极与所述第二节点耦接；
    所述第四晶体管的控制极与所述第二时钟信号端耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第一节点耦接；
    所述第五晶体管的控制极与所述上拉节点耦接，所述第五晶体管的第一极与所述第二时钟信号端耦接，所述第五晶体管的第二极与所述级联信号输出端耦接；
    所述第六晶体管的控制极与所述上拉节点耦接，所述第六晶体管的第一极与所述第二时钟信号端耦接，所述第六晶体管的第二极与所述扫描信号输出端耦接；
    所述第二电容器的第一极与所述上拉节点耦接，第二极与所述级联信号输出端耦接；
    所述第七晶体管的控制极与所述初始化信号端耦接，所述第七晶体管的第一极与所述第一电压信号端耦接，所述第七晶体管的第二极与所述上拉节点耦接；
    所述第八晶体管的控制极与所述第三时钟信号端耦接，所述第八晶体管的第一极与所述复位信号端耦接，所述第八晶体管的第二极与所述下拉节点耦接；
    所述第九晶体管的控制极与所述上拉节点耦接，所述第九晶体管的第一极与所述第一电压信号端耦接，所述第九晶体管的第二极与所述下拉节点耦接；
    所述第十晶体管的控制极与所述下拉节点耦接，所述第十晶体管的第一极与所述第一电压信号端耦接，所述第十晶体管的第二极与所述上拉节点耦 接；
    所述第十一晶体管的控制极与所述下拉节点耦接，所述第十一晶体管的第一极与所述第一电压信号端耦接，所述第十一晶体管的第二极与所述级联信号输出端耦接；
    所述第十二晶体管的控制极与所述下拉节点耦接，所述第十二晶体管的第一极与所述第一电压端信号耦接，所述第十二晶体管的第二极与所述扫描信号输出端耦接。
  12. 一种如权利要求1～11中任一项所述的移位寄存器的驱动方法，包括：
    一个帧周期包括预充电阶段和输入阶段，
    在所述预充电阶段：
    第一节点接收信号输入端所传输的输入信号；
    在所述输入阶段：
    在第一节点的电压的控制下，第一输入控制单元开启，将在所述第一时钟信号端处接收的第一时钟信号经所述第二节点传输至所述上拉节点；
    增压单元在所述第一时钟信号的作用下，抬升所述第一节点的电压，以使所述第一时钟信号在由所述第一输入控制单元传输至所述上拉节点的过程中的电压损失减小。
  13. 根据权利要求12所述的驱动方法，其中，在所述移位寄存器的输入子电路还包括第二输入控制单元的情况下，
    在所述预充电阶段：
    在所述信号输入端传输的输入信号的控制下，所述第二输入控制单元开启，将所述输入信号传输至所述第一节点。
  14. 根据权利要求13所述的驱动方法，其中，在所述移位寄存器还包括输入复位子电路和输出子电路的情况下，一个帧周期还包括位于所述输入阶段之后的输出阶段，
    在所述输出阶段：
    在第二时钟信号端传输的第二时钟信号的控制下，所述输入复位子电路开启，将在所述第一电压信号端处接收的第一电压信号传输至所述第一节点，以对所述第一节点复位；
    在所述上拉节点的电压的控制下，所述输出子电路开启，将在所述第二时钟信号端处接收的第二时钟信号传输至所述扫描信号输出端和所述级联信号输出端。
  15. 一种栅极驱动电路，包括N级级联的如权利要求1～11中任一项所述 的移位寄存器；其中，N为正整数。
  16. 根据权利要求15所述栅极驱动电路，其中，在所述移位寄存器还包括输出子电路、初始化子电路、下拉控制子电路、第一降噪子电路和第二降噪子电路的情况下，在所述栅极驱动电路中：
    第一级移位寄存器的信号输入端与起始信号端耦接；
    第二级移位寄存器的信号输入端与起始信号端耦接；
    第i级移位寄存器的信号输入端与第i-2级移位寄存器的级联信号输出端耦接；其中，3≤i≤N；i为正整数；
    第j级移位寄存器的复位信号端与第j+1级移位寄存器的级联信号输出端耦接；1≤j≤N-1；j为正整数；
    第N级移位寄存器的复位信号端单独设置，或者与所述起始信号端耦接。
  17. 根据权利要求15或16所述栅极驱动电路，其中，
    第3t+1级移位寄存器的第一时钟信号端、第二时钟信号端、第三时钟信号端分别依次与第一系统时钟信号端、第二系统时钟信号端、第三系统时钟信号端耦接；
    第3t+2级移位寄存器的第一时钟信号端、第二时钟信号端、第三时钟信号端分别依次与所述第二系统时钟信号端、所述第三系统时钟信号端、所述第一系统时钟信号端耦接；
    第3t+3级移位寄存器的第一时钟信号端、第二时钟信号端、第三时钟信号端分别依次与所述第三系统时钟信号端、所述第一系统时钟信号端、所述第二系统时钟信号端耦接；
    其中，3t+3≤N，t为非负整数。
  18. 一种显示装置，包括如权利要求15～17中任一项所述的栅极驱动电路。
PCT/CN2020/085692 2019-05-07 2020-04-20 移位寄存器及其驱动方法、栅极驱动电路、显示装置 WO2020224422A1 (zh)

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