WO2020255347A1

WO2020255347A1 - Micro led device and method for manufacturing same

Info

Publication number: WO2020255347A1
Application number: PCT/JP2019/024564
Authority: WO
Inventors: 克彦岸本
Original assignee: 堺ディスプレイプロダクト株式会社
Priority date: 2019-06-20
Filing date: 2019-06-20
Publication date: 2020-12-24

Abstract

A micro LED device according to the present disclosure is provided with: an insulated crystal- growing substrate, (100) the upper surface of which is covered by a conductive mask layer (150) having a plurality of open sections (150G); and a front plane (200) that includes a plurality of micro LEDs (220), each having a first conductive-type first semiconductor layer (21) and a second conductive-type second semiconductor layer (22), and element separating regions (240) positioned between micro LEDs. The element separating regions each have at least one metal plug (24) electrically connected to the second semiconductor layer. This device is provided with: an intermediate layer (300) that includes a first contact electrode (31) electrically connected to the first semiconductor layer and a second contact electrode (32) electrically connected to the metal plug; and a back plane (400) formed on the intermediate layer. The first and second semiconductor layers are epitaxial layers selectively grown from the plurality of mask open sections of the mask layer, and the second semiconductor layer is in ohmic contact with the mask layer.

Description

Micro LED device and its manufacturing method

This disclosure relates to a micro LED device and a method for manufacturing the same.

In order to put into practical use a display device in which a large number of micro LEDs are arranged at a narrow pitch, it is necessary to develop a mass production technology for mounting fine micro LEDs at predetermined positions on a mounting circuit board such as a TFT board. According to the technology of mounting individual micro LEDs on a circuit by a pick-and-place method, mounting a large number of micro LEDs on a circuit at a pitch of, for example, several tens of μm is a very long working time. And requires a great deal of cost.

Patent Document 1 discloses a display device including a large number of micro LEDs transferred onto a TFT substrate and a method for manufacturing the same.

Patent Document 2 discloses a display device including a GaN wafer on which a plurality of LEDs are formed and a backplane control unit (TFT substrate) to which the GaN wafers are bonded, and a method for manufacturing the display device.

Special Table 2016-522585 Gazette Special Table 2017-538290

The method of transferring a large number of micro LEDs onto the TFT substrate has a problem that the size of the micro LEDs becomes small and the number of the micro LEDs increases, it becomes difficult to align the micro LEDs with respect to the TFT substrate. Further, the method of joining the GaN wafer to the backplane control unit also requires a complicated process of transferring the GaN wafer to the wafer temporarily holding the GaN wafer and further mounting the GaN wafer on the backplane control unit.

The present disclosure provides a new structure and manufacturing method of a micro LED device that can solve the above problems.

In an exemplary embodiment, the micro LED device of the present disclosure is an insulating crystal growth substrate whose upper surface is covered with a mask layer having a plurality of openings, and a front plane supported by the crystal growth substrate. Each includes a plurality of microLEDs each having a first conductive type first semiconductor layer and a second conductive type second semiconductor layer, and an element separation region located between the plurality of microLEDs. A front plane having at least one metal plug electrically connected to the second semiconductor layer and an intermediate layer supported by the front plane, each of the plurality of microLEDs. An intermediate layer including a plurality of first contact electrodes electrically connected to the first semiconductor layer and at least one second contact electrode connected to the metal plug, and a back plane supported by the intermediate layer. The electric circuit includes an electric circuit electrically connected to the plurality of micro LEDs via the plurality of first contact electrodes and the at least one second contact electrode, and the electric circuit includes a plurality of thin film transistors. , With a back plane. The mask layer is formed of a conductive material, and the mask layer has a plurality of mask openings defining the positions of the plurality of micro LEDs and a connection portion connected to the metal plug. The first semiconductor layer and the second semiconductor layer of the micro LED are epitaxial layers selectively grown from the plurality of mask openings of the mask layer, and the second semiconductor layer is ohmic to the mask layer. Are in contact. Each of the plurality of thin film transistors has a semiconductor layer grown on the front plane and / or the intermediate layer.

In certain embodiments, the mask layer is in electrical resistant or insulating contact with the first semiconductor layer.

In certain embodiments, the second semiconductor layer partially overlaps the mask layer.

In certain embodiments, the conductive type of the second semiconductor layer is p-type, and the mask layer is at least one refractory metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ta. Is formed from.

In a certain embodiment, an insulating layer that insulates the mask layer from the first semiconductor layer is provided on the mask layer.

In certain embodiments, the second semiconductor layer has a portion that grows laterally on the mask layer, and the portion that grows laterally partially overlaps the insulating layer. ing.

In certain embodiments, the mask opening has a different size or shape depending on its position on the substrate, and the size or shape of the mask opening is the size or shape of the light emitted from each micro LED. Define the wavelength.

In certain embodiments, the element separation region of the front plane has an embedded insulator that fills between the plurality of micro LEDs, the embedded insulator being at least one through hole for the metal plug. have.

In certain embodiments, the front plane has a flat surface, which is in contact with the intermediate layer.

In certain embodiments, the intermediate layer comprises an interlayer insulating layer having a flat surface, and the interlayer insulating layer connects the plurality of first contact electrodes and the at least one second contact electrode to the electric circuit, respectively. It has a plurality of contact holes for forming the contact holes and via electrodes for filling the contact holes.

In certain embodiments, each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode formed on the flat surface of the interlayer insulating layer, and the semiconductor layer is the gate electrode. It is located above and is in contact with the upper surfaces of the source electrode and the drain electrode.

In certain embodiments, each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode located above the semiconductor layer, and the semiconductor layer is a flat surface of the interlayer insulating layer. A part of the semiconductor layer is formed above, and is sandwiched from above and below by at least one of the source electrode and the drain electrode and the via electrode.

The method for manufacturing the micro LED device of the present disclosure is, in an exemplary embodiment, a front plane supported by an insulating crystal growth substrate, the first semiconductor layer of the first conductive type and the second conductive type, respectively. The element separation region includes a plurality of micro LEDs having the second semiconductor layer, and an element separation region located between the plurality of micro LEDs, and the element separation region is electrically connected to the second semiconductor layer. A front plane having a metal plug, and a plurality of first contacts electrically connected to the first semiconductor layer of the plurality of micro LEDs, each of which is an intermediate layer supported by the front plane. A step of preparing a laminated structure including an intermediate layer including an electrode and at least one second contact electrode connected to the metal plug, and a step of forming a back plane on the laminated structure. It has an electric circuit electrically connected to the plurality of micro LEDs via a plurality of first contact electrodes and the at least one second contact electrode, and the electric circuit forms a back plane including a plurality of thin films. Including the process of The steps of preparing the laminated structure are a step of forming the mask layer which is a mask layer covering the crystal growth substrate and has a plurality of mask openings defining the positions of the plurality of micro LEDs, and a step of forming the mask. This includes a step of sequentially growing the second semiconductor layer and the first semiconductor layer from the opening. The mask layer is formed of a conductive material, the second semiconductor layer is in ohmic contact with the mask layer, and the steps of forming the back plane include a step of depositing the semiconductor layer on the laminated structure and the step of depositing the semiconductor layer on the laminated structure. It includes a step of patterning the semiconductor layer on the laminated structure.

In certain embodiments, the shape and position of the element separation region is defined by the second semiconductor layer and the first semiconductor layer selectively grown from the plurality of mask openings of the mask layer.

In a certain embodiment, the step of preparing the laminated structure is a step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings, and then the mask layer and the second. Includes a heat treatment step to complete ohmic contact with the semiconductor layer.

In a certain embodiment, in the step of preparing the laminated structure, the heat treatment step is performed before the front plane is completed.

In a certain embodiment, ohmic contact between the mask layer and the second semiconductor layer is performed by heating during a step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings. To complete.

According to the embodiment of the present invention, a micro LED device that solves the above-mentioned problems and a method for manufacturing the same are provided.

It is sectional drawing which shows a part of the μLED device 1000 by this disclosure. It is a top view which shows the arrangement example of the μLED 220 in the μLED device 1000. It is a top view which shows the arrangement example of the metal plug 24 in the μLED device 1000. It is a top view which shows the other arrangement example of the metal plug 24 in the μLED device 1000. It is a perspective view which shows the arrangement example of the 1st contact electrode 31 and the 2nd contact electrode 32 in the μLED device 1000. It is a circuit diagram which shows a part example of the electric circuit in the μLED device 1000. It is a perspective view which shows typically the manufacturing process of the μLED device 1000. It is a perspective view which shows typically the manufacturing process of the μLED device 1000. It is a perspective view which shows typically the manufacturing process of the μLED device 1000. It is a perspective view which shows typically the manufacturing process of the μLED device 1000. It is a perspective view which shows typically the manufacturing process of the μLED device 1000. It is a perspective view which shows typically the manufacturing process of the μLED device 1000. It is a perspective view which shows typically the manufacturing process of the μLED device 1000. It is a perspective view which shows typically the manufacturing process of the μLED device 1000. It is a perspective view which shows a part of the μLED device 1000 provided with the cylindrical μLED 220. It is a top view of the μLED device 1000 including the cylindrical μLED 220. It is sectional drawing of the μLED device 1000A in embodiment of this disclosure. It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. It is sectional drawing which shows the other structural example of the μLED device 1000A in embodiment of this disclosure. It is sectional drawing which shows still another structural example of the μLED device 1000A in embodiment of this disclosure. It is sectional drawing which shows the structural example of the μLED device 1100 in the modified example of the embodiment of this disclosure. It is sectional drawing which shows typically the structure of the μLED device 1000B in still another Embodiment by this disclosure. It is sectional drawing which shows typically the structure of the μLED device 1000C in still another Embodiment by this disclosure. It is a perspective view which shows typically the structure of the μLED device 1000C of FIG. 12A. It is sectional drawing which shows typically the structure of the μLED device 1000D in still another Embodiment by this disclosure. It is a perspective view which shows typically the structure of the μLED device 1000D of FIG. 13A.

<Definition>
The “micro LED” in the present disclosure means a light emitting diode (LED) having a size included in an area of 100 μm × 100 μm in which the size of the occupied area is 100 μm × 100 μm. The "light" emitted by the micro LED is not limited to visible light, but includes a wide range of visible, ultraviolet, or infrared electromagnetic waves. Hereinafter, "micro LED" may be referred to as "μLED".

The μLED has a first conductive type first semiconductor layer and a second conductive type second semiconductor layer. The first conductive type is one of the p-type and the n-type, and the second conductive type is the other of the p-type and the n-type. For example, when the first conductive type is p type, the second conductive type is n type. On the contrary, when the first conductive type is n type, the second conductive type is p type. Each of the first semiconductor layer and the second semiconductor layer may have a single-layer structure or a multi-layer structure. Typically, a light emitting layer having at least one quantum well (or double heterostructure) is formed between the first semiconductor layer and the second semiconductor layer.

The "micro LED device (μLED device)" in the present disclosure is a device including a plurality of μLEDs. A plurality of μLEDs in a μLED device may be referred to as a “μLED array”. A typical example of a μLED device is a display device, but the μLED device is not limited to a display device.

<Basic configuration>
A basic configuration example of the μLED device of the present disclosure will be described with reference to FIGS. 1A and 1B. FIG. 1A is a cross-sectional view showing a part of the μLED device 1000. FIG. 1B is a plan view showing an arrangement example of the μLED array in the μLED device 1000. The cross section of the μLED device 1000 shown in FIG. 1A corresponds to the cross section taken along line AA of FIG. 1B.

The μLED device 1000 may include a large number of μLEDs, for example, exceeding 1 million. 1A and 1B show only a portion of the μLED device 1000 containing a few μLEDs. The entire μLED device 1000 has a configuration in which the illustrated portions are periodically arranged.

The μLED device 1000 includes an insulating crystal growth substrate 100, a front plane 200 supported by the crystal growth substrate 100, an intermediate layer 300 supported by the front plane 200, and a backplane 400 supported by the intermediate layer. I have.

In the attached drawings, the ratio of the horizontal size to the vertical size of each component such as μLED does not necessarily reflect the actual ratio in the embodiment. In the drawings, each component is described in a ratio that prioritizes clarity. Further, the orientation of each component in the drawing does not limit the orientation when the μLED device is actually manufactured and the orientation when used. For reference, FIGS. 1A and 1B show right-handed coordinate axes of the X-axis, Y-axis, and Z-axis that are orthogonal to each other.

<Crystal growth substrate>
The crystal growth substrate 100 is a substrate on which semiconductor crystals constituting the μLED grow epitaxially. Hereinafter, such a crystal growth substrate is simply referred to as a "substrate". The surface 100T on which crystal growth of the substrate 100 occurs is referred to as an "upper surface" or "crystal growth surface", and the surface 100B on the opposite side of the substrate 100 is referred to as a "lower surface". As used herein, the terms "top" and "bottom" are used independently of the actual orientation of the substrate 100.

A typical example of a semiconductor crystal that can be used in the embodiment of the present disclosure is a gallium nitride based compound semiconductor. Hereinafter, the gallium nitride based compound semiconductor may be referred to as “GaN”. A part of the gallium (Ga) atom in GaN may be replaced by an aluminum (Al) atom or an indium (In) atom. A GaN in which a part of a Ga atom is replaced with an Al atom may be referred to as "AlGaN". Further, GaN in which a part of Ga atom is replaced with In atom may be referred to as "InGaN". Further, GaN in which a part of Ga atom is replaced with Al atom and In atom may be referred to as "AlInGaN" or "InAlGaN". The bandgap of GaN is smaller than the bandgap of AlGaN and larger than the bandgap of InGaN. In the present disclosure, gallium nitride based compound semiconductors in which some of the constituent atoms are replaced with other atoms may be collectively referred to as “GaN”. The "GaN" can be doped with n-type impurities and / or p-type impurities as impurity ions. GaN whose conductive type is n-type is referred to as "n-GaN", and GaN whose conductive type is p-type is referred to as "p-GaN". The details of the semiconductor crystal growth method will be described later. In the embodiment of the present disclosure, the semiconductor crystal constituting the μLED is not limited to the GaN-based semiconductor, and may be formed of a nitride semiconductor such as AlN, InN, or AlInN, or another semiconductor.

The substrate 100 in the present disclosure has an insulating property, and the upper surface 100T of the substrate 100 is covered with a mask layer 150 having a plurality of openings. The mask layer 150 can be formed of, for example, a refractory metal (conductive material) such as titanium (Ti), chromium (Cr), molybdenum (Mo), manganese (Mn), tungsten (W), and tantalum (Ta). The mask layer 150 has a plurality of mask openings 150G that define the positions and arrangements of a plurality of μLED 220s, which will be described later, and a connection portion 150C that is connected to the metal plug 24. The connection portion 150C is a portion of the mask layer 150 that is in contact with the metal plug 24. Another conductive layer may be interposed between the connection portion 150C and the metal plug 24.

An example of the substrate 100 is a sapphire substrate. The sapphire substrate has high translucency for visible light and ultraviolet rays having a wavelength of 300 nm or more, and is particularly preferable as the insulating crystal growth substrate 100.

In the embodiments of the present disclosure, the substrate 100 is a component of the final μLED device 1000. The thickness of the substrate 100 can be, for example, 30 μm or more and 1000 μm or less, preferably 500 μm or less. Since the role of the substrate 100 is to serve as a base for crystal growth, the rigidity of the μLED device 1000 may be supplemented by a rigid member other than the substrate 100. Such a rigid member can be fixed to, for example, the backplane 400. During the manufacturing process, a support substrate (not shown) that supplements the rigidity of the substrate 100 may be fixed to the lower surface 100B of the substrate 100. Such a support substrate may be removed from the final μLED device 1000, or may be used while being fixed to the substrate 100.

The upper surface (crystal growth surface) 100T of the substrate 100 may be provided with a structure such as a groove or a ridge that alleviates the crystal lattice strain. The lower surface 100B of the substrate 100 may be formed with fine irregularities for improving the extraction efficiency of the light radiated from the μLED array and transmitted through the substrate 100 or for diffusing the light. Examples of fine irregularities include a moth-eye structure. Since the moth-eye structure continuously changes the effective refractive index on the lower surface 100B of the substrate 100, the ratio (reflectance) reflected inside the substrate 100 on the lower surface 100B of the substrate 100 is significantly reduced (substantially). Can be zero).

In the present disclosure, the positive direction of the Z axis (direction of the arrow) shown in FIG. 1A may be referred to as "crystal growth direction" or "semiconductor lamination direction". Further, the lower surface 100B and the upper surface 100T of the substrate 100 may be referred to as "front" and "back" of the substrate 100, respectively.

<Front plane>
The front plane 200 includes a plurality of μLEDs 220 and an element separation region 240 located between the plurality of μLEDs 220. The plurality of μLED 220s can be arranged in rows and columns in a two-dimensional plane (XY plane) parallel to the upper surface 100T of the substrate 100. In the illustrated example, each of the plurality of μLED 220s has a first conductive type first semiconductor layer 21 and a second conductive type second semiconductor layer 22, as shown in FIG. 1A.

In the embodiment of the present disclosure, the second semiconductor layer 22 of each μLED 220 is located in the region defined by the mask opening 150G of the mask layer 150. As will be described later, when the epitaxial growth step of the semiconductor crystal is started, the second semiconductor layer 22 is a semiconductor crystal that is selectively grown from a region exposed through the mask opening 150G on the upper surface 100T of the substrate 100. Is formed from. At this time, ohmic contact is realized at the portion where the mask layer 150 and the second semiconductor layer 22 are in contact with each other. The heat treatment for achieving ohmic contact will be described later.

In the embodiment of the present disclosure, each μLED 220 has a light emitting layer 23 that can emit light independently of the other μLED 220. The light emitting layer 23 is located between the first semiconductor layer 21 and the second semiconductor layer 22. The element separation region 240 has at least one metal plug 24 electrically connected to the second semiconductor layer 22. The metal plug 24 functions as a substrate-side electrode of the μLED 220. More specifically, the metal plug 24 connects the second semiconductor layers 22 of the plurality of μLED 220s to each other via the connecting portion 150C of the mask layer 150.

A typical example of the first conductive type first semiconductor layer 21 is a p-GaN layer. A typical example of the second conductive type second semiconductor layer 22 is an n-GaN layer. The p-GaN layer and the n-GaN layer do not have to have the same composition along the direction perpendicular to the upper surface 100T of the substrate 100 (semiconductor stacking direction: positive direction of the Z axis), and have a multilayer structure. Can have. As mentioned above, Ga in GaN can be at least partially replaced by Al and / or In. Such substitutions may be made to adjust the bandgap and / or index of refraction of the GaN. Further, the concentrations of p-type impurities and n-type impurities, that is, the doping level, need not be uniform along the semiconductor stacking direction (positive direction of the Z axis).

A typical example of the light emitting layer 23 includes at least one InGaN well layer. When the light emitting layer 23 includes a plurality of InGaN well layers, a GaN barrier layer or an AlGaN barrier layer having a bandgap larger than that of the InGaN well layer may be arranged between the InGaN well layers. The InGaN well layer and the AlGaN barrier layer may be the InAlGaN well layer and the InAlGaN barrier layer, respectively. The bandgap of the InGaN well layer defines the emission wavelength. Specifically, assuming that the emission wavelength in vacuum is λ [nm] and the band gap is Eg [electron volt: eV], the relationship of λ × Eg = 1240 is established. Therefore, for example, in order to emit blue light of λ = 450 nm, the bandgap Eg of the InGaN well layer may be adjusted to about 2.76 eV. The bandgap of the InGaN well layer can be adjusted according to the In composition ratio in the InGaN well layer. When the InAlGaN well layer is used, the bandgap can be similarly adjusted according to the In and Al composition ratio. The In composition ratio in the InGaN well layer growing on the substrate 100 has substantially the same value on the entire surface of the substrate 100. Therefore, the plurality of μLED 220s formed on the same substrate 100 emit light having substantially the same wavelength.

The plurality of semiconductor layers constituting each μLED 220 are single crystal layers (epitaxial layers) epitaxially grown on the substrate 100, respectively. The element separation region 240 is defined by a trench-shaped recess (hereinafter referred to as a “trench”) formed by a space between a plurality of semiconductor layers epitaxially grown on the substrate 100. The occupied region of each μLED 220 separated by the trench has a size (for example, a region of 10 μm × 10 μm) included in the region of 100 μm × 100 μm. The occupied area of the μLED 220 is defined by the contour of the first semiconductor layer 21 divided by the element separation area 240.

As shown in FIG. 1B, the element separation region 240 surrounds each μLED 220 and separates each μLED 220 from the other μLED 220. More specifically, the element separation region 240 electrically and spatially separates the first semiconductor layer 21 and the light emitting layer 23 of each μLED 220 from the first semiconductor layer 21 and the light emitting layer 23 of the other μLED 220. ing.

In the present disclosure, the element separation region 240 is a region located between a plurality of μLEDs 220 formed by selective growth of the semiconductor layer, and is not a recess formed by deeply etching the semiconductor layer. According to the embodiment of the present disclosure, steps such as lithography required for etching are not required, and damage to the semiconductor layer due to etching can be prevented.

In this example, the element separation region 240 has an embedded insulator 25 that fills the space between the plurality of μLEDs 220. The embedded insulator 25 has one or more through holes for the metal plug 24. The through holes are filled with the metal material constituting the metal plug 24. The metal plug 24 may have a structure in which different metal layers are stacked.

In the example shown in FIG. 1B, a plurality of metal plugs 24 are arranged discretely, but the embodiment of the present disclosure is not limited to such an example. Each of the plurality of metal plugs 24 may have a ring shape surrounding the corresponding μLED 220. Further, the metal plug 24 may have a striped shape extending in parallel in one direction as shown in FIG. 1C, or may be a single conductor having a lattice shape as shown in FIG. 1D. Good.

The metal plug 24 does not transmit light. Therefore, when the metal plug 24 has a shape surrounding each μLED 220 (for example, when it has the shape of FIG. 1D), the metal plug 24 emits light emitted from each μLED 220 from another μLED 220. Produces the effect of preventing mixing with light. Instead of the metal plug 24 functioning as such a light-shielding member, a light-shielding member surrounding each μLED 220 may be separately provided in the element separation region 240. As described above, the element separation region 240 may have an additional function of optically separating the light emitting layer 23 of each μLED 220 from the light emitting layer 23 of another μLED 220.

In the embodiments of the present disclosure, it is preferable that the upper surface of the front plane 200 is flattened as shown in FIG. 1A. Such flattening is realized by the level of the upper surface of the metal plug 24 and the embedded insulator 25 in the element separation region 240 substantially matching the level of the upper surface of the first semiconductor layer 21 in the μLED 220.

<Middle layer>
The intermediate layer 300 includes a plurality of first contact electrodes 31 and a second contact electrode 32 (see FIG. 1A). Each of the plurality of first contact electrodes 31 is electrically connected to the first semiconductor layer 21 of the plurality of μLED 220s. At least one second contact electrode 32 is connected to the metal plug 24.

FIG. 2 is a perspective view showing an arrangement example of the first contact electrode 31 and the second contact electrode 32. In FIG. 2, since the arrangement example of the

contact electrodes

31 and 32 is shown, the description of the backplane 400 is omitted. The structure shown in FIG. 2 is only a part of the μLED device 1000, and as described above, the embodiment of the μLED device 1000 includes a large number of μLED 220s.

The second contact electrode 32 shown in FIG. 2 is electrically connected to the second semiconductor layer 22 via a metal plug 24. The shape and size of the second contact electrode 32 are not limited to the examples shown. As described above, since the metal plug 24 can take various shapes, the degree of freedom in arranging the second contact electrode 32 is high as long as it is electrically connected to the second semiconductor layer 22 via the metal plug 24. On the other hand, the first contact electrode 31 is independently electrically connected to the first semiconductor layer 21 of the plurality of μLED 220s. When viewed from a direction perpendicular to the upper surface 100T of the substrate 100, the shape and size of the first contact electrode 31 need not match the shape and size of the first semiconductor layer 21.

As described above, since the upper surface of the front plane 200 is flattened, the distance from the substrate 100 to the first contact electrode 31 and the second contact electrode 32, in other words, the “height” of these

contact electrodes

31 and 32. "Or" level "are equal to each other. This facilitates the formation of the backplane 400, which will be described later, using semiconductor manufacturing technology. The "semiconductor manufacturing technique" in the present disclosure includes a step of depositing a thin film of a semiconductor, an insulator, or a conductor, and a step of patterning the thin film by a lithography and etching steps. In the present specification, the "flattened surface" means a surface having a step difference of 300 nm or less due to a convex portion or a concave portion existing on the surface. In a preferred embodiment, this step is 100 nm or less.

Refer to FIG. 1A again. In the example shown in FIG. 1A, the intermediate layer 300 includes an interlayer insulating layer 38 having a flat surface. The interlayer insulating layer 38 has a plurality of contact holes for connecting the first and

second contact electrodes

31 and 32 to the electric circuit of the backplane 400, respectively. The contact hole is filled with the via electrode 36.

In the embodiment of the present disclosure, it is preferable to flatten the upper surface of the interlayer insulating layer 38 before forming the backplane 400. By doing so, it becomes easy to form the backplane 400 on the upper surface of the interlayer insulating layer 38 by using the semiconductor manufacturing technique. When the upper surface of the intermediate layer 300 is flattened, the upper surface of the front plane 200 does not necessarily have to be flattened. However, if both the upper surface of the intermediate layer 300 and the upper surface of the front plane 200 are flattened, the formation of the electric circuit included in the backplane 400 becomes easier.

In addition to etch back, chemical mechanical polishing (CMP) treatment can be preferably used for flattening the insulating layer before or during the process of forming the backplane 400.

<Backplane>
The backplane 400 has an electrical circuit (not shown) in FIG. 1A. The electric circuit is electrically connected to the plurality of μLED 220s via the plurality of first contact electrodes 31 and at least one second contact electrode 32. The electrical circuit includes a plurality of thin film transistors (TFTs) and other circuit elements. As will be described later, each of the TFTs has a semiconductor layer grown on the front plane 200 and / or the intermediate layer 300 supported by the substrate 100.

FIG. 3 is a basic equivalent circuit diagram of sub-pixels when the μLED device 1000 functions as a display device. One pixel of the display device may be composed of sub-pixels of different colors such as R, G, B and the like. In the example shown in FIG. 3, the electric circuit of the backplane 400 has a selection TFT element Tr1, a driving TFT element Tr2, and a holding capacitance CH. The μLED shown in FIG. 3 resides in the front plane 200 rather than in the backplane 400.

In the example of FIG. 3, the selection TFT element Tr1 is connected to the data line DL and the selection line SL. The data line DL is a wiring that carries a data signal that defines an image to be displayed. The data line DL is electrically connected to the gate of the driving TFT element Tr2 via the selection TFT element Tr1. The selection line SL is a wiring that carries a signal for controlling on / off of the selection TFT element Tr1. The driving TFT element Tr2 controls the conduction state between the power line PL and the μLED. When the driving TFT element Tr2 is turned on, a current flows from the power line PL to the ground line GL via the μLED. This current causes the μLED to emit light. Even if the selection TFT element Tr1 is turned off, the driving TFT element Tr2 is maintained in the ON state due to the holding capacitance CH.

The electric circuit of the backplane 400 may include a selection TFT element Tr1, a drive TFT element Tr2, a data line DL, a selection line SL, and the like, but the configuration of the electric circuit is not limited to such an example.

Although the μLED device 1000 in the present embodiment can function as a display device by itself, a plurality of μLED devices 1000 may be tiling to realize a display device having a larger display area.

<Manufacturing method>
Next, a basic example of a method for manufacturing the μLED device 1000 will be described.

First, as shown in FIG. 4A, a substrate 100 having an upper surface (crystal growth surface) 100T is prepared. The substrate 100 in this embodiment is a sapphire substrate. FIG. 4A shows only a part of the substrate 100 extending along a plane parallel to the upper surface 100T.

As shown in FIG. 4B, the upper surface 100T of the substrate 100 is covered with the mask layer 150. The mask layer 150 is obtained by depositing a refractory metal film and then etching a predetermined region of the refractory metal film to form a plurality of mask openings 150G. Alternatively, the lift-off method may be used to form the mask layer 150 having the mask opening 150G in a predetermined region. The mask opening 150G partially exposes the upper surface 100T of the substrate 100. The thickness of the mask layer 150 is, for example, in the range of 100 nm or more and 1000 nm or less (for example, about 300 nm).

The shape and position of the mask opening 150G defines the shape and position of the second semiconductor layer 22 of each μLED 220. In the example shown in FIG. 4B, the shape of the mask opening 150G is rectangular, but the shape of the mask opening 150G is not limited to this example. Further, the arrangement of the mask opening 150G is not limited to the example shown in FIG. 4B. By adjusting the size or shape of the mask opening 150G, the emission wavelength can be changed in a wide range. This makes it possible to simultaneously form a plurality of μLEDs 220 that emit light at different wavelengths on one substrate 100.

As shown in FIG. 4C, the second conductive type second semiconductor layer 22 is epitaxially grown from the exposed portion of the upper surface 100T of the substrate 100. At this time, the second semiconductor layer 22 does not epitaxially grow on the mask layer 150. However, a part of the second semiconductor layer 22 epitaxially grown from the mask opening 150G may grow laterally along the surface of the mask layer 150. At this time, it is preferable that ohmic contact is realized between the mask layer 150 and the second semiconductor layer 22. Heat treatment at an appropriate temperature is required to achieve particularly good ohmic contact. During the epitaxial growth step for forming the μLED 220, the mask layer 150 and the second semiconductor layer 22 are sufficiently heated, and as a result, ohmic contact may be completed. However, if the heating during crystal growth is insufficient to achieve ohmic contact, it is preferable to additionally perform a heat treatment to complete the ohmic contact after the epitaxial growth step for forming the μLED 22 is completed. The lateral growth of the second semiconductor layer 22 expands the contact area between the second semiconductor layer 22 and the surface of the mask layer 150. As described above, good ohmic contact between the second semiconductor layer 22 and the surface of the mask layer 150 is realized by heating during epitaxial growth or by performing appropriate heat treatment after a series of epitaxial growth. Therefore, the electrical resistance (contact resistance) between the second semiconductor layer 22 and the mask layer 150 decreases. The length of the portion of the second semiconductor layer 22 that grows in the horizontal direction does not exceed the thickness of the portion that grows in the vertical direction. Further, the mask layer 150 has a high melting point of at least one selected from the group consisting of materials that realize good ohmic contact with the second semiconductor layer 22, for example, Ti, Cr, Mo, Mn, W, and Ta. It can be formed from metal. Since the work function of these refractory metals is 4.5 eV or less, good ohmic contact with the second semiconductor layer 22 can be formed when the second semiconductor layer 22 is n-type. Further, such a refractory metal exhibits high resistance even when it comes into contact with the light emitting layer 23 and the n-type first semiconductor layer 21.

Therefore, the mask layer 150 exhibits electrical resistance to the light emitting layer 23 and the first semiconductor layer 21 that grow on the second semiconductor layer 22. As described above, the mask layer 150 withstands high temperatures during epitaxial growth of the semiconductor crystal and realizes good ohmic contact with the second semiconductor layer 22, while with respect to the light emitting layer 23 and the first semiconductor layer 21. Is desirable to exhibit electrical resistance.

Next, as shown in FIG. 4D, a plurality of semiconductor layers including the light emitting layer 23 and the first conductive type first semiconductor layer 21 are epitaxially grown from the upper surface and the side surface of the second semiconductor layer 22. Each semiconductor layer is a single crystal epitaxial growth layer of a gallium nitride based compound semiconductor. The gallium nitride based compound semiconductor can be grown by, for example, the MOCVD (Metal Organic Chemical Vapor Deposition) method. Impurities defining each conductive type can be doped from the gas phase during crystal growth.

As a result of the above selective growth, as shown in FIG. 4D, a plurality of μLED 220s having a space (trench) between them can be formed. In this way, a trench for element separation is formed without etching the semiconductor layer. Considering that the semiconductor selectively grown from the upper surface 100T of the substrate 100 exposed through the mask opening 150G can also grow in the lateral direction, the arrangement pitch (intercenter distance) of the μLED 220 is determined by the selective growth. It can be set to twice or more the height of the semiconductor layer (epitaxial growth layer) to be formed. Further, in the region where the metal plug 24 is formed, the arrangement pitch of the μLED 220 is determined so that the width of the trench is larger than the width of the metal plug 24. Even if the mask layer 150 having the same pattern is used, the size of the μLED 220 and the width of the trench can be changed by changing the height of the semiconductor layer formed by selective growth.

In the present embodiment, good ohmic contact is obtained between the refractory metal material constituting the mask layer 150 and the second semiconductor layer 22 by heating in a series of epitaxial growth. If heating during epitaxial growth is insufficient to obtain good ohmic contact, then after the epitaxial growth step, additional to obtain good ohmic contact between the surface of the second semiconductor layer 22 and the mask layer 150. It is preferable to perform heat treatment. The temperature of the heat treatment may be any temperature at which the interaction (alloying near the interface) between the metal material constituting the mask layer 150 and the material of the second semiconductor layer 22 proceeds. For example, in order to realize ohmic contact between the Ti layer and the GaN semiconductor layer, heat treatment with a lower limit of 500 to 600 ° C. may be performed. The heat treatment time depends on the heat treatment temperature, but is, for example, about 1 to 10 minutes or more.

Next, as shown in FIG. 4E, an element separation region 240 is formed in the space (trench) between the μLED 220s. Specifically, the space (trench) formed between the adjacent μLED 220s is filled with an organic or inorganic insulating material to form an embedded insulator 25. For example, after depositing the insulating material by a thin film deposition technique such as the CVD method, flattening such as polishing may be performed until the upper surface of the μLED 220 is exposed. Further, a liquid thermosetting resin or an ultraviolet curable resin may be supplied into the trench and cured by heat or ultraviolet rays. By using the liquid resin material, it becomes easy to form the embedded insulator 25 having a flat upper surface. A through hole for the metal plug 24 (not shown in FIG. 4E) is then formed at the desired location of the embedded insulator 25 by using photolithography and etching techniques.

Next, as shown in FIG. 4F, after forming the metal plug 24 in the through hole in the element separation region 240, the first contact electrode 31 and the second contact electrode 32 are formed. The element separation region 240 in this example has an embedded insulator 25 and a plurality of metal plugs 24 each provided in a plurality of through holes of the embedded insulator 25.

After forming the interlayer insulating layer (thickness: 500 nm to 1500 nm) 38 of the intermediate layer 300 as shown in FIG. 4G, a plurality of contact holes (thickness: for example, 500 nm to 1500 nm) for connecting the electric circuit of the backplane 400 to the μLED 220 of the frontplane 200. (Not shown in FIG. 4G) is formed on the interlayer insulating layer 38. The contact hole is formed so as to reach the

contact electrodes

31 and 32 located in the lower layer. The contact hole is filled with via electrodes. The upper surface of the interlayer insulating layer 38 can be smoothed by CMP treatment.

As shown in FIG. 4H, the backplane 400 is formed on the intermediate layer 300. A characteristic point in the present disclosure is that the backplane 400 is not attached on the intermediate layer 300, but various electronic elements and wirings constituting the backplane 400 are mounted on the front plane 200 and the intermediate layer 300 by semiconductor manufacturing technology. It is to be formed directly on the laminated structure containing. As a result, each of the plurality of TFTs included in the backplane 400 has a semiconductor layer grown on a laminated structure composed of a front plane 200 and an intermediate layer 300 supported by the substrate 100.

As described above, when the upper surface of the front plane 200 and the upper surface of the intermediate layer 300 are flattened, it becomes easy to manufacture the backplane 400 including the TFT by the semiconductor manufacturing technology. Generally, when a TFT is formed by a semiconductor manufacturing technique, it is necessary to pattern the deposited semiconductor layer, insulating layer, and metal layer. Such patterning is realized by a lithography process involving exposure. If there is a large step on the base of the deposited semiconductor layer, insulating layer, and metal layer, the focus will not be achieved during exposure, and highly accurate fine patterning will not be realized. In the embodiment of the present disclosure, by flattening the entire front plane 200 including the element separation region 240, the intermediate layer 300 is also flattened, and the backplane 400 can be easily formed by the semiconductor manufacturing technique.

In the above example, the shape of the μLED 220 is generally a rectangular parallelepiped, but the shape of the μLED 220 may be a cylinder, a polygonal column such as a hexagonal column, or a polygonal column as shown in FIGS. 5A and 5B. It may be an elliptical column. FIG. 5A is a perspective view showing a part of the μLED device including the cylindrical μLED 220, and FIG. 5B is a plan view thereof. In the example shown in FIG. 5B, the element separation region 240 includes an embedded insulator 25 that covers the sides of each μLED 220 and a metal plug 24 that fills the space between the μLED 220s. By the action of the metal plug 24, the element separation region 240 can prevent the light emitted from each μLED 220 from being mixed with the light emitted from another μLED 220.

Since the shape and position of each μLED 220 is defined by the shape and position of the mask opening 150G of the mask layer 150, by adjusting the pattern of the mask layer 150, the shape and position of each μLED 220 and further the μLED 220 The array pattern can be controlled arbitrarily.

<Embodiment>
Hereinafter, a basic embodiment of the μLED device according to the present disclosure will be described in more detail.

Refer to FIG. The μLED device 1000A in this embodiment is a display device having the same configuration as the above-mentioned basic configuration example. The μLED device 1000A includes a crystal growth substrate (hereinafter, “substrate”) 100 that transmits visible light and / or ultraviolet rays, a front plane 200 formed on the substrate 100, and an intermediate layer formed on the front plane 200. It includes a 300 and a backplane 400 formed on the intermediate layer 300.

Next, an example of the configuration and manufacturing method of the μLED device 1000A in the present embodiment will be described with reference to FIGS. 7A to 11.

First, refer to FIG. 7A. FIG. 7A shows a configuration example of the substrate 100 used in this embodiment. The mask layer 150 can be formed, for example, from a layer of refractory metal having a thickness of 100 to 1000 nm, typically 300 nm. The metal mask layer 150 can function as a part of the common electrode on the n side by making good ohmic contact with the n-GaN layer 22n. The mask layer 150 is formed by a thin film deposition technique such as a sputtering method, and then patterned by a photolithography and etching technique. By this patterning, a plurality of mask openings 150G having a predetermined shape are formed. Each of the plurality of mask openings 150G in the present embodiment determines the shape and position of the n-GaN layer 22n of each μLED 220.

In the present embodiment, the substrate 100 is placed in the reaction chamber of the MOCVD apparatus, and various gases are supplied to perform epitaxial growth of the gallium nitride (GaN) -based compound semiconductor. The main body of the substrate 100 in this embodiment is, for example, a sapphire substrate having a thickness of about 50 to 600 μm. The upper surface 100T of the substrate 100 is typically a C surface (0001), but may have a non-polar surface or a semi-polar surface such as an m surface, an a surface, or an r surface on the upper surface. Further, the upper surface 100T may be inclined by about several degrees from these crystal planes. The substrate 100 is typically disc-shaped, and its diameter can be, for example, 1 to 8 inches. The shape and size of the substrate 100 are not limited to this example, and may be rectangular. Further, the manufacturing process may be advanced using the disk-shaped substrate 100, and finally the periphery of the substrate 100 may be cut and processed into a rectangular shape. Further, the manufacturing process may be advanced using the relatively large substrate 100, and finally one substrate 100 may be divided to form a plurality of μLED devices (singulation).

In the reaction chamber of the MOCVD equipment, first, trimethylgallium (TMG) or triethylgallium (TEG), hydrogen (H ₂ ) and nitrogen (N ₂ ) as carrier gases, ammonia (NH ₃ ) and silane (SiH ₄ ) To supply. The substrate 100 is heated to about 1100 ° C. Thus, as shown in FIG. 7B, the n-GaN layer (thickness: for example, 2 μm) 22n is selectively selected from the region not covered by the mask layer 150 of the substrate 100, that is, the region defined by the mask opening 150G. Grow. Silane is a raw material gas that supplies Si, which is an n-type dopant. The doping concentration of n-type impurities can be, for example, 5 × 10 ¹⁷ cm ^-3 .

Next, the supply of SiH ₄ is stopped, the temperature of the substrate 100 is lowered to less than 800 ° C., and the light emitting layer 23 is formed on the surface of the n—GaN layer 22n as shown in FIG. 7C. Specifically, first, the GaN barrier layer is grown. Further, the supply of trimethylindium (TMI) is started to grow the In _y Ga _1-y N (0 <y <1) well layer. A light emitting layer (thickness) having a GaN / InGaN multiple quantum well that functions as a light emitting part by alternately growing a GaN barrier layer and an In _y Ga _1-y N (0 <y <1) well layer in two or more cycles. : For example, 100 nm) 23 can be formed. When the number of In _y Ga _1-y N (0 <y <1) well layers is large, it is possible to prevent the carrier density inside the well layers from becoming excessively large when driven by a large current. One light emitting layer 23 may have a single In _y Ga _1-y N (0 <y <1) well layer sandwiched between two GaN barrier layers. An In _y Ga _1-y N (0 <y <1) well layer is directly formed on the n-GaN layer 22n, and a GaN barrier is formed on the In _y Ga _1-y N (0 <y <1) well layer. Layers may be formed. The In _y Ga _1-y N (0 <y <1) well layer may contain Al. For _{_{example, In y Ga 1-y N}} (0 <y <1) well _{_{_{layer, Al x In y Ga z N}}} (0 ≦ x <1,0 <y <1,0 <z <1) formed from You may.

Next, after the light emitting layer 23 is formed, the supply of TMI is temporarily stopped. After that, the carrier gas (hydrogen) is added to nitrogen, and the supply of ammonia is restarted. The growth temperature was raised to 850 ° C to 1000 ° C, and trimethylaluminum (TMA) and biscyclopentadienyl magnesium (Cp ₂ Mg) were supplied as raw materials for Mg, which is a p-type dopant, to form a p-AlGaN overflow suppression layer. You may grow it. Next, the supply of TMA is stopped, and the p-GaN layer (thickness: for example, 0.5 μm) 21p is grown. The doping concentration of p-type impurities can be, for example, 5 × 10 ¹⁷ cm ^-3 . Therefore, the refractory metal used for the mask layer 150 of the present embodiment preferably has a melting point of at least 1100 ° C., Ti (melting point: 1666 ° C.), Cr (same: 1857 ° C.), Mo ( The same: 2623 ° C.), Mn (same as above: 1246 ° C.), W (same as above: 3407 ° C.), Ta (same as above: 2985 ° C.) and the like can be preferably used.

According to this embodiment, the μLED 220 can be formed in any shape and arrangement depending on the shape and arrangement of the mask opening 150G of the mask layer 150.

In the present embodiment, as described above, the temperature of the epitaxial growth step is high, and good ohmic contact can be obtained between the n-GaN layer 22n and the surface of the mask layer 150. Therefore, it is not particularly necessary to perform an additional heat treatment step for completing the ohmic contact before the completion of the front plane 200.

As shown in FIG. 7D, the space defining the element separation region 240 is filled with the embedded insulator 25. The material and method of forming the embedded insulator 25 are arbitrary. In the illustrated example, the upper surface of the embedded insulator 25 is flattened and located at the same level as the upper surface of the p-GaN layer 21p. In the present embodiment, the surface is flattened by selectively dropping a thermosetting resin onto the device separation region 240 using an inkjet method and allowing it to stand for a while. Then it is heated to cure the resin.

As shown in FIG. 7E, a through hole 26 reaching the mask layer 150 is formed in a part of the embedded insulator 25. The through hole 26 defines the position and shape of the metal plug 24. The through hole 26 has, for example, a rectangular shape having a side of 5 μm or more and a circular shape having a diameter of 5 μm or more. Further, the through hole 26 may have a shape for accommodating a metal plug 24 having a shape as shown in FIGS. 1C and 1D, for example.

As shown in FIG. 7F, a metal plug 24 that fills the through hole 26 is formed, and the upper surface of the front plane 200 is flattened. The lower end of the metal plug 24 comes into electrical contact with the mask layer 150. The portion of the mask layer 150 that comes into contact with the lower end of the metal plug 24 functions as the connecting portion 150C. After that, the first contact electrode 31 and the second contact electrode 32 are formed. Flattening can be performed by various processes such as etchback, selective growth, CMP or lift-off.

Since the metal plug 24 comes into contact with the metal mask layer 150, the degree of freedom of combination increases unlike the case of contacting with the semiconductor layer, so that the metal plug 24 can be formed from any metal or other conductive material.

The first and

second contact electrodes

31 and 32 can be formed by depositing and patterning a metal layer. A metal-semiconductor interface is formed between the first contact electrode 31 and the p-GaN layer 21p of the μLED 220. To achieve p-type ohmic contact, the material of the first contact electrode 31 can be selected from metals with a high work function, such as platinum (Pt) and / or palladium (Pd). After forming the Pt or Pd layer (thickness: about 50 nm), heat treatment can be performed, for example, at a temperature of 350 ° C. or higher and 400 ° C. or lower for about 30 seconds. If a Pt or Pd layer is present in the portion that is in direct contact with the p-GaN layer 21p, another metal such as a Ti layer (thickness: about 50 nm) and / or an Au layer (thickness: about 50 nm) and / or Au layer (thickness: about 50 nm) and / or Au layer Thickness: about 200 nm) may be laminated.

A region in which p-type impurities are doped at a relatively high concentration may be formed in the upper part of the p-GaN layer 21p and in the lower layer of the first contact electrode 31. The second contact electrode 32 is electrically connected to the metal plug 24 instead of the semiconductor. Therefore, the material of the second contact electrode 32 can be selected from a wide range. The first contact electrode 31 and the second contact electrode 32 may be formed by patterning one continuous metal layer. This patterning also includes lift-off. When the thicknesses of the first contact electrode 31 and the second contact electrode 32 are equal to each other, it becomes easy to connect to an electric circuit in the backplane 400 such as the TFT 40 described later.

After forming the first and

second contact electrodes

31 and 32, these are covered with an interlayer insulating layer (thickness: for example, 500 nm to 1500 nm) 38. In a preferred example, the upper surface of the interlayer insulating layer 38 can be flattened by CMP treatment or the like. The thickness of the interlayer insulating layer 38 whose upper surface is flattened means "average thickness".

As shown in FIG. 7G, a contact hole 39 is formed in the interlayer insulating layer 38. The contact hole 39 is used to electrically connect the electrical circuit of the backplane 400 to the μLED 220 of the frontplane 200 by a via electrode 36 (not shown) formed thereafter.

With reference to FIG. 6 again, a structural example of the TFT included in the electric circuit of the backplane 400 and a method of forming the TFT will be described below.

In the example shown in FIG. 6, the TFT 40 is a semiconductor that contacts at least a part of the upper surfaces of the drain electrode 41 and the source electrode 42 formed on the interlayer insulating layer 38 and the drain electrode 41 and the source electrode 42, respectively. It has a thin film 43, a gate insulating film 44 formed on the semiconductor thin film 43, and a gate electrode 45 formed on the gate insulating film 44. In the illustrated example, the drain electrode 41 and the source electrode 42 are connected to the first contact electrode 31 and the second contact electrode 32 by a via electrode 36 formed in the contact hole, respectively. Each of these components of the TFT 40 can be formed by known semiconductor manufacturing techniques. The TFT 40 shown has a known TFT configuration in that it is electrically connected to the μLED 220 of the front plane 200 to be driven by a via electrode 36 formed directly below the drain electrode 41 and the source electrode 42. Is different.

The semiconductor thin film 43 can be formed from polycrystalline silicon, amorphous silicon, oxide semiconductors, and / or gallium nitride based semiconductors. The polycrystalline silicon can be formed, for example, by depositing amorphous silicon on the interlayer insulating layer 38 of the intermediate layer 300 by a thin film deposition technique, and then crystallizing the amorphous silicon with a laser beam. The polycrystalline silicon formed in this way is called LTPS (Low-Temperature Poly Silicon). The polycrystalline silicon is patterned into the desired shape in the lithography and etching steps.

The TFT 40 in FIG. 6 is covered with an insulating layer (thickness: for example, 500 nm to 3000 nm) 46. The insulating layer 46 is provided with an opening hole (not shown), which makes it possible to connect the TFT 40, for example, the gate electrode 45 to an external driver integrated circuit element or the like. It is preferable that the upper surface of the insulating layer 46 is also flattened. The electrical circuit of the backplane 400 may include circuit elements such as TFTs, capacitors, and diodes (not shown). Therefore, the insulating layer 46 may have a structure in which a plurality of insulating layers are laminated, and in that case, each insulating layer may be provided with a via electrode for connecting circuit elements, if necessary. Further, wiring may be formed on each insulating layer as needed.

The backplane 400 in the present embodiment is formed by semiconductor manufacturing technology on the μLED 220 located in the lower layer, and the contact hole 39 and the via electrode 36 are electrically formed in the μLED 220 arranged in the lower layer than the backplane 400. It is characterized in that it is formed so as to be joined. Therefore, for example, the drain electrode 41 and the source electrode 42 of the TFT 40 can be formed by patterning a metal layer deposited so as to cover the front plane 200. Such patterning enables highly accurate alignment by lithographic techniques. In particular, in the present embodiment, since the front plane 200 and / or the intermediate layer 300 are both flattened, it is possible to increase the resolution of lithography. As a result, it becomes possible to manufacture a device having a large number of μLED 220s arranged at a fine pitch of, for example, 20 μm or less, and in an extreme case, 5 μm or less, with good yield and at a low price.

The configuration of the TFT 40 shown in FIG. 6 is an example. For the sake of clarity, an example in which the drain electrode 41 of the TFT 40 is electrically connected to the first contact electrode 31 is described, but the drain electrode 41 of the TFT 40 may be another circuit element in the backplane 400 or It may be connected to the wiring. Further, the source electrode 42 of the TFT 40 does not need to be electrically connected to the second contact electrode 32. The second contact electrode 32 may be connected to a wiring (for example, a ground wiring) that commonly gives a predetermined potential to the n-GaN layer 22n of the μLED 220. An important point is that the metal plug 24 provided in the element separation region 240 is connected to the electric circuit in the backplane 400 located directly above the metal plug 24. In order to pass a current through a large number of μLED 220s through one continuous metal plug 24 or a plurality of metal plugs 24, it is necessary to reduce the electric resistance on the current path.

In the present embodiment, the electric circuit of the backplane 400 has a plurality of metal layers (drain electrode 41 and source electrode) connected to the first contact electrode 31 and the second contact electrode 32 provided below the backplane 400, respectively. It has a metal layer) that functions as 42). By adopting such a configuration, it is possible to reduce the above-mentioned electric resistance and reduce power consumption. In order to form the electric circuit in these

electrodes

31, 32 and the backplane 400 by the lithography technique, a flat base is required. This is because the presence of large irregularities on the base reduces the accuracy of pattern formation in the lithography process. In the present embodiment, since the front plane 200 and the intermediate layer 300 are flattened, the backplane 400 can be formed with high accuracy and high yield by using a lithography technique. Further, in the present embodiment, the plurality of first contact electrodes 31 each cover the p-GaN layer 21p of the plurality of μLED 220s and function as a light-shielding layer or a reflective layer. The individual first contact electrodes 31 do not have to completely cover the upper surface of the μLED 220, that is, the entire upper surface of the p-GaN layer 21p. The shape, size, and position of the first contact electrode 31 are determined to achieve a sufficiently low contact resistance and to sufficiently suppress the light emitted from the light emitting layer 23 from entering the channel region of the TFT 40. Will be done. It should be noted that preventing the light emitted from the light emitting layer 23 from entering the channel region of the TFT 40 can also be realized by arranging another metal layer at an appropriate position.

According to the embodiment of the present disclosure, an intermediate layer 300 having a flat upper surface is formed on a front plane 200 having a flat upper surface realized by embedding the element separation region 240 with a metal plug 24 and an embedded insulator 25. To do. These structures (substructures) function as a base for forming circuit elements such as TFTs on the structures. When depositing a semiconductor for a TFT, or when heat-treating after deposition, the above-mentioned substructure is treated at a temperature of, for example, 350 ° C. or higher. Therefore, it is preferable that the embedded insulator 25 in the device separation region 240 and the interlayer insulating layer 38 contained in the intermediate layer 300 are formed of a material that does not deteriorate even by heat treatment at 350 ° C. or higher. For example, polyimide and SOG (Spin-on Glass) can be preferably used.

The configuration of the TFT included in the electric circuit in the backplane 400 is not limited to the above example.

FIG. 8 is a cross-sectional view schematically showing another example of the TFT. FIG. 9 is a cross-sectional view schematically showing still another example of the TFT.

In the example of FIG. 8, the TFT 40 has a drain electrode 41, a source electrode 42, and a gate electrode 45 formed on a flat interlayer insulating layer 38, a gate insulating film 44 formed on the gate electrode 45, and gate insulation. It has a semiconductor thin film 43 formed on the film 44 and in contact with at least a part of the upper surface of each of the drain electrode 41 and the source electrode 42. In the illustrated example, the drain electrode 41 and the source electrode 42 are connected to the first contact electrode 31 and the second contact electrode 32 by a via electrode 36 located directly below, respectively. According to the configuration of FIG. 8, the drain electrode 41, the source electrode 42, and the gate electrode 45 can be formed from the same conductive film. In order to pattern a metal film with high accuracy by lithography technology, it is important that the substrate is flat. In this embodiment, the voids between the μLEDs 220 formed by selective growth are filled with the embedded insulator 25 and / or the metal plug 24, and the entire front plane 200 is flattened. As a result, as shown in FIG. 8, it becomes possible to realize a TFT 40 in which

electrodes

41, 42, and 45 are arranged at a narrow interval. The drain electrode 41, the source electrode 42, and the gate electrode 45 may be formed of different conductive materials. Unlike the gate electrode 45, the drain electrode 41 and the source electrode 42 are in electrical contact with the semiconductor thin film 43, so that the drain electrode 41 and the source electrode 42 have a material or layer structure suitable for achieving low contact resistance. You may be doing it.

In the TFT 40 of FIG. 8, the drain electrode 41, the source electrode 42, and the gate electrode 45 are all located below the semiconductor thin film 43. Therefore, it is easy to electrically connect to the front plane 200 located below the TFT 40. Further, it is easy to shorten the distance from the μLED 220 or the metal plug 24 to the drain electrode 41 or the source electrode 42. As shown in FIG. 8, an interlayer insulating layer 38 having a simple structure is present between the upper surface of the front plane 200 and the drain electrode 41 or the source electrode 42. The thickness of the interlayer insulating layer 38 is, for example, 300 nm or more and 1000 nm or less, and when the height of the via electrode 36 is T and the pore diameter (in the case of a rectangle, the length of the short side) is R, the aspect ratio (T). / R) can be, for example, 1/3 or less. In general, the higher the aspect ratio, the lower the yield of forming via electrodes, and the more likely it is that poor electrical connection between the front plane 200 and the back plane 400 will occur. However, as shown in FIG. 8, the drain electrode 41, the source electrode 42, and the gate electrode 45 are formed on the same flattened base layer, and a semiconductor is formed on the upper layers of the

electrodes

41, 42, and 45. According to the configuration in which the thin film 43 is arranged, the aspect ratio can be lowered, so that even when the μLED 220s are arranged in various patterns in the front plane 200, the electrical connection between the front plane 200 and the back plane 400 can be easily performed. Become.

In the example of FIG. 9, the TFT 40 has a semiconductor thin film 43 formed on the interlayer insulating layer 38, and a drain electrode 41 and a source electrode 42 formed on the interlayer insulating layer 38 and in contact with a part of the semiconductor thin film 43, respectively. And a gate insulating film 44 formed on the semiconductor thin film 43, and a gate electrode 45 formed on the gate insulating film 44. In the illustrated example, the drain electrode 41 and the source electrode 42 are connected to the first contact electrode 31 and the second contact electrode 32 by the via electrode 36, respectively. According to the configuration of FIG. 9, since the semiconductor thin film 43 is located below the drain electrode 41, the source electrode 42, and the gate electrode 45, the semiconductor thin film 43 is formed before the

electrodes

41, 42, and 45 are formed. Can be annealed with a laser to improve crystal quality. Therefore, it is possible to select an electrode material having a low melting point without considering the temperature rise due to laser annealing. Specifically, it becomes possible to adopt an electrode having a multi-layer structure including an aluminum layer in part.

Further, in the example of FIG. 9, since the semiconductor thin film 43 serving as the channel of the TFT 40 is formed on the flattened interlayer insulating layer 38, the film quality or the film quality due to the underlying step is formed in the step of growing the semiconductor layer during manufacturing. The film thickness is unlikely to be non-uniform. As a result, when polycrystallized by laser annealing, it is easy to form a semiconductor thin film 43 having high carrier mobility and excellent crystallinity. Further, since the gate electrode 45 is located above the semiconductor thin film 43, the LDD (Lightly Drain Dope) structure can be self-consistently formed by using the gate electrode 45 as a mask for ion implantation.

The semiconductor thin film 43 partially overlaps the contact hole 39 and the via electrode 36 provided in the intermediate layer 300. Both the upper surface and the lower surface of the semiconductor thin film 43 are in contact with the electrodes. More specifically, the drain region of the semiconductor thin film 43 is sandwiched between the drain electrode 41 in the upper layer and the via electrode 36 in the lower layer. The sort region of the semiconductor thin film 43 is sandwiched from above and below by the source electrode 42 in the upper layer and the via electrode 36 in the lower layer. As a result, the contact resistance of the electrode is reduced and the TFT characteristics are improved. It is not necessary that both the drain region and the source region of the semiconductor thin film 43 are in contact with the via electrode 36 of the lower layer, and one of the drain region and the source region may be in contact with the via electrode 36 of the lower layer.

The configuration of the TFT 40 is not limited to the above example, but the configuration shown in the above example of the present embodiment is preferable so that the μLED 220 formed in the lower layer of the backplane 400 can be appropriately contacted. In the embodiment of the present disclosure, in the initial stage of the process of forming the TFT 40, it is connected to the first and

second contact electrodes

31 and 32 of the front plane 200 via the contact hole 39 of the interlayer insulating layer 38 in the intermediate layer 300. Multiple metal layers are formed. These metal layers can be, but are not limited to, the drain electrode 41 or the source electrode 42 of the TFT 40.

The drain electrode 41 and the source electrode 42 in this embodiment are patterned by a photolithography and etching process after depositing a metal layer on the interlayer insulating layer 38 in the flattened intermediate layer 300. Therefore, there is no misalignment between the front plane 200 (intermediate layer 300) and the back plane 400 that causes a decrease in yield.

In the embodiments of the present disclosure, a large number of μLED 220s are arranged over a wide range, and at least one metal plug 24 connects the n-GaN layer 22n of the μLED 220 to the electric circuit of the backplane 400. Therefore, if the electric resistance component (sheet resistance) with respect to the current flowing from the n-GaN layer 22n to the metal plug 24 is too high, the power consumption will increase.

In the present embodiment, since one continuous mask layer 150 is electrically connected to the n-GaN layer 22n in all μLED 220s by an appropriate heat treatment step, the metal plug 24 and the n-GaN of each μLED 220 are n-GaN. Electrical continuity with the layer 22n is ensured. In this example, the mask layer 150 functions as an n-side common electrode of the plurality of μLED 220s. In the embodiment of the present disclosure, since the electrodes on the second conductive side of the plurality of μLED 220s are shared by the mask layer 150 having conductivity, there is a problem that some μLED 220s have poor continuity due to disconnection. Avoided.

The trench is filled with the embedded insulator 25. Specifically, the embedded insulator 25 can be formed by applying a resin material such as thermosetting polyimide and then curing the resin material by heat treatment at 400 ° C. for 60 minutes, for example. The embedded insulator 25 does not have to be formed of a resin, and may be formed of an inorganic insulating material such as silicon nitride or silicon oxide.

In the embodiments of the present disclosure, the TFTs and other components contained in the backplane 400 are formed on the upper layers of the front plane 200 and the intermediate layer 300 by semiconductor manufacturing technology, so that the process temperature for forming these components is set. It is necessary to form the front plane 200 and the intermediate layer 300 using a material that can withstand. For example, the embedded insulator 25, the interlayer insulating layer 38, and the insulating layer 46 can be formed from an organic material, which must withstand the maximum temperature of the process of forming the backplane 400. Specifically, when a heat treatment exceeding 300 ° C. is performed in the process of forming the TFT, from a heat-resistant resin material (for example, polyimide) that is not easily deteriorated even by the heat treatment at 300 ° C., the embedded insulator 25 and the layers The insulating layer 38 and / or the insulating layer 46 can be formed.

The embedded insulator 25, the interlayer insulating layer 38, and the insulating layer 46 do not necessarily have a single-layer structure, and may have a multi-layer structure. The multilayer structure may include, for example, a stack of organic and inorganic materials.

Since the upper surface of the metal plug 24 in the above example is at almost the same level as the upper surface of each μLED 220, it is possible to form circuit elements such as TFT 40 and fine wiring on it with high accuracy by semiconductor manufacturing technology. ..

In the above example, the metal plug 24 that fills the through hole 26 is used, but as described above, the form of the metal plug 24 can be various.

<Modification example>
FIG. 10 is a cross-sectional view showing a part of the μLED device 1100 in the modified example. The difference between the μLED device 1100 of FIG. 10 and the μLED device 1000 of FIG. 1A is that the insulating layer 160 is provided on the mask layer 150. The insulating layer 160 has an opening 160G that enables contact between the metal plug 24 and the connecting portion 150C of the mask layer 150. Further, the insulating layer 160 does not cover the peripheral region of the mask opening 150G on the upper surface of the mask layer 150. Therefore, the portion where the second semiconductor layer 22 grows in the lateral direction and the upper surface of the mask layer 150 are brought into contact with each other. Therefore, good ohmic contact is also realized between the second semiconductor layer 22 and the surface of the mask layer 150 by heating during epitaxial growth or by performing appropriate heat treatment after epitaxial growth.

The insulating layer 160 may be deposited before the growth of the second semiconductor layer 22, or may be deposited after the growth of the second semiconductor layer 22 and before the growth of the light emitting layer 23. The step of forming the opening 160G in the insulating layer 160 can be performed, for example, after the step of forming the through holes 26 in the embedded insulator 25.

The insulating layer 160 prevents the mask layer 150 from coming into contact with the light emitting layer 23 and the first semiconductor layer 21. Therefore, in this modification, the mask layer 150 may be formed of a metal material capable of realizing some kind of electrical conduction such as ohmic contact with the first semiconductor layer 21.

In the example of FIG. 10, the laterally grown portion of the second semiconductor layer 22 reaches the edge of the insulating layer 160 on the mask layer 150. The second semiconductor layer 22 may overlap a part of the insulating layer 160. Further, when the mask layer 150 is formed of a material exhibiting high electrical resistance to the light emitting layer 23, the second semiconductor layer 22 does not need to reach the edge of the insulating layer 160. In that case, the portion of the mask layer 150 that is not covered by the insulating layer 160 may come into contact with the light emitting layer 23 and / or the first semiconductor layer 21. In order to ensure electrical insulation between the mask layer 150 and the light emitting layer 23 and the first semiconductor layer 21, an insulating layer 160 exists between the mask layer 150 and the light emitting layer 23 and the first semiconductor layer 21. Is preferable. Considering the mask alignment deviation that may occur during the manufacturing process, the laterally grown portion of the second semiconductor layer 22 overcomes the edge of the insulating layer 160 on the mask layer 150 and partially over the insulating layer 160. It is desirable to wrap it. The insulating layer 160 may be formed of a material that does not deteriorate at the growth temperature of the light emitting layer 23 and the first semiconductor layer 21, such as silicon oxide or silicon nitride.

Hereinafter, embodiments of a color display using the μLED device of the present disclosure will be described.

<Color display I>
Hereinafter, a configuration example of the μLED device 1000B capable of full-color display according to the embodiment of the present disclosure will be described with reference to FIG. In FIG. 11, the direction of the Z axis is reversed from the direction of the Z axis in FIG. 1A. The same reference numerals are given to the components corresponding to the components in the μLED device 1000A described above, and the description of these components will not be repeated here.

The μLED device 1000B in the present embodiment includes a substrate 100, a front plane 200, an intermediate layer 300, and a back plane 400. These elements may have the various configurations described above.

The μLED device 1000B shown in FIG. 11 further includes a phosphor layer 600 that converts light emitted from each of the plurality of μLED 220s into white light, and a color filter array 620 that selectively transmits each color component of white light. I have. The color filter array 620 is supported by the substrate 100 with the phosphor layer 600 interposed therebetween, and has a red filter 62R, a green filter 62G, and a blue filter 62B.

In the present embodiment, the composition and bandgap of the light emitting layer 23 are adjusted so that the light emitted from the light emitting layer 23 of the μLED 220 has a blue wavelength (435 to 485 nm).

An example of the phosphor layer 600 may be a sheet containing a large number of nanoparticles (quantum dot phosphors) called "quantum dots". The quantum dot phosphor can be formed from a semiconductor such as CdTe, InP, or GaN. The wavelength of light emitted from a quantum dot phosphor changes according to its size. A quantum dot dispersion sheet adjusted to receive excitation light and emit red and green light can be used as the phosphor layer 600. When blue light is used as the light for exciting the phosphor layer 600, the blue light transmitted through the phosphor layer 600 and the light converted into red or green by the quantum dots of the phosphor layer 600 are mixed. The white light thus formed can be emitted from the phosphor layer 600.

The particle size of the quantum dot phosphor is, for example, 2 nm or more and 30 nm or less. The particle size of the quantum dot phosphor is significantly smaller than that of general phosphor powder particles having a particle size of more than 10 μm. When μLED220s are arranged at a narrow pitch of, for example, about 5 to 10 μm, it is difficult to perform efficient wavelength conversion for phosphor powder particles having a particle size of more than 10 μm because the phosphors are too large for the arrangement pitch of μLED220. Become. Further, it is known that when ordinary phosphor powder particles are pulverized to make the particle size smaller than 1 μm, the performance as a phosphor is remarkably deteriorated.

The phosphor layer 600 may include a scatterer having a size that mainly causes Rayleigh scattering of blue light (excitation light). Rayleigh scattering is caused by particles smaller than the wavelength of light, and the degree of scattering is inversely proportional to the fourth power of the wavelength. Therefore, the shorter the wavelength of light, the more it is scattered. As a scatterer that selectively scatters blue light, titanium oxide (TiO ₂ ) ultrafine particles having a diameter of 10 nm or more and 50 nm or less (typically 30 nm or less) can be preferably used. In particular, TiO ₂ ultrafine particles of rutile-type crystals are preferable because they are physically and chemically stable. Such TiO ₂ ultrafine particles have a low effect of scattering light of colors (green and red) having a wavelength longer than that of blue.

In order to uniformly disperse the TiO ₂ ultrafine particles in the phosphor layer 600, it is preferable to perform a surface treatment using an organic substance such as an alkanolamine, a polyol, a siloxane, or a carboxylic acid (for example, stearic acid or lauric acid). Further, the surface treatment may be performed using an inorganic substance such as Al (OH) ₃ or SiO ₂ .

As the blue scatterer, zinc oxide fine particles (particle diameter: for example, 20 nm or more and 100 nm or less) may be used instead of the titanium oxide fine particles or together with the titanium oxide fine particles. Since such blue scatterers are uniformly dispersed, color unevenness depending on the direction is less likely to occur, and a display having excellent viewing angle characteristics is realized.

As is clear from the above description, the μLED device 1000B of the present embodiment needs to transmit the light emitted from the light emitting layer 23 of the μLED 220. If the substrate 100 is a sapphire substrate, high translucency is exhibited in a wide range of visible light and ultraviolet rays.

The red filter 62R, the green filter 62G, and the blue filter 62B in the color filter array 620 are arranged at positions facing the μLED 220, respectively. The red filter 62R, the green filter 62G, and the blue filter 62B receive white light from the phosphor layer 600 excited by the light emitted from the corresponding μLED 220, and the red component and the green component contained in the white light, respectively. And the blue component is transmitted.

In order for the light emitted from each μLED 220 to be efficiently incident on any of the corresponding red filter 62R, green filter 62G, and blue filter 62B, the metal plug 24 should be shaped to surround each individual μLED device 1000B. It is desirable to have.

In the color filter array 620, it is preferable that a portion that functions as a black matrix formed of a light-shielding or absorbent material is located between the red filter 62R, the green filter 62G, and the blue filter 62B.

The phosphor layer 600 may be a stacked phosphor sheet on the color filter array 620.

The phosphor layer 600 does not have to be a sheet in which quantum dot phosphors are dispersed. The phosphor layer 600 may be formed by dispersing the quantum dot phosphor (fluorescent powder) in a resin, applying and curing the lower surface 100B of the substrate 100. In this case, the phosphor powder is located on the lower surface 100B of the substrate 100.

An optical sheet, a protective sheet, a touch sensor, or the like other than the phosphor layer 600 and the color filter array 620 may be attached to the substrate 100. This also applies to other embodiments described later.

<Color Display II>
Hereinafter, a configuration example of the μLED device 1000C capable of full-color display according to the embodiment of the present disclosure will be described with reference to FIGS. 12A and 12B. In FIG. 12A, the direction of the Z axis is reversed from the direction of the Z axis in FIG. 1A. FIG. 12B is a perspective view of the μLED device 1000C.

The μLED device 1000C in the present embodiment includes a substrate 100, a front plane 200, an intermediate layer 300, and a back plane 400. These elements may have the various configurations described above.

The illustrated μLED device 1000C is a bank layer (thickness: 0.5 to 3.0 μm) that is supported by the substrate 100 and defines a plurality of pixel openings 645 in which light emitted from the plurality of μLEDs is incident. It has 640. Further, the μLED device 1000C includes a red phosphor 64R, a green phosphor 64G, and a blue scatterer 64B respectively arranged in a plurality of pixel openings 645 of the bank layer 640. The red phosphor 64R converts the blue light emitted from the μLED 220 into red light, and the green phosphor 64G converts the blue light emitted from the μLED 220 into green light. The blue scatterer 64B scatters the blue light emitted from the μLED 220. The blue scatterer 64B can be designed to have a radiation angle dependence similar to the radiation angle dependence (eg, Lambersian distribution) exhibited by the intensity of light emitted from the red phosphor 64R or the green phosphor 64G.

In the example shown in FIG. 12A, the μLED device 1000C includes a transparent protective layer 650 that covers the pixel openings 645 in the bank layer 640. For simplicity, the description of the transparent protective layer 650 is omitted in FIG. 12B. When the red phosphor 64R and the green phosphor 64G are easily deteriorated by moisture absorption, it is desirable that the transparent protective layer 650 exerts a sealing function so that moisture in the atmosphere does not adversely affect these phosphors. The transparent protective layer 650 may be a laminate of an organic layer and an inorganic layer.

The bank layer 640 has, for example, a lattice shape, and can be formed from a light-shielding material in which a black dye is dissolved or a light-shielding material in which a black pigment such as carbon black is dispersed. The bank layer 640 can be formed of a photosensitive material, a resin material such as acrylic or polyimide, a paste material containing low melting point glass, a sol-gel material (for example, SOG), or the like. When the bank layer 640 is formed from a photosensitive material, the pixel opening 645 is formed at a predetermined position by applying the photosensitive material to the lower surface 100B of the substrate 100 and then performing patterning by exposure and development in a lithography process. Just do it. The position and size of the pixel openings 645 are determined to match the placement of the μLED 220. The size of the pixel opening 645 can be, for example, 10 μm × 10 μm or less. At this time, the particle sizes of the red phosphor 64R, the green phosphor 64G, and the blue scatterer 64B arranged in the pixel opening 645 are preferably 1 μm or less, and are uniformly and densely arranged in the pixel opening 645. Considering the arrangement, it is more desirable to be 100 nm or less. Therefore, the red phosphor 64R and the green phosphor 64G can each be suitably formed from the quantum dot phosphor. The blue scatterer 64B can be formed from transparent powder particles having a particle size of 10 nm or more and 60 nm or less.

The blue scatterer 64B is a matrix material having a refractive index sufficiently lower than the refractive index (n) of particles having a particle size of about 10% of the wavelength of blue light (for example, about 450 nm) emitted from the μLED 220. Can be formed by dispersing in. The blue scatterer 64B formed in this way can cause Rayleigh scattering in blue light. The powder particles constituting the blue scatterer 64B are, for example, titanium oxide (n = 2.5 to 2.7), chromium oxide (n = 2.5), zirconium oxide (n = 2.2), zinc oxide (n). = 1.95), can be formed from inorganic oxides such as alumina (n = 1.76). The refractive index of the matrix material is preferably 0.25 or more, for example 0.5 or more, lower than the refractive index of the powder particles.

The lower surface 100B of the substrate 100 may have an uneven surface that acts on the light emitted from the μLED 220. The presence of such an uneven surface adjusts the radiation intensity dependence of the light emitted from the red phosphor 64R, the green phosphor 64G, and the blue scatterer 64B, or the reflectance on the lower surface 100B of the substrate 100.

<Color Display III>
Hereinafter, a configuration example of the μLED device 1000D capable of full-color display according to the embodiment of the present disclosure will be described with reference to FIGS. 13A and 13B. In FIG. 13A, the direction of the Z axis is reversed from the direction of the Z axis in FIG. 1A. FIG. 13B is a perspective view of the μLED device 1000D.

The μLED device 1000D in the present embodiment includes a substrate 100, a front plane 200, an intermediate layer 300, and a back plane 400. These elements may have the various configurations described above.

The illustrated μLED device 1000D has a plurality of recesses 660 formed on the substrate 100. These recesses 660 are arranged so that the light emitted from the plurality of μLEDs 220 is incident on each of them. In other words, each recess 660 defines a pixel area.

The μLED device 1000D further includes a red phosphor 66R, a green phosphor 66G, and a blue scatterer 66B, which are respectively arranged in a plurality of recesses 660 of the substrate 100. The red phosphor 66R converts the blue light emitted from the μLED 220 into red light, and the green phosphor 66G converts the blue light emitted from the μLED 220 into green light. The blue scatterer 66B scatters the blue light emitted from the μLED 220. The blue scatterer 66B can be designed to have a radiation angle dependence similar to the radiation angle dependence (eg, Lambersian distribution) exhibited by the intensity of light emitted from the red phosphor 66R or the green phosphor 66G.

The roles and materials of the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B are similar to the roles and materials of the red phosphor 66R, the green phosphor 64G, and the blue scatterer 64B in the μLED device 1000C described above. ..

Also in this embodiment, the composition and bandgap of the light emitting layer 23 are adjusted so that the light emitted from the light emitting layer 23 of the μLED 220 has a blue wavelength (435 to 485 nm).

Also in the example shown in FIG. 13A, the μLED device 1000D includes a transparent protective layer 650 that covers the recess 660. For the sake of simplicity, the description of the transparent protective layer 650 is omitted in FIG. 13B. When the red phosphor 66R and the green phosphor 66G are easily deteriorated by moisture absorption, it is desirable that the transparent protective layer 650 exerts a sealing function so that moisture in the atmosphere does not adversely affect these phosphors. The transparent protective layer 650 may be a laminate of an organic layer and an inorganic layer.

The main difference between the μLED device 1000C and the μLED device 1000D is that in the μLED device 1000D, the substrate 100 itself has a recess (recess 660) that accommodates the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B. ) Is provided.

The shape of the recess 660 is not limited to a rectangle when viewed from the normal direction of the lower surface 100B of the substrate 100, and may be a circle, an ellipse, a triangle, or another polygon. Further, the inner wall of the recess 660 does not have to be orthogonal to the lower surface 100B of the substrate 100, and may be inclined. Specifically, the recess 660 may be composed of mortar-shaped or pyramidal-shaped recesses.

The depth of the recess 660 can be, for example, 500 nm or more and 250 μm or less. When the thickness of the substrate 100 is T, the depth of the recess 660 is, for example, 0.001 T or more and 0.5 T or less, and more preferably 0.1 T or more and 0.3 T or less. The location of the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B at the bottom of the recess 660 reduces the distance from each to the light emitting layer 23 of the μLED 220. As a result, the luminous flux emitted from the light emitting layer 23 of the μLED 220 and incident on each of the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B increases. The viewing angle characteristics are also improved.

According to this embodiment, it is possible to shorten the distance from the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B to the light emitting layer 23 of the μLED 220 while maintaining a large thickness and intensity of the substrate 100. become.

The recess 660 can be formed by processing the lower surface 100B of the substrate 100 with an ultrashort pulse laser such as a femtosecond laser or a picosecond laser (ablation method). The recess 660 can also be formed by forming a resist mask having a plurality of openings that define the shape and position of the recess 660 on the lower surface 100B of the substrate 100 by lithography technology, and then etching the exposed portion of the lower surface 100B of the substrate 100. Can be formed. Such etching can be achieved, for example, by a combination of ICP and RIE.

Fine irregularities may be formed on the bottom surface and / or the side surface of the recess 660. Such irregularities can improve image quality because they diffuse light and increase extraction efficiency.

In the above-mentioned

μLED devices

1000B, 1000C, 1000D capable of full-color display, the wavelength of the light (excitation light) emitted from the μLED 220 is in the range of 435 to 485 nm, that is, the composition of the light emitting layer 23 and the light emitting layer 23 so as to emit blue light. The bandgap has been adjusted. However, the μLED device in the embodiments of the present disclosure is not limited to these examples. For example, the composition and band of the light emitting layer 23 such that the light emitted from the light emitting layer 23 of the μLED 220 has an ultraviolet wavelength (eg, 365 to 400 nm) or a bluish-purple wavelength (400 nm to 420 nm, typically 405 nm). The gap may be adjusted. Specifically, the composition ratio y of In in In _y Ga _1-y N constituting the light emitting layer 23 may be set within the range of, for example, 0 ≦ y ≦ 0.15. When y = 0, light emission with a wavelength of 365 nm can be obtained. When y = 0.1, light emission having a bluish-purple wavelength near 410 nm can be obtained. By forming the semiconductor layer constituting the light emitting layer 23 from AlGaN or InAlGaN, light having a wavelength shorter than 365 nm can be emitted. In such an example, the light emitted from the μLED 220 is used to excite the red, green, and blue phosphors, respectively. Therefore, even if the emission wavelength of the μLED 220 fluctuates or shifts, color unevenness is less likely to occur. The emission wavelength of the μLED 220 may vary depending on the composition ratio of the light emitting layer 23, the magnitude of the drive current, the temperature, and the like. However, when a quantum dot phosphor is used for each of the three primary colors, even if the wavelength of the excitation light fluctuates due to the above-mentioned cause, the wavelength of the light emitted from the phosphor is hardly affected. Therefore, according to the present embodiment, color unevenness is less likely to occur, and better display characteristics are realized.

An example of a phosphor can be a large number of nanoparticles (quantum dot phosphors) called "quantum dots". The quantum dot phosphor can be formed from a semiconductor such as CdTe, InP, or GaN. The wavelength of light emitted from a quantum dot phosphor changes according to its size. A quantum dot dispersion sheet adjusted to emit red, green, and blue light in response to excitation light can be used as the phosphor layer 600 in FIG. 11 or as the phosphor in FIGS. 12 and 13. Good.

Quantum dot phosphors are dispersed and used in a matrix formed of an inorganic material such as an organic resin or low melting point glass, or a hybrid material of an organic material and an inorganic material. The amount (weight ratio) of the dispersed phosphors decreases in the order of blue, green, and red.

The quantum dot phosphor in one example has a core-shell structure. The core can be formed from, for example, CdS, InP, InGaP, InN, CdSe, InGaN, or ZnCdSe. In particular, in the case of obtaining light emission having a wavelength of 360 nm to 460 nm, a phosphor having a core formed from CdS can be preferably used. When forming a core from CdS, if the particle size of the core is adjusted in the range of 4.0 nm to 7.3 nm, blue light emission having a wavelength of 440 nm to 460 nm can be obtained. When forming a core from other materials (InP, InGaP, InN, CdSe), for example, blue light (center wavelength 475 nm) has a particle size of 1.4 nm to 3.3 nm, and green light (center wavelength 530 nm). A particle size of 1.7 nm to 4.2 nm and red light (center wavelength of 630 nm) can be obtained with a particle size of 2.0 nm to 6.1 nm. The material from which the quantum dots are formed can be appropriately determined based on the quantum efficiency, particle size, and the like. The quantum dot phosphor having a core formed from In _0.5 Ga _0.5 P has an advantage that it is easy to manufacture because it has a relatively large particle size. When it is desired to realize higher quantum efficiency, it is desirable to use, for example, a quantum dot whose core is formed from InP containing no Ga.

An embodiment of the present invention provides a new micro LED device. When used as a display, the micro LED device can be widely applied to smartphones, tablet terminals, in-vehicle displays, and small to medium to large television devices. Applications of micro LED devices are not limited to displays.

21 ... 1st semiconductor layer, 22 ... 2nd semiconductor layer, 23 ... light emitting layer, 24 ... metal plug, 25 ... embedded insulator, 31 ... 1st contact electrode, 32 ... 2nd contact electrode, 36 ... via electrode, 38 ... interlayer insulating layer, 100 ... crystal growth substrate, 200 ... front plane, 220 ... μLED, 240 ... element separation Region, 300 ... Intermediate layer, 400 ... Back plane, 1000 ... μLED device

Claims

An insulating crystal growth substrate whose upper surface is covered with a mask layer having a plurality of openings,
Between the plurality of micro LEDs supported by the crystal growth substrate, each having a first conductive type first semiconductor layer and a second conductive type second semiconductor layer, and the plurality of micro LEDs. A front plane comprising an element separation region located in, wherein the element separation region has at least one metal plug electrically connected to the second semiconductor layer.
A plurality of first contact electrodes, each of which is an intermediate layer supported by the front plane and electrically connected to the first semiconductor layer of the plurality of micro LEDs, and at least one connected to the metal plug. In the intermediate layer, including the second contact electrode of
It is a backplane supported by the intermediate layer and has an electric circuit electrically connected to the plurality of micro LEDs via the plurality of first contact electrodes and the at least one second contact electrode. The electrical circuit comprises a backplane containing a plurality of thin film transistors.
The mask layer is formed of a conductive material and
The mask layer has a plurality of mask openings that define the positions of the plurality of micro LEDs, and a connection portion that connects to the metal plug.
The first semiconductor layer and the second semiconductor layer of the plurality of micro LEDs are epitaxial layers selectively grown from the plurality of mask openings of the mask layer, and the second semiconductor layer is the mask layer. Have an ohmic contact with
A micro LED device in which each of the plurality of thin film transistors has a semiconductor layer grown on the front plane and / or the intermediate layer.
The micro LED device according to claim 1, wherein the mask layer is in electrical resistant or insulating contact with the first semiconductor layer.
The micro LED device according to claim 1, wherein the second semiconductor layer partially overlaps the mask layer.
The conductive type of the second semiconductor layer is p type, and is
The micro LED according to any one of claims 1 to 3, wherein the mask layer is formed of at least one refractory metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ta. device.
The micro LED device according to any one of claims 1 to 4, wherein an insulating layer that insulates the mask layer from the first semiconductor layer is provided on the mask layer.
The second semiconductor layer has a portion that grows laterally on the mask layer.
The micro LED device according to any one of claims 1 to 5, wherein the laterally grown portion partially overlaps the insulating layer.
The mask opening has a different size or shape depending on the position on the substrate.
The micro LED device according to any one of claims 1 to 6, wherein the size or shape of the mask opening defines a wavelength of light emitted from each micro LED.
The element separation region of the front plane has an embedded insulator that fills between the plurality of micro LEDs, and the embedded insulator has at least one through hole for the metal plug. , The micro LED device according to any one of claims 1 to 7.
The front plane has a flat surface and
The micro LED device according to any one of claims 1 to 8, wherein the flat surface is in contact with the intermediate layer.
The intermediate layer includes an interlayer insulating layer having a flat surface.
The interlayer insulating layer includes a plurality of contact holes for connecting the plurality of first contact electrodes and the at least one second contact electrode to the electric circuit, respectively.
A via electrode that fills the contact hole and
The micro LED device according to any one of claims 1 to 9.
Each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode formed on the flat surface of the interlayer insulating layer.
The micro LED device according to claim 10, wherein the semiconductor layer is located above the gate electrode and is in contact with the upper surfaces of the source electrode and the drain electrode.
Each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode located above the semiconductor layer.
The semiconductor layer is formed on the flat surface of the interlayer insulating layer.
The micro LED device according to claim 10, wherein a part of the semiconductor layer is sandwiched from above and below by at least one of the source electrode and the drain electrode and the via electrode.
A plurality of microLEDs supported by an insulating crystal growth substrate, each having a first conductive type first semiconductor layer and a second conductive type second semiconductor layer, and the plurality of microLEDs. The element separation region includes an element separation region located between the two, and the front plane having at least one metal plug electrically connected to the second semiconductor layer, and supported by the front plane. A plurality of first contact electrodes, each of which is electrically connected to the first semiconductor layer of the plurality of microLEDs, and at least one second contact electrode connected to the metal plug. Including, middle layer,
And the process of preparing a laminated structure
In the step of forming a back plane on the laminated structure, an electric circuit electrically connected to the plurality of micro LEDs via the plurality of first contact electrodes and the at least one second contact electrode is provided. The electric circuit has a step of forming a back plane including a plurality of thin film transistors, and
Including
The steps of preparing the laminated structure include a step of forming the mask layer that covers the crystal growth substrate and has a plurality of mask openings that define the positions of the plurality of micro LEDs.
A step of sequentially growing the second semiconductor layer and the first semiconductor layer from the mask opening, and
Including
The mask layer is formed of a conductive material, and the second semiconductor layer is in ohmic contact with the mask layer.
The step of forming the backplane is
A step of depositing a semiconductor layer on the laminated structure and
The step of patterning the semiconductor layer on the laminated structure and
A method for manufacturing a micro LED device, including.
The production according to claim 13, wherein the shape and position of the element separation region are defined by the second semiconductor layer and the first semiconductor layer selectively grown from the plurality of mask openings of the mask layer. Method.
The step of preparing the laminated structure is
After the step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings, a heat treatment step of completing ohmic contact between the mask layer and the second semiconductor layer is included. , The manufacturing method according to claim 13 or 14.
The manufacturing method according to claim 15, wherein in the step of preparing the laminated structure, the heat treatment step is performed before the front plane is completed.
Claims to complete ohmic contact between the mask layer and the second semiconductor layer by heating during the step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings. Item 13. The manufacturing method according to Item 13.