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WO2020116499A1 - Thin film transistor and production method therefor - Google Patents

Thin film transistor and production method therefor Download PDF

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Publication number
WO2020116499A1
WO2020116499A1 PCT/JP2019/047389 JP2019047389W WO2020116499A1 WO 2020116499 A1 WO2020116499 A1 WO 2020116499A1 JP 2019047389 W JP2019047389 W JP 2019047389W WO 2020116499 A1 WO2020116499 A1 WO 2020116499A1
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Prior art keywords
semiconductor layer
oxide semiconductor
thin film
film transistor
layer
Prior art date
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PCT/JP2019/047389
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French (fr)
Japanese (ja)
Inventor
松尾　大輔
靖典 安東
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日新電機株式会社
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Priority to KR1020217016500A priority Critical patent/KR20210080549A/en
Priority to CN201980080222.XA priority patent/CN113169232A/en
Publication of WO2020116499A1 publication Critical patent/WO2020116499A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a thin film transistor having an oxide semiconductor film and a method for manufacturing the thin film transistor.
  • TFT thin film transistor
  • IGZO In—Ga—Zn—O-based oxide semiconductor film
  • Patent Document 1 After forming an oxide semiconductor film on a gate insulating layer by sputtering or the like, a metal film is formed on the oxide semiconductor film. And forming a source electrode and a drain electrode by etching the metal film.
  • an insulating film such as SiO 2 that functions as an etching stopper is formed using an oxide so as to protect the oxide semiconductor film from an etching solution or the like. It needs to be separately formed on the semiconductor film. Since the oxide semiconductor film functioning as a channel layer and the insulating film functioning as an etching stopper have different compositions, it is necessary to change a sputtering target or change a film formation chamber, which results in an increase in the number of steps and a thin film transistor. Cannot be manufactured with high productivity.
  • the present invention has been made in view of such problems, and a main object thereof is to manufacture a thin film transistor having an oxide semiconductor film with high productivity.
  • etching resistance resistance to etching due to their high crystallinity (that is, crystallinity).
  • crystallinity that is, crystallinity
  • sex crystallinity
  • the thin film transistor according to the present invention is a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode are arranged in this order on a substrate, and the oxide semiconductor layer is , A first semiconductor layer and a second semiconductor layer made of oxide semiconductor films containing the same constituent elements are provided in order from the substrate side, and the crystallinity of the oxide semiconductor film forming the second semiconductor layer is The crystallinity is higher than the crystallinity of the oxide semiconductor film forming the first semiconductor layer.
  • the crystallinity of the oxide semiconductor film forming the second semiconductor layer functioning as a channel layer is higher than that of the oxide semiconductor film forming the first semiconductor layer.
  • the second semiconductor layer can function as an etching stopper to protect the first semiconductor layer. Therefore, it is not necessary to form a film by CVD or sputtering in order to separately provide an insulating film made of, for example, SiO 2 as an etching stopper.
  • the first semiconductor layer and the second semiconductor layer are made of oxide semiconductor films containing the same constituent elements, when they are formed by sputtering, the same target is used to change the sputtering conditions. Since the film formation can be continuously performed, it is not necessary to change the target or change the film formation chamber, and the thin film transistor can be manufactured with high productivity.
  • the first semiconductor layer is made of the amorphous oxide semiconductor film
  • the second semiconductor layer is made of the crystalline oxide semiconductor film.
  • both the first semiconductor layer and the second semiconductor layer are made of an oxide semiconductor film containing In, and a Cu-K ⁇ ray for the second semiconductor layer is used.
  • the full width at half maximum of can be mentioned.
  • the diffraction angle 2 ⁇ 31 in the X-ray diffraction measurement by the ⁇ -2 ⁇ method using Cu-K ⁇ ray on the second semiconductor layer.
  • the full width at half maximum of the peak confirmed in the vicinity of ° is preferably 4.5° or less, more preferably 3.0° or less, and further preferably 2.5° or less.
  • the etching resistance of the oxide semiconductor film forming the second semiconductor layer is preferably higher than the etching resistance of the material forming the source electrode and the drain electrode. With such a structure, the function of the second semiconductor layer as an etching stopper can be made more prominent.
  • a method for manufacturing a thin film transistor of the invention is a method for manufacturing a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode are arranged in this order on a substrate, and a plasma And a semiconductor layer forming step of forming a first semiconductor layer and a second semiconductor layer made of oxide semiconductor films having different crystallinities from each other on the gate insulating layer in order from the substrate side by sputtering a target using And a step of forming the source/drain electrodes by performing etching using the second semiconductor layer as an etching stopper to form the source electrode and the drain electrode on the oxide semiconductor layer.
  • a thin film transistor having an oxide semiconductor layer can be manufactured with high productivity.
  • FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the thin film transistor of the same embodiment.
  • FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the thin film transistor of the same embodiment. It is a figure which shows typically the structure of the sputtering device used in the semiconductor layer formation process of the thin-film transistor of the same embodiment.
  • 3 is a graph showing the relationship between the crystallinity of the oxide semiconductor layer and the etching resistance of the thin film transistor of the same embodiment.
  • a thin film transistor according to an embodiment of the present invention and a method for manufacturing the thin film transistor will be described below.
  • the thin film transistor 1 of this embodiment is a so-called bottom gate type. Specifically, as shown in FIG. 1, the substrate 2, the gate electrode 3, the gate insulating layer 4, the oxide semiconductor layer 5, the source electrode 6 and the drain electrode 7 are provided, and the substrate 2 side Are arranged (formed) in this order.
  • the thin film transistor 1 of the present embodiment is a so-called etching stopper type, and a part of the oxide semiconductor layer 5 that functions as a channel layer functions as an etching stopper in the manufacturing process as described later. Hereinafter, each part will be described in detail.
  • the substrate 2 is made of a material capable of transmitting light, and includes, for example, plastics (synthetic resin) such as polyethylene terephthalate (PET), polyethylene terephthalate (PEN), polyether sulfone (PES), acrylic, and polyimide. It may be made of glass or the like.
  • plastics synthetic resin
  • PET polyethylene terephthalate
  • PEN polyethylene terephthalate
  • PES polyether sulfone
  • acrylic acrylic
  • polyimide polyimide
  • the gate electrode 3 is provided on the surface of the substrate 2.
  • the gate electrode 3 is made of a material having high conductivity, and may be made of, for example, one or more kinds of metal selected from Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag and the like. Further, the conductivity of metal oxides such as Al—Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and In—Ga—Zn—O (IGZO). It may be composed of a membrane.
  • the gate electrode 3 may have a single layer structure of these conductive films or a laminated structure of two or more layers.
  • a gate insulating layer 4 is arranged on the gate electrode 3.
  • the gate insulating layer 4 is made of a material having a high insulating property, and is selected from, for example, SiO 2 , SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , and Hf 2. It may be an insulating film containing one or more oxides.
  • the gate insulating layer 4 may have such a conductive film as a single layer structure or a laminated structure of two or more layers.
  • the oxide semiconductor layer 5 is arranged on the gate insulating layer 4.
  • the oxide semiconductor layer 5 has a two-layer structure in which the first semiconductor layer 5a and the second semiconductor layer 5b are sequentially arranged from the substrate 2 side.
  • the first semiconductor layer 5a and the second semiconductor layer 5b are composed of oxide semiconductor films containing the same constituent elements, and are composed of oxide semiconductor films composed of the same constituent elements and unavoidable impurities. Is preferred.
  • each of the first semiconductor layer 5a and the second semiconductor layer 5b is made of an oxide semiconductor film containing an oxide containing In as a main component, and the oxide containing In is, for example, In—Ga—Zn—O. , In-Al-Mg-O, In-Al-Zn-O, In-Hf-Zn-O, and the like.
  • the first semiconductor layer 5a and the second semiconductor layer 5b are composed of oxide semiconductor films having different crystallinity levels (degrees).
  • the degree of crystallinity (degree) of this oxide semiconductor layer is determined by the full width at half maximum (FWHM) of the peak that can be confirmed in XRD (X-ray diffraction) measurement by the ⁇ -2 ⁇ method using a Cu light source (Cu-K ⁇ ray). You can check.
  • IGZO In—Ga—Zn—O
  • the first semiconductor layer 5a is a layer made of an amorphous oxide semiconductor film
  • the second semiconductor layer 5b is a layer made of a crystalline oxide semiconductor film. That is, the crystallinity of the oxide semiconductor film forming the second semiconductor layer 5b is higher than the crystallinity of the oxide semiconductor film forming the first semiconductor layer 5a.
  • the second semiconductor layer 5b functions as an etching stopper that protects the first semiconductor layer 5a.
  • a source electrode 6 and a drain electrode 7 are arranged on the oxide semiconductor layer 5.
  • the source electrode 6 and the drain electrode 7 are each made of a material having high conductivity so as to function as an electrode.
  • the source electrode 6 and the drain electrode 7 may have a single-layer structure of metal or conductive oxide, or may have a laminated structure of two or more layers.
  • the source electrode 6 and the drain electrode 7 of the present embodiment are made of a material having a lower etching resistance than the second semiconductor layer 5b (that is, a faster etching rate).
  • the source electrode 6 and the drain electrode 7 include zinc indium oxide (IZO), gallium indium oxide (IGO), and amorphous IGZO. It is composed of a metal oxide such as a film or a conductive film of a metal such as Mo.
  • a protective film may be disposed on the oxide semiconductor 5, the source electrode 6, and the drain electrode 7 to protect them.
  • the protective film may be made of, for example, a silicon oxide film (SiO 2 ), a fluorinated silicon nitride film (SiN:F) containing fluorine in the silicon nitride film, or the like.
  • the method of manufacturing the thin film transistor 1 of the present embodiment includes a gate electrode forming step, a gate insulating layer forming step, a semiconductor layer forming step, and a source/drain electrode forming step. Hereinafter, each step will be described.
  • a substrate 2 made of, for example, quartz glass is prepared, and a gate electrode 3 is formed on the surface of the substrate 2.
  • the method of forming the gate electrode 3 is not particularly limited, and may be formed by a known method such as a vacuum vapor deposition method or a DC sputtering method.
  • the gate insulating layer 4 is formed so as to cover the surfaces of the substrate 2 and the gate electrode 3.
  • the method for forming the gate insulating layer 4 is not particularly limited, and the gate insulating layer 4 may be formed by a known method.
  • the semiconductor layer forming step includes a first film forming step of forming the first semiconductor layer 5a and a second film forming step of forming the second semiconductor layer 5b.
  • an oxide semiconductor film is formed by sputtering a target with plasma.
  • a sputtering apparatus 100 for forming a film by sputtering a target T using inductively coupled plasma P is used.
  • the sputtering apparatus 100 includes a vacuum container 20, a substrate holding unit 30 that holds the substrate 2 in the vacuum container 20, a target holding unit 40 that faces the substrate 2 and holds the target T in the vacuum container 20, and a substrate holding unit.
  • a plurality of antennas 50 arranged along the surface of the substrate 2 held by the unit 30 and generating the plasma P are provided.
  • the high frequency voltage supplied to the antenna 50 and the bias voltage of the target T can be set independently. Therefore, the bias voltage can be set to a low voltage such that the ions in the plasma are attracted to the target and sputtered independently of the generation of the plasma P, and the negative bias voltage applied to the target T during sputtering is -1 kV. It is possible to set the negative voltage above (that is, the absolute value is 1 kV or less).
  • the target T is arranged in the target holding part 40 and the substrate 2 is arranged in the substrate holding part 30.
  • a conductive oxide sintered body such as InGaZnO that is a raw material of the oxide semiconductor 5 is used.
  • the first semiconductor layer 5a is formed on the gate insulating layer 4. Specifically, after the vacuum container 20 of the sputtering apparatus 100 is evacuated to 3 ⁇ 10 ⁇ 6 Torr or less, the pressure in the vacuum container 20 is 0.5 Pa or more 3 while introducing the sputtering gas at 50 sccm or more and 200 sccm or less. It is adjusted so that it becomes 1 Pa or less. Then, high frequency power of 1 kW or more and 10 kW or less is supplied to the plurality of antennas 50 to generate/maintain inductively coupled plasma. A DC voltage pulse is applied to the target to sputter the target.
  • the voltage applied to the target T is set to a negative voltage of ⁇ 1 kV or more from the viewpoint of suppressing generation of sputtered particles from which oxygen is desorbed and forming the oxide semiconductor film 5a with few oxygen defects in the film.
  • the first semiconductor layer 5 a is formed on the gate insulating layer 4.
  • the pressure inside the vacuum container 20, the flow rate of the sputtering gas, and the amount of electric power supplied to the antenna may be changed as appropriate.
  • the second semiconductor layer 5b is formed on the first semiconductor layer 5a.
  • the second semiconductor layer 5b is formed by sputtering the target T using the sputtering apparatus 100, as in the first film forming step.
  • the voltage applied to the target T in the second film forming step be a negative voltage of ⁇ 1 kV or more.
  • Conditions such as the pressure in the vacuum container 20, the flow rate of the sputtering gas, and the amount of electric power supplied to the antenna in the second film forming step may be the same as those in the first film forming step, and may be appropriately changed.
  • the oxygen gas concentration contained in the sputtering gas supplied in the second film forming step is the oxygen gas contained in the sputtering gas supplied in the first film forming step. Make it higher than the concentration.
  • the second film forming step as compared with the first film forming step, it is possible to further suppress the generation of sputtered particles from which oxygen is desorbed and to form a film while maintaining the oxidation state of the target more.
  • the crystallinity of the oxide semiconductor film forming the second semiconductor layer 5b can be made higher than the crystallinity of the oxide semiconductor film forming the first semiconductor layer 5a.
  • the oxygen gas concentration contained in the sputtering gas supplied in the second film formation step is 20 vol% or more in terms of volume fraction. Is preferable, and more preferably 50 vol% or more. Most preferably, only oxygen gas (that is, the volume fraction is 99.999 vol% or more) is supplied as the sputtering gas.
  • the oxygen gas concentration contained in the sputtering gas supplied in the first film forming step may be lower than the oxygen gas concentration contained in the sputtering gas supplied in the second film forming step.
  • the oxygen gas concentration contained in the sputtering gas is preferably 2 vol% or less in volume fraction, and only argon gas is supplied as the sputtering gas. Is preferred.
  • the source electrode 6 and the drain electrode 7 are formed on the oxide semiconductor layer 5.
  • the source electrode 6 and the drain electrode 7 are formed by forming the conductive film M on the second semiconductor layer 5b and then performing patterning by photolithography.
  • a conductive film M made of a metal or a conductive oxide is formed so as to cover the gate insulating layer 4 and the second semiconductor layer 5b.
  • the conductive film M may be formed by a known method such as DC sputtering or RF sputtering.
  • a resist R is applied on the conductive film M, and then exposure and development are performed to form the source electrode 6 and the drain electrode 7 on the conductive film M later, as shown in FIG.
  • the resist R is left only on the part.
  • the portions of the conductive film M to which the resist R is not applied are removed by etching to form the source electrode 6 and the drain electrode 7.
  • etching method dry etching using CF 4 gas or the like may be performed, or wet etching using acid such as HCl may be performed.
  • the second conductive layer 5b has better etching resistance than the first conductive layer 5a and the conductive film M, and functions as an etching stopper to protect the first conductive layer 5a from an etchant. Is becoming
  • a protective film is formed so as to cover the upper surfaces of the formed oxide semiconductor layer 5, the source electrode 6, and the drain electrode 7 by using, for example, a plasma CVD method.
  • heat treatment may be performed in an atmosphere containing oxygen under atmospheric pressure.
  • the temperature in the furnace during the heat treatment is not particularly limited and is, for example, 150° C. or higher and 300° C. or lower.
  • the heat treatment time is not particularly limited and is, for example, 1 hour or more and 3 hours or less.
  • the thin film transistor 1 of this embodiment can be obtained.
  • the protective film forming step and the heat treatment step are not essential steps and may be omitted.
  • sample making Specifically, a plurality of silicon substrates are prepared, and an oxide semiconductor film made of In-Ga-Zn-O (IGZO1114) is formed on the substrate by sputtering based on the "semiconductor manufacturing process" of the manufacturing method described above. Multiple samples were prepared.
  • IGZO1114 oxide semiconductor film made of In-Ga-Zn-O
  • the pressure inside the vacuum container is reduced to 0.9 Pa or less, high-frequency power of 7 kW is supplied to the plurality of antennas, and a DC pulse voltage of ⁇ 400 V is applied to the target.
  • the voltage was applied and sputtering of the target was performed to form an oxide semiconductor film.
  • one or two samples (total of 5 vol%, 5 vol%, 20 vol%, 50 vol%, and 100 vol%, respectively) of 5 kinds of samples with different oxygen gas concentrations in the supplied sputtering gas (total volume fraction, respectively) (total: 9) were created.
  • the manufacturing conditions not particularly described are the same as those described in the above-described manufacturing method.
  • the oxide semiconductor film forming the second semiconductor layer 5b functioning as a channel layer has a crystallinity forming the first semiconductor layer 5a. Since the crystallinity of the film is higher than that of the film, when the electrode source electrode 6 and the drain electrode 7 are formed by etching in the source/drain electrode forming step, the second semiconductor layer 5b functions as an etching stopper to form the first semiconductor layer 5a. It can be protected from the etching solution. Therefore, it is not necessary to perform sputtering to separately provide an insulating film made of, for example, SiO 2 as an etching stopper.
  • the first semiconductor layer 5a and the second semiconductor layer 5b are made of oxide semiconductor films containing the same constituent elements, when they are formed by sputtering, the same target T is used in the sputtering gas. Since it is possible to continue film formation simply by changing the sputtering conditions such as the oxygen gas concentration, it is possible to manufacture the thin film transistor 1 with high productivity without changing the target T or changing the film forming chamber. ..
  • the configuration has the plurality of target holding units 40, but the configuration may have one target holding unit 40. Even in this case, the configuration having the plurality of antennas 50 is desirable, but the configuration having one antenna 50 may be used.

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Abstract

A thin film transistor having arranged, in order, upon a substrate: a gate electrode; a gate insulating layer; an oxide semiconductor layer; and a source electrode and a drain electrode. The thin film transistor is characterized by: the oxide semiconductor layer comprising, in order from the substrate side, a first semiconductor layer and a second semiconductor layer that comprise an oxide semiconductor film that has the same constituent element in both; and the crystallinity of the oxide semiconductor film constituting the second semiconductor layer being higher than the crystallinity of the oxide semiconductor film constituting the first semiconductor layer.

Description

薄膜トランジスタ及びその製造方法Thin film transistor and manufacturing method thereof
  本発明は、酸化物半導体膜を有する薄膜トランジスタ及びその製造方法に関するものである。 The present invention relates to a thin film transistor having an oxide semiconductor film and a method for manufacturing the thin film transistor.
  近年、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系（ＩＧＺＯ）等の酸化物半導体膜をチャネル層に用いた薄膜トランジスタ（ＴＦＴ）の開発が活発に行われている。酸化物半導体膜をチャネル層に用いた薄膜トランジスタの製造方法として、例えば特許文献１には、スパッタリング等によりゲート絶縁層の上に酸化物半導体膜を形成した後、酸化物半導体膜の上に金属膜を形成し、この金属膜をエッチングすることによりソース電極及びドレイン電極を形成する方法が開示されている。 In recent years, a thin film transistor (TFT) using an In—Ga—Zn—O-based (IGZO)-based oxide semiconductor film as a channel layer has been actively developed. As a method of manufacturing a thin film transistor using an oxide semiconductor film as a channel layer, for example, in Patent Document 1, after forming an oxide semiconductor film on a gate insulating layer by sputtering or the like, a metal film is formed on the oxide semiconductor film. And forming a source electrode and a drain electrode by etching the metal film.
特開２００８－１６６７１６号公報JP, 2008-166716, A
  しかしながら特許文献１に開示される製造方法では、ソース電極及びドレイン電極を形成するにあたり、エッチング液等から酸化物半導体膜を保護するために、エッチングストッパとして機能するＳｉＯ２等の絶縁膜を酸化物半導体膜の上に別途形成する必要がある。チャネル層として機能する酸化物半導体膜と、エッチングストッパとして機能する絶縁膜とは組成が異なるため、スパッタリングターゲットを付け替えたり、成膜室を変更したりする必要があり、工程数が増加して薄膜トランジスタを生産性良く製造することができない。 However, in the manufacturing method disclosed in Patent Document 1, in forming the source electrode and the drain electrode, an insulating film such as SiO 2 that functions as an etching stopper is formed using an oxide so as to protect the oxide semiconductor film from an etching solution or the like. It needs to be separately formed on the semiconductor film. Since the oxide semiconductor film functioning as a channel layer and the insulating film functioning as an etching stopper have different compositions, it is necessary to change a sputtering target or change a film formation chamber, which results in an increase in the number of steps and a thin film transistor. Cannot be manufactured with high productivity.
  本発明はこのような問題に鑑みてなされたものであり、酸化物半導体膜を有する薄膜トランジスタを生産性良く製造することを主たる課題とするものである。 The present invention has been made in view of such problems, and a main object thereof is to manufacture a thin film transistor having an oxide semiconductor film with high productivity.
  本発明者らは上記課題を解決するために鋭意検討をした結果、同じ構成元素から成る酸化物半導体膜であっても、その結晶性の高さ（すなわち結晶度合）によってエッチングに対する耐性（耐エッチング性ともいう）が異なることに着眼した。さらに鋭意検討した結果、その結晶性の高さが高いほど優れた耐エッチング性を示し、チャネル層たる酸化物半導体膜を、製造過程においてエッチングストッパとしても機能させることができることを見出し本発明に至った。 As a result of intensive studies for solving the above problems, the present inventors have found that even oxide semiconductor films composed of the same constituent elements have resistance to etching (etching resistance) due to their high crystallinity (that is, crystallinity). (Also referred to as sex). As a result of further diligent studies, the inventors found that the higher the crystallinity, the better the etching resistance, and that the oxide semiconductor film serving as the channel layer can also function as an etching stopper in the manufacturing process. It was
  すなわち本発明に係る薄膜トランジスタは、基板上に、ゲート電極と、ゲート絶縁層と、酸化物半導体層と、ソース電極及びドレイン電極とがこの順に配置された薄膜トランジスタであって、前記酸化物半導体層は、互いに同一の構成元素を含む酸化物半導体膜から成る第１半導体層と第２半導体層とを前記基板側から順に備えており、前記第２半導体層を構成する酸化物半導体膜の結晶性が、前記第１半導体層を構成する前記酸化物半導体膜の結晶性よりも高いことを特徴とする。 That is, the thin film transistor according to the present invention is a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode are arranged in this order on a substrate, and the oxide semiconductor layer is , A first semiconductor layer and a second semiconductor layer made of oxide semiconductor films containing the same constituent elements are provided in order from the substrate side, and the crystallinity of the oxide semiconductor film forming the second semiconductor layer is The crystallinity is higher than the crystallinity of the oxide semiconductor film forming the first semiconductor layer.
  このようなものであれば、チャネル層として機能する第２半導体層を構成する酸化物半導体膜の結晶性が第１半導体層を構成する酸化物半導体膜の結晶性よりも高いので、ソース・ドレイン電極をエッチングにより形成する際に、第２半導体層がエッチングストッパとして機能して第１半導体層を保護することができる。そのため、エッチングストッパとして、例えばＳｉＯ２等からなる絶縁膜を別途設けるためにＣＶＤやスパッタリング等による成膜を行う必要がない。
  しかも、第１半導体層と第２半導体層は互いに同一の構成元素を含む酸化物半導体膜から成るので、これらをスパッタリングにより形成する場合には、同一のターゲットを用いてスパッタリング条件を変更することにより続けて成膜することができるので、ターゲットを付け替えたり、成膜室を変更する必要がなく、生産性良く薄膜トランジスタを製造することができる。 With such a structure, the crystallinity of the oxide semiconductor film forming the second semiconductor layer functioning as a channel layer is higher than that of the oxide semiconductor film forming the first semiconductor layer. When forming the electrode by etching, the second semiconductor layer can function as an etching stopper to protect the first semiconductor layer. Therefore, it is not necessary to form a film by CVD or sputtering in order to separately provide an insulating film made of, for example, SiO 2 as an etching stopper.
Moreover, since the first semiconductor layer and the second semiconductor layer are made of oxide semiconductor films containing the same constituent elements, when they are formed by sputtering, the same target is used to change the sputtering conditions. Since the film formation can be continuously performed, it is not necessary to change the target or change the film formation chamber, and the thin film transistor can be manufactured with high productivity.
  前記第１半導体層が非晶質の前記酸化物半導体膜から成り、前記第２半導体層が結晶質の前記酸化物半導体膜から成るものであることが好ましい。
  このようなものであれば、第２半導体層の耐エッチング性を第１半導体層の耐エッチング性に比べてより優れたものにでき、第２半導体層のエッチングストッパとしての機能をより高めることができる。 It is preferable that the first semiconductor layer is made of the amorphous oxide semiconductor film, and the second semiconductor layer is made of the crystalline oxide semiconductor film.
With such a structure, the etching resistance of the second semiconductor layer can be made higher than that of the first semiconductor layer, and the function of the second semiconductor layer as an etching stopper can be further enhanced. it can.
  前記酸化物半導体層の具体的な態様として、前記第１半導体層及び前記第２半導体層がいずれもＩｎを含む酸化物半導体膜から成り、前記第２半導体層に対するＣｕ‐Ｋα線を用いたθ－２θ法によるＸ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅が、前記第１半導体層に対する前記Ｘ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅よりも小さいものを挙げることができる。 As a specific mode of the oxide semiconductor layer, both the first semiconductor layer and the second semiconductor layer are made of an oxide semiconductor film containing In, and a Cu-Kα ray for the second semiconductor layer is used. The full width at half maximum of the peak confirmed in the vicinity of the diffraction angle 2θ=31° in the X-ray diffraction measurement by the −2θ method is the peak confirmed in the vicinity of the diffraction angle 2θ=31° in the X-ray diffraction measurement with respect to the first semiconductor layer. The full width at half maximum of can be mentioned.
  第２半導体層の結晶性を高くし、耐エッチング性をより向上させるためには、前記第２半導体層に対するＣｕ‐Ｋα線を用いたθ－２θ法によるＸ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅が４．５°以下であることが好ましく、３．０°以下であることがより好ましく、２．５°以下であることがさらに好ましい。 In order to increase the crystallinity of the second semiconductor layer and further improve the etching resistance, the diffraction angle 2θ=31 in the X-ray diffraction measurement by the θ-2θ method using Cu-Kα ray on the second semiconductor layer. The full width at half maximum of the peak confirmed in the vicinity of ° is preferably 4.5° or less, more preferably 3.0° or less, and further preferably 2.5° or less.
  前記第２半導体層を構成する前記酸化物半導体膜の耐エッチング性が、前記ソース電極及び前記ドレイン電極を構成する材料の耐エッチング性よりも優れていることが好ましい。
  このようなものであれば、第２半導体層のエッチングストッパとしての機能をより顕著にできる。 The etching resistance of the oxide semiconductor film forming the second semiconductor layer is preferably higher than the etching resistance of the material forming the source electrode and the drain electrode.
With such a structure, the function of the second semiconductor layer as an etching stopper can be made more prominent.
  また本発明の薄膜トランジスタの製造方法は、基板上に、ゲート電極と、ゲート絶縁層と、酸化物半導体層と、ソース電極及びドレイン電極とがこの順に配置された薄膜トランジスタの製造方法であって、プラズマを用いてターゲットをスパッタリングして、結晶性が互いに異なる酸化物半導体膜から成る第１半導体層と第２半導体層とを前記ゲート絶縁層の上に前記基板側から順に形成する半導体層形成工程と、前記第２半導体層をエッチングストッパとしてエッチングを行い、前記ソース電極及び前記ドレイン電極を前記酸化物半導体層の上に形成する前記ソース・ドレイン電極形成工程とを含む。
  このような薄膜トランジスタの製造方法であれば、上記した薄膜トランジスタと同様の作用効果を奏し得る。 A method for manufacturing a thin film transistor of the invention is a method for manufacturing a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode are arranged in this order on a substrate, and a plasma And a semiconductor layer forming step of forming a first semiconductor layer and a second semiconductor layer made of oxide semiconductor films having different crystallinities from each other on the gate insulating layer in order from the substrate side by sputtering a target using And a step of forming the source/drain electrodes by performing etching using the second semiconductor layer as an etching stopper to form the source electrode and the drain electrode on the oxide semiconductor layer.
With such a method of manufacturing a thin film transistor, the same operational effect as the above-described thin film transistor can be obtained.
  このように構成した本発明によれば、酸化物半導体層を有する薄膜トランジスタを生産性良く製造することができる。 According to the present invention thus configured, a thin film transistor having an oxide semiconductor layer can be manufactured with high productivity.
本実施形態の薄膜トランジスタの構成を模式的に示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the thin-film transistor of this embodiment typically. 同実施形態の薄膜トランジスタの製造工程を模式的に示す断面図である。FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the thin film transistor of the same embodiment. 同実施形態の薄膜トランジスタの製造工程を模式的に示す断面図である。FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the thin film transistor of the same embodiment. 同実施形態の薄膜トランジスタの半導体層形成工程で用いられるスパッタリング装置の構成を模式的に示す図である。It is a figure which shows typically the structure of the sputtering device used in the semiconductor layer formation process of the thin-film transistor of the same embodiment. 同実施形態の薄膜トランジスタの酸化物半導体層の結晶性と耐エッチング性との関係性を示すグラフである。3 is a graph showing the relationship between the crystallinity of the oxide semiconductor layer and the etching resistance of the thin film transistor of the same embodiment.
  以下に、本発明の一実施形態に係る薄膜トランジスタおよびその製造方法について説明する。 A thin film transistor according to an embodiment of the present invention and a method for manufacturing the thin film transistor will be described below.
＜１．薄膜トランジスタ＞
  本実施形態の薄膜トランジスタ１は所謂ボトムゲート型のものである。具体的には図１に示すように、基板２と、ゲート電極３と、ゲート絶縁層４と、酸化物半導体層５と、ソース電極６及びドレイン電極７とを有しており、基板２側からこの順に配置（形成）されている。なお本実施形態の薄膜トランジスタ１は所謂エッチングストッパ型のものであり、後述するようにチャネル層として機能する酸化物半導体層５の一部が、製造過程においてはエッチングストッパとして機能する。以下、各部について詳述する。 <1. Thin film transistor>
The thin film transistor 1 of this embodiment is a so-called bottom gate type. Specifically, as shown in FIG. 1, the substrate 2, the gate electrode 3, the gate insulating layer 4, the oxide semiconductor layer 5, the source electrode 6 and the drain electrode 7 are provided, and the substrate 2 side Are arranged (formed) in this order. The thin film transistor 1 of the present embodiment is a so-called etching stopper type, and a part of the oxide semiconductor layer 5 that functions as a channel layer functions as an etching stopper in the manufacturing process as described later. Hereinafter, each part will be described in detail.
  基板２は光を透過できるような材料から構成されており、例えば、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレナフタレート（ＰＥＮ）、ポリエーテルサルフォン（ＰＥＳ）、アクリル、ポリイミド等のプラスチック（合成樹脂）やガラス等によって構成されてよい。 The substrate 2 is made of a material capable of transmitting light, and includes, for example, plastics (synthetic resin) such as polyethylene terephthalate (PET), polyethylene terephthalate (PEN), polyether sulfone (PES), acrylic, and polyimide. It may be made of glass or the like.
  基板２の表面にはゲート電極３が設けられている。ゲート電極３は高い導電性を有する材料から構成されており、例えばＳｉ、Ａｌ、Ｍｏ、Ｃｒ、Ｔａ、Ｔｉ、Ｐｔ、Ａｕ、Ａｇ等から選択される１種以上の金属から構成されてよい。また、Ａｌ－Ｎｄ、Ａｇ合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩＺＯ）、Ｉｎ－Ｇａ－Ｚｎ－Ｏ（ＩＧＺＯ）等の金属酸化物の導電性膜から構成されてよい。ゲート電極３は、これらの導電性膜の単層構造又は２層以上の積層構造から構成されてもよい。 The gate electrode 3 is provided on the surface of the substrate 2. The gate electrode 3 is made of a material having high conductivity, and may be made of, for example, one or more kinds of metal selected from Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag and the like. Further, the conductivity of metal oxides such as Al—Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and In—Ga—Zn—O (IGZO). It may be composed of a membrane. The gate electrode 3 may have a single layer structure of these conductive films or a laminated structure of two or more layers.
  ゲート電極３の上にはゲート絶縁層４が配置されている。ゲート絶縁層４は高い絶縁性を有する材料から構成されており、例えば、ＳｉＯ２、ＳｉＮｘ、ＳｉＯＮ、Ａｌ２Ｏ３、Ｙ２Ｏ３、Ｔａ２Ｏ５、Ｈｆ２等から選択される１つ以上の酸化物を含む絶縁膜であってよい。ゲート絶縁層４は、これらの導電性膜を単層構造又は２層以上の積層構造としたものであってよい。 A gate insulating layer 4 is arranged on the gate electrode 3. The gate insulating layer 4 is made of a material having a high insulating property, and is selected from, for example, SiO 2 , SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , and Hf 2. It may be an insulating film containing one or more oxides. The gate insulating layer 4 may have such a conductive film as a single layer structure or a laminated structure of two or more layers.
  ゲート絶縁層４の上には酸化物半導体層５が配置されている。酸化物半導体層５は、第１半導体層５ａと第２半導体層５ｂが基板２側から順に配置された二層構造を成している。 The oxide semiconductor layer 5 is arranged on the gate insulating layer 4. The oxide semiconductor layer 5 has a two-layer structure in which the first semiconductor layer 5a and the second semiconductor layer 5b are sequentially arranged from the substrate 2 side.
  第１半導体層５ａと第２半導体層５ｂは、互いに同一の構成元素を含む酸化物半導体膜から構成されており、互いに同一の構成元素及び不可避的な不純物から成る酸化物半導体膜から構成されていることが好ましい。ここでは第１半導体層５ａと第２半導体層５ｂはいずれも、Ｉｎを含む酸化物を主成分とする酸化物半導体膜からなり、Ｉｎを含む酸化物とは、例えばＩｎ－Ｇａ－Ｚｎ－Ｏ、Ｉｎ－Ａｌ－Ｍｇ－Ｏ、Ｉｎ－Ａｌ－Ｚｎ－Ｏ又はＩｎ－Ｈｆ－Ｚｎ－Ｏ等の酸化物である。 The first semiconductor layer 5a and the second semiconductor layer 5b are composed of oxide semiconductor films containing the same constituent elements, and are composed of oxide semiconductor films composed of the same constituent elements and unavoidable impurities. Is preferred. Here, each of the first semiconductor layer 5a and the second semiconductor layer 5b is made of an oxide semiconductor film containing an oxide containing In as a main component, and the oxide containing In is, for example, In—Ga—Zn—O. , In-Al-Mg-O, In-Al-Zn-O, In-Hf-Zn-O, and the like.
  第１半導体層５ａと第２半導体層５ｂは、結晶性の高さ（度合）が互いに異なる酸化物半導体膜から構成されている。この酸化物半導体層の結晶性の高さ（度合）は、Ｃｕ光源（Ｃｕ－Ｋα線）を用いたθ‐２θ法によるＸＲＤ（Ｘ線回折）測定において確認できるピークの半値全幅（ＦＷＨＭ）により確認することができる。具体的には、第１半導体層５ａ及び第２半導体層５ｂがＩｎ－Ｇａ－Ｚｎ－Ｏ（ＩＧＺＯ）等のＩｎを含む酸化物を主成分（体積分率で９０％以上）とする酸化物半導体膜から成る場合には、Ｘ線回折測定において２θ＝３１°近傍（例えば３０°～３２°）で確認できるピークの半値全幅の大きさにより評価することができる。より具体的には当該ピークの半値全幅が小さいほど結晶性が高いと評価できる。 The first semiconductor layer 5a and the second semiconductor layer 5b are composed of oxide semiconductor films having different crystallinity levels (degrees). The degree of crystallinity (degree) of this oxide semiconductor layer is determined by the full width at half maximum (FWHM) of the peak that can be confirmed in XRD (X-ray diffraction) measurement by the θ-2θ method using a Cu light source (Cu-Kα ray). You can check. Specifically, the oxide in which the first semiconductor layer 5a and the second semiconductor layer 5b contain an oxide containing In such as In—Ga—Zn—O (IGZO) as a main component (90% or more in volume fraction) In the case of using a semiconductor film, the full width at half maximum of the peak that can be confirmed in the vicinity of 2θ=31° (for example, 30° to 32°) in X-ray diffraction measurement can be evaluated. More specifically, it can be evaluated that the smaller the full width at half maximum of the peak is, the higher the crystallinity is.
  本実施形態では、第１半導体層５ａは非晶質（アモルファス）の酸化物半導体膜からなる層であり、第２半導体層５ｂは結晶質の酸化物半導体膜からなる層である。すなわち、第２半導体層５ｂを構成する酸化物半導体膜の結晶性は、第１半導体層５ａを構成する酸化物半導体膜の結晶性よりも高い。言い換えれば、第２半導体層５ｂに対するＸ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅が、第１半導体層５ａに対するＸ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅よりも小さい。これにより、ソース電極及びドレイン電極をエッチングにより形成する工程において、第２半導体層５ｂが、第１半導体層５ａを保護するエッチングストッパとして機能する。 In the present embodiment, the first semiconductor layer 5a is a layer made of an amorphous oxide semiconductor film, and the second semiconductor layer 5b is a layer made of a crystalline oxide semiconductor film. That is, the crystallinity of the oxide semiconductor film forming the second semiconductor layer 5b is higher than the crystallinity of the oxide semiconductor film forming the first semiconductor layer 5a. In other words, the full width at half maximum of the peak confirmed in the vicinity of the diffraction angle 2θ=31° in the X-ray diffraction measurement for the second semiconductor layer 5b is in the vicinity of the diffraction angle 2θ=31° in the X-ray diffraction measurement for the first semiconductor layer 5a. It is smaller than the full width at half maximum of the confirmed peak. Thereby, in the step of forming the source electrode and the drain electrode by etching, the second semiconductor layer 5b functions as an etching stopper that protects the first semiconductor layer 5a.
  第２半導体層５ｂを構成する酸化物半導体膜の結晶性が高いほど、耐エッチング性を向上でき、エッチングストッパとして優れた機能を発揮する（すなわち、エッチング速度が低下する）。そのため、第２半導体層５ｂに対するＸ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅は、４．５°以下であることが好ましく、３．０°以下であることがより好ましく、２．５°以下であることがさらに好ましい。 As the crystallinity of the oxide semiconductor film forming the second semiconductor layer 5b is higher, the etching resistance can be improved and the excellent function as the etching stopper can be exhibited (that is, the etching rate will be decreased). Therefore, the full width at half maximum of the peak confirmed in the vicinity of the diffraction angle 2θ=31° in the X-ray diffraction measurement on the second semiconductor layer 5b is preferably 4.5° or less, and preferably 3.0° or less. It is more preferably 2.5° or less, and further preferably 2.5° or less.
  酸化物半導体層５の上には、ソース電極６およびドレイン電極７が配置されている。ソース電極６およびドレイン電極７はそれぞれ、電極として機能するように高い導電性を有する材料から構成されている。ソース電極６及びドレイン電極７は、金属や導電性酸化物の単層構造から構成されてもよく、２層以上の積層構造から構成されてもよい。 A source electrode 6 and a drain electrode 7 are arranged on the oxide semiconductor layer 5. The source electrode 6 and the drain electrode 7 are each made of a material having high conductivity so as to function as an electrode. The source electrode 6 and the drain electrode 7 may have a single-layer structure of metal or conductive oxide, or may have a laminated structure of two or more layers.
  ここで本実施形態のソース電極６及びドレイン電極７は、第２半導体層５ｂよりも耐エッチング性が劣る（すなわち、エッチング速度が速い）材料から構成されている。具体的には、例えば第２半導体層が結晶質のＩＧＺＯ膜から成る場合には、ソース電極６及びドレイン電極７は、酸化亜鉛インジウム（ＩＺＯ）、酸化ガリウムインジウム（ＩＧＯ）、非晶質のＩＧＺＯ膜等の金属酸化物やＭｏ等の金属の導電性膜から構成される。 Here, the source electrode 6 and the drain electrode 7 of the present embodiment are made of a material having a lower etching resistance than the second semiconductor layer 5b (that is, a faster etching rate). Specifically, for example, when the second semiconductor layer is made of a crystalline IGZO film, the source electrode 6 and the drain electrode 7 include zinc indium oxide (IZO), gallium indium oxide (IGO), and amorphous IGZO. It is composed of a metal oxide such as a film or a conductive film of a metal such as Mo.
  必要に応じて、酸化物半導体５、ソース電極６およびドレイン電極７の上には、これらを保護するための保護膜が配置されていてもよい。保護膜は、例えばシリコン酸化膜（ＳｉＯ２）、シリコン窒化膜中にフッ素を含有するフッ素化シリコン窒化膜（ＳｉＮ：Ｆ）等によって構成されてもよい。 If necessary, a protective film may be disposed on the oxide semiconductor 5, the source electrode 6, and the drain electrode 7 to protect them. The protective film may be made of, for example, a silicon oxide film (SiO 2 ), a fluorinated silicon nitride film (SiN:F) containing fluorine in the silicon nitride film, or the like.
＜２．薄膜トランジスタの製造方法＞
  次に、上述した構造の薄膜トランジスタ１の製造方法を、図２を参照して説明する。
  本実施形態の薄膜トランジスタ１の製造方法は、ゲート電極形成工程、ゲート絶縁層形成工程、半導体層形成工程、ソース・ドレイン電極形成工程を含む。以下、各工程について説明する。 <2. Method of manufacturing thin film transistor>
Next, a method of manufacturing the thin film transistor 1 having the above structure will be described with reference to FIG.
The method of manufacturing the thin film transistor 1 of the present embodiment includes a gate electrode forming step, a gate insulating layer forming step, a semiconductor layer forming step, and a source/drain electrode forming step. Hereinafter, each step will be described.
（１）ゲート電極形成工程
  まず図２の（ａ）に示すように、例えば石英ガラスからなる基板２を準備し、基板２の表面にゲート電極３を形成する。ゲート電極３の形成方法は特に制限されず、例えば真空蒸着法、ＤＣスパッタリング法等の既知の方法により形成してよい。 (1) Gate Electrode Forming Step First, as shown in FIG. 2A, a substrate 2 made of, for example, quartz glass is prepared, and a gate electrode 3 is formed on the surface of the substrate 2. The method of forming the gate electrode 3 is not particularly limited, and may be formed by a known method such as a vacuum vapor deposition method or a DC sputtering method.
（２）ゲート絶縁層形成工程
  次に、図２の（ｂ）に示すように、基板２及びゲート電極３の表面を覆うようにゲート絶縁層４を形成する。ゲート絶縁層４の形成方法は特に限定されず、既知の方法により形成してよい。 (2) Gate Insulating Layer Forming Step Next, as shown in FIG. 2B, the gate insulating layer 4 is formed so as to cover the surfaces of the substrate 2 and the gate electrode 3. The method for forming the gate insulating layer 4 is not particularly limited, and the gate insulating layer 4 may be formed by a known method.
（３）半導体層形成工程
  次に、図２の（ｃ）及び（ｄ）に示すように、ゲート絶縁層４上にチャネル層としての酸化物半導体層５を形成する。半導体層形成工程は、第１半導体層５ａを形成する第１成膜工程と、第２半導体層５ｂを形成する第２成膜工程とを含む。 (3) Semiconductor Layer Forming Step Next, as shown in FIGS. 2C and 2D, the oxide semiconductor layer 5 as a channel layer is formed on the gate insulating layer 4. The semiconductor layer forming step includes a first film forming step of forming the first semiconductor layer 5a and a second film forming step of forming the second semiconductor layer 5b.
  なお本実施形態の半導体層形成工程は、プラズマを用いてターゲットをスパッタリングすることにより酸化物半導体膜を形成する。具体的には、図４に示すような、誘導結合型のプラズマＰを用いてターゲットＴをスパッタリングして成膜するスパッタリング装置１００が用いられる。スパッタリング装置１００は、真空容器２０と、真空容器２０内において基板２を保持する基板保持部３０と、真空容器２０内において基板２と対向してターゲットＴを保持するターゲット保持部４０と、基板保持部３０に保持された基板２の表面に沿って配列され、プラズマＰを発生させる複数のアンテナ５０とを備える。スパッタリング装置１００を使用することにより、アンテナ５０に供給する高周波電圧とターゲットＴのバイアス電圧との設定を独立して行うことができる。そのため、バイアス電圧をプラ
ズマＰの生成とは独立してプラズマ中のイオンをターゲットに引き込んでスパッタさせる程度の低電圧に設定することができ、スパッタリング時にターゲットＴに印加する負のバイアス電圧を－１ｋＶ以上（すなわち絶対値が１ｋＶ以下）の負電圧に設定することが可能になる。第１成膜工程及び第２成膜工程では、ターゲット保持部４０にターゲットＴを配置し、基板保持部３０に基板２を配置して行われる。ここではターゲットＴとして、酸化物半導体５の原料となるＩｎＧａＺｎＯ等の導電性酸化物焼結体が用いられる。 Note that in the semiconductor layer formation step of this embodiment, an oxide semiconductor film is formed by sputtering a target with plasma. Specifically, as shown in FIG. 4, a sputtering apparatus 100 for forming a film by sputtering a target T using inductively coupled plasma P is used. The sputtering apparatus 100 includes a vacuum container 20, a substrate holding unit 30 that holds the substrate 2 in the vacuum container 20, a target holding unit 40 that faces the substrate 2 and holds the target T in the vacuum container 20, and a substrate holding unit. A plurality of antennas 50 arranged along the surface of the substrate 2 held by the unit 30 and generating the plasma P are provided. By using the sputtering apparatus 100, the high frequency voltage supplied to the antenna 50 and the bias voltage of the target T can be set independently. Therefore, the bias voltage can be set to a low voltage such that the ions in the plasma are attracted to the target and sputtered independently of the generation of the plasma P, and the negative bias voltage applied to the target T during sputtering is -1 kV. It is possible to set the negative voltage above (that is, the absolute value is 1 kV or less). In the first film forming step and the second film forming step, the target T is arranged in the target holding part 40 and the substrate 2 is arranged in the substrate holding part 30. Here, as the target T, a conductive oxide sintered body such as InGaZnO that is a raw material of the oxide semiconductor 5 is used.
（３－１）第１成膜工程
  まず、ゲート絶縁層４上に第１半導体層５ａを形成する。具体的には、スパッタリング装置１００の真空容器２０を３×１０－６Ｔｏｒｒ以下に真空排気した後、５０ｓｃｃｍ以上２００ｓｃｃｍ以下でスパッタリングガスを導入しつつ、真空容器内２０の圧力を０．５Ｐａ以上３．１Ｐａ以下となるように調整する。そして複数のアンテナ５０に１ｋＷ以上１０ｋＷ以下の高周波電力を供給し、誘導結合型のプラズマを生成・維持する。ターゲットに直流電圧パルスを印加して、ターゲットのスパッタリングを行う。酸素が脱離したスパッタ粒子の生成を抑制し、膜中の酸素欠陥が少ない酸化物半導体膜５ａを形成する観点から、ターゲットＴに印加する電圧を－１ｋＶ以上の負電圧とする。これにより、図２（ｃ）に示すように、ゲート絶縁層４上に第１半導体層５ａを形成する。なお、真空容
器２０内の圧力、スパッタリングガスの流量、アンテナに供給する電力量は適宜変更されてもよい。 (3-1) First Film Forming Step First, the first semiconductor layer 5a is formed on the gate insulating layer 4. Specifically, after the vacuum container 20 of the sputtering apparatus 100 is evacuated to 3×10 −6 Torr or less, the pressure in the vacuum container 20 is 0.5 Pa or more 3 while introducing the sputtering gas at 50 sccm or more and 200 sccm or less. It is adjusted so that it becomes 1 Pa or less. Then, high frequency power of 1 kW or more and 10 kW or less is supplied to the plurality of antennas 50 to generate/maintain inductively coupled plasma. A DC voltage pulse is applied to the target to sputter the target. The voltage applied to the target T is set to a negative voltage of −1 kV or more from the viewpoint of suppressing generation of sputtered particles from which oxygen is desorbed and forming the oxide semiconductor film 5a with few oxygen defects in the film. Thereby, as shown in FIG. 2C, the first semiconductor layer 5 a is formed on the gate insulating layer 4. The pressure inside the vacuum container 20, the flow rate of the sputtering gas, and the amount of electric power supplied to the antenna may be changed as appropriate.
（３－２）第２成膜工程
  第１成膜工程の後、第１半導体層５ａの上に第２半導体層５ｂを形成する。具体的には、第１成膜工程と同様に、スパッタリング装置１００を用いて、ターゲットＴのスパッタリングを行うことにより第２半導体層５ｂを形成する。第１成膜工程と同様に、第２成膜工程においても、ターゲットＴに印加する電圧を－１ｋＶ以上の負電圧とすることが好ましい。第２成膜工程における真空容器２０内の圧力、スパッタリングガスの流量、アンテナに供給する電力量等の条件は第１成膜工程と同じであってよく、適宜変更してもよい。 (3-2) Second Film Forming Step After the first film forming step, the second semiconductor layer 5b is formed on the first semiconductor layer 5a. Specifically, the second semiconductor layer 5b is formed by sputtering the target T using the sputtering apparatus 100, as in the first film forming step. Similar to the first film forming step, it is preferable that the voltage applied to the target T in the second film forming step be a negative voltage of −1 kV or more. Conditions such as the pressure in the vacuum container 20, the flow rate of the sputtering gas, and the amount of electric power supplied to the antenna in the second film forming step may be the same as those in the first film forming step, and may be appropriately changed.
  （３－３）スパッタリングガス中の酸素ガス濃度
  本実施形態では、第２成膜工程において供給するスパッタリングガスに含まれる酸素ガス濃度を、第１成膜工程において供給するスパッタリングガスに含まれる酸素ガス濃度よりも高くする。これにより第２成膜工程では、第１成膜工程に比べて、酸素が脱離したスパッタ粒子の生成をより抑えて、ターゲットの酸化状態をより維持したまま成膜することができるので、第２半導体層５ｂを構成する酸化物半導体膜の結晶性を、第１半導体層５ａを構成する酸化物半導体膜の結晶性よりも高くすることができる。 (3-3) Oxygen Gas Concentration in Sputtering Gas In the present embodiment, the oxygen gas concentration contained in the sputtering gas supplied in the second film forming step is the oxygen gas contained in the sputtering gas supplied in the first film forming step. Make it higher than the concentration. As a result, in the second film forming step, as compared with the first film forming step, it is possible to further suppress the generation of sputtered particles from which oxygen is desorbed and to form a film while maintaining the oxidation state of the target more. The crystallinity of the oxide semiconductor film forming the second semiconductor layer 5b can be made higher than the crystallinity of the oxide semiconductor film forming the first semiconductor layer 5a.
  第２半導体層５ｂを構成する酸化物半導体膜の結晶性を高くする観点から、第２成膜工程において供給されるスパッタリングガスに含まれる酸素ガス濃度は、体積分率で２０ｖоｌ％以上であることが好ましく、５０ｖоｌ％以上であることがより好ましい。スパッタリングガスとして酸素ガスのみ（すなわち、体積分率が９９．９９９ｖоｌ％以上）が供給されることが最も好ましい。 From the viewpoint of increasing the crystallinity of the oxide semiconductor film forming the second semiconductor layer 5b, the oxygen gas concentration contained in the sputtering gas supplied in the second film formation step is 20 vol% or more in terms of volume fraction. Is preferable, and more preferably 50 vol% or more. Most preferably, only oxygen gas (that is, the volume fraction is 99.999 vol% or more) is supplied as the sputtering gas.
  第１成膜工程において供給されるスパッタリングガスに含まれる酸素ガス濃度は、第２成膜工程において供給されるスパッタリングガスに含まれる酸素ガス濃度より低ければよい。第１成膜工程において非晶質の酸化物半導体膜を形成する観点から、スパッタリングガスに含まれる酸素ガス濃度は体積分率で２ｖоｌ％以下が好ましく、スパッタリングガスとしてアルゴンガスのみが供給されることが好ましい。 The oxygen gas concentration contained in the sputtering gas supplied in the first film forming step may be lower than the oxygen gas concentration contained in the sputtering gas supplied in the second film forming step. From the viewpoint of forming an amorphous oxide semiconductor film in the first film formation step, the oxygen gas concentration contained in the sputtering gas is preferably 2 vol% or less in volume fraction, and only argon gas is supplied as the sputtering gas. Is preferred.
（４）ソース・ドレイン電極形成工程
  次に、酸化物半導体層５上にソース電極６およびドレイン電極７を形成する。ここでは、第２半導体層５ｂの上に導電性膜Ｍを形成した後、フォトリソグラフィによりパターニングを行うことで、ソース電極６及びドレイン電極７を形成する。 (4) Source/Drain Electrode Forming Step Next, the source electrode 6 and the drain electrode 7 are formed on the oxide semiconductor layer 5. Here, the source electrode 6 and the drain electrode 7 are formed by forming the conductive film M on the second semiconductor layer 5b and then performing patterning by photolithography.
  具体的にはまず、図３の（ｅ）に示すように、ゲート絶縁層４及び第２半導体層５ｂを覆うように、金属や導電性酸化物から成る導電性膜Ｍを形成する。導電性膜Ｍは、例えばＤＣスパッタリングやＲＦスパッタリング等の既知の方法により形成されてよい。 Specifically, first, as shown in FIG. 3E, a conductive film M made of a metal or a conductive oxide is formed so as to cover the gate insulating layer 4 and the second semiconductor layer 5b. The conductive film M may be formed by a known method such as DC sputtering or RF sputtering.
  次に、導電性膜Ｍの上にレジストＲを塗布した後露光・現像等を行い、図３の（ｆ）に示すように、導電性膜Ｍ上において後にソース電極６及びドレイン電極７とする部位にのみレジストＲを残すようにする。 Next, a resist R is applied on the conductive film M, and then exposure and development are performed to form the source electrode 6 and the drain electrode 7 on the conductive film M later, as shown in FIG. The resist R is left only on the part.
  そして、図３の（ｇ）に示すように、導電性膜ＭにおけるレジストＲが塗布されていない部分をエッチングにより除去し、ソース電極６及びドレイン電極７を形成する。エッチングの手法として、ＣＦ４ガス等を用いたドライエッチングを行ってもよく、ＨＣｌ等の酸を用いたウェットエッチングを行ってもよい。ここで第２導電層５ｂは、第１導電層５ａ及び導電性膜Ｍよりも優れた耐エッチング性を有しており、エッチングストッパとして機能して第１導電層５ａをエッチャントから保護するようになっている。 Then, as shown in (g) of FIG. 3, the portions of the conductive film M to which the resist R is not applied are removed by etching to form the source electrode 6 and the drain electrode 7. As an etching method, dry etching using CF 4 gas or the like may be performed, or wet etching using acid such as HCl may be performed. Here, the second conductive layer 5b has better etching resistance than the first conductive layer 5a and the conductive film M, and functions as an etching stopper to protect the first conductive layer 5a from an etchant. Is becoming
（５）保護膜形成工程
  必要に応じて、形成された酸化物半導体層５、ソース電極６およびドレイン電極７の上面を覆うように、例えばプラズマＣＶＤ法を用いて保護膜を形成する。 (5) Protective Film Forming Step As necessary, a protective film is formed so as to cover the upper surfaces of the formed oxide semiconductor layer 5, the source electrode 6, and the drain electrode 7 by using, for example, a plasma CVD method.
（６）熱処理工程
  最後に、必要に応じて酸素を含む大気圧下の雰囲気中で熱処理を行ってもよい。熱処理における炉内温度は特に限定されず、例えば１５０℃以上３００℃以下である。また熱処理時間は特に限定されず、例えば１時間以上３時間以下である。 (6) Heat Treatment Step Finally, if necessary, heat treatment may be performed in an atmosphere containing oxygen under atmospheric pressure. The temperature in the furnace during the heat treatment is not particularly limited and is, for example, 150° C. or higher and 300° C. or lower. The heat treatment time is not particularly limited and is, for example, 1 hour or more and 3 hours or less.
  以上により、本実施形態の薄膜トランジスタ１を得ることができる。なお、本実施形態において保護膜形成工程及び熱処理工程は必須の工程ではなく、これらを省略してもよい。 As described above, the thin film transistor 1 of this embodiment can be obtained. Note that, in the present embodiment, the protective film forming step and the heat treatment step are not essential steps and may be omitted.
＜３．酸化物半導体層の結晶性の耐エッチング性との関係性評価＞
  本実施形態の酸化物半導体層５（第１半導体層５ａ及び第２半導体層５ｂ）の結晶性と耐エッチング性との関係性を評価した。 <3. Evaluation of relationship between crystallinity of oxide semiconductor layer and etching resistance>
The relationship between the crystallinity and etching resistance of the oxide semiconductor layer 5 (first semiconductor layer 5a and second semiconductor layer 5b) of this embodiment was evaluated.
（サンプル作成）
  具体的には、シリコン基板を複数準備し、前記した製造方法の“半導体製造工程”に基づいて、スパッタリングにより、Ｉｎ－Ｇａ－Ｚｎ－Ｏ（ＩＧＺＯ１１１４）から成る酸化物半導体膜を基板上に形成したサンプルを複数個作成した。 (Sample making)
Specifically, a plurality of silicon substrates are prepared, and an oxide semiconductor film made of In-Ga-Zn-O (IGZO1114) is formed on the substrate by sputtering based on the "semiconductor manufacturing process" of the manufacturing method described above. Multiple samples were prepared.
  より具体的には、前記したスパッタリング装置１００を用いて、真空容器内の圧力を０．９Ｐａ以下まで減圧し、複数のアンテナに７ｋＷの高周波電力を供給し、ターゲットに－４００Ｖの直流パルス電圧を印加してターゲットのスパッタリングを行い、酸化物半導体膜を形成した。ここで、供給するスパッタリングガス中の酸素ガス濃度を変えた５種類のサンプル（それぞれ、体積分率で０ｖｏｌ％、５ｖｏｌ％、２０ｖｏｌ％、５０ｖｏｌ％、１００ｖｏｌ％）を１個又は２個ずつ（計９個）作成した。なお、特に記載していない製造条件は、前記した製造方法に記載したものと同等である。 More specifically, using the sputtering apparatus 100 described above, the pressure inside the vacuum container is reduced to 0.9 Pa or less, high-frequency power of 7 kW is supplied to the plurality of antennas, and a DC pulse voltage of −400 V is applied to the target. The voltage was applied and sputtering of the target was performed to form an oxide semiconductor film. Here, one or two samples (total of 5 vol%, 5 vol%, 20 vol%, 50 vol%, and 100 vol%, respectively) of 5 kinds of samples with different oxygen gas concentrations in the supplied sputtering gas (total volume fraction, respectively) (total: 9) were created. The manufacturing conditions not particularly described are the same as those described in the above-described manufacturing method.
（ＸＲＤ測定におけるピークの半値全幅の測定）
  作成した５種類のサンプルの酸化物半導体膜に対して、Ｃｕ光源（Ｃｕ－Ｋα線）を使用したブルカー・エイエックスエス社製のＸ線回折装置（型番：Ｄ８  ＤＩＳＣＯＶＥＲ）を用いてＸ線回折（ＸＲＤ）測定を行い、２θ＝３１°近傍で確認できるＩｎに由来するピークの半値全幅（ＦＷＨＭ）の大きさを測定した。スパッタリング中の酸素ガス濃度と、ピークの半値全幅との関係は表１に示すとおりである。なお、酸素ガス濃度が５ｖоｌ％、２０ｖоｌ％、５０ｖоｌ％及び１００ｖоｌ％のサンプルでは、２θ＝３１°近傍において鋭いピークが見られ、結晶質の酸化物半導体膜（ｃ‐ＩＧＺＯ）が形成されていることを確認できた。また酸素ガス濃度が０ｖоｌ％のサンプルでは、２θ＝３１°近傍において鋭いピークが見られず、非晶質の酸化物半導体膜（ａ‐ＩＧＺＯ）が形成されていることを確認できた。 (Measurement of full width at half maximum of peak in XRD measurement)
X-ray diffraction was performed on the prepared five types of sample oxide semiconductor films using an X-ray diffractometer (model number: D8 DISCOVER) manufactured by Bruker AXS Co., which uses a Cu light source (Cu-Kα ray). (XRD) measurement was performed to measure the full width at half maximum (FWHM) of the peak derived from In that can be confirmed in the vicinity of 2θ=31°. The relationship between the oxygen gas concentration during sputtering and the full width at half maximum of the peak is shown in Table 1. Note that in the samples with oxygen gas concentrations of 5 vol%, 20 vol%, 50 vol%, and 100 vol%, a sharp peak was observed near 2θ=31°, and a crystalline oxide semiconductor film (c-IGZO) was formed. I was able to confirm that. Further, in the sample having an oxygen gas concentration of 0 vol%, no sharp peak was observed near 2θ=31°, and it could be confirmed that an amorphous oxide semiconductor film (a-IGZO) was formed.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
（エッチング速度の測定）
  作成した５種類のサンプルの酸化物半導体膜に対して、ＨＣｌ水溶液（体積：０．０５Ｍ、０．５Ｍ）をエッチャントとしてエッチングを行い、そのエッチング速度を測定した。酸素ガス濃度とスパッタリング中の酸素ガス濃度と、エッチング速度との関係は表２に示すとおりである。 (Measurement of etching rate)
The five types of sample oxide semiconductor films thus prepared were etched using an aqueous HCl solution (volume: 0.05 M, 0.5 M) as an etchant, and the etching rate was measured. Table 2 shows the relationship between the oxygen gas concentration, the oxygen gas concentration during sputtering, and the etching rate.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
（酸化物半導体膜の結晶性と耐エッチング性との関係性）
  これらの結果に基づき、ＸＲＤ測定における酸化物半導体膜のピークの半値全幅とエッチング速度との関係を図５に示す。図５から分かるように、２θ＝３１°近傍で確認できるピークの半値全幅が４．５°以下である結晶質の酸化物半導体膜（ｃ‐ＩＧＺＯ）は、ピークの半値全幅が５°を超える非晶質（アモルファス）の酸化物半導体膜（ａ‐ＩＧＺＯ）に比べて、エッチング速度が大幅に低下し、優れた耐エッチング性を示すことを確認できた。そして、結晶質の酸化物半導体膜（ｃ‐ＩＧＺＯ）の結晶性が高いほど、すなわちピークの半値全幅が小さいほど、エッチング速度がより低下し、耐エッチング性が高まり、エッチングストッパとして好適であることを確認できた。 (Relationship between crystallinity of oxide semiconductor film and etching resistance)
Based on these results, the relationship between the full width at half maximum of the peak of the oxide semiconductor film in the XRD measurement and the etching rate is shown in FIG. As can be seen from FIG. 5, the crystalline oxide semiconductor film (c-IGZO) having a peak full width at half maximum of 4.5° or less that can be confirmed near 2θ=31° has a full width at half maximum of more than 5°. It was confirmed that the etching rate was significantly lower than that of the amorphous oxide semiconductor film (a-IGZO), and that it exhibited excellent etching resistance. The higher the crystallinity of the crystalline oxide semiconductor film (c-IGZO), that is, the smaller the full width at half maximum of the peak, the lower the etching rate, the higher the etching resistance, and the better as an etching stopper. I was able to confirm.
＜４．本実施形態の効果＞
  このようにした本実施形態の薄膜トランジスタ１およびその製造方法によれば、チャネル層として機能する第２半導体層５ｂを構成する酸化物半導体膜の結晶性が第１半導体層５ａを構成する酸化物半導体膜の結晶性よりも高いので、ソース・ドレイン電極形成工程において電極ソース電極６及びドレイン電極７をエッチングにより形成する際に、第２半導体層５ｂがエッチングストッパとして機能して第１半導体層５ａをエッチング液から保護することができる。そのため、エッチングストッパとして、例えばＳｉＯ２等からなる絶縁膜を別途設けるためにスパッタリングを行う必要がない。しかも、第１半導体層５ａと第２半導体層５ｂは互いに同一の構成元素を含む酸化物半導体膜から成るので、これらをスパッタリングにより形成する場合には、同一のターゲットＴを用いて、スパッタリン
グガス中の酸素ガス濃度等のスパッタリング条件を変更するだけで続けて成膜することができるので、ターゲットＴを付け替えたり、成膜室を変更する必要がなく、生産性良く薄膜トランジスタ１を製造することができる。 <4. Effect of this embodiment>
According to the thin film transistor 1 of this embodiment and the method of manufacturing the thin film transistor thus configured, the oxide semiconductor film forming the second semiconductor layer 5b functioning as a channel layer has a crystallinity forming the first semiconductor layer 5a. Since the crystallinity of the film is higher than that of the film, when the electrode source electrode 6 and the drain electrode 7 are formed by etching in the source/drain electrode forming step, the second semiconductor layer 5b functions as an etching stopper to form the first semiconductor layer 5a. It can be protected from the etching solution. Therefore, it is not necessary to perform sputtering to separately provide an insulating film made of, for example, SiO 2 as an etching stopper. Moreover, since the first semiconductor layer 5a and the second semiconductor layer 5b are made of oxide semiconductor films containing the same constituent elements, when they are formed by sputtering, the same target T is used in the sputtering gas. Since it is possible to continue film formation simply by changing the sputtering conditions such as the oxygen gas concentration, it is possible to manufacture the thin film transistor 1 with high productivity without changing the target T or changing the film forming chamber. ..
＜その他の変形実施形態＞
  なお、本発明は前記実施形態に限られるものではない。 <Other modified embodiments>
The present invention is not limited to the above embodiment.
  前記実施形態では、複数のターゲット保持部４０を有する構成であったが、１つのターゲット保持部４０を有する構成であってもよい。この場合であっても、複数のアンテナ５０を有する構成が望ましいが、１つのアンテナ５０を有する構成であってもよい。 In the above-described embodiment, the configuration has the plurality of target holding units 40, but the configuration may have one target holding unit 40. Even in this case, the configuration having the plurality of antennas 50 is desirable, but the configuration having one antenna 50 may be used.
  その他、本発明は前記実施形態に限られず、その趣旨を逸脱しない範囲で種々の変形が可能であるのは言うまでもない。 In addition, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
  １    ・・・薄膜トランジスタ
  ２    ・・・基板
  ３    ・・・ゲート電極
  ４    ・・・ゲート絶縁層
  ５    ・・・酸化物半導体層
  ５ａ  ・・・第１半導体層
  ５ｂ  ・・・第２半導体層
  ６    ・・・ソース電極
  ７    ・・・ドレイン電極 DESCRIPTION OF SYMBOLS 1... Thin film transistor 2... Substrate 3... Gate electrode 4... Gate insulating layer 5... Oxide semiconductor layer 5a... 1st semiconductor layer 5b... 2nd semiconductor layer 6...・Source electrode 7 ・・・Drain electrode

Claims (8)

  1.   基板上に、ゲート電極と、ゲート絶縁層と、酸化物半導体層と、ソース電極及びドレイン電極とがこの順に配置された薄膜トランジスタであって、
      前記酸化物半導体層は、互いに同一の構成元素を含む酸化物半導体膜から成る第１半導体層と第２半導体層とを前記基板側から順に備えており、
      前記第２半導体層を構成する酸化物半導体膜の結晶性が、前記第１半導体層を構成する前記酸化物半導体膜の結晶性よりも高いことを特徴とする薄膜トランジスタ。     A thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode are arranged in this order on a substrate,
    The oxide semiconductor layer includes a first semiconductor layer and a second semiconductor layer, which are oxide semiconductor films containing the same constituent elements, in order from the substrate side,
    A thin film transistor, wherein crystallinity of an oxide semiconductor film forming the second semiconductor layer is higher than crystallinity of the oxide semiconductor film forming the first semiconductor layer.
  2.   前記第１半導体層が非晶質の前記酸化物半導体膜から成り、前記第２半導体層が結晶質の前記酸化物半導体膜から成る、請求項１に記載の薄膜トランジスタ。 The thin film transistor according to claim 1, wherein the first semiconductor layer is made of the amorphous oxide semiconductor film, and the second semiconductor layer is made of the crystalline oxide semiconductor film.
  3.   前記第１半導体層及び前記第２半導体層がいずれもＩｎを含む酸化物半導体膜から成り、
      前記第２半導体層に対するＣｕ‐Ｋα線を用いたθ－２θ法によるＸ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅が、前記第１半導体層に対する前記Ｘ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅よりも小さい請求項１又は２に記載の薄膜トランジスタ。     Each of the first semiconductor layer and the second semiconductor layer is made of an oxide semiconductor film containing In,
    The full width at half maximum of the peak confirmed in the vicinity of the diffraction angle 2θ=31° in the X-ray diffraction measurement by the θ-2θ method using the Cu-Kα ray for the second semiconductor layer is the X-ray diffraction for the first semiconductor layer. The thin film transistor according to claim 1 or 2, which is smaller than the full width at half maximum of the peak confirmed in the vicinity of the diffraction angle 2θ=31° in the measurement.
  4.     前記第２半導体層に対するＣｕ‐Ｋα線を用いたθ－２θ法によるＸ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅が４．５°以下である請求項３に記載の薄膜トランジスタ。 4. The full width at half maximum of the peak confirmed in the vicinity of the diffraction angle 2θ=31° in the X-ray diffraction measurement by the θ-2θ method using Cu-Kα ray for the second semiconductor layer is 4.5° or less. The thin film transistor described.
  5.   前記第２半導体層に対するＣｕ‐Ｋα線を用いたθ－２θ法によるＸ線回折測定における回折角２θ＝３１°近傍において確認されるピークの半値全幅が３．０°以下である請求項３に記載の薄膜トランジスタ。 4. The full width at half maximum of the peak confirmed in the vicinity of the diffraction angle 2θ=31° in the X-ray diffraction measurement by the θ-2θ method using Cu-Kα ray for the second semiconductor layer is 3.0° or less. The thin film transistor described.
  6.   前記第２半導体層を構成する前記酸化物半導体膜の耐エッチング性が、前記ソース電極及び前記ドレイン電極を構成する材料の耐エッチング性よりも優れた請求項１～５のいずれかに記載の薄膜トランジスタ。 6. The thin film transistor according to claim 1, wherein the oxide semiconductor film forming the second semiconductor layer has an etching resistance higher than that of a material forming the source electrode and the drain electrode. ..
  7.   エッチングストッパ型のものであり、前記第２半導体層がエッチングストッパとして機能する請求項１～６のいずれかに記載の薄膜トランジスタ。 7. The thin film transistor according to claim 1, wherein the thin film transistor is of an etching stopper type and the second semiconductor layer functions as an etching stopper.
  8.   基板上に、ゲート電極と、ゲート絶縁層と、酸化物半導体層と、ソース電極及びドレイン電極とがこの順に配置された薄膜トランジスタの製造方法であって、
      プラズマを用いてターゲットをスパッタリングして、結晶性が互いに異なる酸化物半導体膜から成る第１半導体層と第２半導体層とを前記ゲート絶縁層の上に前記基板側から順に形成する半導体層形成工程と、
      前記第２半導体層をエッチングストッパとしてエッチングを行い、前記ソース電極及び前記ドレイン電極を前記酸化物半導体層の上に形成する前記ソース・ドレイン電極形成工程と
    を含む薄膜トランジスタの製造方法。     A method of manufacturing a thin film transistor, in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode are arranged in this order on a substrate,
    Semiconductor layer forming step of sputtering a target using plasma to sequentially form a first semiconductor layer and a second semiconductor layer made of oxide semiconductor films having different crystallinities on the gate insulating layer from the substrate side. When,
    A method of manufacturing a thin film transistor, comprising the step of forming the source electrode and the drain electrode on the oxide semiconductor layer by performing etching using the second semiconductor layer as an etching stopper.
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