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WO2020101572A1 - Multi-chip system and method of forming the same - Google Patents

Multi-chip system and method of forming the same Download PDF

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Publication number
WO2020101572A1
WO2020101572A1 PCT/SG2019/050553 SG2019050553W WO2020101572A1 WO 2020101572 A1 WO2020101572 A1 WO 2020101572A1 SG 2019050553 W SG2019050553 W SG 2019050553W WO 2020101572 A1 WO2020101572 A1 WO 2020101572A1
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WO
WIPO (PCT)
Prior art keywords
chip
redistribution layer
electrical
substrate
signal
Prior art date
Application number
PCT/SG2019/050553
Other languages
French (fr)
Inventor
Teck Guan Lim
Original Assignee
Agency For Science, Technology And Research
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Publication date
Application filed by Agency For Science, Technology And Research filed Critical Agency For Science, Technology And Research
Publication of WO2020101572A1 publication Critical patent/WO2020101572A1/en

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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Definitions

  • Various aspects of this disclosure relate to a multi-chip system. Various aspects of this disclosure relate to a method of forming a multi-chip system.
  • FIG. 1 shows a schematic showing a conventional system having a High Bandwidth Memory (HBM) and Graphics Processing Unit (GPU)/ Application Specific Integrated Circuit (ASIC) Chip interface.
  • HBM High Bandwidth Memory
  • GPU Graphics Processing Unit
  • ASIC Application Specific Integrated Circuit
  • the line width is typically in the range of about 2 pm, and the spacing is typically about 4pm.
  • the line length is about 6 mm .
  • the long length and the narrow width of the line lead to high signal loss, while the narrow spacing leads to high signal interference.
  • the narrow line width of 2 pm is the current minimum limit of several fabrication processes.
  • the multi-chip system may include a first chip having an active surface.
  • the multi-chip system may also include a second chip having an active surface facing the active surface of the first chip.
  • the multi-chip system may additionally include a redistribution layer between the first chip and the second chip.
  • the redistribution layer may include a dielectric material.
  • the redistribution layer may also include a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip.
  • the redistribution layer may additionally include an electromagnetic shield having an opening in which the through via structure passes through.
  • the redistribution layer may further include an electrical via in electrical connection with the electromagnetic shield.
  • the multi-chip system may further include a solder bump array connection at a side of the redistribution layer as the second chip, the solder bump array connection configured to connect to a substrate or an external circuit and including a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip.
  • Various embodiments may provide a method of forming a multi-chip system.
  • the method may include providing or forming a redistribution layer between a first chip and a second chip.
  • the second chip may have an active surface facing an active surface of the first chip.
  • the redistribution layer may include a dielectric material.
  • the redistribution layer may also include a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip.
  • the redistribution layer may further include an electromagnetic shield having an opening in which the through via structure passes through. An electrical via may be in electrical connection with the electromagnetic shield.
  • the method may further include providing a solder bump array connection at a side of the redistribution layer as the second chip, the solder bump array connection configured to connect to a substrate or an external circuit and including a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip
  • FIG. 1 shows a schematic showing a conventional system having a High Bandwidth Memory (HBM) and Graphics Processing Unit (GPU)/Application Specific Integrated Circuit (ASIC) Chip interface.
  • HBM High Bandwidth Memory
  • GPU Graphics Processing Unit
  • ASIC Application Specific Integrated Circuit
  • FIG. 2 is a general illustration of a multi-chip system according to various embodiments.
  • FIG. 3 is a general illustration of a method of forming a multi-chip system according to various embodiments.
  • FIG. 4A is a cross-sectional schematic of a multi-chip system according to various embodiments.
  • FIG. 4B is another cross-sectional schematic showing part of the multi-chip system shown in FIG. 4A according to various embodiments.
  • FIG. 4C shows a magnification of a portion of the multi-chip system shown in FIG. 4A according to various embodiments.
  • FIG. 4D is a schematic showing the top view of the multi-chip system according to various embodiments.
  • FIG. 5A shows through via structures connecting a first chip and a second chip according to various embodiments.
  • FIG. 5B shows through via structures connecting a first chip and a second chip according to various other embodiments.
  • FIG. 6 is a cross-sectional schematic of a portion of a multi-chip system according to various embodiments.
  • FIG. 7 shows a schematic of a shielding plane of a multi-chip system according to various embodiments.
  • FIG. 8 shows a schematic of another shielding plane of a multi-chip system according to various embodiments.
  • FIG. 9 shows a schematic of yet another shielding plane of a multi-chip system according to various embodiments.
  • FIG. 10A is a cross-sectional schematic of a portion of a multi-chip system according to various embodiments.
  • FIG. 1 OB is a schematic of a portion of the multi-chip system according to various embodiments that is used as the simulation model.
  • FIG. IOC is a plot of insertion loss (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated insertion loss of the multi-chip system according to various embodiments shown in FIGS. 10A-B.
  • FIG. 10D is a plot of return loss (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated return loss of the multi-chip system according to various embodiments shown in FIGS. 10A-B.
  • FIG. 10E is a plot of cross-talk (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated cross-talk of the multi-chip system according to various embodiments shown in FIGS. 10A-B.
  • Embodiments described in the context of one of the methods or multi-chip systems are analogously valid for the other methods or multi-chip systems. Similarly, embodiments described in the context of a method are analogously valid for a multi-chip system, and vice versa.
  • the articles“a”,“an” and“the” as used with regard to a feature or element include a reference to one or more of the features or elements.
  • the term“about” or“approximately” as applied to a numeric value encompasses the exact value and a reasonable variance.
  • High Bandwidth Memory is designed to meet the extreme high bandwidth dynamic random access memory (DRAM) requirement applications such as high performance Computing (HPC), Terabit Ethernet (TbE) and Graphics Processing Unit (GPU).
  • HPC high performance Computing
  • TbE Terabit Ethernet
  • GPU Graphics Processing Unit
  • the HBM and the Graphics Processing Unit (GPU)/Central Processing Unit (CPU)/Application Specific Integrated Circuit (ASIC)/System on Chip (SoC) are integrated laterally, and the typical interconnect length is about 8mm long.
  • the fine width, fine spacing and long length lead to poor signal integrity and fabrication process challenges.
  • Various embodiments may seek to address or mitigate the high signal loss facing conventional systems.
  • Various embodiments may address or mitigate the process complexity of conventional systems.
  • through vias including micro-vias may be designed, thus reducing the interconnection length.
  • the vertical interconnections may mean that the system no longer require the fine line width and spacing of lateral wire connections. In this way, the electrical performance may be greatly improved.
  • the process complexity may also be reduced as fine line width and spacing are no longer required.
  • the through via design may still face with the issue of limited number of through mold interconnects/through mold vias (TMI TMV) to support the external electrical connections.
  • TMI/TMV is a costly FOWLP process.
  • Various embodiments may relate to a system which uses a direct chip face-to-face connection using fan-out wafer level packaging (FOWLP) with only the top chip embedded.
  • the system may be without TMI/TMV.
  • the substrate/PCB may be formed with one or more openings to fit the bottom chips so that the external I/Os may be connected just by solder or micro bumps to the redistribution layer (RDL).
  • RDL redistribution layer
  • FIG. 2 is a general illustration of a multi-chip system 200 according to various embodiments.
  • the multi-chip system 200 may include a first chip 202 having an active surface.
  • the multi-chip system 200 may also include a second chip 204 having an active surface facing the active surface of the first chip 202.
  • the multi-chip system 200 may additionally include a redistribution layer 206 between the first chip 202 and the second chip 204.
  • the redistribution layer 206 may include a dielectric material.
  • the redistribution layer 206 may also include a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip.
  • the redistribution layer 206 may additionally include an electromagnetic shield having an opening in which the through via structure passes through.
  • the redistribution layer 206 may further include an electrical via in electrical connection with the electromagnetic shield.
  • the multi-chip system 200 may include a redistribution layer 206 between a first chip 202 and a second chip 204.
  • the redistribution layer 206 may include a through via structure pass through an opening of an electromagnetic shield of the redistribution layer 206.
  • the electrical via may be a power (PWR) via.
  • the electromagnetic shield connected to the power via may be referred to as a PWR plane or a RDL- PWR plane.
  • the electrical via may be a ground (GND) via.
  • the electromagnetic shield connected to the ground via may be referred to as a GND plane or a RDL- GND plane.
  • the through via structure may extend from a first surface of the redistribution layer 206 to a second surface of the redistribution layer 206 opposite the first surface.
  • the redistribution layer 206 may further include one or more additional through via structures extending from the first surface of the redistribution layer 206 to the second surface of the redistribution layer 206 opposite the first surface.
  • Each through via structure may include one or more signal vias.
  • the one or more signal vias may be micro vias.
  • Each through via structure may also include one or more electrical interconnects, e.g. signal pads or metal contacts. An electrical interconnect may electrically connect a first signal via and a second signal via of the one or more signal vias.
  • the electromagnetic shield may form a shielding plane in the redistribution layer 206.
  • the redistribution layer 206 may include a suitable metal such as copper, gold, aluminum, or nickel.
  • An“active surface” as described herein may refer to a surface of a chip in which components such as transistors, diodes, capacitors, and/or other electrical components are formed.
  • the multi-chip system 200 may further include a solder bump array connection at a side of the redistribution layer 206 as the second chip 204, the solder bump array connection configured to connect to a substrate or an external circuit and including a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip.
  • the second chip 204 and the solder bump array connection may be on a side of the redistribution layer 206, while the first chip 202 may be on an opposing side of the redistribution layer 206.
  • the multi-chip system 200 may include the substrate.
  • the substrate may include one or more electrical connections.
  • the first chip 202 and the second chip 204 may be over the substrate.
  • the redistribution layer 206 may further include one or more (first) interconnections configured to electrically connect the first chip with the one or more electrical connections of the substrate.
  • the redistribution layer 206 may further include one or more (second) interconnections configured to electrically connect the second chip with the one or more electrical connections of the substrate.
  • the substrate may include a cavity configured to receive the second chip 204.
  • the cavity may also include a heat spreader or a heat conductive compound.
  • the first chip 202 may be over or above the second chip 204.
  • the through via structure may have a via on via design.
  • the through via structure may include a plurality of signal vias aligned to form a straight line between the first chip 202 and the second chip 204.
  • the straight line may be a vertical line between the first chip 202 and the second chip 204.
  • the through via structure may also include a plurality of electrical interconnects.
  • An electrical interconnect may have a first surface in contact with a first signal via and a second surface (opposite the first surface) in contact with a second signal via.
  • the through via structure may have an offset via design.
  • the through via structure may include a first signal via, and a second signal via laterally offset from the first signal via.
  • the redistribution layer 206 may further include an electrical interconnect in contact with the first signal via and the second signal via.
  • the electrical interconnect may extend laterally between the first signal via and the second signal via.
  • the electrical interconnect may electrically connect the first signal via and the second signal via.
  • the first signal via may contact a first surface of the electrical interconnect, while the second signal via may contact a second surface of the electrical interconnect opposite the first suface.
  • the first chip may be any one chip selected from a group consisting of a graphic processing unit (GPU) chip, a processor chip such as a central processing unit (CPU) chip, an application specific integrated circuit (ASIC) chip, and a system on chip (SoC).
  • the second chip may be a High Bandwidth Memory (HDM) chip, a Hybrid Memory Cube (HMC) chip, or a high density input/output (I/O) chip.
  • HDMI High Bandwidth Memory
  • HMC Hybrid Memory Cube
  • I/O input/output
  • a chip area of the first chip 202 may be greater than a chip area of the second chip 204. Accordingly, the electrical connections in the redistibution layer 206 from connections of the first chip 202 to the substrate may be formed around the bottom second chip 204.
  • the multi-chip system may include a third chip.
  • the third chip may be lateral to the second chip 204.
  • the redistribution layer 206 may also be between the first chip 202 and the third chip.
  • the second chip 204 and the third chip may be on the same side of the redistribution layer 206.
  • the first chip 202 may be on an opposing side of the redistribution layer 206 as the second chip 204 or the third chip.
  • the third chip may have an active surface facing the active surface of the first chip.
  • the redistribution layer 206 may include a further through via structure configured to carry a further electrical signal between the first chip and the third chip.
  • the further through via structure may extend from a first surface of the redistribution layer 206 to a second surface of the redistribution layer 206 opposite the first surface.
  • the redistribution layer 206 may further include one or more additional further through via structures extending from the first surface of the redistribution layer 206 to the second surface of the redistribution layer 206 opposite the first surface.
  • Each further through via structure may include one or more further signal vias.
  • the one or more further signal vias may be micro vias.
  • Each through via structure may also include one or more further electrical interconnects, e.g. signal pads or metal contacts.
  • a further electrical interconnect may electrically connect a further first signal via and a second further signal via of the one or more further signal vias.
  • the further through via structure may include a plurality of further signal vias aligned to form a straight line between the first chip 202 and the third chip.
  • the further through via structure may include a further first signal via, and a further second signal via laterally offset from the further first signal via.
  • the third chip may be a High Bandwidth Memory (HDM) chip, a Hybrid Memory Cube (HMC) chip, or a high density input/output (I/O) chip.
  • a chip area of the first chip 202 may be greater than a chip area of the third chip.
  • the multi-chip system may further include one or more additional chips.
  • the one or more additional chips may each have an active surface facing the first chip 202, and may be on the same side of the redistribution layer 206 as the second chip 204 and the third chip.
  • the second chip 204, the third chip, and the one or more additional chips may be on a side of the redistribution layer 206, while the first chip 202 may be on an opposing side of the redistribution layer 206.
  • the redistribution layer 206 may also be between the first chip 202 and each of the one or more additional chips.
  • Each of the one or more additional chips may be a High Bandwidth Memory (HDM) chip, a Hybrid Memory Cube (HMC) chip, or a high density input/output (I/O) chip.
  • the multi-chip system 200 may also be referred to as a multi chip package.
  • the through via structure may alternatively be referred to as a through via, and the further through via structure may alternatively be referred to as a further through via.
  • FIG. 3 is a general illustration of a method of forming a multi-chip system according to various embodiments.
  • the method may include, in 302, providing or forming a redistribution layer between a first chip and a second chip.
  • the second chip may have an active surface facing an active surface of the first chip.
  • the redistribution layer may include a dielectric material.
  • the redistribution layer may also include a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip.
  • the redistribution layer may further include an electromagnetic shield having an opening in which the through via structure passes through. An electrical via may be in electrical connection with the electromagnetic shield.
  • the method may include providing or forming a redistribution layer between a first chip and a second chip.
  • the redistribution layer may include an electromagnetic shield having an opening for a through via structure carrying electrical signals between the first chip and the second chip to pass through.
  • the first chip may be above or over the second chip.
  • the redistribution layer may be formed on the first chip before arranging the second chip so that the first chip is above the second chip, and the redistribution layer is between the first chip and the second chip.
  • the method may further include providing a solder bump array connection at a side of the redistribution layer as the second chip, the solder bump array connection configured to connect to a substrate or an external circuit and including a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip.
  • the method may include providing or forming the substrate.
  • the substrate may include one or more electrical connections.
  • the first chip and the second chip may be over the substrate.
  • the method may include arranging a substrate such that the first chip and the second chip are over the substrate.
  • the method may include providing a third chip.
  • the redistribution layer may be also between the first chip and the third chip.
  • the method may include arranging a third chip such that the redistribution layer is between the first chip and the third chip.
  • the third chip may also be arranged over the substrate.
  • the redistribution layer may include a further through via structure configured to carry a further electrical signal between the first chip and the third chip.
  • the method may include providing one or more additional chips.
  • the method may include arranging the one or more additional chips such that the redistribution layer is between the first chip and each of the one or more additional chips.
  • FIG. 4A is a cross-sectional schematic of a multi-chip system 400 according to various embodiments.
  • FIG. 4B is another cross-sectional schematic showing part of the multi-chip system 400 shown in FIG. 4A according to various embodiments.
  • FIG. 4C shows a magnification of a portion of the multi-chip system 400 shown in FIG. 4A according to various embodiments.
  • various embodiments may utilize a 3D integration for the HBM and the GPU/ASIC/CPU/SoC chips.
  • the system 400 (also referred to as package) may include a first chip 402, which may be a GPU/ASIC/CPU/SoC chip.
  • the system 400 may also include a second chip 404a, which may be a HBM chip, and a third chip 404b which may be a further HBM chip.
  • the system 400 may further include a redistribution layer 406 extending between the first chip 402 and the second chip 404a, and extending between the first chip 402 and the third chip 404b.
  • the redistribution layer 406 may include a dielectric material.
  • the redistribution layer 406 may also include through via structures 408a electrically connecting the first chip 402 and the second chip 404a, as well as further through via structures 408b electrically connecting the first chip 402 and the third chip 404b.
  • Each through via structure 408a may include a plurality of signal vias
  • each further through via structure 408b may include a plurality of further signal vias.
  • the GPU/ASIC/CPU/SoC chip 402 and the HBM chips 404a, 404b may be assembled faee to face so that the signal input/outputs, i.e. signals vias and further signal vias may be vertically aligned as shown in FIGS. 4A-C.
  • the signals vias may extend from a first surface of the redistribution layer 406 to a second surface of the redistribution layer 406 opposite the first surface to connect the first chip 402 and the second chip 404a.
  • the further signals vias may extend from the first surface of the redistribution layer 406 to the second surface of the redistribution layer 406 to connect the first chip 402 and the third chip 404b.
  • the signal vias and the further signal vias may be micro-vias.
  • the I/O positions of the chips 402, 404a-b and design may be required to be matched.
  • the memory I/O configuration may be set by industry standards under JEDEC (Joint Electron Device Engineering Council). Flence, the I/O positions of the GPU/ASIC/CPU/SoC chip 402 may be required to be designed for matching with the I/O configuration of the memory chips 404a-b.
  • the system 400 may further include a substrate 410.
  • the substrate 410 may be a printed circuit board (PCB).
  • the substrate 410 may include cavities or through holes to receive or accommodate the chips 404a, 404b.
  • the chips 404a, 404b may be seated unobstructed.
  • the chips 402, 404a, 404b may be arranged over the substrate 410.
  • the substrate 410 may also include one or more electrical connections 412.
  • the redistribution layer 406 may include electrical lines 414.
  • the system 400 may also include a solder bump array connection including solder balls 416 joining the redistribution layer 406 to the substrate 410.
  • the one or more electrical connections 412 in the substrate 410 may be electrically connected to the first chip 402, the second chip 404a and/or the third chip 404b via electrical lines 414 in the redistribution layer 406 and via the solder bump array connection including solder balls 416.
  • Communication signals to or from the chips 402, 404a, 404b may be routed to external connections via the one or more electrical connections 412, the electrical lines 414 and the solder balls 416.
  • the system 400 may include power connections and ground connections to chips 402, 404a, 404b via the one or more electrical connections 412, the electrical lines 414 and the solder balls 416.
  • the communication signals, as well as the power connections and the ground connections may be routed through the center of the system 400 or to the side of the system 400.
  • the fan-out wafer level package (FOWLP) redistribution layer (RDL) 406 may be formed only on the top chip 402.
  • the bottom chips 404a, 404b may then be assembled directly on the bottom of the redistribution layer 406.
  • the redistribution layer 406 may provide the electrical connections 408a, 408b for internal electrical connections (chip to chip), as well as electrical lines 414 external electrical connections (various chips to the substrate).
  • the system 400 may include an encapsulation 420 covering at least a portion of the first chip 402.
  • the cavities in the substrate 410 may include a heat spreader and/or a heat conductive compound 418 (also referred to as thermal compound).
  • the heat spreader may include a thermally conductive material, e.g. a metal such as copper or aluminum.
  • the heat conductive compound may be an epoxy resin including thermally conductive materials such as metal or metal oxide particles.
  • the heat spreader and/or heat conductive compound 418 may be arranged at the bottom of the cavities so that heat may be dissipated from the backsides of the chips 404a, 404b through the heat spreader and/or heat conductive compound 418.
  • the heat conductive compound may provide physical contact between the chips 404a, 404b and the substrate 410 or the heat spreader.
  • FIG. 4D is a schematic showing the top view of the multi-chip system 400 according to various embodiments.
  • the system 400 may also include a fourth chip 404c and a fifth chip 404d.
  • the active surface of the fourth chip 404c and the active surface of the fifth chip 404d may also face the active surface of the first chip 404a.
  • the fourth chip 404c and the fifth chips may be HBM chips.
  • the redistribution layer 406 may extend between the first chip 402 and the fourth chip 404c, and between the first chip 402 and the fifth chip 404d.
  • FIG. 4A may correspond to the view across the dashed line as indicated in FIG. 4D.
  • the top chip 402 may be much larger than each of the bottom chips 404a-d arranged below the top chip 402.
  • the second chip 404a may be arranged below a first lateral side of the first chip 402
  • the third chip 404b may be arranged below a second lateral side of the first chip 402
  • the fourth chip 404c may be arranged below a third lateral side of the first chip 402
  • the fifth chip 404d may be arranged between a fourth lateral side of the first chip 402.
  • the center portion of the top chip 402 may not be obstructed by the bottom chips 404a- d so that electrical connection from the top chip 402 can be routed to the substrate 410 directly. Cavities may be formed in the substrate to accommodate bottom chips 404a-d.
  • FIG. 5A shows through via structures connecting a first chip 502 and a second chip 504 according to various embodiments.
  • a redistribution layer 506 may be between the first chip 502 and the second chip 504.
  • the through via structure may extend from a first surface of the redistribution layer 506 to a second surface of the redistribution layer 506 opposite the first surface.
  • the through via structure may include a plurality of micro vias 522a-c and a plurality of electrical interconnects 524a-d. As shown in FIG.
  • the through via structure may include a first electrical interconnect 524a, a first micro via 522a having a first end in contact with the first electrical interconnect 524a, a second electrical interconnect 524b in contact with a second end of the first micro via 522a, a second micro via 522b having a first end in contact with the second electrical interconnect 524b, a third electrical interconnect 524c in contact with a second end of the second micro via 522b, a third micro via 522c having a first end in contact with the third electrical interconnect 524c, and a fourth electrical interconnect 524d in contact with a second end of the third micro via 522c.
  • Electrical interconnects 524a, 524d may be or may include solder bumps and/or under-bump metallization (UBM), while electrical interconnects 524b, 524c may be signal pads or metal contacts.
  • UBM under-bump metallization
  • micro vias 522a, 522e may be aligned with each other, and micro via 522b may be laterally offset from micro vias 522a, 522c.
  • FIG. 5B shows through via structures connecting a first chip 502 and a second chip 504 according to various other embodiments. Similar to FIG. 5A, FIG. 5B shows the redistribution layer 506 between the first chip 502 and the second chip 504.
  • the through via structure may extend from a first surface of the redistribution layer 506 to a second surface of the redistribution layer 506 opposite the first surface.
  • the through via structure may include a plurality of micro vias 526a- c and a plurality of electrical interconnects 528a-d. As shown in FIG.
  • the through via structure may include a first electrical interconnect 528a, a first micro via 526a having a first end in contact with the first electrical interconnect 528a, a second electrical interconnect 528b in contact with a second end of the first micro via 526a, a second micro via 526b having a first end in contact with the second electrical interconnect 528b, a third electrical interconnect 528c in contact with a second end of the second micro via 526b, a third micro via 526c having a first end in contact with the third electrical interconnect 528c, and a fourth electrical interconnect 528d in contact with a second end of the third micro via 526c.
  • Electrical interconnects 528a, 528d may be or may include solder bumps and/or under-bump metallization (UBM), while electrical interconnects 528b, 528c may be signal pads or metal contacts.
  • UBM under-bump metallization
  • the micro vias 526a-c may be aligned with one another along a straight line.
  • FIG. 6 is a cross-sectional schematic of a portion of a multi-chip system according to various embodiments.
  • the system may include a first chip 602, a second chip 604, and a redistribution layer 606 between the first chip 602 and the second chip 604.
  • the redistribution layer 606 may include through via structures 608 configured to carry electrical signals between the first chip 602 and the second chip 604.
  • the through via structures 608 may extend from a first surface of the redistribution layer 606 to a second surface of the redistribution layer 606 opposite the first surface
  • the redistribution layer 606 may also include electromagnetic shielding structures 630.
  • the electromagnetic shielding structures 630 may define openings (along planes, e.g. planes 632a, 632b) for through via structures 608 to pass through).
  • the electromagnetic shielding structures 630 may be in electrical connection with electrical vias 634, which may be ground vias or power vias.
  • a ground via may be in or may be configured to be in electrical connection with an external ground line.
  • a power via may be in or may be configured to be in electrical connection with an external power line.
  • a ground via may be at about 0 V, and a power via may be at a suitable non-zero voltage.
  • FIG. 7 shows a schematic of a shielding plane of a multi-chip system according to various embodiments.
  • the shielding plane may be defined by the electromagnetic shielding structure 730.
  • the electromagnetic shielding structure 730 may be electrically connected to ground vias 734.
  • the electromagnetic shielding structure 730 may be at ground, and may be referred to as ground RDL.
  • the shielding plane may include openings for through via structures 708 carrying electrical signals to pass through.
  • the RDL may include one or more Power (PWR) and/or Ground (GND) planes with openings.
  • Each opening may include a signal pad (or metal contact) of the through via structure.
  • the opening may include a suitable dielectric material separating the signal pad/ signal via from the PWR plane or GND plane.
  • the Power (PWR) and/or Ground (GND) planes may act as electromagnetic shields for the signal vias.
  • FIG. 8 shows a schematic of another shielding plane of a multi-chip system according to various embodiments.
  • the shielding plane may include a first electromagnetic shielding structure 830a which may be electrically connected to power vias 834a, and a second electromagnetic shielding structure 830b which may be electrically connected to ground vias 834b.
  • the first electromagnetic shielding structure 830a and the second electromagnetic shielding structure 830b may be (electrically) disconnected.
  • the first electromagnetic shielding structure 830a may include openings for through via structures 808a to pass through, while the second electromagnetic shielding structure 830b may include openings for through via structures 808b to pass through.
  • FIG. 9 shows a schematic of yet another shielding plane of a multi-chip system according to various embodiments.
  • the shielding plane may include a first electromagnetic shielding structure 930a which may be electrically connected to power vias 934a, and a second electromagnetic shielding structure 930b which may be electrically connected to ground vias 934b.
  • the first electromagnetic shielding structure 930a and the second electromagnetic shielding structure 930b may be (electrically) disconnected.
  • the second electromagnetic shielding structure 930b may include openings. A first opening may only allow one through via structure 908a to pass through, while a second opening may allow two through via structures 908b to pass through.
  • each opening may allow only one through via structure to pass through. In various embodiments, each opening may allow a plurality of through via structures to pass through. Each opening may include a plurality of signal pads (or metal contacts).
  • a redistribution sub-layer of the RDL may be split to form a Power (PWR) plane and a Ground (GND) plane.
  • PWR Power
  • GND Ground
  • only one power (or ground) via may be required to connect to each of the power (or ground) plane for forming the electromagnetic shield.
  • the power via may be used for the electrical connection of the power planes of all redistribution sub-layers.
  • the ground via may be used for the electrical connection of the ground planes of all redistribution sub-layers.
  • FIG. 10A is a cross-sectional schematic of a portion of a multi-chip system according to various embodiments.
  • FIG. 10B is a schematic of a portion of the multi-chip system according to various embodiments that is used as the simulation model.
  • the electrical characteristic of the micro-via is simulated using the commercial three-dimensional electromagnetic (3D EM) simulator.
  • the system may include a first chip (top chip) 1002, a second chip (bottom chip) 1004, and a redistribution layer 1006 between the first chip 1002 and the second chip 1004.
  • the system may include through via structures 1008 extending from the first chip 1002 to the second chip 1004.
  • Each through via structure 1008 may include micro-vias 1022, as well as under-bump metallization (UBM) 1024a with solder bump structures 1024b, and signal pads 1024c with receiving pads 1024d.
  • UBM under-bump metallization
  • each solder bump structure 1024b may be set to 25 pm
  • the thickness of each UBM 1024a may be set to 5 pm
  • the thickness of each signal layer or metal pad 1024c may be set to 5 pm
  • the diameter of each receiving pad 1024d may be set to 20 pm.
  • Ground planes may be formed around the micro-vias 1022 on each layer, and the opening diameter may be set to 40 pm.
  • 4 through via structures 1008 and 4 ground vias 1034 at the sides may be modelled, as shown in FIG. 10B.
  • the metal layers 1024c of the through via structures 1008 may be electrically connected to the ground vias 1034. This may help to reduce the cross talk between the through via structures 1008.
  • FIG. IOC is a plot of insertion loss (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated insertion loss of the multi-chip system according to various embodiments shown in FIGS. 10A-B.
  • FIG. IOC shows that the through via structures 1008 have a insertion loss of less than 0.5dB up to 20GHz.
  • FIG. 10D is a plot of return loss (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated return loss of the multi-chip system according to various embodiments shown in FIGS. 10A-B.
  • FIG. 10D shows that the return loss is less than -28dB throughout the frequency range.
  • FIG. 10E is a plot of cross-talk (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated cross-talk of the multi-chip system according to various embodiments shown in FIGS. 10A-B.
  • the worst cross talk can from the adjacent channel and has a level of -25dB, as shown in FIG. 10E.
  • the cross talk performance may be further improved by designing a series of additional ground vias around the through via structures 1008. The number of additional ground vias which can be designed may be dependent on the process capability. Nevertheless, the simulated performance exceeds the requirement of the HBM and GPU communication requirement of 2Gbps per channel.
  • Micro-via direct connections between the top chip and the bottom chips may effectively overcome poor signal integrity and may reduce the process complexity.
  • the micro-via designs may operate beyond the frequency of 20GHz, and may hence extend the date rate of the communicating integrated chips (ICs). These designs may be applicable for current and future GPU/ASIC/SoC to HBM (top chip and bottom chip) integration or other applications which use wide input/output (I/O) connections.
  • multiple chips may be assembled on the both sides of the redistribution layer (RDL) without through mold interconnects/through mold vias (TMI/IMV), with partial overlapping of active surfaces.
  • the bottom chips may be extended to the sides beyond the top chip.
  • the top chip and the bottom chip may be aligned such that their connecting I/O are connected through a series of micro-vias, and each micro-via may be surrounded by connected multi-layer ground/power RDL.
  • the top and bottom chip may be connected using multiple micro-vias directly, with multi-layer ground/power ring formed by multilayer RDL shorted together.
  • no interposer or substrate may be between the top chip and the bottom chips.
  • only multi-layered RDL may be present between the top chip and the bottom chips.
  • only the top chip may be embedded/molded and may have the RDL. Multiple chips may be integrated below an embedded chip (with FOWLP). The multiple chips may be integrated face-to-face with the embedded chip. In order to implement face-to-face integration, the I/O design of the chip may be required to be reconfigured from two dimensional (2D) integration. As the I/O design of the memoty chips follows industry standards, the I/O of the GPU/SoC/ASIC chip may be designed to match the I/O of the memory chips. In various other embodiments, the top chip and the bottom chips may be molded.
  • both the top chip and the bottom chips may have their external I/Os routed through RDL to the external board or substrate directly.
  • the top chip and the bottom chips may have I/Os routed through back end-of-line (BEOL).
  • BEOL back end-of-line
  • the top chip may have its I/Os (usually power and ground) connected vertically at the centre to the package, without routing to the sides.
  • I/Os usually power and ground
  • one or more cavities or through openings may be made on the substrate or external board to accommodate the bottom chips so that the solder bumps can be used to connect the other I/O of the package without using TMI/TMV.
  • Heat spreaders may be formed or provided at the bottom of the one or more cavities to support the bottom chips.
  • Various embodiments may improve signal integrity. Various embodiments may lower loss. Various embodiments may reduce power consumption. Various embodiments may not require fine pitch and line width, which may reduce process complexity.
  • Various embodiments may find applications in high performance computers. Various embodiments may be used as GPU/ASIC and HBM connections.
  • Various embodiments may have good electrical performance. Various embodiments may reduce process complexity.

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Abstract

Various embodiments may provide a multi-chip system. The multi-chip system may include a first chip having an active surface. The multi-chip system may also include a second chip having an active surface facing the active surface of the first chip. The multi-chip system may additionally include a redistribution layer between the first chip and the second chip. The redistribution layer may include a dielectric material. The redistribution layer may also include a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip. The redistribution layer may additionally include an electromagnetic shield having an opening in which the through via structure passes through. The redistribution layer may further include an electrical via in electrical connection with the electromagnetic shield.

Description

MULTI-CHIP SYSTEM AND METHOD OF FORMING THE SAME
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of priority of Singapore application No. 10201810060V filed November 12, 2018, the contents of it being hereby incorporated by reference in its entirety for all purposes.
TECHNICAL FIELD
[0002] Various aspects of this disclosure relate to a multi-chip system. Various aspects of this disclosure relate to a method of forming a multi-chip system.
BACKGROUND
[0003] A conventional system having a High Bandwidth Memory (HBM) and Graphics Processing Unit (GPU) interface is a 2.5-dimension (2.5D) integrated system. FIG. 1 shows a schematic showing a conventional system having a High Bandwidth Memory (HBM) and Graphics Processing Unit (GPU)/ Application Specific Integrated Circuit (ASIC) Chip interface. As shown in FIG. 1, the HBM chips and the GPU/ASIC chip are assembled side-by-side. The HBM memory interface standard is developed based on wide input/output (I/O) with very fine pitch. Currently, it has 1024 data I/O width, with 25 pm diameter I/O micro bumps, and 55 pm minimum pitch. Due to this high density I/O connection, the line width is typically in the range of about 2 pm, and the spacing is typically about 4pm. In addition, the line length is about 6 mm . The long length and the narrow width of the line lead to high signal loss, while the narrow spacing leads to high signal interference. In addition, the narrow line width of 2 pm is the current minimum limit of several fabrication processes.
SUMMARY
[0004] Various embodiments may provide a multi-chip system. The multi-chip system may include a first chip having an active surface. The multi-chip system may also include a second chip having an active surface facing the active surface of the first chip. The multi-chip system may additionally include a redistribution layer between the first chip and the second chip. The redistribution layer may include a dielectric material. The redistribution layer may also include a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip. The redistribution layer may additionally include an electromagnetic shield having an opening in which the through via structure passes through. The redistribution layer may further include an electrical via in electrical connection with the electromagnetic shield. The multi-chip system may further include a solder bump array connection at a side of the redistribution layer as the second chip, the solder bump array connection configured to connect to a substrate or an external circuit and including a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip.
[0005] Various embodiments may provide a method of forming a multi-chip system. The method may include providing or forming a redistribution layer between a first chip and a second chip. The second chip may have an active surface facing an active surface of the first chip. The redistribution layer may include a dielectric material. The redistribution layer may also include a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip. The redistribution layer may further include an electromagnetic shield having an opening in which the through via structure passes through. An electrical via may be in electrical connection with the electromagnetic shield. The method may further include providing a solder bump array connection at a side of the redistribution layer as the second chip, the solder bump array connection configured to connect to a substrate or an external circuit and including a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The invention will be better understood with reference to the detailed description when considered in conjunction with the non-limiting examples and the accompanying drawings, in which: FIG. 1 shows a schematic showing a conventional system having a High Bandwidth Memory (HBM) and Graphics Processing Unit (GPU)/Application Specific Integrated Circuit (ASIC) Chip interface.
FIG. 2 is a general illustration of a multi-chip system according to various embodiments.
FIG. 3 is a general illustration of a method of forming a multi-chip system according to various embodiments.
FIG. 4A is a cross-sectional schematic of a multi-chip system according to various embodiments. FIG. 4B is another cross-sectional schematic showing part of the multi-chip system shown in FIG. 4A according to various embodiments.
FIG. 4C shows a magnification of a portion of the multi-chip system shown in FIG. 4A according to various embodiments.
FIG. 4D is a schematic showing the top view of the multi-chip system according to various embodiments.
FIG. 5A shows through via structures connecting a first chip and a second chip according to various embodiments.
FIG. 5B shows through via structures connecting a first chip and a second chip according to various other embodiments.
FIG. 6 is a cross-sectional schematic of a portion of a multi-chip system according to various embodiments.
FIG. 7 shows a schematic of a shielding plane of a multi-chip system according to various embodiments.
FIG. 8 shows a schematic of another shielding plane of a multi-chip system according to various embodiments.
FIG. 9 shows a schematic of yet another shielding plane of a multi-chip system according to various embodiments.
FIG. 10A is a cross-sectional schematic of a portion of a multi-chip system according to various embodiments.
FIG. 1 OB is a schematic of a portion of the multi-chip system according to various embodiments that is used as the simulation model. FIG. IOC is a plot of insertion loss (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated insertion loss of the multi-chip system according to various embodiments shown in FIGS. 10A-B.
FIG. 10D is a plot of return loss (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated return loss of the multi-chip system according to various embodiments shown in FIGS. 10A-B.
FIG. 10E is a plot of cross-talk (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated cross-talk of the multi-chip system according to various embodiments shown in FIGS. 10A-B.
DETAILED DESCRIPTION
[0007] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
[0008] Embodiments described in the context of one of the methods or multi-chip systems are analogously valid for the other methods or multi-chip systems. Similarly, embodiments described in the context of a method are analogously valid for a multi-chip system, and vice versa.
[0009] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.
[0010] In the context of various embodiments, the articles“a”,“an” and“the” as used with regard to a feature or element include a reference to one or more of the features or elements. [0011] In the context of various embodiments, the term“about” or“approximately” as applied to a numeric value encompasses the exact value and a reasonable variance.
[0012] As used herein, the term“and/or” includes any and all combinations of one or more of the associated listed items.
[0013] High Bandwidth Memory (HBM) is designed to meet the extreme high bandwidth dynamic random access memory (DRAM) requirement applications such as high performance Computing (HPC), Terabit Ethernet (TbE) and Graphics Processing Unit (GPU). Currently, the HBM and the Graphics Processing Unit (GPU)/Central Processing Unit (CPU)/Application Specific Integrated Circuit (ASIC)/System on Chip (SoC) are integrated laterally, and the typical interconnect length is about 8mm long. The fine width, fine spacing and long length lead to poor signal integrity and fabrication process challenges.
[0014] Various embodiments may seek to address or mitigate the high signal loss facing conventional systems. Various embodiments may address or mitigate the process complexity of conventional systems.
[0015] Instead of designing the wide I/O connections laterally, through vias (or 3D connections) including micro-vias may be designed, thus reducing the interconnection length. The vertical interconnections may mean that the system no longer require the fine line width and spacing of lateral wire connections. In this way, the electrical performance may be greatly improved. The process complexity may also be reduced as fine line width and spacing are no longer required. However, the through via design may still face with the issue of limited number of through mold interconnects/through mold vias (TMI TMV) to support the external electrical connections. In addition, TMI/TMV is a costly FOWLP process.
[0016] Various embodiments may relate to a system which uses a direct chip face-to-face connection using fan-out wafer level packaging (FOWLP) with only the top chip embedded. The system may be without TMI/TMV. The substrate/PCB may be formed with one or more openings to fit the bottom chips so that the external I/Os may be connected just by solder or micro bumps to the redistribution layer (RDL).
[0017] FIG. 2 is a general illustration of a multi-chip system 200 according to various embodiments. The multi-chip system 200 may include a first chip 202 having an active surface. The multi-chip system 200 may also include a second chip 204 having an active surface facing the active surface of the first chip 202. The multi-chip system 200 may additionally include a redistribution layer 206 between the first chip 202 and the second chip 204. The redistribution layer 206 may include a dielectric material. The redistribution layer 206 may also include a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip. The redistribution layer 206 may additionally include an electromagnetic shield having an opening in which the through via structure passes through. The redistribution layer 206 may further include an electrical via in electrical connection with the electromagnetic shield.
[0018] In other words, the multi-chip system 200 may include a redistribution layer 206 between a first chip 202 and a second chip 204. The redistribution layer 206 may include a through via structure pass through an opening of an electromagnetic shield of the redistribution layer 206.
[0019] In various embodiments, the electrical via may be a power (PWR) via. The electromagnetic shield connected to the power via may be referred to as a PWR plane or a RDL- PWR plane.
[0020] In various other embodiments, the electrical via may be a ground (GND) via. The electromagnetic shield connected to the ground via may be referred to as a GND plane or a RDL- GND plane.
[0021] The through via structure may extend from a first surface of the redistribution layer 206 to a second surface of the redistribution layer 206 opposite the first surface. The redistribution layer 206 may further include one or more additional through via structures extending from the first surface of the redistribution layer 206 to the second surface of the redistribution layer 206 opposite the first surface. Each through via structure may include one or more signal vias. The one or more signal vias may be micro vias. Each through via structure may also include one or more electrical interconnects, e.g. signal pads or metal contacts. An electrical interconnect may electrically connect a first signal via and a second signal via of the one or more signal vias.
[0022] The electromagnetic shield may form a shielding plane in the redistribution layer 206. In various embodiments, the redistribution layer 206 may include a suitable metal such as copper, gold, aluminum, or nickel.
[0023] An“active surface” as described herein may refer to a surface of a chip in which components such as transistors, diodes, capacitors, and/or other electrical components are formed. [0024] In various embodiments, the multi-chip system 200 may further include a solder bump array connection at a side of the redistribution layer 206 as the second chip 204, the solder bump array connection configured to connect to a substrate or an external circuit and including a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip. In other words, the second chip 204 and the solder bump array connection may be on a side of the redistribution layer 206, while the first chip 202 may be on an opposing side of the redistribution layer 206. In various embodiments, the multi-chip system 200 may include the substrate. The substrate may include one or more electrical connections. The first chip 202 and the second chip 204 may be over the substrate.
[0025] The redistribution layer 206 may further include one or more (first) interconnections configured to electrically connect the first chip with the one or more electrical connections of the substrate. The redistribution layer 206 may further include one or more (second) interconnections configured to electrically connect the second chip with the one or more electrical connections of the substrate.
[0026] In various embodiments, the substrate may include a cavity configured to receive the second chip 204. The cavity may also include a heat spreader or a heat conductive compound.
[0027] In various embodiments, the first chip 202 may be over or above the second chip 204.
[0028] In various embodiments, the through via structure may have a via on via design. The through via structure may include a plurality of signal vias aligned to form a straight line between the first chip 202 and the second chip 204. The straight line may be a vertical line between the first chip 202 and the second chip 204. The through via structure may also include a plurality of electrical interconnects. An electrical interconnect may have a first surface in contact with a first signal via and a second surface (opposite the first surface) in contact with a second signal via.
[0029] In various other embodiments, the through via structure may have an offset via design.The through via structure may include a first signal via, and a second signal via laterally offset from the first signal via. The redistribution layer 206 may further include an electrical interconnect in contact with the first signal via and the second signal via. The electrical interconnect may extend laterally between the first signal via and the second signal via. The electrical interconnect may electrically connect the first signal via and the second signal via. The first signal via may contact a first surface of the electrical interconnect, while the second signal via may contact a second surface of the electrical interconnect opposite the first suface.
[0030] In various embodiments, the first chip may be any one chip selected from a group consisting of a graphic processing unit (GPU) chip, a processor chip such as a central processing unit (CPU) chip, an application specific integrated circuit (ASIC) chip, and a system on chip (SoC). In various embodiments, the second chip may be a High Bandwidth Memory (HDM) chip, a Hybrid Memory Cube (HMC) chip, or a high density input/output (I/O) chip.
[0031 ] In various embodiments, a chip area of the first chip 202 may be greater than a chip area of the second chip 204. Accordingly, the electrical connections in the redistibution layer 206 from connections of the first chip 202 to the substrate may be formed around the bottom second chip 204.
[0032] In various embodiments, the multi-chip system may include a third chip. The third chip may be lateral to the second chip 204. The redistribution layer 206 may also be between the first chip 202 and the third chip. The second chip 204 and the third chip may be on the same side of the redistribution layer 206. The first chip 202 may be on an opposing side of the redistribution layer 206 as the second chip 204 or the third chip. The third chip may have an active surface facing the active surface of the first chip.
[0033] The redistribution layer 206 may include a further through via structure configured to carry a further electrical signal between the first chip and the third chip.
[0034] The further through via structure may extend from a first surface of the redistribution layer 206 to a second surface of the redistribution layer 206 opposite the first surface. The redistribution layer 206 may further include one or more additional further through via structures extending from the first surface of the redistribution layer 206 to the second surface of the redistribution layer 206 opposite the first surface. Each further through via structure may include one or more further signal vias. The one or more further signal vias may be micro vias. Each through via structure may also include one or more further electrical interconnects, e.g. signal pads or metal contacts. A further electrical interconnect may electrically connect a further first signal via and a second further signal via of the one or more further signal vias.
[0035] In various embodiments, the further through via structure may include a plurality of further signal vias aligned to form a straight line between the first chip 202 and the third chip. In various other embodiments, the further through via structure may include a further first signal via, and a further second signal via laterally offset from the further first signal via.
[0036] The third chip may be a High Bandwidth Memory (HDM) chip, a Hybrid Memory Cube (HMC) chip, or a high density input/output (I/O) chip. A chip area of the first chip 202 may be greater than a chip area of the third chip.
[0037] In various embodiments, the multi-chip system may further include one or more additional chips. The one or more additional chips may each have an active surface facing the first chip 202, and may be on the same side of the redistribution layer 206 as the second chip 204 and the third chip. In other words, the second chip 204, the third chip, and the one or more additional chips may be on a side of the redistribution layer 206, while the first chip 202 may be on an opposing side of the redistribution layer 206. The redistribution layer 206 may also be between the first chip 202 and each of the one or more additional chips. Each of the one or more additional chips may be a High Bandwidth Memory (HDM) chip, a Hybrid Memory Cube (HMC) chip, or a high density input/output (I/O) chip. The multi-chip system 200 may also be referred to as a multi chip package. The through via structure may alternatively be referred to as a through via, and the further through via structure may alternatively be referred to as a further through via.
[0038] FIG. 3 is a general illustration of a method of forming a multi-chip system according to various embodiments. The method may include, in 302, providing or forming a redistribution layer between a first chip and a second chip. The second chip may have an active surface facing an active surface of the first chip. The redistribution layer may include a dielectric material. The redistribution layer may also include a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip. The redistribution layer may further include an electromagnetic shield having an opening in which the through via structure passes through. An electrical via may be in electrical connection with the electromagnetic shield.
[0039] In other words, the method may include providing or forming a redistribution layer between a first chip and a second chip. The redistribution layer may include an electromagnetic shield having an opening for a through via structure carrying electrical signals between the first chip and the second chip to pass through. [0040] In various embodiments, the first chip may be above or over the second chip. The redistribution layer may be formed on the first chip before arranging the second chip so that the first chip is above the second chip, and the redistribution layer is between the first chip and the second chip.
[0041 ] In various embodiments, the method may further include providing a solder bump array connection at a side of the redistribution layer as the second chip, the solder bump array connection configured to connect to a substrate or an external circuit and including a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip. In various embodiments, the method may include providing or forming the substrate. The substrate may include one or more electrical connections. The first chip and the second chip may be over the substrate. The method may include arranging a substrate such that the first chip and the second chip are over the substrate.
[0042] In various embodiments, the method may include providing a third chip. The redistribution layer may be also between the first chip and the third chip. The method may include arranging a third chip such that the redistribution layer is between the first chip and the third chip. The third chip may also be arranged over the substrate. The redistribution layer may include a further through via structure configured to carry a further electrical signal between the first chip and the third chip. In various embodiments, the method may include providing one or more additional chips. The method may include arranging the one or more additional chips such that the redistribution layer is between the first chip and each of the one or more additional chips.
[0043] FIG. 4A is a cross-sectional schematic of a multi-chip system 400 according to various embodiments. FIG. 4B is another cross-sectional schematic showing part of the multi-chip system 400 shown in FIG. 4A according to various embodiments. FIG. 4C shows a magnification of a portion of the multi-chip system 400 shown in FIG. 4A according to various embodiments. In order to address the poor signal quality and fabrication process difficulties associated with conventional systems, various embodiments may utilize a 3D integration for the HBM and the GPU/ASIC/CPU/SoC chips. As shown in FIGS.4A-C, the system 400 (also referred to as package) may include a first chip 402, which may be a GPU/ASIC/CPU/SoC chip. The system 400 may also include a second chip 404a, which may be a HBM chip, and a third chip 404b which may be a further HBM chip. The system 400 may further include a redistribution layer 406 extending between the first chip 402 and the second chip 404a, and extending between the first chip 402 and the third chip 404b. The redistribution layer 406 may include a dielectric material. The redistribution layer 406 may also include through via structures 408a electrically connecting the first chip 402 and the second chip 404a, as well as further through via structures 408b electrically connecting the first chip 402 and the third chip 404b. Each through via structure 408a may include a plurality of signal vias, and each further through via structure 408b may include a plurality of further signal vias.
[0044] The GPU/ASIC/CPU/SoC chip 402 and the HBM chips 404a, 404b may be assembled faee to face so that the signal input/outputs, i.e. signals vias and further signal vias may be vertically aligned as shown in FIGS. 4A-C. The signals vias may extend from a first surface of the redistribution layer 406 to a second surface of the redistribution layer 406 opposite the first surface to connect the first chip 402 and the second chip 404a. Likewise, the further signals vias may extend from the first surface of the redistribution layer 406 to the second surface of the redistribution layer 406 to connect the first chip 402 and the third chip 404b. The signal vias and the further signal vias may be micro-vias. In order to achieve vertical alignment, the I/O positions of the chips 402, 404a-b and design may be required to be matched. For the targeted application of the memory integration, the memory I/O configuration may be set by industry standards under JEDEC (Joint Electron Device Engineering Council). Flence, the I/O positions of the GPU/ASIC/CPU/SoC chip 402 may be required to be designed for matching with the I/O configuration of the memory chips 404a-b.
[0045] The system 400 may further include a substrate 410. The substrate 410 may be a printed circuit board (PCB). The substrate 410 may include cavities or through holes to receive or accommodate the chips 404a, 404b. The chips 404a, 404b may be seated unobstructed. The chips 402, 404a, 404b may be arranged over the substrate 410. The substrate 410 may also include one or more electrical connections 412. The redistribution layer 406 may include electrical lines 414. The system 400 may also include a solder bump array connection including solder balls 416 joining the redistribution layer 406 to the substrate 410. The one or more electrical connections 412 in the substrate 410 may be electrically connected to the first chip 402, the second chip 404a and/or the third chip 404b via electrical lines 414 in the redistribution layer 406 and via the solder bump array connection including solder balls 416. Communication signals to or from the chips 402, 404a, 404b may be routed to external connections via the one or more electrical connections 412, the electrical lines 414 and the solder balls 416. Additionally, the system 400 may include power connections and ground connections to chips 402, 404a, 404b via the one or more electrical connections 412, the electrical lines 414 and the solder balls 416. The communication signals, as well as the power connections and the ground connections may be routed through the center of the system 400 or to the side of the system 400.
[0046] In various embodiments, the fan-out wafer level package (FOWLP) redistribution layer (RDL) 406 may be formed only on the top chip 402. The bottom chips 404a, 404b may then be assembled directly on the bottom of the redistribution layer 406. The redistribution layer 406 may provide the electrical connections 408a, 408b for internal electrical connections (chip to chip), as well as electrical lines 414 external electrical connections (various chips to the substrate).
[0047] In various embodiments, the system 400 may include an encapsulation 420 covering at least a portion of the first chip 402.
[0048] The cavities in the substrate 410 may include a heat spreader and/or a heat conductive compound 418 (also referred to as thermal compound). The heat spreader may include a thermally conductive material, e.g. a metal such as copper or aluminum. The heat conductive compound may be an epoxy resin including thermally conductive materials such as metal or metal oxide particles. The heat spreader and/or heat conductive compound 418 may be arranged at the bottom of the cavities so that heat may be dissipated from the backsides of the chips 404a, 404b through the heat spreader and/or heat conductive compound 418. The heat conductive compound may provide physical contact between the chips 404a, 404b and the substrate 410 or the heat spreader.
[0049] FIG. 4D is a schematic showing the top view of the multi-chip system 400 according to various embodiments. In various embodiments, the system 400 may also include a fourth chip 404c and a fifth chip 404d. The active surface of the fourth chip 404c and the active surface of the fifth chip 404d may also face the active surface of the first chip 404a. The fourth chip 404c and the fifth chips may be HBM chips. The redistribution layer 406 may extend between the first chip 402 and the fourth chip 404c, and between the first chip 402 and the fifth chip 404d. FIG. 4A may correspond to the view across the dashed line as indicated in FIG. 4D.
[0050] The top chip 402 may be much larger than each of the bottom chips 404a-d arranged below the top chip 402. As seen from FIG. 4D, the second chip 404a may be arranged below a first lateral side of the first chip 402, the third chip 404b may be arranged below a second lateral side of the first chip 402, the fourth chip 404c may be arranged below a third lateral side of the first chip 402, and the fifth chip 404d may be arranged between a fourth lateral side of the first chip 402.
[0051] The center portion of the top chip 402 may not be obstructed by the bottom chips 404a- d so that electrical connection from the top chip 402 can be routed to the substrate 410 directly. Cavities may be formed in the substrate to accommodate bottom chips 404a-d.
[0052] FIG. 5A shows through via structures connecting a first chip 502 and a second chip 504 according to various embodiments. A redistribution layer 506 may be between the first chip 502 and the second chip 504. The through via structure may extend from a first surface of the redistribution layer 506 to a second surface of the redistribution layer 506 opposite the first surface. The through via structure may include a plurality of micro vias 522a-c and a plurality of electrical interconnects 524a-d. As shown in FIG. 5A, the through via structure may include a first electrical interconnect 524a, a first micro via 522a having a first end in contact with the first electrical interconnect 524a, a second electrical interconnect 524b in contact with a second end of the first micro via 522a, a second micro via 522b having a first end in contact with the second electrical interconnect 524b, a third electrical interconnect 524c in contact with a second end of the second micro via 522b, a third micro via 522c having a first end in contact with the third electrical interconnect 524c, and a fourth electrical interconnect 524d in contact with a second end of the third micro via 522c. Electrical interconnects 524a, 524d may be or may include solder bumps and/or under-bump metallization (UBM), while electrical interconnects 524b, 524c may be signal pads or metal contacts.
[0053] As shown in FIG. 5A, micro vias 522a, 522e may be aligned with each other, and micro via 522b may be laterally offset from micro vias 522a, 522c.
[0054] FIG. 5B shows through via structures connecting a first chip 502 and a second chip 504 according to various other embodiments. Similar to FIG. 5A, FIG. 5B shows the redistribution layer 506 between the first chip 502 and the second chip 504. The through via structure may extend from a first surface of the redistribution layer 506 to a second surface of the redistribution layer 506 opposite the first surface. The through via structure may include a plurality of micro vias 526a- c and a plurality of electrical interconnects 528a-d. As shown in FIG. 5B, the through via structure may include a first electrical interconnect 528a, a first micro via 526a having a first end in contact with the first electrical interconnect 528a, a second electrical interconnect 528b in contact with a second end of the first micro via 526a, a second micro via 526b having a first end in contact with the second electrical interconnect 528b, a third electrical interconnect 528c in contact with a second end of the second micro via 526b, a third micro via 526c having a first end in contact with the third electrical interconnect 528c, and a fourth electrical interconnect 528d in contact with a second end of the third micro via 526c. Electrical interconnects 528a, 528d may be or may include solder bumps and/or under-bump metallization (UBM), while electrical interconnects 528b, 528c may be signal pads or metal contacts.
[0055] As shown in FIG. 5B, the micro vias 526a-c may be aligned with one another along a straight line.
[0056] FIG. 6 is a cross-sectional schematic of a portion of a multi-chip system according to various embodiments. The system may include a first chip 602, a second chip 604, and a redistribution layer 606 between the first chip 602 and the second chip 604. The redistribution layer 606 may include through via structures 608 configured to carry electrical signals between the first chip 602 and the second chip 604. The through via structures 608 may extend from a first surface of the redistribution layer 606 to a second surface of the redistribution layer 606 opposite the first surface
[0057] The redistribution layer 606 may also include electromagnetic shielding structures 630. The electromagnetic shielding structures 630 may define openings (along planes, e.g. planes 632a, 632b) for through via structures 608 to pass through). The electromagnetic shielding structures 630 may be in electrical connection with electrical vias 634, which may be ground vias or power vias. A ground via may be in or may be configured to be in electrical connection with an external ground line. Conversely, a power via may be in or may be configured to be in electrical connection with an external power line. A ground via may be at about 0 V, and a power via may be at a suitable non-zero voltage.
[0058] FIG. 7 shows a schematic of a shielding plane of a multi-chip system according to various embodiments. The shielding plane may be defined by the electromagnetic shielding structure 730. The electromagnetic shielding structure 730 may be electrically connected to ground vias 734. As such, the electromagnetic shielding structure 730 may be at ground, and may be referred to as ground RDL. The shielding plane may include openings for through via structures 708 carrying electrical signals to pass through.
[0059] In various embodiments, the RDL may include one or more Power (PWR) and/or Ground (GND) planes with openings. Each opening may include a signal pad (or metal contact) of the through via structure. The opening may include a suitable dielectric material separating the signal pad/ signal via from the PWR plane or GND plane. The Power (PWR) and/or Ground (GND) planes may act as electromagnetic shields for the signal vias.
[0060] FIG. 8 shows a schematic of another shielding plane of a multi-chip system according to various embodiments. The shielding plane may include a first electromagnetic shielding structure 830a which may be electrically connected to power vias 834a, and a second electromagnetic shielding structure 830b which may be electrically connected to ground vias 834b. The first electromagnetic shielding structure 830a and the second electromagnetic shielding structure 830b may be (electrically) disconnected. The first electromagnetic shielding structure 830a may include openings for through via structures 808a to pass through, while the second electromagnetic shielding structure 830b may include openings for through via structures 808b to pass through.
[0061] FIG. 9 shows a schematic of yet another shielding plane of a multi-chip system according to various embodiments. The shielding plane may include a first electromagnetic shielding structure 930a which may be electrically connected to power vias 934a, and a second electromagnetic shielding structure 930b which may be electrically connected to ground vias 934b. The first electromagnetic shielding structure 930a and the second electromagnetic shielding structure 930b may be (electrically) disconnected. The second electromagnetic shielding structure 930b may include openings. A first opening may only allow one through via structure 908a to pass through, while a second opening may allow two through via structures 908b to pass through.
[0062] In various embodiments, each opening may allow only one through via structure to pass through. In various embodiments, each opening may allow a plurality of through via structures to pass through. Each opening may include a plurality of signal pads (or metal contacts).
[0063] In various embodiments, a redistribution sub-layer of the RDL may be split to form a Power (PWR) plane and a Ground (GND) plane. In various embodiments, only one power (or ground) via may be required to connect to each of the power (or ground) plane for forming the electromagnetic shield.
[0064] The power via may be used for the electrical connection of the power planes of all redistribution sub-layers. The ground via may be used for the electrical connection of the ground planes of all redistribution sub-layers.
[0065] FIG. 10A is a cross-sectional schematic of a portion of a multi-chip system according to various embodiments. FIG. 10B is a schematic of a portion of the multi-chip system according to various embodiments that is used as the simulation model. The electrical characteristic of the micro-via is simulated using the commercial three-dimensional electromagnetic (3D EM) simulator.
[0066] The system may include a first chip (top chip) 1002, a second chip (bottom chip) 1004, and a redistribution layer 1006 between the first chip 1002 and the second chip 1004. The system may include through via structures 1008 extending from the first chip 1002 to the second chip 1004.
[0067] Each through via structure 1008 may include micro-vias 1022, as well as under-bump metallization (UBM) 1024a with solder bump structures 1024b, and signal pads 1024c with receiving pads 1024d.
[0068] The diameter of each solder bump structure 1024b may be set to 25 pm, the thickness of each UBM 1024a may be set to 5 pm, the thickness of each signal layer or metal pad 1024c may be set to 5 pm, and the diameter of each receiving pad 1024d may be set to 20 pm.
[0069] Ground planes may be formed around the micro-vias 1022 on each layer, and the opening diameter may be set to 40 pm. For the simulation setup, 4 through via structures 1008 and 4 ground vias 1034 at the sides may be modelled, as shown in FIG. 10B. The metal layers 1024c of the through via structures 1008 may be electrically connected to the ground vias 1034. This may help to reduce the cross talk between the through via structures 1008.
[0070] FIG. IOC is a plot of insertion loss (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated insertion loss of the multi-chip system according to various embodiments shown in FIGS. 10A-B. FIG. IOC shows that the through via structures 1008 have a insertion loss of less than 0.5dB up to 20GHz. [0071] FIG. 10D is a plot of return loss (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated return loss of the multi-chip system according to various embodiments shown in FIGS. 10A-B. FIG. 10D shows that the return loss is less than -28dB throughout the frequency range.
[0072] FIG. 10E is a plot of cross-talk (in decibels or dB) as a function of frequency (in gigahertz or GHz) showing the simulated cross-talk of the multi-chip system according to various embodiments shown in FIGS. 10A-B. The worst cross talk can from the adjacent channel and has a level of -25dB, as shown in FIG. 10E. The cross talk performance may be further improved by designing a series of additional ground vias around the through via structures 1008. The number of additional ground vias which can be designed may be dependent on the process capability. Nevertheless, the simulated performance exceeds the requirement of the HBM and GPU communication requirement of 2Gbps per channel.
[0073] Micro-via direct connections between the top chip and the bottom chips may effectively overcome poor signal integrity and may reduce the process complexity. The micro-via designs may operate beyond the frequency of 20GHz, and may hence extend the date rate of the communicating integrated chips (ICs). These designs may be applicable for current and future GPU/ASIC/SoC to HBM (top chip and bottom chip) integration or other applications which use wide input/output (I/O) connections.
[0074] In various embodiments, multiple chips may be assembled on the both sides of the redistribution layer (RDL) without through mold interconnects/through mold vias (TMI/IMV), with partial overlapping of active surfaces. The bottom chips may be extended to the sides beyond the top chip.
[0075] In various embodiments, the top chip and the bottom chip may be aligned such that their connecting I/O are connected through a series of micro-vias, and each micro-via may be surrounded by connected multi-layer ground/power RDL. The top and bottom chip may be connected using multiple micro-vias directly, with multi-layer ground/power ring formed by multilayer RDL shorted together.
[0076] In various embodiments, no interposer or substrate may be between the top chip and the bottom chips. In various embodiments, only multi-layered RDL may be present between the top chip and the bottom chips. [0077] In various embodiments, only the top chip may be embedded/molded and may have the RDL. Multiple chips may be integrated below an embedded chip (with FOWLP). The multiple chips may be integrated face-to-face with the embedded chip. In order to implement face-to-face integration, the I/O design of the chip may be required to be reconfigured from two dimensional (2D) integration. As the I/O design of the memoty chips follows industry standards, the I/O of the GPU/SoC/ASIC chip may be designed to match the I/O of the memory chips. In various other embodiments, the top chip and the bottom chips may be molded.
[0078] In various embodiments, both the top chip and the bottom chips may have their external I/Os routed through RDL to the external board or substrate directly. In various embodiments, the top chip and the bottom chips may have I/Os routed through back end-of-line (BEOL).
[0079] In various embodiments, the top chip may have its I/Os (usually power and ground) connected vertically at the centre to the package, without routing to the sides.
[0080] In various embodiments, one or more cavities or through openings may be made on the substrate or external board to accommodate the bottom chips so that the solder bumps can be used to connect the other I/O of the package without using TMI/TMV. Heat spreaders may be formed or provided at the bottom of the one or more cavities to support the bottom chips.
[0081] Various embodiments may improve signal integrity. Various embodiments may lower loss. Various embodiments may reduce power consumption. Various embodiments may not require fine pitch and line width, which may reduce process complexity.
[0082] Various embodiments may find applications in high performance computers. Various embodiments may be used as GPU/ASIC and HBM connections.
[0083] Various embodiments may have good electrical performance. Various embodiments may reduce process complexity.
[0084] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

1. A multi-chip system comprising:
a first chip having an active surface;
a second chip having an active surface facing the active surface of the first chip; and
a redistribution layer between the first chip and the second chip;
wherein the redistribution layer comprises:
a dielectric material;
a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip;
an electromagnetic shield having an opening in which the through via structure passes through;
an electrical via in electrical connection with the electromagnetic shield; and
a solder bump array connection at a side of the redistribution layer as the second chip, the solder bump array connection configured to connect to a substrate or an external circuit and comprising a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip.
2. The multi-chip system according to claim 1,
wherein the electrical via is a power via.
3. The multi-chip system according to claim 1,
wherein the electrical via is a ground via.
4. The multi-chip system according to claim 1, further comprising:
the substrate;
wherein the substrate includes one or more electrical connections; and wherein the first chip and the second chip are over the substrate.
5. The multi-chip system according to claim 4,
wherein the redistribution layer further comprises one or more interconnections configured to electrically connect the first chip with the one or more electrical connections of the substrate; and
wherein the redistribution layer further comprises one or more interconnections configured to electrically connect the second chip with the one or more electrical connections of the substrate.
6. The multi-chip system according to claim 4,
wherein the substrate includes a cavity configured to receive the second chip.
7. The multi-chip system according to claim 6,
wherein the cavity includes a heat spreader or a heat conductive compound.
8. The multi-chip system according to claim 1,
wherein the through via structure comprises a plurality of signal vias aligned to form a vertical line between the first chip and the second chip.
9. The multi-chip system according to claim 1,
wherein the through via structure comprises a first signal via, and a second signal via laterally offset from the first signal via; and
wherein the redistribution layer further comprises an electrical interconnect in contact with the first signal via and the second signal via.
10. The multi-chip system according to claim 1,
wherein the first chip is above the second chip.
11. The multi-chip system according to claim 1,
wherein first chip is any one chip selected from a group consisting of a graphic processing unit (GPU) chip, an application specific integrated circuit (ASIC) chip, a processor chip, and a system on chip (SoC).
12. The multi-chip system according to claim 1,
wherein the second chip is a High Bandwidth Memory (HDM) chip, a Hybrid Memory Cube (HMC) chip, or a high density input/output (I/O) chip.
13. The multi-chip system according to claim 1,
wherein a chip area of the first chip is greater than a chip area of the second chip.
14. The multi-chip system according to claim 1, further comprising:
a third chip;
wherein the redistribution layer is also between the first chip and the third chip.
15. The multi-chip system according to claim 14,
wherein the redistribution layer comprises a further through via structure configured to carry a further electrical signal between the first chip and the third chip.
16. A method of forming a multi-chip system, the method comprising:
providing a redistribution layer between a first chip and a second chip, the second chip having an active surface facing an active surface of the first chip; wherein the redistribution layer comprises:
a dielectric material; a through via structure at least partially covered by the dielectric material, the through via structure configured to carry an electrical signal between the first chip and the second chip;
an electromagnetic shield having an opening in which the through via structure passes through; and
an electrical via in electrical connection with the electromagnetic shield; and
wherein the method further comprises providing a solder bump array connection at a side of the redistribution layer as the second chip, the solder bump array connection configured to connect to a substrate or an external circuit and comprising a plurality of solder bumps, each of the plurality of solder bumps having a diameter or a height smaller than a height of the second chip.
17. The method according to claim 16,
wherein the first chip is above the second chip; and
wherein the redistribution layer is formed on the first chip before arranging the second chip so that the first chip is above the second chip, and the redistribution layer is between the first chip and the second chip.
18. The method according to claim 16, further comprising:
providing a substrate;
wherein the substrate includes one or more electrical connections; and wherein the first chip and the second chip are over the substrate.
19. The method according to claim 16, further comprising:
providing a third chip;
wherein the redistribution layer is also between the first chip and the third chip.
20. The method according to claim 16, wherein the redistribution layer comprises a further through via structure configured to carry a further electrical signal between the first chip and the third chip.
PCT/SG2019/050553 2018-11-12 2019-11-11 Multi-chip system and method of forming the same WO2020101572A1 (en)

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