WO2019105085A1

WO2019105085A1 - Heterojunction solar cell and method for fabrication thereof

Info

Publication number: WO2019105085A1
Application number: PCT/CN2018/103606
Authority: WO
Inventors: 杨苗; 郁操; 徐希翔
Original assignee: 君泰创新（北京）科技有限公司
Priority date: 2017-11-30
Filing date: 2018-08-31
Publication date: 2019-06-06
Also published as: CN108110079A

Abstract

Provided are a heterojunction solar cell and a method for fabrication thereof; said cell comprises a crystalline silicon substrate, the front side of the crystalline silicon substrate is provided with a first intrinsic layer; the first intrinsic layer is provided with a first n-type doped layer and a first p-type doped layer; the first n-type doped layer is provided with a first negative electrode, and the first p-type doped layer is provided with a first positive electrode; the reverse side of the crystalline silicon substrate is provided with a second intrinsic layer; the second intrinsic layer is provided with a second n-type doped layer and a second p-type doped layer; the second n-type doped layer is provided with a second negative electrode, and the second p-type doped layer is provided with a second positive electrode.

Description

Heterojunction solar cell and preparation method thereof

Technical field

The present application relates to, but is not limited to, the field of solar cell technology, and in particular, but not limited to, a heterojunction solar cell and a method of fabricating the same.

Background technique

Silicon-based heterojunction solar cells have excellent power generation performance. Existing silicon-based heterojunction solar cells are usually composed of a plurality of battery chips connected in series, and adjacent battery chips are connected in series by a solder ribbon.

Summary of invention

The following is an overview of the topics detailed in this article. This Summary is not intended to limit the scope of the claims.

The application provides a heterojunction solar cell, the heterojunction solar cell comprising:

Crystalline silicon substrate;

The front surface of the crystalline silicon substrate is provided with a first intrinsic layer;

a first N-type doped layer and a first P-type doped layer are disposed on the first intrinsic layer; a first negative electrode is disposed on the first N-type doped layer, and the first P-type doped a first positive electrode is disposed on the impurity layer;

a second intrinsic layer is disposed on a reverse side of the crystalline silicon substrate;

a second N-type doped layer and a second P-type doped layer are disposed on the second intrinsic layer; a second negative electrode is disposed on the second N-type doped layer, and the second P-type doped A second positive electrode is disposed on the hybrid layer.

The present application provides a method for preparing a heterojunction solar cell, the method comprising the following steps:

Depositing a first intrinsic layer and a second intrinsic layer on the front side and the back side of the crystalline silicon substrate;

Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic layer of the front surface of the crystalline silicon substrate, the second intrinsic on the opposite side of the crystalline silicon substrate Depositing a second N-type doped layer and a second P-type doped layer on the layer;

An electrode is formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

BRIEF abstract

The drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, which is used together with the embodiments of the present application to explain the technical solutions of the present application, and does not constitute a limitation of the technical solutions of the present application.

1 is a schematic structural view of a heterojunction solar cell according to an embodiment of the present application;

2 is a schematic view of two heterojunction solar cells provided in an embodiment of the present application in series;

3 is a flow chart of a method for preparing a heterojunction solar cell according to an embodiment of the present application.

Description of the reference signs:

10-first battery chip 20-second battery chip

30-weld tape 100-crystalline silicon substrate

110-first intrinsic amorphous silicon layer 120-second intrinsic amorphous silicon layer

200-first N-type amorphous silicon layer 300-first P-type amorphous silicon layer

400-second N-type amorphous silicon layer 500-second P-type amorphous silicon layer

600-first transparent conductive layer 700-second transparent conductive layer

40-first negative electrode 50-first positive electrode

60-second positive electrode 70-second negative electrode

Detailed

The embodiments of the present application are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are intended to be illustrative only, and are not to be construed as limiting.

Since the positive and negative electrodes on the existing battery chip are respectively disposed on the front and back sides of the battery chip, when two adjacent battery chips are arranged, the positive electrode of one battery chip is above the battery chip, and the negative electrode of the other battery chip is at the battery chip. Below, when two battery chips need to be connected in series by a solder ribbon, one end of the solder ribbon needs to be connected to the positive pole of one battery chip, and the other end of the solder ribbon needs to be connected to the negative pole of the battery chip, then the solder ribbon is on the two battery chips. The position may be bent, which may easily cause chipping of the battery chip; and in order to be able to connect the opposite poles on the two battery chips, the size of the ribbon is required to be long, which undoubtedly increases the resistance of the ribbon, resulting in The power generation capacity of the assembled heterojunction solar cell is weakened.

The embodiment of the present application provides a heterojunction solar cell and a preparation method thereof, which reduce the series resistance and improve the conversion efficiency of the photovoltaic module.

The embodiment of the present application provides a heterojunction solar cell, and the heterojunction solar cell includes:

Crystalline silicon substrate;

In the embodiment of the present application, the first N-type doped layer and the first P-type doped layer may be insulated from each other; the second N-type doped layer and the second P-type doped layer may be The insulation can be set between the two.

In the embodiment of the present application, the first N-type doped layer and the second P-type doped layer correspond to positions on the front side and the back side of the crystalline silicon substrate, and the first P-type doped layer and The positions of the second N-type doped layer on the front and back sides of the crystalline silicon substrate are corresponding.

In the embodiment of the present application, the heterojunction solar cell may further include:

a first transparent conductive layer disposed on the first N-type doped layer and the first P-type doped layer;

a second transparent conductive layer disposed on the second N-type doped layer and the second P-type doped layer;

The first negative electrode and the first positive electrode are both disposed on the first transparent conductive layer;

The second negative electrode and the second positive electrode are both disposed on the second transparent conductive layer.

In an embodiment of the present application, the first negative electrode and the first positive electrode or between the second negative electrode and the second positive electrode may be connected by a solder ribbon.

In an embodiment of the present application, an edge of the first N-type doping layer and an edge of the second P-type doped layer may be aligned in a direction perpendicular to the crystalline silicon substrate; the first P-type The edges of the doped layer and the edges of the second N-type doped layer may be aligned in a direction perpendicular to the crystalline silicon substrate.

In an embodiment of the present application, the first positive electrode, the first negative electrode, the second positive electrode, and the second negative electrode may each include a fine gate line and a main gate line.

In the embodiment of the present application, the diameter of the fine grid line may range from 20 μ to 60 μm.

In the embodiment of the present application, optionally, the number of the main gate lines is 2 to 6.

In the embodiment of the present application, the first intrinsic layer and the second intrinsic layer may be intrinsic amorphous silicon layers.

In the embodiment of the present application, the first P-type doped layer and the second P-type doped layer may be a P-type amorphous silicon layer, a P-type polysilicon layer, or a P-type microcrystalline silicon layer.

In the embodiment of the present application, the first N-type doped layer and the second N-type doped layer may be an N-type amorphous silicon layer, an N-type polysilicon layer, or an N-type microcrystalline silicon layer.

The embodiment of the present application further provides a method for preparing a heterojunction solar cell, and the method includes the following steps:

In an embodiment of the present application, the method may further include: after depositing the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer, Before the electrodes are formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer,

Depositing a transparent conductive layer on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer, respectively;

An electrode is then formed on the transparent conductive layer.

In the embodiment of the present application, a first N-type doped layer and a first P-type doped layer are respectively deposited on the first intrinsic doped layer on the front surface of the crystalline silicon substrate, where the crystalline silicon substrate is deposited Depositing the second N-type doped layer and the second P-type doped layer respectively on the second intrinsic doped layer on the reverse side may include:

Depositing a first N-type doped layer on the first intrinsic doped layer of the front side of the crystalline silicon substrate;

Depositing a second N-type doped layer on the second intrinsic doped layer on the reverse side of the crystalline silicon substrate;

Depositing a first P-type doped layer on the first intrinsic doped layer of the front side of the crystalline silicon substrate;

A second P-type doped layer is deposited on the second intrinsic doped layer on the reverse side of the crystalline silicon substrate.

Masking a portion of the first intrinsic doped layer on the front surface of the crystalline silicon substrate other than the region for depositing the first N-type doped layer;

Depositing the first N-type doped layer on a region of the first intrinsic doped layer on the front side of the crystalline silicon substrate for depositing the first N-type doped layer;

Masking a portion of the second intrinsic doped layer on the opposite side of the crystalline silicon substrate other than the region for depositing the second N-type doped layer;

Depositing the second N-type doped layer on a region of the second intrinsic doped layer on the opposite side of the crystalline silicon substrate for depositing the second N-type doped layer;

Masking a portion of the first intrinsic doped layer on the front surface of the crystalline silicon substrate other than the region for depositing the first P-type doped layer;

Depositing the first P-type doped layer on a region of the first intrinsic doped layer on the front side of the crystalline silicon substrate for depositing the first P-type doped layer;

Masking a portion of the second intrinsic doped layer on the opposite side of the crystalline silicon substrate other than the region for depositing the second P-type doped layer;

Depositing the second P-type doped layer on a region of the second intrinsic doped layer on the reverse side of the crystalline silicon substrate for depositing the second P-type doped layer.

Depositing a first N-type doped layer at a corresponding position of the first intrinsic doped layer on the front side of the crystalline silicon substrate and the second intrinsic doped layer on the opposite side of the crystalline silicon substrate, respectively a second P-type doped layer;

Depositing a first P-type doped layer at a corresponding position of the first intrinsic doped layer on the front side of the crystalline silicon substrate and the second intrinsic doped layer on the opposite side of the crystalline silicon substrate The second N-type doped layer.

In an embodiment of the present application, the method may further include: the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P Before the transparent conductive layer is deposited on the doped layer,

Masking a region other than the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.

In an embodiment of the present application, the method may further include: after depositing the first intrinsic doped layer and the second intrinsic doped layer on the front side and the back side of the crystalline silicon substrate, respectively, on the front side of the crystalline silicon substrate Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic doped layer, respectively depositing on the second intrinsic doped layer on the opposite side of the crystalline silicon substrate Before the two N-type doped layers and the second P-type doped layer,

Masking the first intrinsic doped layer and the second intrinsic doped layer.

In the embodiment of the present application, masking the first intrinsic doped layer and the second intrinsic doped layer may include:

A mask or mask tape is disposed on the first intrinsic doped layer and the second intrinsic doped layer.

In an embodiment of the present application, the method may further include: after forming an electrode on the transparent conductive layer,

The mask or the mask tape disposed on the first intrinsic doped layer and the second intrinsic doped layer is removed.

In the embodiment of the present application, the first intrinsic layer and the second intrinsic layer are both intrinsic amorphous silicon layers;

The first P-type doped layer and the second P-type doped layer are both a P-type amorphous silicon layer, a P-type polysilicon layer or a P-type microcrystalline silicon layer;

The first N-type doped layer and the second N-type doped layer may each be an N-type amorphous silicon layer, an N-type polysilicon layer or an N-type microcrystalline silicon layer.

The first P-type doped layer and the second P-type doped layer are both P-type amorphous silicon layers;

Each of the first N-type doped layer and the second N-type doped layer may be an N-type amorphous silicon layer.

In the embodiment of the present application, the electrode may be formed by screen printing.

Referring to FIG. 1 and FIG. 2, an embodiment of the present application provides a heterojunction solar cell including a crystalline silicon substrate 100, and a front surface of the crystalline silicon substrate 100 is provided with a first intrinsic amorphous silicon layer 110; A first N-type amorphous silicon layer 200 and a first P-type amorphous silicon layer 300 are disposed on the amorphous silicon layer 110; a first negative electrode 40 is disposed on the first N-type amorphous silicon layer 200, and the first P The first amorphous electrode 50 is disposed on the amorphous silicon layer 300; the second intrinsic amorphous silicon layer 120 is disposed on the reverse side of the crystalline silicon substrate 100; and the second N-type non-shaped is disposed on the second intrinsic amorphous silicon layer 120. a crystalline silicon layer 400 and a second P-type amorphous silicon layer 500; a second negative electrode 70 disposed on the second N-type amorphous silicon layer 400, and a second positive electrode 60 disposed on the second P-type amorphous silicon layer 500 .

In the embodiment of the present application, by depositing an N-type amorphous silicon layer and a P-type amorphous silicon layer on the front side and the back side of the crystalline silicon substrate 100, respectively, the front side and the back side of the crystalline silicon substrate 100 can respectively form a positive electrode and The negative electrode is equivalent to forming two battery chips, that is, the first battery chip 10 and the second battery chip 20, on the same crystalline silicon substrate 100, as shown in FIG. The first battery chip 10 and the second battery chip 20 can be independently powered, but the battery chip assembly composed of one crystalline silicon substrate 100 is generally used as a whole, so that the first battery chip 10 and the second battery chip 20 can be connected in series . Since the positive electrode and the negative electrode are disposed on both the front side and the back side of the crystalline silicon substrate 100, only the small solder ribbon 30 is required to connect the positive electrode on the front side or the back side of the crystalline silicon substrate 100 to the negative electrode to achieve the first The series connection of the battery chip 10 and the second battery chip 20 is as shown in FIG. If it is necessary to use two battery chip assemblies composed of two crystalline silicon substrates 100 in series, the second battery chip 20 on one battery chip assembly and the first battery chip 10 on the other battery chip assembly may be disposed in The position to be connected in series, since the polarity of the lower side of the second battery chip 20 in one battery chip assembly (as viewed in FIG. 2) is opposite to the polarity below the first battery chip 10 of another battery chip assembly to be connected in series Therefore, the second battery chip 20 on one battery chip assembly can be directly connected to the first battery chip 10 on the other battery chip assembly by the solder ribbon 30, as shown in FIG.

Since the distance between the two battery chip assemblies is small, only a small number of solder ribbons 30 are required to achieve a series connection of the two battery chip assemblies. Therefore, in the heterojunction solar cell provided by the embodiment of the present application, by providing a positive electrode and a negative electrode on both the front side and the back side of a crystalline silicon substrate 100, the adjacent two battery chip assemblies pass through the smaller solder ribbon 30. The series connection can be realized, and the solder ribbon 30 does not need to be bent, which solves the problem that the battery chip is chipped when it is used.

The drawings of the present application clearly show the various layer structures of the heterojunction solar cell, and the thicknesses of the layers in Figures 1 and 2 are not drawn to scale. As shown in FIG. 1, the first N-type amorphous silicon layer 200 and the first P-type amorphous silicon layer 300 are insulated from each other, and the second N-type amorphous silicon layer 400 and the second P-type amorphous silicon layer 500 are The insulation is arranged to prevent the N-type amorphous silicon layer and the P-type amorphous silicon layer on the front or back side of the crystalline silicon substrate 100 from sticking during the deposition process, thereby causing deposition precision at the adhesion and electronic movement difficult to control, affecting the conductive performance.

In the embodiment of the present application, an insulator may be disposed between the first N-type amorphous silicon layer 200 and the first P-type amorphous silicon layer 300 to implement the first N-type amorphous silicon layer 200 and the first P-type. Insulation between the amorphous silicon layers 300; or separating the first N-type amorphous silicon layer 200 and the first P-type amorphous silicon layer 300 from each other to achieve the first N-type amorphous silicon layer 200 and The insulation between the first P-type amorphous silicon layer 300; the second N-type amorphous silicon layer 400 and the second P-type amorphous silicon layer 500 may also be separated by a distance by providing an insulator or separating the two To achieve insulation.

As shown in FIG. 1 and FIG. 2, in the embodiment of the present application, the positions of the first N-type amorphous silicon layer 200 and the second P-type amorphous silicon layer 500 on the front and back sides of the crystalline silicon substrate are Correspondingly, the first N-type amorphous silicon layer 200 and the second P-type amorphous silicon layer 500 are respectively located on the front side and the reverse side of the same first battery chip 10; the first P-type amorphous silicon The layer 300 and the second N-type amorphous silicon layer 400 correspond to positions on the front and back sides of the crystalline silicon substrate, that is, the first P-type amorphous silicon layer 300 and the second N-type amorphous silicon The layers 400 are respectively located on the front and back sides of the same first battery chip 20.

In order to simplify the processing process and reduce the production cost, as shown in FIG. 1, the edge of the first N-type amorphous silicon layer 200 and the edge of the second P-type amorphous silicon layer 500 may be aligned in a direction perpendicular to the crystalline silicon substrate 100. The edge of the first P-type amorphous silicon layer 300 and the edge of the second N-type amorphous silicon layer 400 may be aligned in a direction perpendicular to the crystalline silicon substrate 100, thereby avoiding aligning the end faces of the amorphous silicon layer, and subsequently The laser cutting process is required to perform the cutting process of the amorphous silicon layer, thereby ensuring the alignment of the edges of the film during the deposition process, eliminating the need for cutting the edge by the subsequent laser cutting process, simplifying the process, and improving the battery chip. Yield. For the same battery chip assembly, when the first battery chip 10 and the second battery chip 20 are connected in series, since the first battery chip 10 is above (as shown in FIG. 1), the first negative electrode 40, the second battery chip Above the 20 is a first positive electrode 50, whereby the first negative electrode 40 and the first positive electrode 50 can be connected by the solder ribbon 30 to realize the series connection of the first battery chip 10 and the second battery chip 20; The second positive electrode 60 below the battery chip 10 and the second negative electrode 70 below the second battery chip 20 are connected to realize the series connection of the first battery chip 10 and the second battery chip 20. When the two battery chip assemblies are connected in series, as shown in FIG. 2, the second negative electrode 70 and the other battery under the second battery chip 20 on the bottom of one battery chip assembly (as shown in FIG. 2) may be used. The second positive electrode 60 under the first battery chip 10 on the chip assembly is electrically connected by the solder ribbon 30, whereby the series connection of the two battery chip assemblies can be achieved.

As shown in FIG. 1 , in order to enhance the conductivity of the heterojunction solar cell, the heterojunction solar cell may further include a first N-type amorphous silicon layer 200 and a first P-type amorphous silicon layer 300. a first transparent conductive layer 600; and a second transparent conductive layer 700 disposed on the second N-type amorphous silicon layer 400 and the second P-type amorphous silicon layer 500. The first negative electrode 40 and the first positive electrode 50 are both disposed on the first transparent conductive layer 600; the second negative electrode 70 and the second positive electrode 60 are both disposed on the second transparent conductive layer 700.

The first positive electrode 50, the first negative electrode 40, the second positive electrode 60, and the second negative electrode 70 may each be formed by screen printing.

The first positive electrode 50, the first negative electrode 40, the second positive electrode 60, and the second negative electrode 70 may each include a thin gate line and a main gate line. In the process of forming a silver gate line by screen printing, both the fine gate line and the main gate line are deposited on the transparent conductive layer, wherein the fine gate line is for receiving the light excited by the electron and the external output current, and the fine gate line is transparent The distribution on the conductive layer is relatively dense, and the diameter of the single fine grid line is generally 20 μ to 60 μm. In the embodiment of the present application, the diameter of the single fine grid line may be 35 μm to increase the distribution density of the fine grid lines and increase the output. Current. The current output is realized by the main gate line, and the number of the main gate lines is generally 2 to 6. In the embodiment of the present application, in order to avoid waste of the silver paste, the combination of the main gate line and the fine gate line is enhanced. Intensity, the number of main grid lines can be four.

The solder ribbon 30 can be soldered only on the main gate line, thereby requiring only a smaller size solder ribbon 30 to achieve the connection of the main gate lines on the adjacent two battery chips, thereby reducing the resistance of the solder ribbon 30. Improve the conversion efficiency of photovoltaic modules.

As shown in FIG. 3, the embodiment of the present application further provides a method for preparing a heterojunction solar cell, and the method includes the following steps:

S100, depositing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front side and the back side of the crystalline silicon substrate, respectively.

S200, depositing a first N-type amorphous silicon layer and a first P-type amorphous silicon layer on the first intrinsic amorphous silicon layer on the front surface of the crystalline silicon substrate, respectively, and a second intrinsic non-positive surface on the opposite side of the crystalline silicon substrate A second N-type amorphous silicon layer and a second P-type amorphous silicon layer are respectively deposited on the crystalline silicon layer.

a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a first N-type amorphous silicon layer, a first P-type amorphous silicon layer, a second N-type amorphous silicon layer, and a second P-type non- The crystalline silicon layer can be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD).

S300, respectively depositing a transparent conductive layer on the first N-type amorphous silicon layer, the first P-type amorphous silicon layer, the second N-type amorphous silicon layer, and the second P-type amorphous silicon layer.

S400, forming an electrode by screen printing on the transparent conductive layer.

In the heterojunction solar cell provided by the embodiment of the present application, the N-type amorphous silicon layer and the P-type amorphous silicon layer are respectively deposited on the front side and the reverse side of the crystalline silicon substrate, so that the front and back sides of the crystalline silicon substrate respectively have Positive and negative electrodes. When the two battery chip assemblies are connected in series by the soldering strip, the series connection can be realized by the soldering strip only on the same side of the two battery chip assemblies, and the size of the soldering strip can be effectively reduced, thereby reducing the two battery chips. The series resistance of the assembly; in addition, the welding strip does not need to be bent, thereby solving the problem that the welding strip is bent and easily causes chipping.

The deposition of the N-type amorphous silicon layer and the P-type amorphous silicon layer may all be in the same deposition chamber, but the parameters such as temperature and pressure during the deposition process are generally different if the front surface of the crystalline silicon substrate is deposited first. The first N-type amorphous silicon layer and the first P-type amorphous silicon layer, after depositing the first N-type amorphous silicon layer, before depositing the first P-type amorphous silicon layer, it is necessary to readjust the deposition chamber Various parameters to meet the deposition requirements of the first P-type amorphous silicon layer; then, when depositing the second N-type amorphous silicon layer and the second P-type amorphous silicon layer on the reverse side of the crystalline silicon substrate, it is necessary to adjust again Various parameters in the chamber are deposited to meet the deposition requirements of the second N-type amorphous silicon layer. Repeating the adjustment of the parameters of the deposition chamber may cause errors in the adjustment of the deposition parameters, thereby affecting the deposition precision of the film layer.

Therefore, in the embodiment of the present application, step S200 may include:

S210, depositing a first N-type amorphous silicon layer on the first intrinsic amorphous silicon layer on the front surface of the crystalline silicon substrate.

S220, depositing a second N-type amorphous silicon layer on the second intrinsic amorphous silicon layer on the reverse side of the crystalline silicon substrate.

S230, depositing a first P-type amorphous silicon layer on the first intrinsic amorphous silicon layer on the front surface of the crystalline silicon substrate.

S240, depositing a second P-type amorphous silicon layer on the second intrinsic amorphous silicon layer on the reverse side of the crystalline silicon substrate.

In steps S210 to S240, deposition parameters of the first N-type amorphous silicon layer and the second N-type amorphous silicon layer may be the same, and deposition parameters of the first P-type amorphous silicon layer and the second P-type amorphous silicon layer It can also be the same. Therefore, after the deposition of the second N-type amorphous silicon layer, before the deposition of the first P-type amorphous silicon layer, only one adjustment of each parameter in the deposition chamber is required, thereby achieving two N-type non- The deposition of the crystalline silicon layer and the two P-type amorphous silicon layers enhances the deposition efficiency while ensuring the consistency of the deposition parameters of the two N-type amorphous silicon layers and the deposition parameters of the two P-type amorphous silicon layers. The consistency ensures the accuracy of film deposition.

In the embodiment of the present application, step S200 may further include:

Masking a portion of the first intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate for depositing the first N-type amorphous silicon layer, thereby preventing deposition of the first N-type amorphous silicon layer Depositing a first N-type amorphous silicon layer to other regions;

Depositing a first N-type amorphous silicon layer on a region of the first intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate for depositing the first N-type amorphous silicon layer;

Masking a portion of the second intrinsic amorphous silicon layer on the opposite side of the crystalline silicon substrate for depositing the second N-type amorphous silicon layer, thereby preventing deposition of the second N-type amorphous silicon layer Depositing a second N-type amorphous silicon layer to other regions;

Depositing a second N-type amorphous silicon layer on a region of the second intrinsic amorphous silicon layer on the opposite side of the crystalline silicon substrate for depositing the second N-type amorphous silicon layer;

Masking a portion of the first intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate other than the region for depositing the first P-type amorphous silicon layer, thereby preventing deposition of the first P-type amorphous silicon layer Depositing the first P-type amorphous silicon layer to other regions to avoid depositing the first P-type amorphous silicon layer on the first N-type amorphous silicon layer;

Depositing a first P-type amorphous silicon layer on a region of the first intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate for depositing the first P-type amorphous silicon layer;

Masking a portion of the second intrinsic amorphous silicon layer on the opposite side of the crystalline silicon substrate for depositing the second P-type amorphous silicon layer, thereby preventing deposition of the second P-type amorphous silicon layer Depositing a second P-type amorphous silicon layer to other regions to avoid depositing a second P-type amorphous silicon layer on the second N-type amorphous silicon layer;

A second P-type amorphous silicon layer is deposited on a region of the second intrinsic amorphous silicon layer on the reverse side of the crystalline silicon substrate for depositing the second P-type amorphous silicon layer.

In the embodiment of the present application, the method may further include: after step S200, before step S300,

Masking a region other than the first N-type amorphous silicon layer, the first P-type amorphous silicon layer, the second N-type amorphous silicon layer, and the second P-type amorphous silicon layer to prevent deposition of the transparent conductive layer The regions other than the respective N-type and P-type amorphous silicon layers affect the photoelectric conversion performance of the heterojunction solar cell.

In the embodiment of the present application, the method may further include: after step S100, before step S200,

S110, masking the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer.

During the deposition process, the intrinsic amorphous silicon layer and the N, P-type amorphous silicon layer are easily deposited on the side of the crystalline silicon substrate. Therefore, after deposition of each film layer, a film removal process is usually employed to eliminate the side of the battery chip. The film layer avoids the side conduction phenomenon of the battery chip. In order to achieve the above effects, the side edges of the battery chip are usually cut or polished by a laser process or a manual sanding process to insulate the sides of the battery chip. However, the laser cutting process has high requirements on the equipment for realizing the process, and the cost is high, and when cutting, the cutting size can not be too small for convenient operation, which may reduce the effective area of the battery chip and reduce The power generation efficiency, and the manual grinding process requires experienced personnel to operate, otherwise it will easily cause the battery to rupture.

Therefore, in the method for fabricating a heterojunction solar cell provided by the embodiment of the present application, the first intrinsic amorphous silicon layer and the second portion may be deposited before depositing the N-type amorphous silicon layer and the P-type amorphous silicon layer. The amorphous silicon layer is masked to shield the area where the film layer is not required to be deposited, thereby completely solving the problem of deposition of the film layer to the non-deposited area, and also eliminating the film removing process, thereby effectively improving the preparation of the battery chip. effectiveness.

Step S110 may include:

A mask or mask tape is disposed on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer, and the mask or mask tape may be placed on the film layer during the masking operation. The position of the film can be deposited, which ensures the accuracy of the deposition position of the film layer, and is also convenient for personnel operation.

In the embodiment of the present application, when a mask or mask tape is disposed on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer, the mask or mask tape may be placed in the first A portion other than a region on the amorphous silicon layer and the second intrinsic amorphous silicon layer for depositing the N-type amorphous silicon layer and the P-type amorphous silicon layer.

In the embodiment of the present application, the method may further include: after step S200, before step S300, in order to prevent the transparent conductive layer from being deposited on the side of the two N-type amorphous silicon layers or the two P-type amorphous silicon layers.

S30, masking the first N-type amorphous silicon layer, the first P-type amorphous silicon layer, the second N-type amorphous silicon layer, and the second P-type amorphous silicon layer.

In the embodiment of the present application, the method may further include: after step S400,

A mask or mask tape disposed on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer is removed to complete the preparation of the battery chip.

The heterojunction solar cell and the preparation method thereof are provided by the embodiments of the present application, and the positive electrode and the negative electrode are disposed on the front and back sides of a crystalline silicon substrate, so that the adjacent two battery chip assemblies can be realized by a small solder ribbon. The series connection reduces the series resistance, improves the photoelectric conversion efficiency, and the solder ribbon does not need to be bent, thereby solving the problem that the battery chip is broken during use. In addition, by masking before deposition of the film layer, the deposition of the upper film layer to the edge of the underlying film layer is avoided, thereby eliminating the risk of damage to the battery chip by the film removal process, and effectively improving the preparation efficiency of the battery chip.

The disclosure is an exemplification of the principles of the embodiments of the present application, and is not intended to limit the scope of the present application. It is obvious to those skilled in the art that the elements, methods, systems, and the like of the technical solutions of the embodiments of the present application can be changed, changed, modified, and evolved without departing from the embodiments and technical solutions of the present application as described above. The principles, spirit and scope as defined in the claims. The implementations of the present invention are intended to be included within the scope of the present invention as defined by the appended claims. While the embodiments of the present application can be embodied in many different forms, the embodiments of the present application are described in detail herein. Furthermore, the embodiments of the present application include any possible combinations of some or all of the various embodiments described herein, and are included within the scope of the claims as defined by the claims. All of the patents, patent applications, and other references cited in this application, or in the entirety of each of the entire entire entire entire entire entire entire entire entire entire entire entireties

The above disclosure is intended to be illustrative rather than exhaustive. This description will suggest many variations and alternatives to those skilled in the art. All such alternatives and modifications are intended to be included within the scope of the claims, wherein the term "comprising" means "including, but not limited to." A description of alternative embodiments of the present application is completed herein. Other equivalents to the embodiments described herein will be recognized by those skilled in the art, and these equivalents are also included in the claims appended hereto.

Claims

A heterojunction solar cell, the heterojunction solar cell comprising:

Crystalline silicon substrate;

The front surface of the crystalline silicon substrate is provided with a first intrinsic layer;

a first N-type doped layer and a first P-type doped layer are disposed on the first intrinsic layer; a first negative electrode is disposed on the first N-type doped layer, and the first P-type doped a first positive electrode is disposed on the impurity layer;

a second intrinsic layer is disposed on a reverse side of the crystalline silicon substrate;

a second N-type doped layer and a second P-type doped layer are disposed on the second intrinsic layer; a second negative electrode is disposed on the second N-type doped layer, and the second P-type doped A second positive electrode is disposed on the hybrid layer.
The heterojunction solar cell according to claim 1, wherein said first N-type doped layer and said first P-type doped layer are insulated from each other; said second N-type doped layer and said An insulating arrangement between the second P-type doped layers is described.
The heterojunction solar cell according to claim 1 or 2, wherein the positions of the first N-type doped layer and the second P-type doped layer on the front and back sides of the crystalline silicon substrate are corresponding, The positions of the first P-type doped layer and the second N-type doped layer on the front and back sides of the crystalline silicon substrate correspond.
The heterojunction solar cell according to any one of claims 1 to 3, further comprising:

a first transparent conductive layer disposed on the first N-type doped layer and the first P-type doped layer;

a second transparent conductive layer disposed on the second N-type doped layer and the second P-type doped layer;

The first negative electrode and the first positive electrode are both disposed on the first transparent conductive layer;

The second negative electrode and the second positive electrode are both disposed on the second transparent conductive layer.
The heterojunction solar cell according to any one of claims 1 to 4, wherein the first negative electrode and the first positive electrode or the second negative electrode and the second positive electrode Connected by a solder ribbon.
The heterojunction solar cell according to any one of claims 1 to 5, wherein an edge of the first N-type doping layer and an edge of the second P-type doped layer are perpendicular to the crystal The silicon substrate is aligned in a direction; an edge of the first P-type doped layer is aligned with an edge of the second N-type doped layer in a direction perpendicular to the crystalline silicon substrate.
The heterojunction solar cell according to any one of claims 1 to 6, wherein the first positive electrode, the first negative electrode, the second positive electrode, and the second negative electrode are each included Fine gate line and main gate line.
The heterojunction solar cell according to claim 7, wherein the fine gate line has a diameter ranging from 20 μ to 60 μm.
The heterojunction solar cell according to claim 7 or 8, wherein the number of the main gate lines is 2 to 6.
The heterojunction solar cell according to any one of claims 1 to 9, wherein the first intrinsic layer and the second intrinsic layer are both intrinsic amorphous silicon layers.
The heterojunction solar cell according to any one of claims 1 to 10, wherein the first P-type doped layer and the second P-type doped layer are both P-type amorphous silicon layers, P Type polysilicon layer or P type microcrystalline silicon layer.
The heterojunction solar cell according to any one of claims 1 to 11, wherein the first N-type doped layer and the second N-type doped layer are both N-type amorphous silicon layers, N A type of polysilicon layer or an N type microcrystalline silicon layer.
A method of preparing a heterojunction solar cell, the method comprising the steps of:

Depositing a first intrinsic layer and a second intrinsic layer on the front side and the back side of the crystalline silicon substrate;

Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic layer of the front surface of the crystalline silicon substrate, the second intrinsic on the opposite side of the crystalline silicon substrate Depositing a second N-type doped layer and a second P-type doped layer on the layer;

An electrode is formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.
The method of fabricating a heterojunction solar cell according to claim 13, further comprising: depositing said first N-type doped layer, said first P-type doped layer, said second N-type After the doped layer and the second P-type doped layer, the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second Before forming an electrode on the P-type doped layer,

Depositing a transparent conductive layer on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer, respectively;

An electrode is then formed on the transparent conductive layer.
The method of fabricating a heterojunction solar cell according to claim 13 or 14, wherein the first N-type doped layer and the first layer are respectively deposited on the first intrinsic layer of the front surface of the crystalline silicon substrate a P-type doped layer, respectively depositing a second N-type doped layer and a second P-type doped layer on the second intrinsic layer on the opposite side of the crystalline silicon substrate comprises:

Depositing the first N-type doped layer on the first intrinsic layer of the front side of the crystalline silicon substrate;

Depositing the second N-type doped layer on the second intrinsic layer on the reverse side of the crystalline silicon substrate;

Depositing the first P-type doped layer on the first intrinsic layer of the front side of the crystalline silicon substrate;

Depositing the second P-type doped layer on the second intrinsic layer on the reverse side of the crystalline silicon substrate.
The method of producing a heterojunction solar cell according to any one of claims 13 to 15, wherein said first N-type doping is deposited on said first intrinsic layer of a front surface of said crystalline silicon substrate And depositing a second N-type doped layer and a second P-type doped layer on the second intrinsic layer on the opposite side of the crystalline silicon substrate, respectively:

Masking a portion of the first intrinsic layer of the front surface of the crystalline silicon substrate other than the region for depositing the first N-type doped layer;

Depositing the first N-type doped layer on a region of the first intrinsic layer of the front side of the crystalline silicon substrate for depositing the first N-type doped layer;

Masking a portion of the second intrinsic layer on the opposite side of the crystalline silicon substrate other than the region for depositing the second N-type doped layer;

Depositing the second N-type doped layer on a region of the second intrinsic layer on the reverse side of the crystalline silicon substrate for depositing the second N-type doped layer;

Masking a portion of the first intrinsic layer of the front surface of the crystalline silicon substrate other than the region for depositing the first P-type doped layer;

Depositing the first P-type doped layer on a region of the first intrinsic layer of the front side of the crystalline silicon substrate for depositing the first P-type doped layer;

Masking a portion of the second intrinsic layer on the opposite side of the crystalline silicon substrate other than the region for depositing the second P-type doped layer;

Depositing the second P-type doped layer on a region of the second intrinsic layer on the reverse side of the crystalline silicon substrate for depositing the second P-type doped layer.
The method of producing a heterojunction solar cell according to any one of claims 13 to 16, wherein said first N-type doping is deposited on said first intrinsic layer of a front surface of said crystalline silicon substrate And depositing a second N-type doped layer and a second P-type doped layer on the second intrinsic layer on the opposite side of the crystalline silicon substrate, respectively:

Depositing a first N-type doped layer and a second P-type, respectively, at corresponding positions of the first intrinsic layer on the front side of the crystalline silicon substrate and the second intrinsic layer on the reverse side of the crystalline silicon substrate Doped layer

Depositing a first P-type doped layer and the second portion respectively at corresponding positions of the first intrinsic layer of the front surface of the crystalline silicon substrate and the second intrinsic layer of the reverse side of the crystalline silicon substrate N-type doped layer.
The method of fabricating a heterojunction solar cell according to any one of claims 14 to 17, further comprising: said first N-type doped layer, said first P-type doped layer, said Before the transparent conductive layer is deposited on the second N-type doped layer and the second P-type doped layer, respectively.

Masking a region other than the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.
The method of producing a heterojunction solar cell according to any one of claims 13 to 18, further comprising: depositing a first intrinsic layer and a second intrinsic layer on the front side and the back side of the crystalline silicon substrate, respectively Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic layer of the front surface of the crystalline silicon substrate, the second portion on the reverse side of the crystalline silicon substrate Before depositing the second N-type doped layer and the second P-type doped layer respectively on the acquisition layer,

Masking the first intrinsic layer and the second intrinsic layer.
The method of fabricating a heterojunction solar cell according to claim 19, wherein masking the first intrinsic layer and the second intrinsic layer comprises:

A mask or mask tape is disposed on the first intrinsic layer and the second intrinsic layer.
The method of preparing a heterojunction solar cell according to claim 19 or 20, further comprising: after forming the electrode,

The mask or the mask tape disposed on the first intrinsic layer and the second intrinsic layer is removed.
The method of producing a heterojunction solar cell according to any one of claims 13 to 21, wherein the electrode is formed by screen printing.
The method for producing a heterojunction solar cell according to any one of claims 13 to 22, wherein the first intrinsic layer and the second intrinsic layer are intrinsic amorphous silicon layers;

The first P-type doped layer and the second P-type doped layer are both a P-type amorphous silicon layer, a P-type polysilicon layer or a P-type microcrystalline silicon layer;

The first N-type doped layer and the second N-type doped layer may each be an N-type amorphous silicon layer, an N-type polysilicon layer or an N-type microcrystalline silicon layer.
The method for producing a heterojunction solar cell according to any one of claims 13 to 23, wherein the first intrinsic layer and the second intrinsic layer are intrinsic amorphous silicon layers;

The first P-type doped layer and the second P-type doped layer are both P-type amorphous silicon layers;

Each of the first N-type doped layer and the second N-type doped layer may be an N-type amorphous silicon layer.