WO2019103508A1

WO2019103508A1 - Self-destruct device and method, and semiconductor chip to which same is applied

Info

Publication number: WO2019103508A1
Application number: PCT/KR2018/014486
Authority: WO
Inventors: 박성천
Original assignee: 한국전자통신연구원
Priority date: 2017-11-24
Filing date: 2018-11-23
Publication date: 2019-05-31

Abstract

The present invention relates to a self-destruct device and method, the device including: a self-destruct operation unit which is composed of a plurality of cavity cells; a variable voltage/current supplying unit which supplies a variable voltage and current to the self-destruct operation unit; an identification value match verifying unit which compares an externally input identification value with physically unclonable digital values designated to each of the cavity cells, and determines whether the two identification values match in order to supply power from the variable voltage/current supplying unit only to desired cavity cells among the plurality of cavity cells of the self-destruct operation unit; a physically unclonable digital value generation unit which gives input to the identification value match verifying unit; and an external identification value input unit which gives input to the identification value match verifying unit.

Description

Self-extinguishing device and method, and semiconductor chip using the same

The present invention relates to a self-destructing apparatus and method for identifying and operating with a digital identification value that can not be duplicated, and more particularly, to a self-destructing apparatus and method for identifying a digital identification value (PUF: Physical Unclonable Function) Destroying, disappearing, and exploding through the self-destructing device.

Devices such as cell phones, external or embedded semiconductor memory devices, digital cameras, military drones, autonomous vehicles, and artificial intelligence systems have built-in system semiconductors and memory semiconductors.

However, due to the insufficient security against important data stored in the memory semiconductor of the device and the insufficient security of the system semiconductor responsible for controlling the device, when the device is lost, deodorized or robbed, important data And control functions are exposed to others, causing serious damage.

On the other hand, in order to secure the data and main control functions embedded in the semiconductor, data is encrypted and stored, or a cryptographic technique such as user authentication and access control, in which only an authorized user accesses data, is used.

However, using hacking techniques such as power analysis attack, reverse design, or duplication technology, there is a limit of information security technology that can extract data and functions built in the device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device having a built-in function capable of self-destruction, extinction and explosion in a semiconductor chip, And a remote control signal is transmitted to the semiconductor chip to cause the semiconductor chip to disappear, disappear, or explode.

In addition, it can be used for an electronic detonator that can embed a digital identification value (ID) that can not be duplicated in a semiconductor (PUF: Physical Unclonable Function) and which can selectively ignite and explode only semiconductor chips desired to disappear, It is an object of the present invention to provide a self-destructing apparatus and method capable of manufacturing a SoC (System on Chip).

A self-destructing apparatus according to an embodiment of the present invention includes a self-destructing operation unit configured with a plurality of cavity cells; A variable voltage / current supply unit for supplying a variable voltage and a current to the self-destructive operation unit; A physical non-replicable digital value given to each cavity cell is compared with an externally input identification value to supply power to the variable voltage / current supply unit only to a desired cavity cell among a plurality of cavity cells of the self-destructive operation unit An identification value conformity check unit for discriminating whether two identification values match; A physical non-replicable digital value generation unit input to the identification value conformity check unit; And an identification value external input unit that is input to the identification value match confirmation unit.

A self-destructing apparatus and method according to the present invention can form a pad mask at a planned position where a metal pad is not disposed on a semiconductor die and perform a dry (plasma) etching process to form a desired area of the semiconductor die at a desired position At the same time, it is possible to expose a facing pin-shaped metal layer or a rod-shaped metal layer which is disposed in advance in a plurality of stacked spaces in the space, fill and seal the sparkable or explosible material in the empty space, A variable voltage / current supply unit for setting a predetermined voltage and current can be connected to the cavity cell structure, and a variable voltage / current supply unit configured to supply a variable voltage / This will not only cause ignition and temperature rise of explosive materials, (Spark) through free metal discharge through the pin-shaped metal layer facing each other, so that the ignition and explosive materials react and the semiconductor die or chip can disappear, disappear or explode. Therefore, There is an effect that the function of the circuit for operation can be stopped or the chip can be destroyed.

In addition, the self-destructing apparatus and method according to the present invention can realize the function of the semiconductor self-destruction, extinction and explosion by implementing the cavity cell in the semiconductor chip, so that the device loaded with the semiconductor can not be controlled It is possible to prevent the infiltration, hacking and deception of the data or control function built in the chip by allowing the loss, destruction and explosion function to be performed by transmitting or receiving a wireless control signal remotely in a specific location or environment which is not desired have.

In addition, the self-destructing apparatus and method according to the present invention has the effect of replacing the electromagnetic aeration used in bullets and bombs, etc., which are limited in miniaturization due to their large volume, by a single semiconductor chip .

The self-destructing apparatus and method according to the present invention further includes a metal pattern having coil characteristics by serially connecting bar-shaped metal patterns arranged horizontally, and a variable voltage / current is generated through an adjustable voltage / And a variable voltage / current is applied to the pin-

shaped metal patterns

1, 2, 3 and 1 ', 2', 3 ', an ignition or explosive substance contained in the cavity cell explodes, : Electromagnetic Pulse effect), so that it has the effect of destroying the semiconductor chip including the self-destructive operation part influenced by the electromagnetic pulse as well as all the surrounding electronic devices.

In addition, the self-destructing apparatus and method according to the present invention may comprise a physically unclonable function (PUF) digital identification (ID) generation unit and an identification value conformity check unit. When the PUF ID matches the externally designated ID Only the variable voltage / current supply unit is configured to be able to apply the voltage and current set in the cavity cell, so that only the cavity cell of the semiconductor specified for the case where the cavity cell disappears, disappears or explodes due to malfunction, , There is an effect that can cause explosion.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a self-destructing apparatus according to the present invention;

2 to 19 are views showing an embodiment of a self-extinguishing operation unit constituting a self-destructing apparatus according to the present invention.

20 and 21 are views showing an embodiment of a cavity cell constituting a self-destructing apparatus according to the present invention.

22 and 23 are views showing a process of filling a cavity cell constituting the self-destructing device with a fire or explosive material and sealing the same.

24 is a view showing a process of assembling a semiconductor chip package having a self-extinguishing operation unit according to the present invention.

25 and 26 are views showing an example in which a free discharge spark occurs when a voltage is applied in a variable voltage / current supply unit applied to a metal layer exposed in a cavity cell according to the present invention.

Figures 27 to 30 illustrate another forming process for the arrangement or arrangement of the stacked metal layers of the self-extinguishing operation according to the present invention.

Figures 31 and 32 illustrate a vertical self-destructing operation and a horizontal self-destructing operation according to the present invention.

FIG. 33 is a flowchart illustrating a process according to an embodiment of the identification value consistency checking unit of the self-destructing apparatus according to the present invention; FIG.

34 and 35 are a perspective view and a sectional view showing an identification value generating element A constituting a self-destructing apparatus according to the present invention.

36 to 38 are a perspective view, a side sectional view and a flat sectional view showing an identification value generating element B constituting a self-destructing apparatus according to the present invention.

39 is a view showing a digital non-reproducible digital identification value generator constituting a self-destructing apparatus according to the present invention;

40 is a block diagram showing an identification value generating element constituting a self-destructing apparatus according to the present invention;

41 to 43 are views showing an embodiment of a unit cell constituting a self-destructing apparatus according to the present invention.

44 and 45 are diagrams showing an embodiment of an identification value fetch unit constituting a self-destructing apparatus according to the present invention.

FIG. 46 is a flowchart illustrating a digital value generating method of the self-destructing apparatus according to the present invention; FIG.

FIG. 47 is a diagram showing that the variable voltage / current supply unit according to the present invention is enabled through the configuration and the output of the identification value conformity check unit; FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. And is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined by the claims. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that " comprises, " or " comprising, " as used herein, means the presence or absence of one or more other components, steps, operations, and / Do not exclude the addition.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1, the self-destructing apparatus 100 according to the present invention includes a self-destruct operation unit 300, a variable voltage / current supply unit 400, an identification value conformity check unit 500, a physical non- 600).

The self-destructing operation unit 300 includes a first insulating layer 211 formed on the substrate 210,

first metal layers

212 and 213 formed on the first insulating layer 211, A second insulating layer 221 formed on the second

insulating layers

212 and 213, a

second metal layer

231 and 232 formed on the second insulating layer 221 and a second insulating layer 221 formed on the second metal layers 231 and 232 A

third metal layer

251 and 252 formed on the third insulating layer 241 and a fourth insulating layer 261 formed on the

third metal layer

251 and 252. The third insulating layer 241, A

fourth metal layer

271 and 272 formed on the fourth insulating layer 261 and a fifth insulating layer 281 formed on the

fourth metal layer

271 and 272.

Here, the metal layer and the insulating layer may be stacked by a desired number of layers up to the maximum number of layers provided in the process of manufacturing a semiconductor.

The first metal layer 212 and the second metal layer 231 are formed on the first and

second metal layers

231 and 232 and the third and

fourth metal layers

251 and 252 and the

fourth metal layers

271 and 272, In order to connect the "

metal patterns

213, 231, 252, and 271 facing each other in parallel", inter-layer connection conductive vias (VIA) 291, 293 and 295 are coupled to each other, and the interlayer connection conductive vias (VIA) 292, 204 and 295 are coupled to the pin-shaped metal pattern disposed on the other side so that the two forks have a shape facing each other.

second metal layers

231 and 232 and the third and

fourth metal layers

251 and 252 and the

fourth metal layers

271 and 272, Interlayer interconnecting via vias (VIA) 301, 302, 303 are coupled to serially connect "stick-shaped metal patterns" 212, 232, 251 and 272 to form a stacked metal pattern Is formed so as to have a shape in which " d "

Here, the pin-shaped metal pattern is mainly used for generating a spark, and the rod-shaped metal pattern is used for a role of heating. As in the above embodiment, the first metal layer 212 and the second metal layer 213, All of the pin-shaped metal patterns and the bar-shaped metal patterns arranged in the second metal layers 231 232, the third metal layers 251 252 and the fourth metal layers 271 272 may be connected in series or in parallel by interlayer connection conductive vias , A pin-like metal pattern and a bar-shaped metal pattern of only the layer to which connection is desired can be connected in series or in parallel.

At this time, the unconnected pin-shaped metal pattern and the rod-shaped metal pattern can be used as a metal layer for connecting circuits performing general functions of a semiconductor, not for operating as the self-destructing operation portion 300.

That is, the self-destructive operation unit 300 can be used to stop the operation of a circuit that performs a general function of a semiconductor when the self-destructive operation unit 300 is simultaneously disconnected, destroyed, or exploded.

As in the above embodiment, all of the

first metal layers

212 and 213, the

second metal layers

231 and 232, the

third metal layers

251 and 252, and the

fourth metal layers

271 and 272, The pin-shaped metal pattern and the rod-shaped metal pattern may be stacked vertically and horizontally arranged as shown in FIG. 32 to form a pin-shaped metal pattern and a rod-shaped metal pattern.

As in the above embodiment, all of the

first metal layers

212 and 213, the

second metal layers

231 and 232, the

third metal layers

251 and 252, and the

fourth metal layers

271 and 272, The pin-shaped metal pattern is mainly used for generating a spark, and the rod-shaped metal pattern is used for a heating function or a coil application. The pin-shaped metal pattern can be formed by stacking or arranging only the pin- Only the shape metal pattern may be laminated or arranged.

As in the above embodiment, all of the

first metal layers

212 and 213, the

second metal layers

231 and 232, the

third metal layers

251 and 252, and the

fourth metal layers

271 and 272, The pin-shaped metal pattern and the bar-shaped metal pattern may be arranged so as to cross each layer. The pin-shaped metal pattern and the bar-shaped metal pattern may be arranged in parallel to each other. As shown in FIG. 27, the metal layers may be arranged in parallel. And a plurality of pin-shaped metal patterns may be arranged in parallel on the same layer as shown in FIG.

All the pin-shaped metal patterns arranged on the

first metal layers

212 and 213, the

second metal layers

231 and 232, the

third metal layers

251 and 252 and the

fourth metal layers

271 and 272, And a pattern may be formed in a shape curved toward the central portion as shown in FIG. 30, and a straight pattern and a curved pattern may be mixed with each other.

In an embodiment, the etching process may be performed by preparing an etching mask 321 having an opening 322 on the fifth insulating layer 281 or the uppermost insulating layer.

Specifically, the fifth insulating layer 281, the fourth insulating layer 261, the third insulating layer 241, and the second insulating layer 221 are formed by etching the opening portion 322 of the etching mask, The fourth insulating layer 261, the third insulating layer 241, the second insulating layer 281, the third insulating layer 241, and the second insulating layer 281 are formed on the second insulation layer 281, The layer 221 may be removed entirely or only the fifth insulating layer 281 may be removed or only the fifth insulating layer 281 and the fourth insulating layer 261 may be removed or only the fifth insulating layer 281 Only the fourth insulating layer 261 and the third insulating layer 261 can be removed and voids can be formed in such a state that only the metal layer is exposed in the removed insulating layer.

That is, the exposed

fourth metal layers

271 and 272, the

third metal layers

251 and 252, the

second metal layers

231 and 232, and the

first metal layers

212 and 213 are subjected to the dry (plasma) Is exposed to the inside of the cavity in a state where only the insulating layer is removed by the process.

At this time, if the cavity cell 800 is formed as described above, it is possible to form a plurality of cavity cells with a desired number of such cavity cells as shown in FIG.

An ignition or explosive substance 801 is injected into the plurality of cavity cells as described above and the adhesive 802 is injected into the vicinity of the cavity cell 800 through the injector 803, The glass 804 is adhered to form the self-extinguishing operation unit 300.

The

first metal layers

212 and 213, the

second metal layers

231 and 232, the

third metal layers

251 and 252 and the

fourth metal layers

271 and 272 formed in the self-destructive operation unit 300 are illustrated in FIG. Although a pair of pins facing each layer and a stick-shaped metal pattern are shown for ease of representation, a plurality of pin-shaped and rod-shaped metal pattern layers can be arranged on one layer .

In addition, the pin-like pattern can be arranged by setting a distance between the left pattern and the right pattern at a desired interval, and the width of the pin-shaped pattern and the bar-shaped pattern can be changed and arranged. The patterns may be stacked side by side or stacked separately for each layer.

In addition, although the number of metal layers is represented by only four layers in one embodiment, the number of metal layers is not limited, and it is not necessary to arrange patterns of pins and rods in all the metal layers. It is possible.

In addition, the openings of the etching mask may be formed in various shapes other than the rectangular shape shown, and the number of the cavity cells 800 may also be formed in a plurality of numbers depending on environments, purposes, and the like.

22 and 23 illustrate the shape of the self-extinguishing operation unit by exemplifying the cavity cell in which the metal layers are vertically stacked and exposed as shown in FIGS. 18 and 19, respectively. However, as shown in FIG. 32, The self-destructive operation unit can be formed through the same process in the cavity cell 800 having the exposed shape.

A plurality of the cavity cells may be arranged in the semiconductor die 805 shown in FIG. 24, and the semiconductor die (semiconductor die) may be designed to include a circuit that functions as a semiconductor.

That is, when the semiconductor die 805 in which the plurality of cavity cells 800 and the circuit for the original function of the semiconductor are integrated is completed, the semiconductor die 805 is subjected to a packaging process to complete the semiconductor chip .

The variable voltage / current supply unit 400 includes a first metal layer, a second metal layer, a third metal layer and a fourth

metal layer pattern

213, 231, 252, and 271 are connected in parallel to supply a variable voltage / current 401 between the pin-shaped left metal pattern 271 of the uppermost metal layer and the fin-shaped right metal pattern 297.

The variable voltage / current supply unit 400 includes a first metal layer, a second metal layer, a third metal layer, and a fourth

metal layer pattern

212, 232, 251, and 272 in the form of a vertically stacked or horizontally arranged stick. Are connected in series to supply a variable voltage / current (401) between the uppermost metal patterns (272, 305).

That is, when a variable voltage / current 401 is applied between the

metal patterns

272 and 305 at the top of the stick-shaped metal pattern, the wrinkled metal pattern acts as an electric heater to generate heat 403, This allows the ignition or explosive substance 801 contained in the capillary cell 800 of the self-destructive operation unit 300 to reach a temperature suitable for ignition or explosion.

A variable voltage / current (401) voltage is applied between the left fin-shaped metal pattern (271) and the right fin-shaped metal pattern (297) The free ignition flame 402 is generated to increase the current size so that the ignition or explosive material 801 embedded in the cavity cell of the self-destructive operation unit 300 ignites or explodes, physically destroying the semiconductor chip, It is impossible to hack or duplicate the data or the function built in the semiconductor chip by causing the chip to malfunction.

32, a metal pattern having coil characteristics is formed by serially connecting bar-shaped metal patterns arranged horizontally, and a variable voltage / current is supplied through the variable voltage / 32 'A and B, and a variable voltage / current is applied to the pin-shaped metal patterns 1/2/3 and 1' / 2 '/ 3' shown in FIG. 31 through the variable voltage / current supply unit 400 The semiconductor chip including the self-extinguishing operation portion within the influence of the electromagnetic pulse, due to the electromagnetic pulse effect (EMP: Electromagnetic Pulse Effect) while exploding the explosive substance contained in the capillary cell, It will be destroyed by affecting all surrounding electronic devices.

Referring to FIG. 47, the variable voltage / current supplying unit 400 includes a voltage generating circuit 400 for receiving a VDD voltage and increasing the voltage to a high voltage VHV And the voltage VDD supplied to the double voltage generating circuit is supplied to the high voltage (VDD) by supplying or cutting off the VDD voltage through the enable signal of 1 or 0, which is the result value of the identification value conformity check unit 500 VHV) to the self-destructing operation unit 300.

33, the identification value conformity check unit 500 checks the digital value (PUF.ID) provided by the non-physically replicable digital value generation unit 600 and the digital value (PUF.ID) provided from the identification value external input unit 700 (EXT. ID), and outputs "1" if they match, and outputs "0" when they do not match, thereby enabling the variable voltage / current supply unit 400 as shown in FIG. Do not.

The non-physically non-reproducible digital value generator 600 selectively identifies only the self-destructive operation unit 300 that is desired to operate and outputs a variable voltage / current through the variable voltage / current supply unit 400 to the self-destructive operation unit 300 .

That is, the digital non-reproducible digital value generation unit 600 prevents the self-destructive operation unit 300 from operating in an undesired condition, and selectively identifies and operates only the self-destructive operation unit 300 that desires to operate .

Referring to FIG. 45, the digital non-reproducible digital identification value generation unit 600 includes an identification value generation unit 610 and an identification value extraction unit 620.

The identification value generating unit 610 includes a plurality of unit cells 11 ₁ to 11 _N and outputs a plurality of digital bits output from each of the plurality of unit cells 11 ₁ to 11 _N to an identification value extractor 620 .

Each of the plurality of unit cells 11 ₁ to 11 _N can generate a 1-bit digital value.

Further, each of the plurality of unit cells 11 ₁ to 11 _N may generate a binary digital value of 0 or 1 through electrical conduction or blocking of the identification value generating element.

The identification value extractor 620 receives the digital values output from the plurality of unit cells 11 ₁ to 11 _N of the identification value generator 610 and outputs N bits And outputs the identification value.

The identification value of the N bits output from the identification value fetch unit 620 corresponds to the PUF. ID.

Next, referring to FIG. 40, an identification value generating element according to an embodiment of the present invention will be described. In the identification value generating element A, the first lower electrode and the second lower electrode are formed in the same layer, The via and the third via are also formed in the same layer, and the first upper electrode and the first via are electrically energized, and the first lower electrode, the second via, the second lower electrode, the third via, and the third lower electrode are electrically And a binary digital value of 0 or 1, depending on whether the first via is electrically connected to or disconnected from the first lower electrode, the second via or the second lower electrode, the third via or the third lower electrode. .

40, the identification value generating element B is formed such that the first lower electrode and the second lower electrode are formed in the same layer, the first upper electrode and the first via are electrically energized, The second via, the second via, and the third lower electrode are formed in an electrically conductive state, and the first via is electrically connected to the first lower electrode, the second via, or the second lower electrode. A binary digital value is generated.

40, the first lower electrode and the second lower electrode and the third lower electrode are located below the first upper electrode, and the first lower electrode and the second lower electrode are located on the same layer And the third lower electrode is formed on the other layer. A second via is formed between the first lower electrode and the third lower electrode, and an insulating film is located where the second via is not formed.

Further, a third via is formed between the second lower electrode and the third lower electrode, and an insulating film is located where the third via is not formed.

Here, for convenience, only the first upper electrode is shown and there is no other electrode on the upper side, but a larger number of upper electrodes may be formed on different layers.

Also, although the second lower electrode and the third lower electrode are shown for convenience, a larger number of lower electrodes may be formed in different layers.

The second via is formed by filling the via hole formed under the first lower electrode with a conductor and provides a connection with the third lower electrode.

The third via is formed by filling the via hole formed under the second lower electrode with a conductor and provides a connection with the third lower electrode. The first via is formed by filling the via hole formed under the first upper electrode with a conductor and provides a connection with the first upper electrode.

Further, when the first via reaches the first lower electrode or the second via or the second lower electrode or the third via or the third lower electrode, the first upper electrode is electrically connected, while the first via is connected to the first lower electrode, Electrode, the second via, the second lower electrode, the third via, and the third lower electrode.

Also, the output portion may include a first upper electrode and a binary digital value of 0 or 1 depending on whether the first via is electrically connected to or disconnected from the first lower electrode and between the second via and the third lower electrode and the second lower electrode and the third via. And outputs the generated binary digital value.

40, the first lower electrode and the second lower electrode and the third lower electrode are located below the first upper electrode, and the first lower electrode and the second lower electrode are disposed on the same layer And the third lower electrode is formed on the other layer.

A second via is formed between the first lower electrode and the third lower electrode, and an insulating film is formed where the second via is not formed.

Further, a second via is formed between the second lower electrode and the third lower electrode, and an insulating film is disposed where the second via is not formed.

Here, although only the first upper electrode is shown and there are no other electrodes on the upper electrode, a larger number of upper electrodes may be formed in different layers.

Also, although the first lower electrode, the second lower electrode, and the third lower electrode are shown for convenience, a larger number of lower electrodes may be formed in different layers.

Also, the second via is formed by filling the via hole formed under the first lower electrode and the second lower electrode with a conductor and provides a connection with the third lower electrode.

The first via is formed by filling the via hole formed under the first upper electrode with a conductor and provides a connection with the first upper electrode.

Further, when the first via reaches the first lower electrode or the second via or the second lower electrode, the first upper electrode is electrically connected.

Whereas the first via is electrically disconnected if it does not reach the first lower electrode, the second via and the second lower electrode.

And the output portion generates a binary digital value of 0 or 1 depending on whether the first upper electrode and the first via are electrically connected or disconnected with the first lower electrode and the second via and the second lower electrode, Output.

Next, FIG. 34 shows an embodiment of the identification value generating element A, in which an insulating film (layer) is formed on a substrate and a third lower electrode (metal layer) M1 is formed on the insulating film , And an insulating film is formed on the third lower electrode.

A second via hole is formed through an etching process to connect the first lower electrode M2 and the third lower electrode M1 and the second lower electrode M2 and the third lower electrode M1 A third via hole is formed through the etching process.

When the second via hole and the third via hole are filled with a conductor, a via (VIA2-1) is formed, a first lower electrode is formed on the second via, and a second lower electrode And an insulating film (layer) is formed on the first lower electrode and the second lower electrode.

Also, a first via hole is formed on the insulating film (layer) for connection with the first upper electrode M3 through an etching process. When the first via hole is filled with a conductor, a via VIA3-2 is formed. And a first upper electrode is formed on the upper portion.

Here, the first upper electrode M3, the first lower electrode M2, the second lower electrode M2, and the third lower electrode M1 may each include a connection member for connection to a voltage source.

As shown in FIG. 34, the length (VIA3-2 length) of the first via is also increased or decreased proportionally as the width (VIA3-2 width) of the first via is increased or decreased.

Therefore, if the width of the first via (VIA3-2) is increased, the first lower electrode (metal layer M2), the second via VIA2-1, the third lower electrode (metal layer M1), and the third via VIA2- M1 & VIA2 & & & & & >, M2) formed of the first lower electrode (metal layer M2)

On the other hand, when the width of the first via (VIA3-2 width) is narrowed, the first lower electrode (metal layer M2), the second via VIA2-1, the third lower electrode (metal layer M1), and the third via VIA2 -1 >) and the second bottom electrode (metal layer, M2), the electrical connection to the hollow metal rectangular pocket shape (M2 & VIA2-1 & M1 &

The first via (VIA3-2), the first lower electrode (metal layer, M2), the second via (VIA2-1), the third lower electrode (metal layer, M1), and the third via Capacitance values are formed between the hollow metal rectangular pocket shapes (M2 & VIA2-1 & M1 & VIA2-1 & M2) composed of the first lower electrode (VIA2-1) and the second lower electrode , M3) and the first lower electrode (metal layer, M2), that is, the dotted line portion in FIG. 38, acts as a capacitance element.

38, an insulation layer (layer) is formed on a substrate and a third lower electrode (metal layer) M1 is formed on the insulation layer (layer). And an insulating film is formed on the third lower electrode.

A second via hole is formed through an etching process to connect the first lower electrode and the second lower electrode. Vias VIA2-1 are formed when the formed second via hole is filled with a conductor, The first lower electrode M2 and the second lower electrode M2 are formed on the upper portion VIA2-1.

An insulating film (layer) is formed on the first lower electrode M2 and the second lower electrode M2. A first via hole is etched to connect the first upper electrode M3 to the upper portion of the insulating film When the conductor is filled in the first dehydration hole, a via VIA3-2 is formed and a first upper electrode M3 is formed on the via.

In this case, the first upper electrode, the first lower electrode, the second lower electrode, and the third lower electrode may each include a connection member for connection with a voltage source. As shown in FIG. 38, -2 width), the length (VIA3-2 length) of the first via also increases or decreases proportionally.

Therefore, if the width of the first via (VIA3-2 width) is widened, a hollow metal square composed of the first lower electrode (metal layer M2), the second via VIA2-1 and the second lower electrode (metal layer M2) And is electrically connected to the pocket shape (M2 & VIA2-1 & M2).

On the other hand, if the width of the first via (VIA3-2 width) is narrowed, the hollow metal rectangular pocket (metal layer M2) composed of the first lower electrode (metal layer M2), the second via VIA2-1 and the second lower electrode The electrical connection with the shape (M2 & VIA2-1 & M2) is cut off.

In the state in which the electrical connection is cut off, a hollow metal (metal layer) composed of the first via VIA3-2, the first lower electrode (metal layer M2), the second via VIA2-1 and the second lower electrode Capacitance values are formed between the rectangular pocket shapes (M2 & VIA2-1 & M2) to form a capacitance between the first upper electrode (metal layer, M3) and the first lower electrode .

The identification value generating elements thus formed can be used as identification value generating elements of the N unit cells 11 ₁ to 11 _{N in} FIG.

Next, shown in FIG. 41 and FIG. 42 is as shown for the unit cell, according to an embodiment of the invention, illustrated Although FIG. 41 and FIG. 42 shows only one unit cell (11 _1), and the remaining unit cells (11 ₂ to 11 _N may be configured to be the same as or similar to the unit cell 11 ₁ .

41 and 42, a unit cell 11 ₁ includes an identification value generating element 11 ₁ and an output node 11 ₃ , and the unit cell 11 ₁ includes a resistor R ₁ , .

The identification value generating element 11 ₁ may be one of the identification value generating element A and the identification value generating element B shown in Figs. 34 and 35 shown in Fig.

That is, the identification value generating element 11 _{1 is} connected between the reference voltage source VDD and one end of the resistor R, and the other end of the resistor R is connected to the ground voltage source GND.

Specifically, the first upper electrode is connected to the reference voltage source VDD, and the first lower electrode, the second lower electrode or the third lower electrode is connected to the resistor R connected to the ground voltage source GND.

The first lower electrode, the second lower electrode or the third lower electrode is connected to the output node 113, and the output node 113 is connected to the first upper electrode and the first lower electrode, And outputs a binary digital value of 0 or 1 through electrical connection or disconnection between the electrodes.

At this time, the length (VIA3-2 length) of the first via is also increased or decreased by increasing or decreasing the width (VIA3-2 width) of the first via as described above. In the identification value generating element A, Or between the first lower electrode and the third lower electrode or between the first lower electrode and the third lower electrode or between the first upper electrode and the third lower electrode, The connection or blocking is determined, and 0 or 1 is determined accordingly.

In the discrimination value generating element B, the distance between the first upper electrode and the first lower electrode or the distance between the third lower electrode or the second lower electrode, depending on whether the first via reaches the first lower electrode or the second via or the second lower electrode, An electrical connection or blocking is determined, and 0 or 1 is determined accordingly.

42, a resistor R is connected between the first upper electrode and the reference voltage source VDD, and the first lower electrode, the third lower electrode, or the second lower electrode is connected to the ground voltage source VDD, (GND), and the first upper electrode may be connected to the output node 113.

And as described in the illustrated Figure 39, identification generator 10 is N comprises an N number of unit cells (11 ₁ to 11 _N) to create an identification value of the bit, N number of unit cells (11 ₁ - 11 _N may all be configured as the unit cell shown in FIG. 41, the unit cells shown in FIG. 42, or the unit cells shown in FIGS. 41 and 42 may be composed as shown in FIG.

In addition, a part of the N unit cells 11 ₁ to 11 _N may consist of the identification value generating element A shown in FIG. 34 so that 1 and 0 appear uniformly in the N unit cells 11 ₁ to 11 _N And the remaining part thereof may be constituted by the identification value generating element B shown in Fig.

For example, if one of the N binary digital values output from the N unit cells 11 ₁ to 11 _N is N / 2 and 0 is N / 2, it is assumed that 0 and 1 are equal in the identification value .

Accordingly, in order to obtain an N-bit identification value equal to 0 and 1, the first upper electrode and the first lower electrode or the second lower electrode or the third lower electrode are electrically connected to each other in the _N unit cells 11 ₁ to 11 _N The first lower electrode, the second lower electrode, or the third lower electrode are electrically isolated from each other so that the ratio of the ID value generating element to the N number of unit cells 11 ₁ to 11 _N ).

At this time, it is determined whether the first upper electrode and the first lower electrode or the third lower electrode or the second lower electrode are electrically connected or disconnected according to whether the width of the first via (VIA3-2 width) is wide or narrow, In addition, various variables may exist. For example, when a via hole for forming the first via is formed in an insulating film, the thickness and material of the insulating film, and the time and temperature of the etching process may act as variables in the semiconductor etching process. (Random) between the first upper electrode and the first lower electrode or between the second lower electrode and the third lower electrode.

Accordingly, it is possible to implement _N unit cells 11 ₁ to 11 _N for obtaining an N-bit identification value equal to 0 and 1 by appropriately adjusting and controlling these variables, A plurality of identification value generating elements according to design values and process values that are different from those of the above parameters are manufactured at an inexpensive chip manufacturing cost by using MPW (Multi-Project Wafer) process, The uniformity of 0 and 1 can be confirmed by confirming the uniformity. Then, the parameters ensuring the uniformity of 0 and 1 are selected and applied to the mass production process, so that the unit cells 11 ₁ to 11 _N ).

34, the identification value generating element A shown in Fig. 34 has a structure in which the first via is connected to the first lower electrode (metal layer, M2) and the second via (VIA2-1) and the third lower electrode (metal layer, M2) (M2 & VIA2-1 & M1 & VIA2-1 & M2) composed of the second lower electrode.

At this time, the width (VIA3-2 width) of the first via is designed to be wide or narrow, and the length of the first via (VIA3-2 length) changes, so that the capacitance values have different values.

38, the identification value generating element B shown in Fig. 38 has a hollow metal rectangular pocket shape M2 (metal layer M2) composed of a first lower electrode (metal layer, M2) and a second via (VIA2-1) & VIA2-1 & & & & & & & & & & & & & M2, and may perform the function of a capacitor of an electronic component.

Referring to Fig. 43 showing a unit cell using this characteristic, the following description will be given.

Referring to FIG. 43, the unit cell 11 ₁ includes an identification value generating element 111, a Schmitt triggered NAND gate 112, a resistor R, and an output node 116.

And the identification value generating element 111 may be one in shown in FIG. 34 or generate 38 identification value generating element A or identification described in the element B, such unit cells (11 ₁₎ is to operate as an oscillator circuit And outputs a square wave frequency f [Hz] of 1 / (2.2 Rcv) through the output node 116.

In FIG. 43 shown here, Cv represents the capacitance value of the identification value generating element 111.

The square wave frequency value output from the unit cell 11 ₁ can be used to generate a fixed binary digital value by sampling at a desired time point and can be used as a clock necessary for driving a digital circuit.

At this time, the identification value generating element A is composed of a first via, a first lower electrode (metal layer, M2), a second via (VIA2-1), a third lower electrode (metal layer, M2) and a third via and a second lower electrode The capacitance values between the hollow metal rectangular pocket shapes (M2 & VIA2-1 & M1 & VIA2-1 & M2) have different values for each of the identification value generating elements 111 of the _N unit cells 11 ₁ to 11 _N . The identification value generating element B also has a hollow metal rectangular pocket shape (M2 & VIA2-1 &num; M2) consisting of a first via, a first lower electrode (metal layer M2), a second via May have different values depending on the identification value generating elements 111 of the _N unit cells 11 ₁ to 11 _N.

The identification value generating element A has a hollow structure composed of a first via, a first lower electrode (metal layer, M2), a second via (VIA2-1), a third lower electrode (metal layer, M2), a third via and a second lower electrode The capacitance value between the empty metal rectangular pocket shapes (M2 & VIA2-1 & M1 & VIA2-1 & M2) and the identification value generating element B are the capacitance between the first via and the first lower electrode (metal layer M2) -1) and the second lower electrode, the capacitance value between the hollow metal rectangular pocket shapes M2 and VIA2-1 & M2 is determined as shown in Equation (1).

[Equation 1]

C =? * A / t

Here,? Is the distance between the first via and the first lower electrode (metal layer, M2), the second via (VIA2-1) and the third lower electrode (metal layer, M2) (M2 & VIA2-1 & M1 & VIA2-1 & M2) composed of the lower electrode.

In addition, the identification value generating element B has a hollow metal rectangular pocket shape (M2 & VIA2-1 &num; 2 &thetas; 2) formed of a first via, a first lower electrode (metal layer, M2), a second via M2). &Lt; / RTI >

34, the identification value generating element A includes a first via, a first lower electrode (metal layer, M2), a second via (VIA2-1), and a third lower electrode (metal layer, M2) And a hollow metal rectangular pocket shape (M2 & VIA2-1 & M1 & VIA2-1 & M2) consisting of the third via and the second lower electrode.

As shown by the dotted line in FIG. 39, the identification value generating element B is a hollow metal rectangle composed of the first via, the first lower electrode (metal layer, M2), the second via (VIA2-1) and the second lower electrode The pocket shape (M2 & VIA2-1 & M2) represents the facing area.

And t represents the spacing between the first via and the hollow metal rectangular pocket shape.

As described above, the width of the etching hole for forming the first via, the thickness and material of the insulating film, the time and temperature of the etching process, etc., can act as variables in the semiconductor etching process, The capacitance value can be determined at random (random).

Therefore, by appropriately adjusting and controlling these parameters, the capacitance value can be differently implemented for each identification value generating element 111 of the _N unit cells 11 ₁ to 11 _N.

In order to confirm the capacitance value of the _N unit cells 11 ₁ to 11 _N , the semiconductor chip may be fabricated through the MPW process and the capacitance value may be measured for each identification value generating device of the fabricated semiconductor chip.

FIG. 44 shows an identification value fetch unit according to an embodiment of the present invention. The identification value fetch unit 20 includes an input / output unit 201. FIG.

The input / output unit 201 receives the binary digital values output from the plurality of unit cells 11 ₁ to 11 _N of the identification value generation unit 10, and outputs an identification value of N bits.

In this case, the plurality of unit cells 11 ₁ to 11 _N may be configured as shown in the unit cell of FIG. 41 or may be configured as the unit cell of FIG. 42, and in FIGS. 41 and 42 The illustrated unit cells may be configured in a mixed manner.

43, when the plurality of unit cells 11 ₁ to 11 _N are configured as shown in FIG. 43, the identification value fetcher 200 generates a plurality of unit cells 11 ₁ to 11 N _N ), respectively.

43, in which a plurality of unit cells 11 ₁ to 11 _N are constructed as shown in FIG. 45, the identification value fetch unit 20 will be described with reference to FIG.

FIG. 45 shows an identification value fetch unit 600 according to another embodiment of the present invention. The identification value fetch unit 600 includes a sampling unit 610 and an output unit 620.

The sampling unit 610 includes a plurality of D flip-flops receiving square wave frequency values f ₁ through f _N output from the plurality of unit cells 11 ₁ through 11 _N , respectively.

The plurality of D flip-flops each have an input terminal D, an output terminal Q and a clock terminal CLK. When the clock signal SCLK is applied to the clock terminal CLK, 1 is output through the output terminal Q when the input signal is 1, and 0 is output through the output terminal Q when the input signal input to the input terminal D is 0.

Further, when the clock signal (SCLK) at the time when the desired sampling is input to the clock terminal (CLK), a plurality of D flip-flop is a square wave the frequency values which are respectively outputted from the plurality of unit cells (11 ₁ ~ 11 _N), respectively (f ₁ ~ f _N), the binary digital value corresponding to the frequency value of this point, via the output terminal (Q), and outputs from the output unit 620.

The output unit 620 receives binary digital values output from the plurality of D flip-flops, and outputs an identification value of N bits.

46 is a flowchart illustrating a digital value generating method according to an embodiment of the present invention. The digital value generating method includes a step S610 of generating a 1-bit digital value by each of a plurality of unit cells, And a step (S620) of extracting a 1-bit digital value generated by each unit cell and outputting an N-bit identification value.

Specifically, the digital value generating device 1 generates a 1-bit digital value by each of the plurality of unit cells 11 ₁ to 11 _N including the above-described identification value generating elements, 11 ₁ to 11 _N ) and outputs an N-bit identification value.

In this case, if configured as shown in Figure 43 a plurality of unit cells (11 ₁ ~ 11 _N) in the drawing, the digital value generating unit (1) is a square wave the frequency value output from each of the plurality of unit cells (11 ₁ ~ 11 _N) And generates a 1-bit digital value corresponding to the frequency value at the time of sampling.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the essential characteristics thereof, .

Therefore, the embodiments described in the present invention are not intended to limit the scope of the present invention, but are intended to be illustrative, and the scope of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted according to the claims below, and all technical ideas which are equivalent or within the scope of equivalents should be interpreted as being included in the upper right of the present invention.

Claims

A self-destructive operation unit configured with a plurality of cavity cells;

A variable voltage / current supply unit for supplying a variable voltage and a current to the self-destructive operation unit;

A physical non-replicable digital value given to each cavity cell is compared with an externally input identification value to supply power to the variable voltage / current supply unit only to a desired cavity cell among a plurality of cavity cells of the self-destructive operation unit An identification value conformity check unit for discriminating whether two identification values match;

A physical non-replicable digital value generation unit input to the identification value conformity check unit; And

And an identification value external input unit that is input to the identification value match confirmation unit.
2. The apparatus according to claim 1, wherein the self-

A first insulating layer formed on the substrate;

A first metal layer of the pin-shaped metal pattern formed on the first insulating layer and the rod-shaped metal pattern;

A second insulating layer formed on the first metal layer;

A second metal layer of the opposite pin-like metal pattern formed on the second insulating layer and the rod-shaped metal pattern;

A third insulating layer formed on the second metal layer;

A third metal layer of the pin-shaped metal pattern formed on the third insulating layer and the rod-shaped metal pattern;

A fourth insulating layer formed on the third metal layer;

A fourth metal layer of the pin-shaped metal pattern formed on the fourth insulating layer and the rod-shaped metal pattern;

And a pair of interlayer interconnection lines connecting the pin-shaped metal patterns disposed on one side and the other side of the opposing pin-shaped metal patterns formed on the first metal layer, the second metal layer, the third metal layer, Connecting conductive vias;

Interlayer connection conductive vias connecting the bar-shaped metal patterns formed in each of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer in series;

A fifth insulating layer formed on the fourth metal layer and the fourth insulating layer;

A plurality of voids formed in the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer through a dry (plasma) etching process;

And a physical non-replicable digital value generator having an auto-extinction operation unit for injecting said igniting or explosive substance into said plurality of void spaces and sealing said film or said glass.
3. The method of claim 2,

Wherein the opposing metal pattern of the pin-shaped metal pattern constituting the metal layer is formed in one of a triangular shape, an arrowhead shape, and a pointed shape while the end portion is horizontally or bendably formed.
3. The method of claim 2,

Wherein the insulating layer and the metal layer constituting the self-extinguishing operation portion are mounted in a horizontal direction.
2. The apparatus according to claim 1, wherein the self-

A first insulating layer formed on the substrate;

A first metal layer of the pin-shaped metal pattern formed on the first insulating layer and the rod-shaped metal pattern;

A second insulating layer formed on the first metal layer;

A second metal layer of the opposite pin-like metal pattern formed on the second insulating layer and the rod-shaped metal pattern;

A third insulating layer formed on the second metal layer;

A third metal layer of the pin-shaped metal pattern formed on the third insulating layer and the rod-shaped metal pattern;

A fourth insulating layer formed on the third metal layer;

A fourth metal layer of the pin-shaped metal pattern formed on the fourth insulating layer and the rod-shaped metal pattern;

Shaped metal patterns formed on the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer, respectively, of the pin-shaped metal patterns formed on the first and second metal layers, Interlayer interconnecting conductive vias;

And a metal pattern not connected to interlayer connection conductive vias among the opposing pin-shaped metal patterns formed on the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer is connected to the metal layer for circuit connection of the semiconductor functional block A pin-shaped metal pattern;

The interlayer connection conductive vias connecting the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer by selecting the bar-shaped metal patterns and connecting them in series;

A bar-shaped metal pattern formed on each of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer to connect the metal pattern not connected to the interlayer connection conductive via among the rod- Of the metal pattern;

A fifth insulating layer formed on the fourth metal layer;

A plurality of voids formed in the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer through a dry (plasma) etching process;

And a physical non-replicable digital value generator having an auto-extinction operation unit for injecting said igniting or explosive substance into said plurality of void spaces and sealing said film or said glass.
2. The apparatus according to claim 1, wherein the self-

A first insulating layer formed on the substrate;

A first metal layer of a metal pattern formed on the first insulating layer and arranged at regular intervals;

A second insulating layer formed on the first metal layer;

A plurality of second vias formed on the second insulating layer and formed to connect the first metal layer;

A plurality of second metal layers formed on the second vias;

A second metal layer of a plurality of pin-shaped metal patterns formed on the second insulating layer and arranged at regular intervals;

A third insulating layer formed on the second metal layer;

A plurality of third vias formed on the third insulating layer and formed to connect the second metal layer;

A third metal layer of a plurality of " I " -shaped metal patterns formed on the third vias and arranged at regular intervals;

A fourth insulating layer formed on the third metal layer;

A pair of metal patterns of the same layer formed on the second metal layer and arranged in parallel and selecting and connecting pin-shaped metal patterns arranged on one side or the other side of the plurality of pin-shaped metal patterns facing each other;

A fifth insulating layer formed on the fourth metal layer;

A plurality of voids formed in the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer through a dry (plasma) etching process;

And a physical non-replicable digital value generator having an auto-extinction operation unit for injecting said igniting or explosive substance into said plurality of void spaces and sealing said film or said glass.
2. The apparatus of claim 1, wherein the non-physically replicable digital value generator comprises:

An identification value generation unit including a plurality of unit cells; And

And an identification value fetch unit for outputting a plurality of identification values using the output values of the plurality of unit cells.
8. The method of claim 7,

Wherein each of the plurality of unit cells includes an identification value generating element including a first upper electrode and a third lower electrode formed on different layers,

The output value is determined by electrical connection or disconnection between the first upper electrode and the third lower electrode,

Wherein the electrical connection or cutoff is determined by a difference in length of the first via formed in the lower portion of the first upper electrode.
8. The apparatus according to claim 7, wherein the identification value generating element

A first insulating film formed on the substrate;

A third lower electrode formed on the first insulating film;

A second insulating layer formed on the third lower electrode;

A second via hole formed through an etching process to a lower portion of the second insulating film and a third via hole formed through an etching process to a lower portion of the first lower electrode;

A second via and a third via formed in the same layer by filling conductors in the second via hole and the third via hole, respectively;

The first lower electrode and the second lower electrode formed on the same layer on the second via and the third via;

A third insulating layer formed on the first lower electrode and the second lower electrode;

A first via hole formed through an etching process to a lower portion of the third insulating film;

A first via formed by filling a conductor in the first via hole; And

And a first upper electrode formed for the first via.
10. The method of claim 9,

Wherein the first via hole is formed at a different depth through the variation of the etching process.
The method of claim 9,

The first upper electrode and the third lower electrode are electrically connected when the first via reaches the first lower electrode or the second lower electrode or the second via or the third via or the third lower electrode,

And the first upper electrode and the third lower electrode are electrically disconnected when the first via does not reach the first lower electrode, the second lower electrode, the second via, the third via, and the third lower electrode A device that dissipates phosphorus.
8. The method of claim 7,

The plurality of unit cells may include an identification value generating element in which the first upper electrode and the first lower electrode or the second lower electrode or the second via or the third via or the third lower electrode are electrically connected,

And a remaining part of the plurality of unit cells includes an identification value generating element in which the first upper electrode and the first lower electrode, the second lower electrode, the second via, the third via, and the third lower electrode are electrically disconnected A self-destruct device.
8. The apparatus of claim 7, wherein each of the plurality of unit cells comprises:

A first voltage source for supplying a first voltage;

The identification value generating element being connected between a second voltage source for supplying a second voltage lower than the first voltage; And

And an output node for outputting 0 or 1 as the output value in accordance with the electrical connection or disconnection of the identification value generating element.
14. The apparatus of claim 13, wherein each of the plurality of unit cells comprises:

Further comprising a resistor connected between the second voltage source and the identification value generating element,

Wherein the first upper electrode is coupled to the first voltage source, the third lower electrode is coupled to the resistor, and the output node is coupled to the third lower electrode.
14. The apparatus of claim 13, wherein each of the plurality of unit cells comprises:

Further comprising a resistor connected between the first voltage source and the identification value generating element,

Wherein the first upper electrode is coupled to the resistor, the third lower electrode is coupled to the second voltage source, and the output node is coupled to the first upper electrode.
14. The method of claim 13,

Wherein each of the plurality of unit cells includes an oscillation circuit that uses the identification value generating element as a capacitor and outputs a square wave frequency as the output value.
8. The apparatus according to claim 7,

A sampling unit for sampling a square wave frequency output from each of the plurality of unit cells and outputting a plurality of binary digital values; And

And outputting the identification value of the plurality of bits from the plurality of binary digital values.
19. The method of claim 18,

Wherein the sampling unit includes a plurality of D flip-flops for receiving a square wave frequency outputted from each of the plurality of unit cells and outputting 0 or 1 from a value of a square wave frequency when a clock signal is applied, .
18. The method of claim 17,

Wherein the plurality of unit cells have different depths of the first vias and the identification value generating elements.
The method according to claim 1,

Wherein the self-destructive actuation is identified and operated with a digital identification value that is non-reproducible with the ignited or explosive material.
The method according to claim 1,

Wherein the variable voltage / current supply unit is capable of applying a desired current using a current mirror.
The method according to claim 1,

Wherein the variable voltage / current supply unit is capable of applying a desired voltage using a voltage multiplier.
Forming a self-extinguishing operation portion composed of a plurality of cavity cells;

Providing a variable voltage / current supply unit for supplying a variable voltage and a current to the self-destructive operation unit;

Inputting an identification value through a non-replicable digital value generation unit and an identification value external input unit in an identification value conformity check unit;

The identification value matching confirmation unit compares the digital non-replicable digital value given to each cavity cell with the externally input identification value, And supplying power to the variable voltage / current supply unit only to a desired cavity cell, thereby self-destroying.
24. The apparatus of claim 23, wherein the non-physically replicable digital value generator comprises:

Generating a plurality of output values using a plurality of unit cells each including an identification value generating element; And

And outputting a plurality of identification values using the plurality of output values.
25. The apparatus according to claim 24,

A first insulating layer formed on the substrate;

A third lower electrode formed on the first insulating film;

A second insulating layer formed on the third lower electrode;

A second via hole and a third via hole formed in the same layer through an etching process to a lower portion of the second insulating film; A second via and a third via formed by filling the second via hole and the third via hole with a conductor;

The first lower electrode and the second lower electrode formed on the same layer for the second via and the third via;

A third insulating layer formed on the first lower electrode and the second lower electrode;

A first via hole formed to have a different depth through an etching process to a lower portion of the third insulating film;

A first via formed by filling a conductor in the first via hole; And

And a first upper electrode formed on the first via.
25. The method of claim 24,

The output value is generated to be 0 or 1 depending on whether the first upper electrode and the first lower electrode or the second via or the second lower electrode or the third via are electrically connected or disconnected through the first via ; &Lt; / RTI >

Wherein the first via hole is formed at a different depth through the etching process.
25. The method of claim 24,

Wherein the generating comprises:

And generating the square wave frequency with the output value using the identification value generating element as a capacitor.
25. The method of claim 24,

The outputting step

Generating a plurality of binary digital values by sampling each square wave frequency output from each of the plurality of unit cells at a desired point in time; And

And outputting the identification value of the plurality of bits from the plurality of binary digital values,

Wherein the first via holes are formed with different depths and widths through the etching process.
24. The apparatus of claim 23, wherein the non-physically replicable digital value generator comprises:

An identification value generation unit including a plurality of unit cells;

And an identification value fetch unit for outputting a plurality of identification values using the output values of the plurality of unit cells,

Wherein each of the plurality of unit cells includes an identification value generating element including a first upper electrode and a third lower electrode formed on different layers,

The output value is determined by electrical connection or disconnection between the first upper electrode and the third lower electrode,

Wherein the electrical connection or blocking is determined by a difference in length of the first vias formed through etching at a lower portion of the first upper electrode.
25. The apparatus according to claim 24,

A first insulating film formed on the substrate;

A third lower electrode formed on the first insulating film;

A second insulating layer on the third lower electrode;

A second via hole formed through an etching process to a lower portion of the second insulating film;

A second via formed in the same layer by filling the second via with a conductor, respectively;

The first lower electrode and the second lower electrode formed on the same layer on the second via;

A third insulating layer formed on the first lower electrode and the second lower electrode;

A first via hole formed through an etching process to a lower portion of the third insulating film;

A first via formed by filling a conductor in the first via hole; And

And a first upper electrode formed for the first via.
31. The method of claim 30,

Wherein the first via hole is formed at a different depth through the variation of the etching process.
32. The method of claim 31,

The first upper electrode and the third lower electrode are electrically connected when the first via reaches the first lower electrode, the second lower electrode, or the second via,

Wherein the first upper electrode and the third lower electrode are electrically disconnected when the first via does not reach the first lower electrode, the second lower electrode, and the second via.
25. The method of claim 24,

Wherein a part of the plurality of unit cells includes an identification value generating element in which the first upper electrode is electrically connected to the first lower electrode or the second lower electrode or the second via or the third lower electrode,

And the remaining part of the plurality of unit cells includes an identification value generating element in which the first upper electrode is electrically disconnected from the first lower electrode, the second lower electrode, the second via, the third via, and the third lower electrode A method of extinction.
The method of claim 24, wherein each of the plurality of unit cells comprises:

The identification value generating element being connected between a first voltage source for supplying a first voltage and a second voltage source for supplying a second voltage lower than the first voltage; And

And an output node for outputting 0 or 1 as the output value in accordance with the electrical connection or disconnection of the identification value generating element.
The method of claim 24, wherein each of the plurality of unit cells comprises:

Further comprising a resistor connected between the second voltage source and the identification value generating element,

Wherein the first upper electrode is coupled to the first voltage source, the third lower electrode is coupled to the resistor, and the output node is coupled to the third lower electrode.
The method of claim 24, wherein each of the plurality of unit cells comprises:

Further comprising a resistor connected between the first voltage source and the identification value generating element,

Wherein the first upper electrode is coupled to the resistor, the third lower electrode is coupled to the second voltage source, and the output node is coupled to the first upper electrode.
30. The apparatus according to claim 29,

A sampling unit for sampling a square wave frequency output from each of the plurality of unit cells and outputting a plurality of binary digital values; And

And outputting the identification value of the plurality of bits from the plurality of binary digital values.
39. The method of claim 37,

Wherein the sampling unit includes a plurality of D flops for receiving a square wave frequency output from each of the plurality of unit cells and outputting 0 or 1 from a value of a square wave frequency when a clock signal is applied, .
37. The method of claim 36,

Wherein at least some of the identification value generating elements of the plurality of unit cells have different depths of the first vias.
24. The apparatus of claim 23, wherein the non-physically replicable digital value generator comprises:

Generating a plurality of output values using a plurality of unit cells each including an identification value generating element; And

And outputting an identification value of a plurality of bits using the plurality of output values,

Wherein the identification value generating element comprises:

A first insulating layer formed on the substrate;

A third lower electrode formed on the first insulating film;

A second insulating layer formed on the third lower electrode;

A second via hole formed through an etching process to a lower portion of the second insulating film, and a second via formed by filling a metal in the second via hole;

The first lower electrode and the second lower electrode formed on the same layer on the second via;

A third insulating layer formed on the first lower electrode and the second lower electrode;

A first via formed by filling a conductor in a first via hole formed at a different depth through an etching process to a lower portion of the third insulating film; And

And a first upper electrode formed on the first via.
41. The method of claim 40,

Generating the output value to 0 or 1 according to whether the first upper electrode and the first lower electrode or the second via or the second lower electrode are electrically connected or disconnected through the first via,

Wherein the first via hole is formed at a different depth through the etching process.
41. The method of claim 40,

And generating the square wave frequency with the output value using the identification value generating element as a capacitor.
A semiconductor chip for use in an electron detonator produced by the method of claim 1 or claim 23.
A semiconductor chip which generates an electron emission effect due to an electromagnetic pulse effect (EMP) to which any one of claims 1, 2, and 6 is applied.